4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #ifdef CONFIG_USER_ONLY
35 #include "qemu_socket.h"
37 /* XXX: these constants may be independent of the host ones even for Unix */
57 typedef struct GDBState
{
58 CPUState
*env
; /* current CPU */
59 enum RSState state
; /* parsing state */
63 char last_packet
[4100];
65 #ifdef CONFIG_USER_ONLY
73 #ifdef CONFIG_USER_ONLY
74 /* XXX: This is not thread safe. Do we care? */
75 static int gdbserver_fd
= -1;
77 /* XXX: remove this hack. */
78 static GDBState gdbserver_state
;
80 static int get_char(GDBState
*s
)
86 ret
= recv(s
->fd
, &ch
, 1, 0);
88 if (errno
!= EINTR
&& errno
!= EAGAIN
)
90 } else if (ret
== 0) {
100 /* GDB stub state for use by semihosting syscalls. */
101 static GDBState
*gdb_syscall_state
;
102 static gdb_syscall_complete_cb gdb_current_syscall_cb
;
110 /* If gdb is connected when the first semihosting syscall occurs then use
111 remote gdb syscalls. Otherwise use native file IO. */
112 int use_gdb_syscalls(void)
114 if (gdb_syscall_mode
== GDB_SYS_UNKNOWN
) {
115 gdb_syscall_mode
= (gdb_syscall_state
? GDB_SYS_ENABLED
118 return gdb_syscall_mode
== GDB_SYS_ENABLED
;
121 static void put_buffer(GDBState
*s
, const uint8_t *buf
, int len
)
123 #ifdef CONFIG_USER_ONLY
127 ret
= send(s
->fd
, buf
, len
, 0);
129 if (errno
!= EINTR
&& errno
!= EAGAIN
)
137 qemu_chr_write(s
->chr
, buf
, len
);
141 static inline int fromhex(int v
)
143 if (v
>= '0' && v
<= '9')
145 else if (v
>= 'A' && v
<= 'F')
147 else if (v
>= 'a' && v
<= 'f')
153 static inline int tohex(int v
)
161 static void memtohex(char *buf
, const uint8_t *mem
, int len
)
166 for(i
= 0; i
< len
; i
++) {
168 *q
++ = tohex(c
>> 4);
169 *q
++ = tohex(c
& 0xf);
174 static void hextomem(uint8_t *mem
, const char *buf
, int len
)
178 for(i
= 0; i
< len
; i
++) {
179 mem
[i
] = (fromhex(buf
[0]) << 4) | fromhex(buf
[1]);
184 /* return -1 if error, 0 if OK */
185 static int put_packet(GDBState
*s
, char *buf
)
191 printf("reply='%s'\n", buf
);
201 for(i
= 0; i
< len
; i
++) {
205 *(p
++) = tohex((csum
>> 4) & 0xf);
206 *(p
++) = tohex((csum
) & 0xf);
208 s
->last_packet_len
= p
- s
->last_packet
;
209 put_buffer(s
, s
->last_packet
, s
->last_packet_len
);
211 #ifdef CONFIG_USER_ONLY
224 #if defined(TARGET_I386)
226 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
229 uint32_t *registers
= (uint32_t *)mem_buf
;
232 /* This corresponds with amd64_register_info[] in gdb/amd64-tdep.c */
233 uint64_t *registers64
= (uint64_t *)mem_buf
;
235 if (env
->hflags
& HF_CS64_MASK
) {
236 registers64
[0] = tswap64(env
->regs
[R_EAX
]);
237 registers64
[1] = tswap64(env
->regs
[R_EBX
]);
238 registers64
[2] = tswap64(env
->regs
[R_ECX
]);
239 registers64
[3] = tswap64(env
->regs
[R_EDX
]);
240 registers64
[4] = tswap64(env
->regs
[R_ESI
]);
241 registers64
[5] = tswap64(env
->regs
[R_EDI
]);
242 registers64
[6] = tswap64(env
->regs
[R_EBP
]);
243 registers64
[7] = tswap64(env
->regs
[R_ESP
]);
244 for(i
= 8; i
< 16; i
++) {
245 registers64
[i
] = tswap64(env
->regs
[i
]);
247 registers64
[16] = tswap64(env
->eip
);
249 registers
= (uint32_t *)®isters64
[17];
250 registers
[0] = tswap32(env
->eflags
);
251 registers
[1] = tswap32(env
->segs
[R_CS
].selector
);
252 registers
[2] = tswap32(env
->segs
[R_SS
].selector
);
253 registers
[3] = tswap32(env
->segs
[R_DS
].selector
);
254 registers
[4] = tswap32(env
->segs
[R_ES
].selector
);
255 registers
[5] = tswap32(env
->segs
[R_FS
].selector
);
256 registers
[6] = tswap32(env
->segs
[R_GS
].selector
);
257 /* XXX: convert floats */
258 for(i
= 0; i
< 8; i
++) {
259 memcpy(mem_buf
+ 16 * 8 + 7 * 4 + i
* 10, &env
->fpregs
[i
], 10);
261 registers
[27] = tswap32(env
->fpuc
); /* fctrl */
262 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
263 registers
[28] = tswap32(fpus
); /* fstat */
264 registers
[29] = 0; /* ftag */
265 registers
[30] = 0; /* fiseg */
266 registers
[31] = 0; /* fioff */
267 registers
[32] = 0; /* foseg */
268 registers
[33] = 0; /* fooff */
269 registers
[34] = 0; /* fop */
270 for(i
= 0; i
< 16; i
++) {
271 memcpy(mem_buf
+ 16 * 8 + 35 * 4 + i
* 16, &env
->xmm_regs
[i
], 16);
273 registers
[99] = tswap32(env
->mxcsr
);
275 return 8 * 17 + 4 * 7 + 10 * 8 + 4 * 8 + 16 * 16 + 4;
279 for(i
= 0; i
< 8; i
++) {
280 registers
[i
] = env
->regs
[i
];
282 registers
[8] = env
->eip
;
283 registers
[9] = env
->eflags
;
284 registers
[10] = env
->segs
[R_CS
].selector
;
285 registers
[11] = env
->segs
[R_SS
].selector
;
286 registers
[12] = env
->segs
[R_DS
].selector
;
287 registers
[13] = env
->segs
[R_ES
].selector
;
288 registers
[14] = env
->segs
[R_FS
].selector
;
289 registers
[15] = env
->segs
[R_GS
].selector
;
290 /* XXX: convert floats */
291 for(i
= 0; i
< 8; i
++) {
292 memcpy(mem_buf
+ 16 * 4 + i
* 10, &env
->fpregs
[i
], 10);
294 registers
[36] = env
->fpuc
;
295 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
296 registers
[37] = fpus
;
297 registers
[38] = 0; /* XXX: convert tags */
298 registers
[39] = 0; /* fiseg */
299 registers
[40] = 0; /* fioff */
300 registers
[41] = 0; /* foseg */
301 registers
[42] = 0; /* fooff */
302 registers
[43] = 0; /* fop */
304 for(i
= 0; i
< 16; i
++)
305 tswapls(®isters
[i
]);
306 for(i
= 36; i
< 44; i
++)
307 tswapls(®isters
[i
]);
311 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
313 uint32_t *registers
= (uint32_t *)mem_buf
;
316 for(i
= 0; i
< 8; i
++) {
317 env
->regs
[i
] = tswapl(registers
[i
]);
319 env
->eip
= tswapl(registers
[8]);
320 env
->eflags
= tswapl(registers
[9]);
321 #if defined(CONFIG_USER_ONLY)
322 #define LOAD_SEG(index, sreg)\
323 if (tswapl(registers[index]) != env->segs[sreg].selector)\
324 cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
334 #elif defined (TARGET_PPC)
335 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
337 uint32_t *registers
= (uint32_t *)mem_buf
, tmp
;
341 for(i
= 0; i
< 32; i
++) {
342 registers
[i
] = tswapl(env
->gpr
[i
]);
345 for (i
= 0; i
< 32; i
++) {
346 registers
[(i
* 2) + 32] = tswapl(*((uint32_t *)&env
->fpr
[i
]));
347 registers
[(i
* 2) + 33] = tswapl(*((uint32_t *)&env
->fpr
[i
] + 1));
349 /* nip, msr, ccr, lnk, ctr, xer, mq */
350 registers
[96] = tswapl(env
->nip
);
351 registers
[97] = tswapl(env
->msr
);
353 for (i
= 0; i
< 8; i
++)
354 tmp
|= env
->crf
[i
] << (32 - ((i
+ 1) * 4));
355 registers
[98] = tswapl(tmp
);
356 registers
[99] = tswapl(env
->lr
);
357 registers
[100] = tswapl(env
->ctr
);
358 registers
[101] = tswapl(ppc_load_xer(env
));
364 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
366 uint32_t *registers
= (uint32_t *)mem_buf
;
370 for (i
= 0; i
< 32; i
++) {
371 env
->gpr
[i
] = tswapl(registers
[i
]);
374 for (i
= 0; i
< 32; i
++) {
375 *((uint32_t *)&env
->fpr
[i
]) = tswapl(registers
[(i
* 2) + 32]);
376 *((uint32_t *)&env
->fpr
[i
] + 1) = tswapl(registers
[(i
* 2) + 33]);
378 /* nip, msr, ccr, lnk, ctr, xer, mq */
379 env
->nip
= tswapl(registers
[96]);
380 ppc_store_msr(env
, tswapl(registers
[97]));
381 registers
[98] = tswapl(registers
[98]);
382 for (i
= 0; i
< 8; i
++)
383 env
->crf
[i
] = (registers
[98] >> (32 - ((i
+ 1) * 4))) & 0xF;
384 env
->lr
= tswapl(registers
[99]);
385 env
->ctr
= tswapl(registers
[100]);
386 ppc_store_xer(env
, tswapl(registers
[101]));
388 #elif defined (TARGET_SPARC)
389 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
391 target_ulong
*registers
= (target_ulong
*)mem_buf
;
395 for(i
= 0; i
< 8; i
++) {
396 registers
[i
] = tswapl(env
->gregs
[i
]);
398 /* fill in register window */
399 for(i
= 0; i
< 24; i
++) {
400 registers
[i
+ 8] = tswapl(env
->regwptr
[i
]);
402 #ifndef TARGET_SPARC64
404 for (i
= 0; i
< 32; i
++) {
405 registers
[i
+ 32] = tswapl(*((uint32_t *)&env
->fpr
[i
]));
407 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
408 registers
[64] = tswapl(env
->y
);
413 registers
[65] = tswapl(tmp
);
415 registers
[66] = tswapl(env
->wim
);
416 registers
[67] = tswapl(env
->tbr
);
417 registers
[68] = tswapl(env
->pc
);
418 registers
[69] = tswapl(env
->npc
);
419 registers
[70] = tswapl(env
->fsr
);
420 registers
[71] = 0; /* csr */
422 return 73 * sizeof(target_ulong
);
425 for (i
= 0; i
< 64; i
+= 2) {
428 tmp
= ((uint64_t)*(uint32_t *)&env
->fpr
[i
]) << 32;
429 tmp
|= *(uint32_t *)&env
->fpr
[i
+ 1];
430 registers
[i
/ 2 + 32] = tswap64(tmp
);
432 registers
[64] = tswapl(env
->pc
);
433 registers
[65] = tswapl(env
->npc
);
434 registers
[66] = tswapl(((uint64_t)GET_CCR(env
) << 32) |
435 ((env
->asi
& 0xff) << 24) |
436 ((env
->pstate
& 0xfff) << 8) |
438 registers
[67] = tswapl(env
->fsr
);
439 registers
[68] = tswapl(env
->fprs
);
440 registers
[69] = tswapl(env
->y
);
441 return 70 * sizeof(target_ulong
);
445 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
447 target_ulong
*registers
= (target_ulong
*)mem_buf
;
451 for(i
= 0; i
< 7; i
++) {
452 env
->gregs
[i
] = tswapl(registers
[i
]);
454 /* fill in register window */
455 for(i
= 0; i
< 24; i
++) {
456 env
->regwptr
[i
] = tswapl(registers
[i
+ 8]);
458 #ifndef TARGET_SPARC64
460 for (i
= 0; i
< 32; i
++) {
461 *((uint32_t *)&env
->fpr
[i
]) = tswapl(registers
[i
+ 32]);
463 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
464 env
->y
= tswapl(registers
[64]);
465 PUT_PSR(env
, tswapl(registers
[65]));
466 env
->wim
= tswapl(registers
[66]);
467 env
->tbr
= tswapl(registers
[67]);
468 env
->pc
= tswapl(registers
[68]);
469 env
->npc
= tswapl(registers
[69]);
470 env
->fsr
= tswapl(registers
[70]);
472 for (i
= 0; i
< 64; i
+= 2) {
475 tmp
= tswap64(registers
[i
/ 2 + 32]);
476 *((uint32_t *)&env
->fpr
[i
]) = tmp
>> 32;
477 *((uint32_t *)&env
->fpr
[i
+ 1]) = tmp
& 0xffffffff;
479 env
->pc
= tswapl(registers
[64]);
480 env
->npc
= tswapl(registers
[65]);
482 uint64_t tmp
= tswapl(registers
[66]);
484 PUT_CCR(env
, tmp
>> 32);
485 env
->asi
= (tmp
>> 24) & 0xff;
486 env
->pstate
= (tmp
>> 8) & 0xfff;
487 PUT_CWP64(env
, tmp
& 0xff);
489 env
->fsr
= tswapl(registers
[67]);
490 env
->fprs
= tswapl(registers
[68]);
491 env
->y
= tswapl(registers
[69]);
494 #elif defined (TARGET_ARM)
495 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
501 /* 16 core integer registers (4 bytes each). */
502 for (i
= 0; i
< 16; i
++)
504 *(uint32_t *)ptr
= tswapl(env
->regs
[i
]);
507 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
508 Not yet implemented. */
509 memset (ptr
, 0, 8 * 12 + 4);
511 /* CPSR (4 bytes). */
512 *(uint32_t *)ptr
= tswapl (cpsr_read(env
));
515 return ptr
- mem_buf
;
518 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
524 /* Core integer registers. */
525 for (i
= 0; i
< 16; i
++)
527 env
->regs
[i
] = tswapl(*(uint32_t *)ptr
);
530 /* Ignore FPA regs and scr. */
532 cpsr_write (env
, tswapl(*(uint32_t *)ptr
), 0xffffffff);
534 #elif defined (TARGET_M68K)
535 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
543 for (i
= 0; i
< 8; i
++) {
544 *(uint32_t *)ptr
= tswapl(env
->dregs
[i
]);
548 for (i
= 0; i
< 8; i
++) {
549 *(uint32_t *)ptr
= tswapl(env
->aregs
[i
]);
552 *(uint32_t *)ptr
= tswapl(env
->sr
);
554 *(uint32_t *)ptr
= tswapl(env
->pc
);
556 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
557 ColdFire has 8-bit double precision registers. */
558 for (i
= 0; i
< 8; i
++) {
560 *(uint32_t *)ptr
= tswap32(u
.l
.upper
);
561 *(uint32_t *)ptr
= tswap32(u
.l
.lower
);
563 /* FP control regs (not implemented). */
564 memset (ptr
, 0, 3 * 4);
567 return ptr
- mem_buf
;
570 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
578 for (i
= 0; i
< 8; i
++) {
579 env
->dregs
[i
] = tswapl(*(uint32_t *)ptr
);
583 for (i
= 0; i
< 8; i
++) {
584 env
->aregs
[i
] = tswapl(*(uint32_t *)ptr
);
587 env
->sr
= tswapl(*(uint32_t *)ptr
);
589 env
->pc
= tswapl(*(uint32_t *)ptr
);
591 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
592 ColdFire has 8-bit double precision registers. */
593 for (i
= 0; i
< 8; i
++) {
594 u
.l
.upper
= tswap32(*(uint32_t *)ptr
);
595 u
.l
.lower
= tswap32(*(uint32_t *)ptr
);
598 /* FP control regs (not implemented). */
601 #elif defined (TARGET_MIPS)
602 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
608 for (i
= 0; i
< 32; i
++)
610 *(target_ulong
*)ptr
= tswapl(env
->gpr
[i
][env
->current_tc
]);
611 ptr
+= sizeof(target_ulong
);
614 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->CP0_Status
);
615 ptr
+= sizeof(target_ulong
);
617 *(target_ulong
*)ptr
= tswapl(env
->LO
[0][env
->current_tc
]);
618 ptr
+= sizeof(target_ulong
);
620 *(target_ulong
*)ptr
= tswapl(env
->HI
[0][env
->current_tc
]);
621 ptr
+= sizeof(target_ulong
);
623 *(target_ulong
*)ptr
= tswapl(env
->CP0_BadVAddr
);
624 ptr
+= sizeof(target_ulong
);
626 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->CP0_Cause
);
627 ptr
+= sizeof(target_ulong
);
629 *(target_ulong
*)ptr
= tswapl(env
->PC
[env
->current_tc
]);
630 ptr
+= sizeof(target_ulong
);
632 if (env
->CP0_Config1
& (1 << CP0C1_FP
))
634 for (i
= 0; i
< 32; i
++)
636 if (env
->CP0_Status
& (1 << CP0St_FR
))
637 *(target_ulong
*)ptr
= tswapl(env
->fpu
->fpr
[i
].d
);
639 *(target_ulong
*)ptr
= tswap32(env
->fpu
->fpr
[i
].w
[FP_ENDIAN_IDX
]);
640 ptr
+= sizeof(target_ulong
);
643 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->fpu
->fcr31
);
644 ptr
+= sizeof(target_ulong
);
646 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->fpu
->fcr0
);
647 ptr
+= sizeof(target_ulong
);
650 /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
651 *(target_ulong
*)ptr
= 0;
652 ptr
+= sizeof(target_ulong
);
654 /* Registers for embedded use, we just pad them. */
655 for (i
= 0; i
< 16; i
++)
657 *(target_ulong
*)ptr
= 0;
658 ptr
+= sizeof(target_ulong
);
662 *(target_ulong
*)ptr
= (int32_t)tswap32(env
->CP0_PRid
);
663 ptr
+= sizeof(target_ulong
);
665 return ptr
- mem_buf
;
668 /* convert MIPS rounding mode in FCR31 to IEEE library */
669 static unsigned int ieee_rm
[] =
671 float_round_nearest_even
,
676 #define RESTORE_ROUNDING_MODE \
677 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
679 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
685 for (i
= 0; i
< 32; i
++)
687 env
->gpr
[i
][env
->current_tc
] = tswapl(*(target_ulong
*)ptr
);
688 ptr
+= sizeof(target_ulong
);
691 env
->CP0_Status
= tswapl(*(target_ulong
*)ptr
);
692 ptr
+= sizeof(target_ulong
);
694 env
->LO
[0][env
->current_tc
] = tswapl(*(target_ulong
*)ptr
);
695 ptr
+= sizeof(target_ulong
);
697 env
->HI
[0][env
->current_tc
] = tswapl(*(target_ulong
*)ptr
);
698 ptr
+= sizeof(target_ulong
);
700 env
->CP0_BadVAddr
= tswapl(*(target_ulong
*)ptr
);
701 ptr
+= sizeof(target_ulong
);
703 env
->CP0_Cause
= tswapl(*(target_ulong
*)ptr
);
704 ptr
+= sizeof(target_ulong
);
706 env
->PC
[env
->current_tc
] = tswapl(*(target_ulong
*)ptr
);
707 ptr
+= sizeof(target_ulong
);
709 if (env
->CP0_Config1
& (1 << CP0C1_FP
))
711 for (i
= 0; i
< 32; i
++)
713 if (env
->CP0_Status
& (1 << CP0St_FR
))
714 env
->fpu
->fpr
[i
].d
= tswapl(*(target_ulong
*)ptr
);
716 env
->fpu
->fpr
[i
].w
[FP_ENDIAN_IDX
] = tswapl(*(target_ulong
*)ptr
);
717 ptr
+= sizeof(target_ulong
);
720 env
->fpu
->fcr31
= tswapl(*(target_ulong
*)ptr
) & 0xFF83FFFF;
721 ptr
+= sizeof(target_ulong
);
723 /* The remaining registers are assumed to be read-only. */
725 /* set rounding mode */
726 RESTORE_ROUNDING_MODE
;
728 #ifndef CONFIG_SOFTFLOAT
729 /* no floating point exception for native float */
730 SET_FP_ENABLE(env
->fcr31
, 0);
734 #elif defined (TARGET_SH4)
736 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
738 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
740 uint32_t *ptr
= (uint32_t *)mem_buf
;
743 #define SAVE(x) *ptr++=tswapl(x)
744 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
745 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
+ 16]);
747 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
]);
749 for (i
= 8; i
< 16; i
++) SAVE(env
->gregs
[i
]);
759 for (i
= 0; i
< 16; i
++)
760 SAVE(env
->fregs
[i
+ ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)]);
763 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
]);
764 for (i
= 0; i
< 8; i
++) SAVE(env
->gregs
[i
+ 16]);
765 return ((uint8_t *)ptr
- mem_buf
);
768 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
770 uint32_t *ptr
= (uint32_t *)mem_buf
;
773 #define LOAD(x) (x)=*ptr++;
774 if ((env
->sr
& (SR_MD
| SR_RB
)) == (SR_MD
| SR_RB
)) {
775 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
+ 16]);
777 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
]);
779 for (i
= 8; i
< 16; i
++) LOAD(env
->gregs
[i
]);
789 for (i
= 0; i
< 16; i
++)
790 LOAD(env
->fregs
[i
+ ((env
->fpscr
& FPSCR_FR
) ? 16 : 0)]);
793 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
]);
794 for (i
= 0; i
< 8; i
++) LOAD(env
->gregs
[i
+ 16]);
796 #elif defined (TARGET_CRIS)
798 static int cris_save_32 (unsigned char *d
, uint32_t value
)
801 *d
++ = (value
>>= 8);
802 *d
++ = (value
>>= 8);
803 *d
++ = (value
>>= 8);
806 static int cris_save_16 (unsigned char *d
, uint32_t value
)
809 *d
++ = (value
>>= 8);
812 static int cris_save_8 (unsigned char *d
, uint32_t value
)
818 /* FIXME: this will bug on archs not supporting unaligned word accesses. */
819 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
821 uint8_t *ptr
= mem_buf
;
825 for (i
= 0; i
< 16; i
++)
826 ptr
+= cris_save_32 (ptr
, env
->regs
[i
]);
828 srs
= env
->pregs
[SR_SRS
];
830 ptr
+= cris_save_8 (ptr
, env
->pregs
[0]);
831 ptr
+= cris_save_8 (ptr
, env
->pregs
[1]);
832 ptr
+= cris_save_32 (ptr
, env
->pregs
[2]);
833 ptr
+= cris_save_8 (ptr
, srs
);
834 ptr
+= cris_save_16 (ptr
, env
->pregs
[4]);
836 for (i
= 5; i
< 16; i
++)
837 ptr
+= cris_save_32 (ptr
, env
->pregs
[i
]);
839 ptr
+= cris_save_32 (ptr
, env
->pc
);
841 for (i
= 0; i
< 16; i
++)
842 ptr
+= cris_save_32 (ptr
, env
->sregs
[srs
][i
]);
844 return ((uint8_t *)ptr
- mem_buf
);
847 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
849 uint32_t *ptr
= (uint32_t *)mem_buf
;
852 #define LOAD(x) (x)=*ptr++;
853 for (i
= 0; i
< 16; i
++) LOAD(env
->regs
[i
]);
857 static int cpu_gdb_read_registers(CPUState
*env
, uint8_t *mem_buf
)
862 static void cpu_gdb_write_registers(CPUState
*env
, uint8_t *mem_buf
, int size
)
868 static int gdb_handle_packet(GDBState
*s
, CPUState
*env
, const char *line_buf
)
871 int ch
, reg_size
, type
;
873 uint8_t mem_buf
[4096];
875 target_ulong addr
, len
;
878 printf("command='%s'\n", line_buf
);
884 /* TODO: Make this return the correct value for user-mode. */
885 snprintf(buf
, sizeof(buf
), "S%02x", SIGTRAP
);
890 addr
= strtoull(p
, (char **)&p
, 16);
891 #if defined(TARGET_I386)
893 #elif defined (TARGET_PPC)
895 #elif defined (TARGET_SPARC)
898 #elif defined (TARGET_ARM)
899 env
->regs
[15] = addr
;
900 #elif defined (TARGET_SH4)
902 #elif defined (TARGET_MIPS)
903 env
->PC
[env
->current_tc
] = addr
;
904 #elif defined (TARGET_CRIS)
908 #ifdef CONFIG_USER_ONLY
909 s
->running_state
= 1;
916 addr
= strtoull(p
, (char **)&p
, 16);
917 #if defined(TARGET_I386)
919 #elif defined (TARGET_PPC)
921 #elif defined (TARGET_SPARC)
924 #elif defined (TARGET_ARM)
925 env
->regs
[15] = addr
;
926 #elif defined (TARGET_SH4)
928 #elif defined (TARGET_MIPS)
929 env
->PC
[env
->current_tc
] = addr
;
930 #elif defined (TARGET_CRIS)
934 cpu_single_step(env
, 1);
935 #ifdef CONFIG_USER_ONLY
936 s
->running_state
= 1;
946 ret
= strtoull(p
, (char **)&p
, 16);
949 err
= strtoull(p
, (char **)&p
, 16);
956 if (gdb_current_syscall_cb
)
957 gdb_current_syscall_cb(s
->env
, ret
, err
);
959 put_packet(s
, "T02");
961 #ifdef CONFIG_USER_ONLY
962 s
->running_state
= 1;
970 reg_size
= cpu_gdb_read_registers(env
, mem_buf
);
971 memtohex(buf
, mem_buf
, reg_size
);
975 registers
= (void *)mem_buf
;
977 hextomem((uint8_t *)registers
, p
, len
);
978 cpu_gdb_write_registers(env
, mem_buf
, len
);
982 addr
= strtoull(p
, (char **)&p
, 16);
985 len
= strtoull(p
, NULL
, 16);
986 if (cpu_memory_rw_debug(env
, addr
, mem_buf
, len
, 0) != 0) {
987 put_packet (s
, "E14");
989 memtohex(buf
, mem_buf
, len
);
994 addr
= strtoull(p
, (char **)&p
, 16);
997 len
= strtoull(p
, (char **)&p
, 16);
1000 hextomem(mem_buf
, p
, len
);
1001 if (cpu_memory_rw_debug(env
, addr
, mem_buf
, len
, 1) != 0)
1002 put_packet(s
, "E14");
1004 put_packet(s
, "OK");
1007 type
= strtoul(p
, (char **)&p
, 16);
1010 addr
= strtoull(p
, (char **)&p
, 16);
1013 len
= strtoull(p
, (char **)&p
, 16);
1014 if (type
== 0 || type
== 1) {
1015 if (cpu_breakpoint_insert(env
, addr
) < 0)
1016 goto breakpoint_error
;
1017 put_packet(s
, "OK");
1018 #ifndef CONFIG_USER_ONLY
1019 } else if (type
== 2) {
1020 if (cpu_watchpoint_insert(env
, addr
) < 0)
1021 goto breakpoint_error
;
1022 put_packet(s
, "OK");
1026 put_packet(s
, "E22");
1030 type
= strtoul(p
, (char **)&p
, 16);
1033 addr
= strtoull(p
, (char **)&p
, 16);
1036 len
= strtoull(p
, (char **)&p
, 16);
1037 if (type
== 0 || type
== 1) {
1038 cpu_breakpoint_remove(env
, addr
);
1039 put_packet(s
, "OK");
1040 #ifndef CONFIG_USER_ONLY
1041 } else if (type
== 2) {
1042 cpu_watchpoint_remove(env
, addr
);
1043 put_packet(s
, "OK");
1046 goto breakpoint_error
;
1049 #ifdef CONFIG_LINUX_USER
1051 if (strncmp(p
, "Offsets", 7) == 0) {
1052 TaskState
*ts
= env
->opaque
;
1055 "Text=" TARGET_ABI_FMT_lx
";Data=" TARGET_ABI_FMT_lx
1056 ";Bss=" TARGET_ABI_FMT_lx
,
1057 ts
->info
->code_offset
,
1058 ts
->info
->data_offset
,
1059 ts
->info
->data_offset
);
1067 /* put empty packet */
1075 extern void tb_flush(CPUState
*env
);
1077 #ifndef CONFIG_USER_ONLY
1078 static void gdb_vm_stopped(void *opaque
, int reason
)
1080 GDBState
*s
= opaque
;
1084 if (s
->state
== RS_SYSCALL
)
1087 /* disable single step if it was enable */
1088 cpu_single_step(s
->env
, 0);
1090 if (reason
== EXCP_DEBUG
) {
1091 if (s
->env
->watchpoint_hit
) {
1092 snprintf(buf
, sizeof(buf
), "T%02xwatch:" TARGET_FMT_lx
";",
1094 s
->env
->watchpoint
[s
->env
->watchpoint_hit
- 1].vaddr
);
1096 s
->env
->watchpoint_hit
= 0;
1101 } else if (reason
== EXCP_INTERRUPT
) {
1106 snprintf(buf
, sizeof(buf
), "S%02x", ret
);
1111 /* Send a gdb syscall request.
1112 This accepts limited printf-style format specifiers, specifically:
1113 %x - target_ulong argument printed in hex.
1114 %lx - 64-bit argument printed in hex.
1115 %s - string pointer (target_ulong) and length (int) pair. */
1116 void gdb_do_syscall(gdb_syscall_complete_cb cb
, char *fmt
, ...)
1125 s
= gdb_syscall_state
;
1128 gdb_current_syscall_cb
= cb
;
1129 s
->state
= RS_SYSCALL
;
1130 #ifndef CONFIG_USER_ONLY
1131 vm_stop(EXCP_DEBUG
);
1142 addr
= va_arg(va
, target_ulong
);
1143 p
+= sprintf(p
, TARGET_FMT_lx
, addr
);
1146 if (*(fmt
++) != 'x')
1148 i64
= va_arg(va
, uint64_t);
1149 p
+= sprintf(p
, "%" PRIx64
, i64
);
1152 addr
= va_arg(va
, target_ulong
);
1153 p
+= sprintf(p
, TARGET_FMT_lx
"/%x", addr
, va_arg(va
, int));
1157 fprintf(stderr
, "gdbstub: Bad syscall format string '%s'\n",
1168 #ifdef CONFIG_USER_ONLY
1169 gdb_handlesig(s
->env
, 0);
1171 cpu_interrupt(s
->env
, CPU_INTERRUPT_EXIT
);
1175 static void gdb_read_byte(GDBState
*s
, int ch
)
1177 CPUState
*env
= s
->env
;
1181 #ifndef CONFIG_USER_ONLY
1182 if (s
->last_packet_len
) {
1183 /* Waiting for a response to the last packet. If we see the start
1184 of a new command then abandon the previous response. */
1187 printf("Got NACK, retransmitting\n");
1189 put_buffer(s
, s
->last_packet
, s
->last_packet_len
);
1193 printf("Got ACK\n");
1195 printf("Got '%c' when expecting ACK/NACK\n", ch
);
1197 if (ch
== '+' || ch
== '$')
1198 s
->last_packet_len
= 0;
1203 /* when the CPU is running, we cannot do anything except stop
1204 it when receiving a char */
1205 vm_stop(EXCP_INTERRUPT
);
1212 s
->line_buf_index
= 0;
1213 s
->state
= RS_GETLINE
;
1218 s
->state
= RS_CHKSUM1
;
1219 } else if (s
->line_buf_index
>= sizeof(s
->line_buf
) - 1) {
1222 s
->line_buf
[s
->line_buf_index
++] = ch
;
1226 s
->line_buf
[s
->line_buf_index
] = '\0';
1227 s
->line_csum
= fromhex(ch
) << 4;
1228 s
->state
= RS_CHKSUM2
;
1231 s
->line_csum
|= fromhex(ch
);
1233 for(i
= 0; i
< s
->line_buf_index
; i
++) {
1234 csum
+= s
->line_buf
[i
];
1236 if (s
->line_csum
!= (csum
& 0xff)) {
1238 put_buffer(s
, reply
, 1);
1242 put_buffer(s
, reply
, 1);
1243 s
->state
= gdb_handle_packet(s
, env
, s
->line_buf
);
1252 #ifdef CONFIG_USER_ONLY
1254 gdb_handlesig (CPUState
*env
, int sig
)
1260 if (gdbserver_fd
< 0)
1263 s
= &gdbserver_state
;
1265 /* disable single step if it was enabled */
1266 cpu_single_step(env
, 0);
1271 snprintf(buf
, sizeof(buf
), "S%02x", sig
);
1277 s
->running_state
= 0;
1278 while (s
->running_state
== 0) {
1279 n
= read (s
->fd
, buf
, 256);
1284 for (i
= 0; i
< n
; i
++)
1285 gdb_read_byte (s
, buf
[i
]);
1287 else if (n
== 0 || errno
!= EAGAIN
)
1289 /* XXX: Connection closed. Should probably wait for annother
1290 connection before continuing. */
1297 /* Tell the remote gdb that the process has exited. */
1298 void gdb_exit(CPUState
*env
, int code
)
1303 if (gdbserver_fd
< 0)
1306 s
= &gdbserver_state
;
1308 snprintf(buf
, sizeof(buf
), "W%02x", code
);
1313 static void gdb_accept(void *opaque
)
1316 struct sockaddr_in sockaddr
;
1321 len
= sizeof(sockaddr
);
1322 fd
= accept(gdbserver_fd
, (struct sockaddr
*)&sockaddr
, &len
);
1323 if (fd
< 0 && errno
!= EINTR
) {
1326 } else if (fd
>= 0) {
1331 /* set short latency */
1333 setsockopt(fd
, IPPROTO_TCP
, TCP_NODELAY
, (char *)&val
, sizeof(val
));
1335 s
= &gdbserver_state
;
1336 memset (s
, 0, sizeof (GDBState
));
1337 s
->env
= first_cpu
; /* XXX: allow to change CPU */
1340 gdb_syscall_state
= s
;
1342 fcntl(fd
, F_SETFL
, O_NONBLOCK
);
1345 static int gdbserver_open(int port
)
1347 struct sockaddr_in sockaddr
;
1350 fd
= socket(PF_INET
, SOCK_STREAM
, 0);
1356 /* allow fast reuse */
1358 setsockopt(fd
, SOL_SOCKET
, SO_REUSEADDR
, (char *)&val
, sizeof(val
));
1360 sockaddr
.sin_family
= AF_INET
;
1361 sockaddr
.sin_port
= htons(port
);
1362 sockaddr
.sin_addr
.s_addr
= 0;
1363 ret
= bind(fd
, (struct sockaddr
*)&sockaddr
, sizeof(sockaddr
));
1368 ret
= listen(fd
, 0);
1376 int gdbserver_start(int port
)
1378 gdbserver_fd
= gdbserver_open(port
);
1379 if (gdbserver_fd
< 0)
1381 /* accept connections */
1386 static int gdb_chr_can_receive(void *opaque
)
1391 static void gdb_chr_receive(void *opaque
, const uint8_t *buf
, int size
)
1393 GDBState
*s
= opaque
;
1396 for (i
= 0; i
< size
; i
++) {
1397 gdb_read_byte(s
, buf
[i
]);
1401 static void gdb_chr_event(void *opaque
, int event
)
1404 case CHR_EVENT_RESET
:
1405 vm_stop(EXCP_INTERRUPT
);
1406 gdb_syscall_state
= opaque
;
1413 int gdbserver_start(const char *port
)
1416 char gdbstub_port_name
[128];
1419 CharDriverState
*chr
;
1421 if (!port
|| !*port
)
1424 port_num
= strtol(port
, &p
, 10);
1426 /* A numeric value is interpreted as a port number. */
1427 snprintf(gdbstub_port_name
, sizeof(gdbstub_port_name
),
1428 "tcp::%d,nowait,nodelay,server", port_num
);
1429 port
= gdbstub_port_name
;
1432 chr
= qemu_chr_open(port
);
1436 s
= qemu_mallocz(sizeof(GDBState
));
1440 s
->env
= first_cpu
; /* XXX: allow to change CPU */
1442 qemu_chr_add_handlers(chr
, gdb_chr_can_receive
, gdb_chr_receive
,
1444 qemu_add_vm_stop_handler(gdb_vm_stopped
, s
);