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Fix off-by-one in address check.
[qemu/qemu_0_9_1_stable.git] / cpu-exec.c
blobd09b564af408441c9cbcdbc1524e1520a62323b6
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 void cpu_loop_exit(void)
44 {
45 /* NOTE: the register at this point must be saved by hand because
46 longjmp restore them */
47 regs_to_env();
48 longjmp(env->jmp_env, 1);
49 }
50
51 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
52 #define reg_T2
53 #endif
54
55 /* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
57 */
58 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 {
60 #if !defined(CONFIG_SOFTMMU)
61 struct ucontext *uc = puc;
62 #endif
63
64 env = env1;
65
66 /* XXX: restore cpu registers saved in host registers */
67
68 #if !defined(CONFIG_SOFTMMU)
69 if (puc) {
70 /* XXX: use siglongjmp ? */
71 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
72 }
73 #endif
74 longjmp(env->jmp_env, 1);
75 }
76
77
78 static TranslationBlock *tb_find_slow(target_ulong pc,
79 target_ulong cs_base,
80 uint64_t flags)
81 {
82 TranslationBlock *tb, **ptb1;
83 int code_gen_size;
84 unsigned int h;
85 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
86 uint8_t *tc_ptr;
87
88 spin_lock(&tb_lock);
89
90 tb_invalidated_flag = 0;
91
92 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93
94 /* find translated block using physical mappings */
95 phys_pc = get_phys_addr_code(env, pc);
96 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 phys_page2 = -1;
98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
104 if (tb->pc == pc &&
105 tb->page_addr[0] == phys_page1 &&
106 tb->cs_base == cs_base &&
107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
110 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 TARGET_PAGE_SIZE;
112 phys_page2 = get_phys_addr_code(env, virt_page2);
113 if (tb->page_addr[1] == phys_page2)
114 goto found;
115 } else {
116 goto found;
117 }
118 }
119 ptb1 = &tb->phys_hash_next;
120 }
121 not_found:
122 /* if no translated code available, then translate it now */
123 tb = tb_alloc(pc);
124 if (!tb) {
125 /* flush must be done */
126 tb_flush(env);
127 /* cannot fail at this point */
128 tb = tb_alloc(pc);
129 /* don't forget to invalidate previous TB info */
130 tb_invalidated_flag = 1;
131 }
132 tc_ptr = code_gen_ptr;
133 tb->tc_ptr = tc_ptr;
134 tb->cs_base = cs_base;
135 tb->flags = flags;
136 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
137 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138
139 /* check next page if needed */
140 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
143 phys_page2 = get_phys_addr_code(env, virt_page2);
144 }
145 tb_link_phys(tb, phys_pc, phys_page2);
146
147 found:
148 /* we add the TB in the virtual pc hash table */
149 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
150 spin_unlock(&tb_lock);
151 return tb;
152 }
153
154 static inline TranslationBlock *tb_find_fast(void)
155 {
156 TranslationBlock *tb;
157 target_ulong cs_base, pc;
158 uint64_t flags;
159
160 /* we record a subset of the CPU state. It will
161 always be the same before a given translated block
162 is executed. */
163 #if defined(TARGET_I386)
164 flags = env->hflags;
165 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
166 flags |= env->intercept;
167 cs_base = env->segs[R_CS].base;
168 pc = cs_base + env->eip;
169 #elif defined(TARGET_ARM)
170 flags = env->thumb | (env->vfp.vec_len << 1)
171 | (env->vfp.vec_stride << 4);
172 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
173 flags |= (1 << 6);
174 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
175 flags |= (1 << 7);
176 cs_base = 0;
177 pc = env->regs[15];
178 #elif defined(TARGET_SPARC)
179 #ifdef TARGET_SPARC64
180 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
181 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
182 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183 #else
184 // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor
185 flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3)
186 | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
187 | env->psrs;
188 #endif
189 cs_base = env->npc;
190 pc = env->pc;
191 #elif defined(TARGET_PPC)
192 flags = env->hflags;
193 cs_base = 0;
194 pc = env->nip;
195 #elif defined(TARGET_MIPS)
196 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
197 cs_base = 0;
198 pc = env->PC[env->current_tc];
199 #elif defined(TARGET_M68K)
200 flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
201 | (env->sr & SR_S) /* Bit 13 */
202 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
203 cs_base = 0;
204 pc = env->pc;
205 #elif defined(TARGET_SH4)
206 flags = env->sr & (SR_MD | SR_RB);
207 cs_base = 0; /* XXXXX */
208 pc = env->pc;
209 #elif defined(TARGET_ALPHA)
210 flags = env->ps;
211 cs_base = 0;
212 pc = env->pc;
213 #elif defined(TARGET_CRIS)
214 flags = 0;
215 cs_base = 0;
216 pc = env->pc;
217 #else
218 #error unsupported CPU
219 #endif
220 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
221 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
222 tb->flags != flags, 0)) {
223 tb = tb_find_slow(pc, cs_base, flags);
224 /* Note: we do it here to avoid a gcc bug on Mac OS X when
225 doing it in tb_find_slow */
226 if (tb_invalidated_flag) {
227 /* as some TB could have been invalidated because
228 of memory exceptions while generating the code, we
229 must recompute the hash index here */
230 T0 = 0;
231 }
232 }
233 return tb;
234 }
235
236
237 /* main execution loop */
238
239 int cpu_exec(CPUState *env1)
240 {
241 #define DECLARE_HOST_REGS 1
242 #include "hostregs_helper.h"
243 #if defined(TARGET_SPARC)
244 #if defined(reg_REGWPTR)
245 uint32_t *saved_regwptr;
246 #endif
247 #endif
248 #if defined(__sparc__) && !defined(HOST_SOLARIS)
249 int saved_i7;
250 target_ulong tmp_T0;
251 #endif
252 int ret, interrupt_request;
253 void (*gen_func)(void);
254 TranslationBlock *tb;
255 uint8_t *tc_ptr;
256
257 if (cpu_halted(env1) == EXCP_HALTED)
258 return EXCP_HALTED;
259
260 cpu_single_env = env1;
261
262 /* first we save global registers */
263 #define SAVE_HOST_REGS 1
264 #include "hostregs_helper.h"
265 env = env1;
266 #if defined(__sparc__) && !defined(HOST_SOLARIS)
267 /* we also save i7 because longjmp may not restore it */
268 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
269 #endif
270
271 env_to_regs();
272 #if defined(TARGET_I386)
273 /* put eflags in CPU temporary format */
274 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
275 DF = 1 - (2 * ((env->eflags >> 10) & 1));
276 CC_OP = CC_OP_EFLAGS;
277 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
278 #elif defined(TARGET_SPARC)
279 #if defined(reg_REGWPTR)
280 saved_regwptr = REGWPTR;
281 #endif
282 #elif defined(TARGET_M68K)
283 env->cc_op = CC_OP_FLAGS;
284 env->cc_dest = env->sr & 0xf;
285 env->cc_x = (env->sr >> 4) & 1;
286 #elif defined(TARGET_ALPHA)
287 #elif defined(TARGET_ARM)
288 #elif defined(TARGET_PPC)
289 #elif defined(TARGET_MIPS)
290 #elif defined(TARGET_SH4)
291 #elif defined(TARGET_CRIS)
292 /* XXXXX */
293 #else
294 #error unsupported target CPU
295 #endif
296 env->exception_index = -1;
297
298 /* prepare setjmp context for exception handling */
299 for(;;) {
300 if (setjmp(env->jmp_env) == 0) {
301 env->current_tb = NULL;
302 /* if an exception is pending, we execute it here */
303 if (env->exception_index >= 0) {
304 if (env->exception_index >= EXCP_INTERRUPT) {
305 /* exit request from the cpu execution loop */
306 ret = env->exception_index;
307 break;
308 } else if (env->user_mode_only) {
309 /* if user mode only, we simulate a fake exception
310 which will be handled outside the cpu execution
311 loop */
312 #if defined(TARGET_I386)
313 do_interrupt_user(env->exception_index,
314 env->exception_is_int,
315 env->error_code,
316 env->exception_next_eip);
317 #endif
318 ret = env->exception_index;
319 break;
320 } else {
321 #if defined(TARGET_I386)
322 /* simulate a real cpu exception. On i386, it can
323 trigger new exceptions, but we do not handle
324 double or triple faults yet. */
325 do_interrupt(env->exception_index,
326 env->exception_is_int,
327 env->error_code,
328 env->exception_next_eip, 0);
329 /* successfully delivered */
330 env->old_exception = -1;
331 #elif defined(TARGET_PPC)
332 do_interrupt(env);
333 #elif defined(TARGET_MIPS)
334 do_interrupt(env);
335 #elif defined(TARGET_SPARC)
336 do_interrupt(env->exception_index);
337 #elif defined(TARGET_ARM)
338 do_interrupt(env);
339 #elif defined(TARGET_SH4)
340 do_interrupt(env);
341 #elif defined(TARGET_ALPHA)
342 do_interrupt(env);
343 #elif defined(TARGET_CRIS)
344 do_interrupt(env);
345 #elif defined(TARGET_M68K)
346 do_interrupt(0);
347 #endif
348 }
349 env->exception_index = -1;
350 }
351 #ifdef USE_KQEMU
352 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
353 int ret;
354 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
355 ret = kqemu_cpu_exec(env);
356 /* put eflags in CPU temporary format */
357 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
358 DF = 1 - (2 * ((env->eflags >> 10) & 1));
359 CC_OP = CC_OP_EFLAGS;
360 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
361 if (ret == 1) {
362 /* exception */
363 longjmp(env->jmp_env, 1);
364 } else if (ret == 2) {
365 /* softmmu execution needed */
366 } else {
367 if (env->interrupt_request != 0) {
368 /* hardware interrupt will be executed just after */
369 } else {
370 /* otherwise, we restart */
371 longjmp(env->jmp_env, 1);
372 }
373 }
374 }
375 #endif
376
377 T0 = 0; /* force lookup of first TB */
378 for(;;) {
379 #if defined(__sparc__) && !defined(HOST_SOLARIS)
380 /* g1 can be modified by some libc? functions */
381 tmp_T0 = T0;
382 #endif
383 interrupt_request = env->interrupt_request;
384 if (__builtin_expect(interrupt_request, 0)
385 #if defined(TARGET_I386)
386 && env->hflags & HF_GIF_MASK
387 #endif
388 ) {
389 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
390 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
391 env->exception_index = EXCP_DEBUG;
392 cpu_loop_exit();
393 }
394 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
395 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS)
396 if (interrupt_request & CPU_INTERRUPT_HALT) {
397 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
398 env->halted = 1;
399 env->exception_index = EXCP_HLT;
400 cpu_loop_exit();
401 }
402 #endif
403 #if defined(TARGET_I386)
404 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
405 !(env->hflags & HF_SMM_MASK)) {
406 svm_check_intercept(SVM_EXIT_SMI);
407 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
408 do_smm_enter();
409 #if defined(__sparc__) && !defined(HOST_SOLARIS)
410 tmp_T0 = 0;
411 #else
412 T0 = 0;
413 #endif
414 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
415 (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) &&
416 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
417 int intno;
418 svm_check_intercept(SVM_EXIT_INTR);
419 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
420 intno = cpu_get_pic_interrupt(env);
421 if (loglevel & CPU_LOG_TB_IN_ASM) {
422 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
423 }
424 do_interrupt(intno, 0, 0, 0, 1);
425 /* ensure that no TB jump will be modified as
426 the program flow was changed */
427 #if defined(__sparc__) && !defined(HOST_SOLARIS)
428 tmp_T0 = 0;
429 #else
430 T0 = 0;
431 #endif
432 #if !defined(CONFIG_USER_ONLY)
433 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
434 (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
435 int intno;
436 /* FIXME: this should respect TPR */
437 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
438 svm_check_intercept(SVM_EXIT_VINTR);
439 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
440 if (loglevel & CPU_LOG_TB_IN_ASM)
441 fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno);
442 do_interrupt(intno, 0, 0, -1, 1);
443 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
444 ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK);
445 #if defined(__sparc__) && !defined(HOST_SOLARIS)
446 tmp_T0 = 0;
447 #else
448 T0 = 0;
449 #endif
450 #endif
451 }
452 #elif defined(TARGET_PPC)
453 #if 0
454 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
455 cpu_ppc_reset(env);
456 }
457 #endif
458 if (interrupt_request & CPU_INTERRUPT_HARD) {
459 ppc_hw_interrupt(env);
460 if (env->pending_interrupts == 0)
461 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
462 #if defined(__sparc__) && !defined(HOST_SOLARIS)
463 tmp_T0 = 0;
464 #else
465 T0 = 0;
466 #endif
467 }
468 #elif defined(TARGET_MIPS)
469 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
470 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
471 (env->CP0_Status & (1 << CP0St_IE)) &&
472 !(env->CP0_Status & (1 << CP0St_EXL)) &&
473 !(env->CP0_Status & (1 << CP0St_ERL)) &&
474 !(env->hflags & MIPS_HFLAG_DM)) {
475 /* Raise it */
476 env->exception_index = EXCP_EXT_INTERRUPT;
477 env->error_code = 0;
478 do_interrupt(env);
479 #if defined(__sparc__) && !defined(HOST_SOLARIS)
480 tmp_T0 = 0;
481 #else
482 T0 = 0;
483 #endif
484 }
485 #elif defined(TARGET_SPARC)
486 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
487 (env->psret != 0)) {
488 int pil = env->interrupt_index & 15;
489 int type = env->interrupt_index & 0xf0;
490
491 if (((type == TT_EXTINT) &&
492 (pil == 15 || pil > env->psrpil)) ||
493 type != TT_EXTINT) {
494 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
495 do_interrupt(env->interrupt_index);
496 env->interrupt_index = 0;
497 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
498 cpu_check_irqs(env);
499 #endif
500 #if defined(__sparc__) && !defined(HOST_SOLARIS)
501 tmp_T0 = 0;
502 #else
503 T0 = 0;
504 #endif
505 }
506 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
507 //do_interrupt(0, 0, 0, 0, 0);
508 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
509 }
510 #elif defined(TARGET_ARM)
511 if (interrupt_request & CPU_INTERRUPT_FIQ
512 && !(env->uncached_cpsr & CPSR_F)) {
513 env->exception_index = EXCP_FIQ;
514 do_interrupt(env);
515 }
516 if (interrupt_request & CPU_INTERRUPT_HARD
517 && !(env->uncached_cpsr & CPSR_I)) {
518 env->exception_index = EXCP_IRQ;
519 do_interrupt(env);
520 }
521 #elif defined(TARGET_SH4)
522 /* XXXXX */
523 #elif defined(TARGET_ALPHA)
524 if (interrupt_request & CPU_INTERRUPT_HARD) {
525 do_interrupt(env);
526 }
527 #elif defined(TARGET_CRIS)
528 if (interrupt_request & CPU_INTERRUPT_HARD) {
529 do_interrupt(env);
530 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
531 }
532 #elif defined(TARGET_M68K)
533 if (interrupt_request & CPU_INTERRUPT_HARD
534 && ((env->sr & SR_I) >> SR_I_SHIFT)
535 < env->pending_level) {
536 /* Real hardware gets the interrupt vector via an
537 IACK cycle at this point. Current emulated
538 hardware doesn't rely on this, so we
539 provide/save the vector when the interrupt is
540 first signalled. */
541 env->exception_index = env->pending_vector;
542 do_interrupt(1);
543 }
544 #endif
545 /* Don't use the cached interupt_request value,
546 do_interrupt may have updated the EXITTB flag. */
547 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
548 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
549 /* ensure that no TB jump will be modified as
550 the program flow was changed */
551 #if defined(__sparc__) && !defined(HOST_SOLARIS)
552 tmp_T0 = 0;
553 #else
554 T0 = 0;
555 #endif
556 }
557 if (interrupt_request & CPU_INTERRUPT_EXIT) {
558 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
559 env->exception_index = EXCP_INTERRUPT;
560 cpu_loop_exit();
561 }
562 }
563 #ifdef DEBUG_EXEC
564 if ((loglevel & CPU_LOG_TB_CPU)) {
565 /* restore flags in standard format */
566 regs_to_env();
567 #if defined(TARGET_I386)
568 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
569 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
570 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
571 #elif defined(TARGET_ARM)
572 cpu_dump_state(env, logfile, fprintf, 0);
573 #elif defined(TARGET_SPARC)
574 REGWPTR = env->regbase + (env->cwp * 16);
575 env->regwptr = REGWPTR;
576 cpu_dump_state(env, logfile, fprintf, 0);
577 #elif defined(TARGET_PPC)
578 cpu_dump_state(env, logfile, fprintf, 0);
579 #elif defined(TARGET_M68K)
580 cpu_m68k_flush_flags(env, env->cc_op);
581 env->cc_op = CC_OP_FLAGS;
582 env->sr = (env->sr & 0xffe0)
583 | env->cc_dest | (env->cc_x << 4);
584 cpu_dump_state(env, logfile, fprintf, 0);
585 #elif defined(TARGET_MIPS)
586 cpu_dump_state(env, logfile, fprintf, 0);
587 #elif defined(TARGET_SH4)
588 cpu_dump_state(env, logfile, fprintf, 0);
589 #elif defined(TARGET_ALPHA)
590 cpu_dump_state(env, logfile, fprintf, 0);
591 #elif defined(TARGET_CRIS)
592 cpu_dump_state(env, logfile, fprintf, 0);
593 #else
594 #error unsupported target CPU
595 #endif
596 }
597 #endif
598 tb = tb_find_fast();
599 #ifdef DEBUG_EXEC
600 if ((loglevel & CPU_LOG_EXEC)) {
601 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
602 (long)tb->tc_ptr, tb->pc,
603 lookup_symbol(tb->pc));
604 }
605 #endif
606 #if defined(__sparc__) && !defined(HOST_SOLARIS)
607 T0 = tmp_T0;
608 #endif
609 /* see if we can patch the calling TB. When the TB
610 spans two pages, we cannot safely do a direct
611 jump. */
612 {
613 if (T0 != 0 &&
614 #if USE_KQEMU
615 (env->kqemu_enabled != 2) &&
616 #endif
617 tb->page_addr[1] == -1
618 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
619 && (tb->cflags & CF_CODE_COPY) ==
620 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
621 #endif
622 ) {
623 spin_lock(&tb_lock);
624 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
625 #if defined(USE_CODE_COPY)
626 /* propagates the FP use info */
627 ((TranslationBlock *)(T0 & ~3))->cflags |=
628 (tb->cflags & CF_FP_USED);
629 #endif
630 spin_unlock(&tb_lock);
631 }
632 }
633 tc_ptr = tb->tc_ptr;
634 env->current_tb = tb;
635 /* execute the generated code */
636 gen_func = (void *)tc_ptr;
637 #if defined(__sparc__)
638 __asm__ __volatile__("call %0\n\t"
639 "mov %%o7,%%i0"
640 : /* no outputs */
641 : "r" (gen_func)
642 : "i0", "i1", "i2", "i3", "i4", "i5",
643 "o0", "o1", "o2", "o3", "o4", "o5",
644 "l0", "l1", "l2", "l3", "l4", "l5",
645 "l6", "l7");
646 #elif defined(__arm__)
647 asm volatile ("mov pc, %0\n\t"
648 ".global exec_loop\n\t"
649 "exec_loop:\n\t"
650 : /* no outputs */
651 : "r" (gen_func)
652 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
653 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
654 {
655 if (!(tb->cflags & CF_CODE_COPY)) {
656 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
657 save_native_fp_state(env);
658 }
659 gen_func();
660 } else {
661 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
662 restore_native_fp_state(env);
663 }
664 /* we work with native eflags */
665 CC_SRC = cc_table[CC_OP].compute_all();
666 CC_OP = CC_OP_EFLAGS;
667 asm(".globl exec_loop\n"
668 "\n"
669 "debug1:\n"
670 " pushl %%ebp\n"
671 " fs movl %10, %9\n"
672 " fs movl %11, %%eax\n"
673 " andl $0x400, %%eax\n"
674 " fs orl %8, %%eax\n"
675 " pushl %%eax\n"
676 " popf\n"
677 " fs movl %%esp, %12\n"
678 " fs movl %0, %%eax\n"
679 " fs movl %1, %%ecx\n"
680 " fs movl %2, %%edx\n"
681 " fs movl %3, %%ebx\n"
682 " fs movl %4, %%esp\n"
683 " fs movl %5, %%ebp\n"
684 " fs movl %6, %%esi\n"
685 " fs movl %7, %%edi\n"
686 " fs jmp *%9\n"
687 "exec_loop:\n"
688 " fs movl %%esp, %4\n"
689 " fs movl %12, %%esp\n"
690 " fs movl %%eax, %0\n"
691 " fs movl %%ecx, %1\n"
692 " fs movl %%edx, %2\n"
693 " fs movl %%ebx, %3\n"
694 " fs movl %%ebp, %5\n"
695 " fs movl %%esi, %6\n"
696 " fs movl %%edi, %7\n"
697 " pushf\n"
698 " popl %%eax\n"
699 " movl %%eax, %%ecx\n"
700 " andl $0x400, %%ecx\n"
701 " shrl $9, %%ecx\n"
702 " andl $0x8d5, %%eax\n"
703 " fs movl %%eax, %8\n"
704 " movl $1, %%eax\n"
705 " subl %%ecx, %%eax\n"
706 " fs movl %%eax, %11\n"
707 " fs movl %9, %%ebx\n" /* get T0 value */
708 " popl %%ebp\n"
709 :
710 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
711 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
712 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
713 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
714 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
715 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
716 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
717 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
718 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
719 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
720 "a" (gen_func),
721 "m" (*(uint8_t *)offsetof(CPUState, df)),
722 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
723 : "%ecx", "%edx"
724 );
725 }
726 }
727 #elif defined(__ia64)
728 struct fptr {
729 void *ip;
730 void *gp;
731 } fp;
732
733 fp.ip = tc_ptr;
734 fp.gp = code_gen_buffer + 2 * (1 << 20);
735 (*(void (*)(void)) &fp)();
736 #else
737 gen_func();
738 #endif
739 env->current_tb = NULL;
740 /* reset soft MMU for next block (it can currently
741 only be set by a memory fault) */
742 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
743 if (env->hflags & HF_SOFTMMU_MASK) {
744 env->hflags &= ~HF_SOFTMMU_MASK;
745 /* do not allow linking to another block */
746 T0 = 0;
747 }
748 #endif
749 #if defined(USE_KQEMU)
750 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
751 if (kqemu_is_ok(env) &&
752 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
753 cpu_loop_exit();
754 }
755 #endif
756 } /* for(;;) */
757 } else {
758 env_to_regs();
759 }
760 } /* for(;;) */
761
762
763 #if defined(TARGET_I386)
764 #if defined(USE_CODE_COPY)
765 if (env->native_fp_regs) {
766 save_native_fp_state(env);
767 }
768 #endif
769 /* restore flags in standard format */
770 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
771 #elif defined(TARGET_ARM)
772 /* XXX: Save/restore host fpu exception state?. */
773 #elif defined(TARGET_SPARC)
774 #if defined(reg_REGWPTR)
775 REGWPTR = saved_regwptr;
776 #endif
777 #elif defined(TARGET_PPC)
778 #elif defined(TARGET_M68K)
779 cpu_m68k_flush_flags(env, env->cc_op);
780 env->cc_op = CC_OP_FLAGS;
781 env->sr = (env->sr & 0xffe0)
782 | env->cc_dest | (env->cc_x << 4);
783 #elif defined(TARGET_MIPS)
784 #elif defined(TARGET_SH4)
785 #elif defined(TARGET_ALPHA)
786 #elif defined(TARGET_CRIS)
787 /* XXXXX */
788 #else
789 #error unsupported target CPU
790 #endif
791
792 /* restore global registers */
793 #if defined(__sparc__) && !defined(HOST_SOLARIS)
794 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
795 #endif
796 #include "hostregs_helper.h"
797
798 /* fail safe : never use cpu_single_env outside cpu_exec() */
799 cpu_single_env = NULL;
800 return ret;
801 }
802
803 /* must only be called from the generated code as an exception can be
804 generated */
805 void tb_invalidate_page_range(target_ulong start, target_ulong end)
806 {
807 /* XXX: cannot enable it yet because it yields to MMU exception
808 where NIP != read address on PowerPC */
809 #if 0
810 target_ulong phys_addr;
811 phys_addr = get_phys_addr_code(env, start);
812 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
813 #endif
814 }
815
816 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
817
818 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
819 {
820 CPUX86State *saved_env;
821
822 saved_env = env;
823 env = s;
824 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
825 selector &= 0xffff;
826 cpu_x86_load_seg_cache(env, seg_reg, selector,
827 (selector << 4), 0xffff, 0);
828 } else {
829 load_seg(seg_reg, selector);
830 }
831 env = saved_env;
832 }
833
834 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
835 {
836 CPUX86State *saved_env;
837
838 saved_env = env;
839 env = s;
840
841 helper_fsave((target_ulong)ptr, data32);
842
843 env = saved_env;
844 }
845
846 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
847 {
848 CPUX86State *saved_env;
849
850 saved_env = env;
851 env = s;
852
853 helper_frstor((target_ulong)ptr, data32);
854
855 env = saved_env;
856 }
857
858 #endif /* TARGET_I386 */
859
860 #if !defined(CONFIG_SOFTMMU)
861
862 #if defined(TARGET_I386)
863
864 /* 'pc' is the host PC at which the exception was raised. 'address' is
865 the effective address of the memory exception. 'is_write' is 1 if a
866 write caused the exception and otherwise 0'. 'old_set' is the
867 signal set which should be restored */
868 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
869 int is_write, sigset_t *old_set,
870 void *puc)
871 {
872 TranslationBlock *tb;
873 int ret;
874
875 if (cpu_single_env)
876 env = cpu_single_env; /* XXX: find a correct solution for multithread */
877 #if defined(DEBUG_SIGNAL)
878 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
879 pc, address, is_write, *(unsigned long *)old_set);
880 #endif
881 /* XXX: locking issue */
882 if (is_write && page_unprotect(h2g(address), pc, puc)) {
883 return 1;
884 }
885
886 /* see if it is an MMU fault */
887 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
888 ((env->hflags & HF_CPL_MASK) == 3), 0);
889 if (ret < 0)
890 return 0; /* not an MMU fault */
891 if (ret == 0)
892 return 1; /* the MMU fault was handled without causing real CPU fault */
893 /* now we have a real cpu fault */
894 tb = tb_find_pc(pc);
895 if (tb) {
896 /* the PC is inside the translated code. It means that we have
897 a virtual CPU fault */
898 cpu_restore_state(tb, env, pc, puc);
899 }
900 if (ret == 1) {
901 #if 0
902 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
903 env->eip, env->cr[2], env->error_code);
904 #endif
905 /* we restore the process signal mask as the sigreturn should
906 do it (XXX: use sigsetjmp) */
907 sigprocmask(SIG_SETMASK, old_set, NULL);
908 raise_exception_err(env->exception_index, env->error_code);
909 } else {
910 /* activate soft MMU for this block */
911 env->hflags |= HF_SOFTMMU_MASK;
912 cpu_resume_from_signal(env, puc);
913 }
914 /* never comes here */
915 return 1;
916 }
917
918 #elif defined(TARGET_ARM)
919 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
920 int is_write, sigset_t *old_set,
921 void *puc)
922 {
923 TranslationBlock *tb;
924 int ret;
925
926 if (cpu_single_env)
927 env = cpu_single_env; /* XXX: find a correct solution for multithread */
928 #if defined(DEBUG_SIGNAL)
929 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
930 pc, address, is_write, *(unsigned long *)old_set);
931 #endif
932 /* XXX: locking issue */
933 if (is_write && page_unprotect(h2g(address), pc, puc)) {
934 return 1;
935 }
936 /* see if it is an MMU fault */
937 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
938 if (ret < 0)
939 return 0; /* not an MMU fault */
940 if (ret == 0)
941 return 1; /* the MMU fault was handled without causing real CPU fault */
942 /* now we have a real cpu fault */
943 tb = tb_find_pc(pc);
944 if (tb) {
945 /* the PC is inside the translated code. It means that we have
946 a virtual CPU fault */
947 cpu_restore_state(tb, env, pc, puc);
948 }
949 /* we restore the process signal mask as the sigreturn should
950 do it (XXX: use sigsetjmp) */
951 sigprocmask(SIG_SETMASK, old_set, NULL);
952 cpu_loop_exit();
953 }
954 #elif defined(TARGET_SPARC)
955 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
956 int is_write, sigset_t *old_set,
957 void *puc)
958 {
959 TranslationBlock *tb;
960 int ret;
961
962 if (cpu_single_env)
963 env = cpu_single_env; /* XXX: find a correct solution for multithread */
964 #if defined(DEBUG_SIGNAL)
965 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
966 pc, address, is_write, *(unsigned long *)old_set);
967 #endif
968 /* XXX: locking issue */
969 if (is_write && page_unprotect(h2g(address), pc, puc)) {
970 return 1;
971 }
972 /* see if it is an MMU fault */
973 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
974 if (ret < 0)
975 return 0; /* not an MMU fault */
976 if (ret == 0)
977 return 1; /* the MMU fault was handled without causing real CPU fault */
978 /* now we have a real cpu fault */
979 tb = tb_find_pc(pc);
980 if (tb) {
981 /* the PC is inside the translated code. It means that we have
982 a virtual CPU fault */
983 cpu_restore_state(tb, env, pc, puc);
984 }
985 /* we restore the process signal mask as the sigreturn should
986 do it (XXX: use sigsetjmp) */
987 sigprocmask(SIG_SETMASK, old_set, NULL);
988 cpu_loop_exit();
989 }
990 #elif defined (TARGET_PPC)
991 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
992 int is_write, sigset_t *old_set,
993 void *puc)
994 {
995 TranslationBlock *tb;
996 int ret;
997
998 if (cpu_single_env)
999 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1000 #if defined(DEBUG_SIGNAL)
1001 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1002 pc, address, is_write, *(unsigned long *)old_set);
1003 #endif
1004 /* XXX: locking issue */
1005 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1006 return 1;
1007 }
1008
1009 /* see if it is an MMU fault */
1010 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1011 if (ret < 0)
1012 return 0; /* not an MMU fault */
1013 if (ret == 0)
1014 return 1; /* the MMU fault was handled without causing real CPU fault */
1015
1016 /* now we have a real cpu fault */
1017 tb = tb_find_pc(pc);
1018 if (tb) {
1019 /* the PC is inside the translated code. It means that we have
1020 a virtual CPU fault */
1021 cpu_restore_state(tb, env, pc, puc);
1022 }
1023 if (ret == 1) {
1024 #if 0
1025 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1026 env->nip, env->error_code, tb);
1027 #endif
1028 /* we restore the process signal mask as the sigreturn should
1029 do it (XXX: use sigsetjmp) */
1030 sigprocmask(SIG_SETMASK, old_set, NULL);
1031 do_raise_exception_err(env->exception_index, env->error_code);
1032 } else {
1033 /* activate soft MMU for this block */
1034 cpu_resume_from_signal(env, puc);
1035 }
1036 /* never comes here */
1037 return 1;
1038 }
1039
1040 #elif defined(TARGET_M68K)
1041 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1042 int is_write, sigset_t *old_set,
1043 void *puc)
1044 {
1045 TranslationBlock *tb;
1046 int ret;
1047
1048 if (cpu_single_env)
1049 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1050 #if defined(DEBUG_SIGNAL)
1051 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1052 pc, address, is_write, *(unsigned long *)old_set);
1053 #endif
1054 /* XXX: locking issue */
1055 if (is_write && page_unprotect(address, pc, puc)) {
1056 return 1;
1057 }
1058 /* see if it is an MMU fault */
1059 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1060 if (ret < 0)
1061 return 0; /* not an MMU fault */
1062 if (ret == 0)
1063 return 1; /* the MMU fault was handled without causing real CPU fault */
1064 /* now we have a real cpu fault */
1065 tb = tb_find_pc(pc);
1066 if (tb) {
1067 /* the PC is inside the translated code. It means that we have
1068 a virtual CPU fault */
1069 cpu_restore_state(tb, env, pc, puc);
1070 }
1071 /* we restore the process signal mask as the sigreturn should
1072 do it (XXX: use sigsetjmp) */
1073 sigprocmask(SIG_SETMASK, old_set, NULL);
1074 cpu_loop_exit();
1075 /* never comes here */
1076 return 1;
1077 }
1078
1079 #elif defined (TARGET_MIPS)
1080 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1081 int is_write, sigset_t *old_set,
1082 void *puc)
1083 {
1084 TranslationBlock *tb;
1085 int ret;
1086
1087 if (cpu_single_env)
1088 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1089 #if defined(DEBUG_SIGNAL)
1090 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1091 pc, address, is_write, *(unsigned long *)old_set);
1092 #endif
1093 /* XXX: locking issue */
1094 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1095 return 1;
1096 }
1097
1098 /* see if it is an MMU fault */
1099 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1100 if (ret < 0)
1101 return 0; /* not an MMU fault */
1102 if (ret == 0)
1103 return 1; /* the MMU fault was handled without causing real CPU fault */
1104
1105 /* now we have a real cpu fault */
1106 tb = tb_find_pc(pc);
1107 if (tb) {
1108 /* the PC is inside the translated code. It means that we have
1109 a virtual CPU fault */
1110 cpu_restore_state(tb, env, pc, puc);
1111 }
1112 if (ret == 1) {
1113 #if 0
1114 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1115 env->PC, env->error_code, tb);
1116 #endif
1117 /* we restore the process signal mask as the sigreturn should
1118 do it (XXX: use sigsetjmp) */
1119 sigprocmask(SIG_SETMASK, old_set, NULL);
1120 do_raise_exception_err(env->exception_index, env->error_code);
1121 } else {
1122 /* activate soft MMU for this block */
1123 cpu_resume_from_signal(env, puc);
1124 }
1125 /* never comes here */
1126 return 1;
1127 }
1128
1129 #elif defined (TARGET_SH4)
1130 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1131 int is_write, sigset_t *old_set,
1132 void *puc)
1133 {
1134 TranslationBlock *tb;
1135 int ret;
1136
1137 if (cpu_single_env)
1138 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1139 #if defined(DEBUG_SIGNAL)
1140 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1141 pc, address, is_write, *(unsigned long *)old_set);
1142 #endif
1143 /* XXX: locking issue */
1144 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1145 return 1;
1146 }
1147
1148 /* see if it is an MMU fault */
1149 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1150 if (ret < 0)
1151 return 0; /* not an MMU fault */
1152 if (ret == 0)
1153 return 1; /* the MMU fault was handled without causing real CPU fault */
1154
1155 /* now we have a real cpu fault */
1156 tb = tb_find_pc(pc);
1157 if (tb) {
1158 /* the PC is inside the translated code. It means that we have
1159 a virtual CPU fault */
1160 cpu_restore_state(tb, env, pc, puc);
1161 }
1162 #if 0
1163 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1164 env->nip, env->error_code, tb);
1165 #endif
1166 /* we restore the process signal mask as the sigreturn should
1167 do it (XXX: use sigsetjmp) */
1168 sigprocmask(SIG_SETMASK, old_set, NULL);
1169 cpu_loop_exit();
1170 /* never comes here */
1171 return 1;
1172 }
1173
1174 #elif defined (TARGET_ALPHA)
1175 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1176 int is_write, sigset_t *old_set,
1177 void *puc)
1178 {
1179 TranslationBlock *tb;
1180 int ret;
1181
1182 if (cpu_single_env)
1183 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1184 #if defined(DEBUG_SIGNAL)
1185 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1186 pc, address, is_write, *(unsigned long *)old_set);
1187 #endif
1188 /* XXX: locking issue */
1189 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1190 return 1;
1191 }
1192
1193 /* see if it is an MMU fault */
1194 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0);
1195 if (ret < 0)
1196 return 0; /* not an MMU fault */
1197 if (ret == 0)
1198 return 1; /* the MMU fault was handled without causing real CPU fault */
1199
1200 /* now we have a real cpu fault */
1201 tb = tb_find_pc(pc);
1202 if (tb) {
1203 /* the PC is inside the translated code. It means that we have
1204 a virtual CPU fault */
1205 cpu_restore_state(tb, env, pc, puc);
1206 }
1207 #if 0
1208 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1209 env->nip, env->error_code, tb);
1210 #endif
1211 /* we restore the process signal mask as the sigreturn should
1212 do it (XXX: use sigsetjmp) */
1213 sigprocmask(SIG_SETMASK, old_set, NULL);
1214 cpu_loop_exit();
1215 /* never comes here */
1216 return 1;
1217 }
1218 #elif defined (TARGET_CRIS)
1219 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1220 int is_write, sigset_t *old_set,
1221 void *puc)
1222 {
1223 TranslationBlock *tb;
1224 int ret;
1225
1226 if (cpu_single_env)
1227 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1228 #if defined(DEBUG_SIGNAL)
1229 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1230 pc, address, is_write, *(unsigned long *)old_set);
1231 #endif
1232 /* XXX: locking issue */
1233 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1234 return 1;
1235 }
1236
1237 /* see if it is an MMU fault */
1238 ret = cpu_cris_handle_mmu_fault(env, address, is_write, 1, 0);
1239 if (ret < 0)
1240 return 0; /* not an MMU fault */
1241 if (ret == 0)
1242 return 1; /* the MMU fault was handled without causing real CPU fault */
1243
1244 /* now we have a real cpu fault */
1245 tb = tb_find_pc(pc);
1246 if (tb) {
1247 /* the PC is inside the translated code. It means that we have
1248 a virtual CPU fault */
1249 cpu_restore_state(tb, env, pc, puc);
1250 }
1251 #if 0
1252 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1253 env->nip, env->error_code, tb);
1254 #endif
1255 /* we restore the process signal mask as the sigreturn should
1256 do it (XXX: use sigsetjmp) */
1257 sigprocmask(SIG_SETMASK, old_set, NULL);
1258 cpu_loop_exit();
1259 /* never comes here */
1260 return 1;
1261 }
1262
1263 #else
1264 #error unsupported target CPU
1265 #endif
1266
1267 #if defined(__i386__)
1268
1269 #if defined(__APPLE__)
1270 # include <sys/ucontext.h>
1271
1272 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1273 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1274 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1275 #else
1276 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1277 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1278 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1279 #endif
1280
1281 #if defined(USE_CODE_COPY)
1282 static void cpu_send_trap(unsigned long pc, int trap,
1283 struct ucontext *uc)
1284 {
1285 TranslationBlock *tb;
1286
1287 if (cpu_single_env)
1288 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1289 /* now we have a real cpu fault */
1290 tb = tb_find_pc(pc);
1291 if (tb) {
1292 /* the PC is inside the translated code. It means that we have
1293 a virtual CPU fault */
1294 cpu_restore_state(tb, env, pc, uc);
1295 }
1296 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1297 raise_exception_err(trap, env->error_code);
1298 }
1299 #endif
1300
1301 int cpu_signal_handler(int host_signum, void *pinfo,
1302 void *puc)
1303 {
1304 siginfo_t *info = pinfo;
1305 struct ucontext *uc = puc;
1306 unsigned long pc;
1307 int trapno;
1308
1309 #ifndef REG_EIP
1310 /* for glibc 2.1 */
1311 #define REG_EIP EIP
1312 #define REG_ERR ERR
1313 #define REG_TRAPNO TRAPNO
1314 #endif
1315 pc = EIP_sig(uc);
1316 trapno = TRAP_sig(uc);
1317 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1318 if (trapno == 0x00 || trapno == 0x05) {
1319 /* send division by zero or bound exception */
1320 cpu_send_trap(pc, trapno, uc);
1321 return 1;
1322 } else
1323 #endif
1324 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1325 trapno == 0xe ?
1326 (ERROR_sig(uc) >> 1) & 1 : 0,
1327 &uc->uc_sigmask, puc);
1328 }
1329
1330 #elif defined(__x86_64__)
1331
1332 int cpu_signal_handler(int host_signum, void *pinfo,
1333 void *puc)
1334 {
1335 siginfo_t *info = pinfo;
1336 struct ucontext *uc = puc;
1337 unsigned long pc;
1338
1339 pc = uc->uc_mcontext.gregs[REG_RIP];
1340 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1341 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1342 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1343 &uc->uc_sigmask, puc);
1344 }
1345
1346 #elif defined(__powerpc__)
1347
1348 /***********************************************************************
1349 * signal context platform-specific definitions
1350 * From Wine
1351 */
1352 #ifdef linux
1353 /* All Registers access - only for local access */
1354 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1355 /* Gpr Registers access */
1356 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1357 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1358 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1359 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1360 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1361 # define LR_sig(context) REG_sig(link, context) /* Link register */
1362 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1363 /* Float Registers access */
1364 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1365 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1366 /* Exception Registers access */
1367 # define DAR_sig(context) REG_sig(dar, context)
1368 # define DSISR_sig(context) REG_sig(dsisr, context)
1369 # define TRAP_sig(context) REG_sig(trap, context)
1370 #endif /* linux */
1371
1372 #ifdef __APPLE__
1373 # include <sys/ucontext.h>
1374 typedef struct ucontext SIGCONTEXT;
1375 /* All Registers access - only for local access */
1376 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1377 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1378 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1379 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1380 /* Gpr Registers access */
1381 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1382 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1383 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1384 # define CTR_sig(context) REG_sig(ctr, context)
1385 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1386 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1387 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1388 /* Float Registers access */
1389 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1390 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1391 /* Exception Registers access */
1392 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1393 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1394 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1395 #endif /* __APPLE__ */
1396
1397 int cpu_signal_handler(int host_signum, void *pinfo,
1398 void *puc)
1399 {
1400 siginfo_t *info = pinfo;
1401 struct ucontext *uc = puc;
1402 unsigned long pc;
1403 int is_write;
1404
1405 pc = IAR_sig(uc);
1406 is_write = 0;
1407 #if 0
1408 /* ppc 4xx case */
1409 if (DSISR_sig(uc) & 0x00800000)
1410 is_write = 1;
1411 #else
1412 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1413 is_write = 1;
1414 #endif
1415 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1416 is_write, &uc->uc_sigmask, puc);
1417 }
1418
1419 #elif defined(__alpha__)
1420
1421 int cpu_signal_handler(int host_signum, void *pinfo,
1422 void *puc)
1423 {
1424 siginfo_t *info = pinfo;
1425 struct ucontext *uc = puc;
1426 uint32_t *pc = uc->uc_mcontext.sc_pc;
1427 uint32_t insn = *pc;
1428 int is_write = 0;
1429
1430 /* XXX: need kernel patch to get write flag faster */
1431 switch (insn >> 26) {
1432 case 0x0d: // stw
1433 case 0x0e: // stb
1434 case 0x0f: // stq_u
1435 case 0x24: // stf
1436 case 0x25: // stg
1437 case 0x26: // sts
1438 case 0x27: // stt
1439 case 0x2c: // stl
1440 case 0x2d: // stq
1441 case 0x2e: // stl_c
1442 case 0x2f: // stq_c
1443 is_write = 1;
1444 }
1445
1446 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1447 is_write, &uc->uc_sigmask, puc);
1448 }
1449 #elif defined(__sparc__)
1450
1451 int cpu_signal_handler(int host_signum, void *pinfo,
1452 void *puc)
1453 {
1454 siginfo_t *info = pinfo;
1455 uint32_t *regs = (uint32_t *)(info + 1);
1456 void *sigmask = (regs + 20);
1457 unsigned long pc;
1458 int is_write;
1459 uint32_t insn;
1460
1461 /* XXX: is there a standard glibc define ? */
1462 pc = regs[1];
1463 /* XXX: need kernel patch to get write flag faster */
1464 is_write = 0;
1465 insn = *(uint32_t *)pc;
1466 if ((insn >> 30) == 3) {
1467 switch((insn >> 19) & 0x3f) {
1468 case 0x05: // stb
1469 case 0x06: // sth
1470 case 0x04: // st
1471 case 0x07: // std
1472 case 0x24: // stf
1473 case 0x27: // stdf
1474 case 0x25: // stfsr
1475 is_write = 1;
1476 break;
1477 }
1478 }
1479 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1480 is_write, sigmask, NULL);
1481 }
1482
1483 #elif defined(__arm__)
1484
1485 int cpu_signal_handler(int host_signum, void *pinfo,
1486 void *puc)
1487 {
1488 siginfo_t *info = pinfo;
1489 struct ucontext *uc = puc;
1490 unsigned long pc;
1491 int is_write;
1492
1493 pc = uc->uc_mcontext.gregs[R15];
1494 /* XXX: compute is_write */
1495 is_write = 0;
1496 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1497 is_write,
1498 &uc->uc_sigmask, puc);
1499 }
1500
1501 #elif defined(__mc68000)
1502
1503 int cpu_signal_handler(int host_signum, void *pinfo,
1504 void *puc)
1505 {
1506 siginfo_t *info = pinfo;
1507 struct ucontext *uc = puc;
1508 unsigned long pc;
1509 int is_write;
1510
1511 pc = uc->uc_mcontext.gregs[16];
1512 /* XXX: compute is_write */
1513 is_write = 0;
1514 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1515 is_write,
1516 &uc->uc_sigmask, puc);
1517 }
1518
1519 #elif defined(__ia64)
1520
1521 #ifndef __ISR_VALID
1522 /* This ought to be in <bits/siginfo.h>... */
1523 # define __ISR_VALID 1
1524 #endif
1525
1526 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1527 {
1528 siginfo_t *info = pinfo;
1529 struct ucontext *uc = puc;
1530 unsigned long ip;
1531 int is_write = 0;
1532
1533 ip = uc->uc_mcontext.sc_ip;
1534 switch (host_signum) {
1535 case SIGILL:
1536 case SIGFPE:
1537 case SIGSEGV:
1538 case SIGBUS:
1539 case SIGTRAP:
1540 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1541 /* ISR.W (write-access) is bit 33: */
1542 is_write = (info->si_isr >> 33) & 1;
1543 break;
1544
1545 default:
1546 break;
1547 }
1548 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1549 is_write,
1550 &uc->uc_sigmask, puc);
1551 }
1552
1553 #elif defined(__s390__)
1554
1555 int cpu_signal_handler(int host_signum, void *pinfo,
1556 void *puc)
1557 {
1558 siginfo_t *info = pinfo;
1559 struct ucontext *uc = puc;
1560 unsigned long pc;
1561 int is_write;
1562
1563 pc = uc->uc_mcontext.psw.addr;
1564 /* XXX: compute is_write */
1565 is_write = 0;
1566 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1567 is_write, &uc->uc_sigmask, puc);
1568 }
1569
1570 #elif defined(__mips__)
1571
1572 int cpu_signal_handler(int host_signum, void *pinfo,
1573 void *puc)
1574 {
1575 siginfo_t *info = pinfo;
1576 struct ucontext *uc = puc;
1577 greg_t pc = uc->uc_mcontext.pc;
1578 int is_write;
1579
1580 /* XXX: compute is_write */
1581 is_write = 0;
1582 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1583 is_write, &uc->uc_sigmask, puc);
1584 }
1585
1586 #else
1587
1588 #error host CPU specific signal handler needed
1589
1590 #endif
1591
1592 #endif /* !defined(CONFIG_SOFTMMU) */
Stable branch of Qemu 0.9.1