2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag
;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) || \
45 /* XXX: unify with i386 target */
46 void cpu_loop_exit(void)
48 longjmp(env
->jmp_env
, 1);
51 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
55 /* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
58 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
60 #if !defined(CONFIG_SOFTMMU)
61 struct ucontext
*uc
= puc
;
66 /* XXX: restore cpu registers saved in host registers */
68 #if !defined(CONFIG_SOFTMMU)
70 /* XXX: use siglongjmp ? */
71 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
74 longjmp(env
->jmp_env
, 1);
78 static TranslationBlock
*tb_find_slow(target_ulong pc
,
82 TranslationBlock
*tb
, **ptb1
;
85 target_ulong phys_pc
, phys_page1
, phys_page2
, virt_page2
;
90 tb_invalidated_flag
= 0;
92 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
94 /* find translated block using physical mappings */
95 phys_pc
= get_phys_addr_code(env
, pc
);
96 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
98 h
= tb_phys_hash_func(phys_pc
);
99 ptb1
= &tb_phys_hash
[h
];
105 tb
->page_addr
[0] == phys_page1
&&
106 tb
->cs_base
== cs_base
&&
107 tb
->flags
== flags
) {
108 /* check next page if needed */
109 if (tb
->page_addr
[1] != -1) {
110 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
112 phys_page2
= get_phys_addr_code(env
, virt_page2
);
113 if (tb
->page_addr
[1] == phys_page2
)
119 ptb1
= &tb
->phys_hash_next
;
122 /* if no translated code available, then translate it now */
125 /* flush must be done */
127 /* cannot fail at this point */
129 /* don't forget to invalidate previous TB info */
130 tb_invalidated_flag
= 1;
132 tc_ptr
= code_gen_ptr
;
134 tb
->cs_base
= cs_base
;
136 cpu_gen_code(env
, tb
, CODE_GEN_MAX_SIZE
, &code_gen_size
);
137 code_gen_ptr
= (void *)(((unsigned long)code_gen_ptr
+ code_gen_size
+ CODE_GEN_ALIGN
- 1) & ~(CODE_GEN_ALIGN
- 1));
139 /* check next page if needed */
140 virt_page2
= (pc
+ tb
->size
- 1) & TARGET_PAGE_MASK
;
142 if ((pc
& TARGET_PAGE_MASK
) != virt_page2
) {
143 phys_page2
= get_phys_addr_code(env
, virt_page2
);
145 tb_link_phys(tb
, phys_pc
, phys_page2
);
148 /* we add the TB in the virtual pc hash table */
149 env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)] = tb
;
150 spin_unlock(&tb_lock
);
154 static inline TranslationBlock
*tb_find_fast(void)
156 TranslationBlock
*tb
;
157 target_ulong cs_base
, pc
;
160 /* we record a subset of the CPU state. It will
161 always be the same before a given translated block
163 #if defined(TARGET_I386)
165 flags
|= (env
->eflags
& (IOPL_MASK
| TF_MASK
| VM_MASK
));
166 cs_base
= env
->segs
[R_CS
].base
;
167 pc
= cs_base
+ env
->eip
;
168 #elif defined(TARGET_ARM)
169 flags
= env
->thumb
| (env
->vfp
.vec_len
<< 1)
170 | (env
->vfp
.vec_stride
<< 4);
171 if ((env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
)
173 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30))
177 #elif defined(TARGET_SPARC)
178 #ifdef TARGET_SPARC64
179 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
180 flags
= (((env
->pstate
& PS_PEF
) >> 1) | ((env
->fprs
& FPRS_FEF
) << 2))
181 | (env
->pstate
& PS_PRIV
) | ((env
->lsu
& (DMMU_E
| IMMU_E
)) >> 2);
183 // FPU enable . MMU enabled . MMU no-fault . Supervisor
184 flags
= (env
->psref
<< 3) | ((env
->mmuregs
[0] & (MMU_E
| MMU_NF
)) << 1)
189 #elif defined(TARGET_PPC)
190 flags
= (msr_pr
<< MSR_PR
) | (msr_fp
<< MSR_FP
) |
191 (msr_se
<< MSR_SE
) | (msr_le
<< MSR_LE
);
194 #elif defined(TARGET_MIPS)
195 flags
= env
->hflags
& (MIPS_HFLAG_TMASK
| MIPS_HFLAG_BMASK
);
198 #elif defined(TARGET_M68K)
199 flags
= env
->fpcr
& M68K_FPCR_PREC
;
202 #elif defined(TARGET_SH4)
203 flags
= env
->sr
& (SR_MD
| SR_RB
);
204 cs_base
= 0; /* XXXXX */
206 #elif defined(TARGET_ALPHA)
211 #error unsupported CPU
213 tb
= env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)];
214 if (__builtin_expect(!tb
|| tb
->pc
!= pc
|| tb
->cs_base
!= cs_base
||
215 tb
->flags
!= flags
, 0)) {
216 tb
= tb_find_slow(pc
, cs_base
, flags
);
217 /* Note: we do it here to avoid a gcc bug on Mac OS X when
218 doing it in tb_find_slow */
219 if (tb_invalidated_flag
) {
220 /* as some TB could have been invalidated because
221 of memory exceptions while generating the code, we
222 must recompute the hash index here */
230 /* main execution loop */
232 int cpu_exec(CPUState
*env1
)
234 #define DECLARE_HOST_REGS 1
235 #include "hostregs_helper.h"
236 #if defined(TARGET_SPARC)
237 #if defined(reg_REGWPTR)
238 uint32_t *saved_regwptr
;
241 #if defined(__sparc__) && !defined(HOST_SOLARIS)
245 int ret
, interrupt_request
;
246 void (*gen_func
)(void);
247 TranslationBlock
*tb
;
250 #if defined(TARGET_I386)
251 /* handle exit of HALTED state */
252 if (env1
->hflags
& HF_HALTED_MASK
) {
253 /* disable halt condition */
254 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
255 (env1
->eflags
& IF_MASK
)) {
256 env1
->hflags
&= ~HF_HALTED_MASK
;
261 #elif defined(TARGET_PPC)
263 if (env1
->msr
[MSR_EE
] &&
264 (env1
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
270 #elif defined(TARGET_SPARC)
272 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
273 (env1
->psret
!= 0)) {
279 #elif defined(TARGET_ARM)
281 /* An interrupt wakes the CPU even if the I and F CPSR bits are
282 set. We use EXITTB to silently wake CPU without causing an
284 if (env1
->interrupt_request
&
285 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
| CPU_INTERRUPT_EXITTB
)) {
291 #elif defined(TARGET_MIPS)
293 if (env1
->interrupt_request
&
294 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
)) {
300 #elif defined(TARGET_ALPHA)
302 if (env1
->interrupt_request
& CPU_INTERRUPT_HARD
) {
310 cpu_single_env
= env1
;
312 /* first we save global registers */
313 #define SAVE_HOST_REGS 1
314 #include "hostregs_helper.h"
316 #if defined(__sparc__) && !defined(HOST_SOLARIS)
317 /* we also save i7 because longjmp may not restore it */
318 asm volatile ("mov %%i7, %0" : "=r" (saved_i7
));
321 #if defined(TARGET_I386)
323 /* put eflags in CPU temporary format */
324 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
325 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
326 CC_OP
= CC_OP_EFLAGS
;
327 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
328 #elif defined(TARGET_ARM)
329 #elif defined(TARGET_SPARC)
330 #if defined(reg_REGWPTR)
331 saved_regwptr
= REGWPTR
;
333 #elif defined(TARGET_PPC)
334 #elif defined(TARGET_M68K)
335 env
->cc_op
= CC_OP_FLAGS
;
336 env
->cc_dest
= env
->sr
& 0xf;
337 env
->cc_x
= (env
->sr
>> 4) & 1;
338 #elif defined(TARGET_MIPS)
339 #elif defined(TARGET_SH4)
341 #elif defined(TARGET_ALPHA)
344 #error unsupported target CPU
346 env
->exception_index
= -1;
348 /* prepare setjmp context for exception handling */
350 if (setjmp(env
->jmp_env
) == 0) {
351 env
->current_tb
= NULL
;
352 /* if an exception is pending, we execute it here */
353 if (env
->exception_index
>= 0) {
354 if (env
->exception_index
>= EXCP_INTERRUPT
) {
355 /* exit request from the cpu execution loop */
356 ret
= env
->exception_index
;
358 } else if (env
->user_mode_only
) {
359 /* if user mode only, we simulate a fake exception
360 which will be handled outside the cpu execution
362 #if defined(TARGET_I386)
363 do_interrupt_user(env
->exception_index
,
364 env
->exception_is_int
,
366 env
->exception_next_eip
);
368 ret
= env
->exception_index
;
371 #if defined(TARGET_I386)
372 /* simulate a real cpu exception. On i386, it can
373 trigger new exceptions, but we do not handle
374 double or triple faults yet. */
375 do_interrupt(env
->exception_index
,
376 env
->exception_is_int
,
378 env
->exception_next_eip
, 0);
379 /* successfully delivered */
380 env
->old_exception
= -1;
381 #elif defined(TARGET_PPC)
383 #elif defined(TARGET_MIPS)
385 #elif defined(TARGET_SPARC)
386 do_interrupt(env
->exception_index
);
387 #elif defined(TARGET_ARM)
389 #elif defined(TARGET_SH4)
391 #elif defined(TARGET_ALPHA)
395 env
->exception_index
= -1;
398 if (kqemu_is_ok(env
) && env
->interrupt_request
== 0) {
400 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
401 ret
= kqemu_cpu_exec(env
);
402 /* put eflags in CPU temporary format */
403 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
404 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
405 CC_OP
= CC_OP_EFLAGS
;
406 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
409 longjmp(env
->jmp_env
, 1);
410 } else if (ret
== 2) {
411 /* softmmu execution needed */
413 if (env
->interrupt_request
!= 0) {
414 /* hardware interrupt will be executed just after */
416 /* otherwise, we restart */
417 longjmp(env
->jmp_env
, 1);
423 T0
= 0; /* force lookup of first TB */
425 #if defined(__sparc__) && !defined(HOST_SOLARIS)
426 /* g1 can be modified by some libc? functions */
429 interrupt_request
= env
->interrupt_request
;
430 if (__builtin_expect(interrupt_request
, 0)) {
431 if (interrupt_request
& CPU_INTERRUPT_DEBUG
) {
432 env
->interrupt_request
&= ~CPU_INTERRUPT_DEBUG
;
433 env
->exception_index
= EXCP_DEBUG
;
436 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
437 defined(TARGET_PPC) || defined(TARGET_ALPHA)
438 if (interrupt_request
& CPU_INTERRUPT_HALT
) {
439 env
->interrupt_request
&= ~CPU_INTERRUPT_HALT
;
441 env
->exception_index
= EXCP_HLT
;
445 #if defined(TARGET_I386)
446 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
447 !(env
->hflags
& HF_SMM_MASK
)) {
448 env
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
450 #if defined(__sparc__) && !defined(HOST_SOLARIS)
455 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
456 (env
->eflags
& IF_MASK
) &&
457 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
459 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
460 intno
= cpu_get_pic_interrupt(env
);
461 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
462 fprintf(logfile
, "Servicing hardware INT=0x%02x\n", intno
);
464 do_interrupt(intno
, 0, 0, 0, 1);
465 /* ensure that no TB jump will be modified as
466 the program flow was changed */
467 #if defined(__sparc__) && !defined(HOST_SOLARIS)
473 #elif defined(TARGET_PPC)
475 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
479 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
480 ppc_hw_interrupt(env
);
481 if (env
->pending_interrupts
== 0)
482 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
483 #if defined(__sparc__) && !defined(HOST_SOLARIS)
489 #elif defined(TARGET_MIPS)
490 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
491 (env
->CP0_Status
& env
->CP0_Cause
& CP0Ca_IP_mask
) &&
492 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
493 !(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
494 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
495 !(env
->hflags
& MIPS_HFLAG_DM
)) {
497 env
->exception_index
= EXCP_EXT_INTERRUPT
;
500 #if defined(__sparc__) && !defined(HOST_SOLARIS)
506 #elif defined(TARGET_SPARC)
507 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
509 int pil
= env
->interrupt_index
& 15;
510 int type
= env
->interrupt_index
& 0xf0;
512 if (((type
== TT_EXTINT
) &&
513 (pil
== 15 || pil
> env
->psrpil
)) ||
515 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
516 do_interrupt(env
->interrupt_index
);
517 env
->interrupt_index
= 0;
518 #if defined(__sparc__) && !defined(HOST_SOLARIS)
524 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
525 //do_interrupt(0, 0, 0, 0, 0);
526 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
528 #elif defined(TARGET_ARM)
529 if (interrupt_request
& CPU_INTERRUPT_FIQ
530 && !(env
->uncached_cpsr
& CPSR_F
)) {
531 env
->exception_index
= EXCP_FIQ
;
534 if (interrupt_request
& CPU_INTERRUPT_HARD
535 && !(env
->uncached_cpsr
& CPSR_I
)) {
536 env
->exception_index
= EXCP_IRQ
;
539 #elif defined(TARGET_SH4)
541 #elif defined(TARGET_ALPHA)
542 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
546 /* Don't use the cached interupt_request value,
547 do_interrupt may have updated the EXITTB flag. */
548 if (env
->interrupt_request
& CPU_INTERRUPT_EXITTB
) {
549 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
550 /* ensure that no TB jump will be modified as
551 the program flow was changed */
552 #if defined(__sparc__) && !defined(HOST_SOLARIS)
558 if (interrupt_request
& CPU_INTERRUPT_EXIT
) {
559 env
->interrupt_request
&= ~CPU_INTERRUPT_EXIT
;
560 env
->exception_index
= EXCP_INTERRUPT
;
565 if ((loglevel
& CPU_LOG_TB_CPU
)) {
566 #if defined(TARGET_I386)
567 /* restore flags in standard format */
569 env
->regs
[R_EAX
] = EAX
;
572 env
->regs
[R_EBX
] = EBX
;
575 env
->regs
[R_ECX
] = ECX
;
578 env
->regs
[R_EDX
] = EDX
;
581 env
->regs
[R_ESI
] = ESI
;
584 env
->regs
[R_EDI
] = EDI
;
587 env
->regs
[R_EBP
] = EBP
;
590 env
->regs
[R_ESP
] = ESP
;
592 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
593 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
594 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
595 #elif defined(TARGET_ARM)
596 cpu_dump_state(env
, logfile
, fprintf
, 0);
597 #elif defined(TARGET_SPARC)
598 REGWPTR
= env
->regbase
+ (env
->cwp
* 16);
599 env
->regwptr
= REGWPTR
;
600 cpu_dump_state(env
, logfile
, fprintf
, 0);
601 #elif defined(TARGET_PPC)
602 cpu_dump_state(env
, logfile
, fprintf
, 0);
603 #elif defined(TARGET_M68K)
604 cpu_m68k_flush_flags(env
, env
->cc_op
);
605 env
->cc_op
= CC_OP_FLAGS
;
606 env
->sr
= (env
->sr
& 0xffe0)
607 | env
->cc_dest
| (env
->cc_x
<< 4);
608 cpu_dump_state(env
, logfile
, fprintf
, 0);
609 #elif defined(TARGET_MIPS)
610 cpu_dump_state(env
, logfile
, fprintf
, 0);
611 #elif defined(TARGET_SH4)
612 cpu_dump_state(env
, logfile
, fprintf
, 0);
613 #elif defined(TARGET_ALPHA)
614 cpu_dump_state(env
, logfile
, fprintf
, 0);
616 #error unsupported target CPU
622 if ((loglevel
& CPU_LOG_EXEC
)) {
623 fprintf(logfile
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
624 (long)tb
->tc_ptr
, tb
->pc
,
625 lookup_symbol(tb
->pc
));
628 #if defined(__sparc__) && !defined(HOST_SOLARIS)
631 /* see if we can patch the calling TB. When the TB
632 spans two pages, we cannot safely do a direct
637 (env
->kqemu_enabled
!= 2) &&
639 tb
->page_addr
[1] == -1
640 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
641 && (tb
->cflags
& CF_CODE_COPY
) ==
642 (((TranslationBlock
*)(T0
& ~3))->cflags
& CF_CODE_COPY
)
646 tb_add_jump((TranslationBlock
*)(long)(T0
& ~3), T0
& 3, tb
);
647 #if defined(USE_CODE_COPY)
648 /* propagates the FP use info */
649 ((TranslationBlock
*)(T0
& ~3))->cflags
|=
650 (tb
->cflags
& CF_FP_USED
);
652 spin_unlock(&tb_lock
);
656 env
->current_tb
= tb
;
657 /* execute the generated code */
658 gen_func
= (void *)tc_ptr
;
659 #if defined(__sparc__)
660 __asm__
__volatile__("call %0\n\t"
664 : "i0", "i1", "i2", "i3", "i4", "i5",
665 "o0", "o1", "o2", "o3", "o4", "o5",
666 "l0", "l1", "l2", "l3", "l4", "l5",
668 #elif defined(__arm__)
669 asm volatile ("mov pc, %0\n\t"
670 ".global exec_loop\n\t"
674 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
675 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
677 if (!(tb
->cflags
& CF_CODE_COPY
)) {
678 if ((tb
->cflags
& CF_FP_USED
) && env
->native_fp_regs
) {
679 save_native_fp_state(env
);
683 if ((tb
->cflags
& CF_FP_USED
) && !env
->native_fp_regs
) {
684 restore_native_fp_state(env
);
686 /* we work with native eflags */
687 CC_SRC
= cc_table
[CC_OP
].compute_all();
688 CC_OP
= CC_OP_EFLAGS
;
689 asm(".globl exec_loop\n"
694 " fs movl %11, %%eax\n"
695 " andl $0x400, %%eax\n"
696 " fs orl %8, %%eax\n"
699 " fs movl %%esp, %12\n"
700 " fs movl %0, %%eax\n"
701 " fs movl %1, %%ecx\n"
702 " fs movl %2, %%edx\n"
703 " fs movl %3, %%ebx\n"
704 " fs movl %4, %%esp\n"
705 " fs movl %5, %%ebp\n"
706 " fs movl %6, %%esi\n"
707 " fs movl %7, %%edi\n"
710 " fs movl %%esp, %4\n"
711 " fs movl %12, %%esp\n"
712 " fs movl %%eax, %0\n"
713 " fs movl %%ecx, %1\n"
714 " fs movl %%edx, %2\n"
715 " fs movl %%ebx, %3\n"
716 " fs movl %%ebp, %5\n"
717 " fs movl %%esi, %6\n"
718 " fs movl %%edi, %7\n"
721 " movl %%eax, %%ecx\n"
722 " andl $0x400, %%ecx\n"
724 " andl $0x8d5, %%eax\n"
725 " fs movl %%eax, %8\n"
727 " subl %%ecx, %%eax\n"
728 " fs movl %%eax, %11\n"
729 " fs movl %9, %%ebx\n" /* get T0 value */
732 : "m" (*(uint8_t *)offsetof(CPUState
, regs
[0])),
733 "m" (*(uint8_t *)offsetof(CPUState
, regs
[1])),
734 "m" (*(uint8_t *)offsetof(CPUState
, regs
[2])),
735 "m" (*(uint8_t *)offsetof(CPUState
, regs
[3])),
736 "m" (*(uint8_t *)offsetof(CPUState
, regs
[4])),
737 "m" (*(uint8_t *)offsetof(CPUState
, regs
[5])),
738 "m" (*(uint8_t *)offsetof(CPUState
, regs
[6])),
739 "m" (*(uint8_t *)offsetof(CPUState
, regs
[7])),
740 "m" (*(uint8_t *)offsetof(CPUState
, cc_src
)),
741 "m" (*(uint8_t *)offsetof(CPUState
, tmp0
)),
743 "m" (*(uint8_t *)offsetof(CPUState
, df
)),
744 "m" (*(uint8_t *)offsetof(CPUState
, saved_esp
))
749 #elif defined(__ia64)
756 fp
.gp
= code_gen_buffer
+ 2 * (1 << 20);
757 (*(void (*)(void)) &fp
)();
761 env
->current_tb
= NULL
;
762 /* reset soft MMU for next block (it can currently
763 only be set by a memory fault) */
764 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
765 if (env
->hflags
& HF_SOFTMMU_MASK
) {
766 env
->hflags
&= ~HF_SOFTMMU_MASK
;
767 /* do not allow linking to another block */
771 #if defined(USE_KQEMU)
772 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
773 if (kqemu_is_ok(env
) &&
774 (cpu_get_time_fast() - env
->last_io_time
) >= MIN_CYCLE_BEFORE_SWITCH
) {
785 #if defined(TARGET_I386)
786 #if defined(USE_CODE_COPY)
787 if (env
->native_fp_regs
) {
788 save_native_fp_state(env
);
791 /* restore flags in standard format */
792 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
793 #elif defined(TARGET_ARM)
794 /* XXX: Save/restore host fpu exception state?. */
795 #elif defined(TARGET_SPARC)
796 #if defined(reg_REGWPTR)
797 REGWPTR
= saved_regwptr
;
799 #elif defined(TARGET_PPC)
800 #elif defined(TARGET_M68K)
801 cpu_m68k_flush_flags(env
, env
->cc_op
);
802 env
->cc_op
= CC_OP_FLAGS
;
803 env
->sr
= (env
->sr
& 0xffe0)
804 | env
->cc_dest
| (env
->cc_x
<< 4);
805 #elif defined(TARGET_MIPS)
806 #elif defined(TARGET_SH4)
807 #elif defined(TARGET_ALPHA)
810 #error unsupported target CPU
813 /* restore global registers */
814 #if defined(__sparc__) && !defined(HOST_SOLARIS)
815 asm volatile ("mov %0, %%i7" : : "r" (saved_i7
));
817 #include "hostregs_helper.h"
819 /* fail safe : never use cpu_single_env outside cpu_exec() */
820 cpu_single_env
= NULL
;
824 /* must only be called from the generated code as an exception can be
826 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
828 /* XXX: cannot enable it yet because it yields to MMU exception
829 where NIP != read address on PowerPC */
831 target_ulong phys_addr
;
832 phys_addr
= get_phys_addr_code(env
, start
);
833 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
837 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
839 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
841 CPUX86State
*saved_env
;
845 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
847 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
848 (selector
<< 4), 0xffff, 0);
850 load_seg(seg_reg
, selector
);
855 void cpu_x86_fsave(CPUX86State
*s
, uint8_t *ptr
, int data32
)
857 CPUX86State
*saved_env
;
862 helper_fsave((target_ulong
)ptr
, data32
);
867 void cpu_x86_frstor(CPUX86State
*s
, uint8_t *ptr
, int data32
)
869 CPUX86State
*saved_env
;
874 helper_frstor((target_ulong
)ptr
, data32
);
879 #endif /* TARGET_I386 */
881 #if !defined(CONFIG_SOFTMMU)
883 #if defined(TARGET_I386)
885 /* 'pc' is the host PC at which the exception was raised. 'address' is
886 the effective address of the memory exception. 'is_write' is 1 if a
887 write caused the exception and otherwise 0'. 'old_set' is the
888 signal set which should be restored */
889 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
890 int is_write
, sigset_t
*old_set
,
893 TranslationBlock
*tb
;
897 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
898 #if defined(DEBUG_SIGNAL)
899 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
900 pc
, address
, is_write
, *(unsigned long *)old_set
);
902 /* XXX: locking issue */
903 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
907 /* see if it is an MMU fault */
908 ret
= cpu_x86_handle_mmu_fault(env
, address
, is_write
,
909 ((env
->hflags
& HF_CPL_MASK
) == 3), 0);
911 return 0; /* not an MMU fault */
913 return 1; /* the MMU fault was handled without causing real CPU fault */
914 /* now we have a real cpu fault */
917 /* the PC is inside the translated code. It means that we have
918 a virtual CPU fault */
919 cpu_restore_state(tb
, env
, pc
, puc
);
923 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
924 env
->eip
, env
->cr
[2], env
->error_code
);
926 /* we restore the process signal mask as the sigreturn should
927 do it (XXX: use sigsetjmp) */
928 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
929 raise_exception_err(env
->exception_index
, env
->error_code
);
931 /* activate soft MMU for this block */
932 env
->hflags
|= HF_SOFTMMU_MASK
;
933 cpu_resume_from_signal(env
, puc
);
935 /* never comes here */
939 #elif defined(TARGET_ARM)
940 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
941 int is_write
, sigset_t
*old_set
,
944 TranslationBlock
*tb
;
948 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
949 #if defined(DEBUG_SIGNAL)
950 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
951 pc
, address
, is_write
, *(unsigned long *)old_set
);
953 /* XXX: locking issue */
954 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
957 /* see if it is an MMU fault */
958 ret
= cpu_arm_handle_mmu_fault(env
, address
, is_write
, 1, 0);
960 return 0; /* not an MMU fault */
962 return 1; /* the MMU fault was handled without causing real CPU fault */
963 /* now we have a real cpu fault */
966 /* the PC is inside the translated code. It means that we have
967 a virtual CPU fault */
968 cpu_restore_state(tb
, env
, pc
, puc
);
970 /* we restore the process signal mask as the sigreturn should
971 do it (XXX: use sigsetjmp) */
972 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
975 #elif defined(TARGET_SPARC)
976 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
977 int is_write
, sigset_t
*old_set
,
980 TranslationBlock
*tb
;
984 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
985 #if defined(DEBUG_SIGNAL)
986 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
987 pc
, address
, is_write
, *(unsigned long *)old_set
);
989 /* XXX: locking issue */
990 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
993 /* see if it is an MMU fault */
994 ret
= cpu_sparc_handle_mmu_fault(env
, address
, is_write
, 1, 0);
996 return 0; /* not an MMU fault */
998 return 1; /* the MMU fault was handled without causing real CPU fault */
999 /* now we have a real cpu fault */
1000 tb
= tb_find_pc(pc
);
1002 /* the PC is inside the translated code. It means that we have
1003 a virtual CPU fault */
1004 cpu_restore_state(tb
, env
, pc
, puc
);
1006 /* we restore the process signal mask as the sigreturn should
1007 do it (XXX: use sigsetjmp) */
1008 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1011 #elif defined (TARGET_PPC)
1012 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1013 int is_write
, sigset_t
*old_set
,
1016 TranslationBlock
*tb
;
1020 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1021 #if defined(DEBUG_SIGNAL)
1022 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1023 pc
, address
, is_write
, *(unsigned long *)old_set
);
1025 /* XXX: locking issue */
1026 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1030 /* see if it is an MMU fault */
1031 ret
= cpu_ppc_handle_mmu_fault(env
, address
, is_write
, msr_pr
, 0);
1033 return 0; /* not an MMU fault */
1035 return 1; /* the MMU fault was handled without causing real CPU fault */
1037 /* now we have a real cpu fault */
1038 tb
= tb_find_pc(pc
);
1040 /* the PC is inside the translated code. It means that we have
1041 a virtual CPU fault */
1042 cpu_restore_state(tb
, env
, pc
, puc
);
1046 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1047 env
->nip
, env
->error_code
, tb
);
1049 /* we restore the process signal mask as the sigreturn should
1050 do it (XXX: use sigsetjmp) */
1051 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1052 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1054 /* activate soft MMU for this block */
1055 cpu_resume_from_signal(env
, puc
);
1057 /* never comes here */
1061 #elif defined(TARGET_M68K)
1062 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1063 int is_write
, sigset_t
*old_set
,
1066 TranslationBlock
*tb
;
1070 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1071 #if defined(DEBUG_SIGNAL)
1072 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1073 pc
, address
, is_write
, *(unsigned long *)old_set
);
1075 /* XXX: locking issue */
1076 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
1079 /* see if it is an MMU fault */
1080 ret
= cpu_m68k_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1082 return 0; /* not an MMU fault */
1084 return 1; /* the MMU fault was handled without causing real CPU fault */
1085 /* now we have a real cpu fault */
1086 tb
= tb_find_pc(pc
);
1088 /* the PC is inside the translated code. It means that we have
1089 a virtual CPU fault */
1090 cpu_restore_state(tb
, env
, pc
, puc
);
1092 /* we restore the process signal mask as the sigreturn should
1093 do it (XXX: use sigsetjmp) */
1094 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1096 /* never comes here */
1100 #elif defined (TARGET_MIPS)
1101 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1102 int is_write
, sigset_t
*old_set
,
1105 TranslationBlock
*tb
;
1109 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1110 #if defined(DEBUG_SIGNAL)
1111 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1112 pc
, address
, is_write
, *(unsigned long *)old_set
);
1114 /* XXX: locking issue */
1115 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1119 /* see if it is an MMU fault */
1120 ret
= cpu_mips_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1122 return 0; /* not an MMU fault */
1124 return 1; /* the MMU fault was handled without causing real CPU fault */
1126 /* now we have a real cpu fault */
1127 tb
= tb_find_pc(pc
);
1129 /* the PC is inside the translated code. It means that we have
1130 a virtual CPU fault */
1131 cpu_restore_state(tb
, env
, pc
, puc
);
1135 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1136 env
->nip
, env
->error_code
, tb
);
1138 /* we restore the process signal mask as the sigreturn should
1139 do it (XXX: use sigsetjmp) */
1140 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1141 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1143 /* activate soft MMU for this block */
1144 cpu_resume_from_signal(env
, puc
);
1146 /* never comes here */
1150 #elif defined (TARGET_SH4)
1151 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1152 int is_write
, sigset_t
*old_set
,
1155 TranslationBlock
*tb
;
1159 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1160 #if defined(DEBUG_SIGNAL)
1161 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1162 pc
, address
, is_write
, *(unsigned long *)old_set
);
1164 /* XXX: locking issue */
1165 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1169 /* see if it is an MMU fault */
1170 ret
= cpu_sh4_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1172 return 0; /* not an MMU fault */
1174 return 1; /* the MMU fault was handled without causing real CPU fault */
1176 /* now we have a real cpu fault */
1177 tb
= tb_find_pc(pc
);
1179 /* the PC is inside the translated code. It means that we have
1180 a virtual CPU fault */
1181 cpu_restore_state(tb
, env
, pc
, puc
);
1184 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1185 env
->nip
, env
->error_code
, tb
);
1187 /* we restore the process signal mask as the sigreturn should
1188 do it (XXX: use sigsetjmp) */
1189 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1191 /* never comes here */
1195 #elif defined (TARGET_ALPHA)
1196 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1197 int is_write
, sigset_t
*old_set
,
1200 TranslationBlock
*tb
;
1204 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1205 #if defined(DEBUG_SIGNAL)
1206 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1207 pc
, address
, is_write
, *(unsigned long *)old_set
);
1209 /* XXX: locking issue */
1210 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1214 /* see if it is an MMU fault */
1215 ret
= cpu_alpha_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1217 return 0; /* not an MMU fault */
1219 return 1; /* the MMU fault was handled without causing real CPU fault */
1221 /* now we have a real cpu fault */
1222 tb
= tb_find_pc(pc
);
1224 /* the PC is inside the translated code. It means that we have
1225 a virtual CPU fault */
1226 cpu_restore_state(tb
, env
, pc
, puc
);
1229 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1230 env
->nip
, env
->error_code
, tb
);
1232 /* we restore the process signal mask as the sigreturn should
1233 do it (XXX: use sigsetjmp) */
1234 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1236 /* never comes here */
1240 #error unsupported target CPU
1243 #if defined(__i386__)
1245 #if defined(__APPLE__)
1246 # include <sys/ucontext.h>
1248 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1249 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1250 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1252 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1253 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1254 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1257 #if defined(USE_CODE_COPY)
1258 static void cpu_send_trap(unsigned long pc
, int trap
,
1259 struct ucontext
*uc
)
1261 TranslationBlock
*tb
;
1264 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1265 /* now we have a real cpu fault */
1266 tb
= tb_find_pc(pc
);
1268 /* the PC is inside the translated code. It means that we have
1269 a virtual CPU fault */
1270 cpu_restore_state(tb
, env
, pc
, uc
);
1272 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
1273 raise_exception_err(trap
, env
->error_code
);
1277 int cpu_signal_handler(int host_signum
, void *pinfo
,
1280 siginfo_t
*info
= pinfo
;
1281 struct ucontext
*uc
= puc
;
1289 #define REG_TRAPNO TRAPNO
1292 trapno
= TRAP_sig(uc
);
1293 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1294 if (trapno
== 0x00 || trapno
== 0x05) {
1295 /* send division by zero or bound exception */
1296 cpu_send_trap(pc
, trapno
, uc
);
1300 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1302 (ERROR_sig(uc
) >> 1) & 1 : 0,
1303 &uc
->uc_sigmask
, puc
);
1306 #elif defined(__x86_64__)
1308 int cpu_signal_handler(int host_signum
, void *pinfo
,
1311 siginfo_t
*info
= pinfo
;
1312 struct ucontext
*uc
= puc
;
1315 pc
= uc
->uc_mcontext
.gregs
[REG_RIP
];
1316 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1317 uc
->uc_mcontext
.gregs
[REG_TRAPNO
] == 0xe ?
1318 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1319 &uc
->uc_sigmask
, puc
);
1322 #elif defined(__powerpc__)
1324 /***********************************************************************
1325 * signal context platform-specific definitions
1329 /* All Registers access - only for local access */
1330 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1331 /* Gpr Registers access */
1332 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1333 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1334 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1335 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1336 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1337 # define LR_sig(context) REG_sig(link, context) /* Link register */
1338 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1339 /* Float Registers access */
1340 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1341 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1342 /* Exception Registers access */
1343 # define DAR_sig(context) REG_sig(dar, context)
1344 # define DSISR_sig(context) REG_sig(dsisr, context)
1345 # define TRAP_sig(context) REG_sig(trap, context)
1349 # include <sys/ucontext.h>
1350 typedef struct ucontext SIGCONTEXT
;
1351 /* All Registers access - only for local access */
1352 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1353 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1354 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1355 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1356 /* Gpr Registers access */
1357 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1358 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1359 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1360 # define CTR_sig(context) REG_sig(ctr, context)
1361 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1362 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1363 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1364 /* Float Registers access */
1365 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1366 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1367 /* Exception Registers access */
1368 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1369 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1370 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1371 #endif /* __APPLE__ */
1373 int cpu_signal_handler(int host_signum
, void *pinfo
,
1376 siginfo_t
*info
= pinfo
;
1377 struct ucontext
*uc
= puc
;
1385 if (DSISR_sig(uc
) & 0x00800000)
1388 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
1391 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1392 is_write
, &uc
->uc_sigmask
, puc
);
1395 #elif defined(__alpha__)
1397 int cpu_signal_handler(int host_signum
, void *pinfo
,
1400 siginfo_t
*info
= pinfo
;
1401 struct ucontext
*uc
= puc
;
1402 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
1403 uint32_t insn
= *pc
;
1406 /* XXX: need kernel patch to get write flag faster */
1407 switch (insn
>> 26) {
1422 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1423 is_write
, &uc
->uc_sigmask
, puc
);
1425 #elif defined(__sparc__)
1427 int cpu_signal_handler(int host_signum
, void *pinfo
,
1430 siginfo_t
*info
= pinfo
;
1431 uint32_t *regs
= (uint32_t *)(info
+ 1);
1432 void *sigmask
= (regs
+ 20);
1437 /* XXX: is there a standard glibc define ? */
1439 /* XXX: need kernel patch to get write flag faster */
1441 insn
= *(uint32_t *)pc
;
1442 if ((insn
>> 30) == 3) {
1443 switch((insn
>> 19) & 0x3f) {
1455 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1456 is_write
, sigmask
, NULL
);
1459 #elif defined(__arm__)
1461 int cpu_signal_handler(int host_signum
, void *pinfo
,
1464 siginfo_t
*info
= pinfo
;
1465 struct ucontext
*uc
= puc
;
1469 pc
= uc
->uc_mcontext
.gregs
[R15
];
1470 /* XXX: compute is_write */
1472 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1474 &uc
->uc_sigmask
, puc
);
1477 #elif defined(__mc68000)
1479 int cpu_signal_handler(int host_signum
, void *pinfo
,
1482 siginfo_t
*info
= pinfo
;
1483 struct ucontext
*uc
= puc
;
1487 pc
= uc
->uc_mcontext
.gregs
[16];
1488 /* XXX: compute is_write */
1490 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1492 &uc
->uc_sigmask
, puc
);
1495 #elif defined(__ia64)
1498 /* This ought to be in <bits/siginfo.h>... */
1499 # define __ISR_VALID 1
1502 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
1504 siginfo_t
*info
= pinfo
;
1505 struct ucontext
*uc
= puc
;
1509 ip
= uc
->uc_mcontext
.sc_ip
;
1510 switch (host_signum
) {
1516 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
))
1517 /* ISR.W (write-access) is bit 33: */
1518 is_write
= (info
->si_isr
>> 33) & 1;
1524 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
1526 &uc
->uc_sigmask
, puc
);
1529 #elif defined(__s390__)
1531 int cpu_signal_handler(int host_signum
, void *pinfo
,
1534 siginfo_t
*info
= pinfo
;
1535 struct ucontext
*uc
= puc
;
1539 pc
= uc
->uc_mcontext
.psw
.addr
;
1540 /* XXX: compute is_write */
1542 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1544 &uc
->uc_sigmask
, puc
);
1549 #error host CPU specific signal handler needed
1553 #endif /* !defined(CONFIG_SOFTMMU) */