target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdlib.h>
  21 #include "exec.h"
  22
  23 #define GETPC() (__builtin_return_address(0))
  24
  25 /*****************************************************************************/
  26 /* Exceptions processing helpers */
  27
  28 void do_raise_exception_err (uint32_t exception, int error_code)
  29 {
  30 #if 1
  31     if (logfile && exception < 0x100)
  32         fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
  33 #endif
  34     env->exception_index = exception;
  35     env->error_code = error_code;
  36     T0 = 0;
  37     cpu_loop_exit();
  38 }
  39
  40 void do_raise_exception (uint32_t exception)
  41 {
  42     do_raise_exception_err(exception, 0);
  43 }
  44
  45 void do_restore_state (void *pc_ptr)
  46 {
  47   TranslationBlock *tb;
  48   unsigned long pc = (unsigned long) pc_ptr;
  49
  50   tb = tb_find_pc (pc);
  51   cpu_restore_state (tb, env, pc, NULL);
  52 }
  53
  54 void do_raise_exception_direct_err (uint32_t exception, int error_code)
  55 {
  56     do_restore_state (GETPC ());
  57     do_raise_exception_err (exception, error_code);
  58 }
  59
  60 void do_raise_exception_direct (uint32_t exception)
  61 {
  62     do_raise_exception_direct_err (exception, 0);
  63 }
  64
  65 #define MEMSUFFIX _raw
  66 #include "op_helper_mem.c"
  67 #undef MEMSUFFIX
  68 #if !defined(CONFIG_USER_ONLY)
  69 #define MEMSUFFIX _user
  70 #include "op_helper_mem.c"
  71 #undef MEMSUFFIX
  72 #define MEMSUFFIX _kernel
  73 #include "op_helper_mem.c"
  74 #undef MEMSUFFIX
  75 #endif
  76
  77 #ifdef TARGET_MIPS64
  78 #if TARGET_LONG_BITS > HOST_LONG_BITS
  79 /* Those might call libgcc functions.  */
  80 void do_dsll (void)
  81 {
  82     T0 = T0 << T1;
  83 }
  84
  85 void do_dsll32 (void)
  86 {
  87     T0 = T0 << (T1 + 32);
  88 }
  89
  90 void do_dsra (void)
  91 {
  92     T0 = (int64_t)T0 >> T1;
  93 }
  94
  95 void do_dsra32 (void)
  96 {
  97     T0 = (int64_t)T0 >> (T1 + 32);
  98 }
  99
 100 void do_dsrl (void)
 101 {
 102     T0 = T0 >> T1;
 103 }
 104
 105 void do_dsrl32 (void)
 106 {
 107     T0 = T0 >> (T1 + 32);
 108 }
 109
 110 void do_drotr (void)
 111 {
 112     target_ulong tmp;
 113
 114     if (T1) {
 115        tmp = T0 << (0x40 - T1);
 116        T0 = (T0 >> T1) | tmp;
 117     }
 118 }
 119
 120 void do_drotr32 (void)
 121 {
 122     target_ulong tmp;
 123
 124     if (T1) {
 125        tmp = T0 << (0x40 - (32 + T1));
 126        T0 = (T0 >> (32 + T1)) | tmp;
 127     }
 128 }
 129
 130 void do_dsllv (void)
 131 {
 132     T0 = T1 << (T0 & 0x3F);
 133 }
 134
 135 void do_dsrav (void)
 136 {
 137     T0 = (int64_t)T1 >> (T0 & 0x3F);
 138 }
 139
 140 void do_dsrlv (void)
 141 {
 142     T0 = T1 >> (T0 & 0x3F);
 143 }
 144
 145 void do_drotrv (void)
 146 {
 147     target_ulong tmp;
 148
 149     T0 &= 0x3F;
 150     if (T0) {
 151        tmp = T1 << (0x40 - T0);
 152        T0 = (T1 >> T0) | tmp;
 153     } else
 154        T0 = T1;
 155 }
 156 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 157 #endif /* TARGET_MIPS64 */
 158
 159 /* 64 bits arithmetic for 32 bits hosts */
 160 #if TARGET_LONG_BITS > HOST_LONG_BITS
 161 static inline uint64_t get_HILO (void)
 162 {
 163     return (env->HI << 32) | (uint32_t)env->LO;
 164 }
 165
 166 static inline void set_HILO (uint64_t HILO)
 167 {
 168     env->LO = (int32_t)HILO;
 169     env->HI = (int32_t)(HILO >> 32);
 170 }
 171
 172 void do_mult (void)
 173 {
 174     set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 175 }
 176
 177 void do_multu (void)
 178 {
 179     set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 180 }
 181
 182 void do_madd (void)
 183 {
 184     int64_t tmp;
 185
 186     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 187     set_HILO((int64_t)get_HILO() + tmp);
 188 }
 189
 190 void do_maddu (void)
 191 {
 192     uint64_t tmp;
 193
 194     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 195     set_HILO(get_HILO() + tmp);
 196 }
 197
 198 void do_msub (void)
 199 {
 200     int64_t tmp;
 201
 202     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 203     set_HILO((int64_t)get_HILO() - tmp);
 204 }
 205
 206 void do_msubu (void)
 207 {
 208     uint64_t tmp;
 209
 210     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 211     set_HILO(get_HILO() - tmp);
 212 }
 213 #endif
 214
 215 #if HOST_LONG_BITS < 64
 216 void do_div (void)
 217 {
 218     /* 64bit datatypes because we may see overflow/underflow. */
 219     if (T1 != 0) {
 220         env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
 221         env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
 222     }
 223 }
 224 #endif
 225
 226 #ifdef TARGET_MIPS64
 227 void do_ddiv (void)
 228 {
 229     if (T1 != 0) {
 230         lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
 231         env->LO = res.quot;
 232         env->HI = res.rem;
 233     }
 234 }
 235
 236 #if TARGET_LONG_BITS > HOST_LONG_BITS
 237 void do_ddivu (void)
 238 {
 239     if (T1 != 0) {
 240         env->LO = T0 / T1;
 241         env->HI = T0 % T1;
 242     }
 243 }
 244 #endif
 245 #endif /* TARGET_MIPS64 */
 246
 247 #if defined(CONFIG_USER_ONLY)
 248 void do_mfc0_random (void)
 249 {
 250     cpu_abort(env, "mfc0 random\n");
 251 }
 252
 253 void do_mfc0_count (void)
 254 {
 255     cpu_abort(env, "mfc0 count\n");
 256 }
 257
 258 void cpu_mips_store_count(CPUState *env, uint32_t value)
 259 {
 260     cpu_abort(env, "mtc0 count\n");
 261 }
 262
 263 void cpu_mips_store_compare(CPUState *env, uint32_t value)
 264 {
 265     cpu_abort(env, "mtc0 compare\n");
 266 }
 267
 268 void cpu_mips_update_irq(CPUState *env)
 269 {
 270     cpu_abort(env, "mtc0 status / mtc0 cause\n");
 271 }
 272
 273 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 274 {
 275     cpu_abort(env, "mtc0 status debug\n");
 276 }
 277
 278 void do_mtc0_status_irqraise_debug (void)
 279 {
 280     cpu_abort(env, "mtc0 status irqraise debug\n");
 281 }
 282
 283 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 284 {
 285     cpu_abort(env, "mips_tlb_flush\n");
 286 }
 287
 288 #else
 289
 290 /* CP0 helpers */
 291 void do_mfc0_random (void)
 292 {
 293     T0 = (int32_t)cpu_mips_get_random(env);
 294 }
 295
 296 void do_mfc0_count (void)
 297 {
 298     T0 = (int32_t)cpu_mips_get_count(env);
 299 }
 300
 301 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 302 {
 303     fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
 304             old, old & env->CP0_Cause & CP0Ca_IP_mask,
 305             val, val & env->CP0_Cause & CP0Ca_IP_mask,
 306             env->CP0_Cause);
 307     (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
 308                                   : fputs("\n", logfile);
 309 }
 310
 311 void do_mtc0_status_irqraise_debug(void)
 312 {
 313     fprintf(logfile, "Raise pending IRQs\n");
 314 }
 315
 316 void fpu_handle_exception(void)
 317 {
 318 #ifdef CONFIG_SOFTFLOAT
 319     int flags = get_float_exception_flags(&env->fp_status);
 320     unsigned int cpuflags = 0, enable, cause = 0;
 321
 322     enable = GET_FP_ENABLE(env->fcr31);
 323
 324     /* determine current flags */
 325     if (flags & float_flag_invalid) {
 326         cpuflags |= FP_INVALID;
 327         cause |= FP_INVALID & enable;
 328     }
 329     if (flags & float_flag_divbyzero) {
 330         cpuflags |= FP_DIV0;
 331         cause |= FP_DIV0 & enable;
 332     }
 333     if (flags & float_flag_overflow) {
 334         cpuflags |= FP_OVERFLOW;
 335         cause |= FP_OVERFLOW & enable;
 336     }
 337     if (flags & float_flag_underflow) {
 338         cpuflags |= FP_UNDERFLOW;
 339         cause |= FP_UNDERFLOW & enable;
 340     }
 341     if (flags & float_flag_inexact) {
 342         cpuflags |= FP_INEXACT;
 343         cause |= FP_INEXACT & enable;
 344     }
 345     SET_FP_FLAGS(env->fcr31, cpuflags);
 346     SET_FP_CAUSE(env->fcr31, cause);
 347 #else
 348     SET_FP_FLAGS(env->fcr31, 0);
 349     SET_FP_CAUSE(env->fcr31, 0);
 350 #endif
 351 }
 352
 353 /* TLB management */
 354 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 355 {
 356     /* Flush qemu's TLB and discard all shadowed entries.  */
 357     tlb_flush (env, flush_global);
 358     env->tlb_in_use = env->nb_tlb;
 359 }
 360
 361 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
 362 {
 363     /* Discard entries from env->tlb[first] onwards.  */
 364     while (env->tlb_in_use > first) {
 365         r4k_invalidate_tlb(env, --env->tlb_in_use, 0);
 366     }
 367 }
 368
 369 static void r4k_fill_tlb (int idx)
 370 {
 371     r4k_tlb_t *tlb;
 372
 373     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
 374     tlb = &env->mmu.r4k.tlb[idx];
 375     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
 376 #ifdef TARGET_MIPS64
 377     tlb->VPN &= env->SEGMask;
 378 #endif
 379     tlb->ASID = env->CP0_EntryHi & 0xFF;
 380     tlb->PageMask = env->CP0_PageMask;
 381     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
 382     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
 383     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
 384     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
 385     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
 386     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
 387     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
 388     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
 389     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
 390 }
 391
 392 void r4k_do_tlbwi (void)
 393 {
 394     /* Discard cached TLB entries.  We could avoid doing this if the
 395        tlbwi is just upgrading access permissions on the current entry;
 396        that might be a further win.  */
 397     r4k_mips_tlb_flush_extra (env, env->nb_tlb);
 398
 399     r4k_invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
 400     r4k_fill_tlb(env->CP0_Index % env->nb_tlb);
 401 }
 402
 403 void r4k_do_tlbwr (void)
 404 {
 405     int r = cpu_mips_get_random(env);
 406
 407     r4k_invalidate_tlb(env, r, 1);
 408     r4k_fill_tlb(r);
 409 }
 410
 411 void r4k_do_tlbp (void)
 412 {
 413     r4k_tlb_t *tlb;
 414     target_ulong mask;
 415     target_ulong tag;
 416     target_ulong VPN;
 417     uint8_t ASID;
 418     int i;
 419
 420     ASID = env->CP0_EntryHi & 0xFF;
 421     for (i = 0; i < env->nb_tlb; i++) {
 422         tlb = &env->mmu.r4k.tlb[i];
 423         /* 1k pages are not supported. */
 424         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 425         tag = env->CP0_EntryHi & ~mask;
 426         VPN = tlb->VPN & ~mask;
 427         /* Check ASID, virtual page number & size */
 428         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
 429             /* TLB match */
 430             env->CP0_Index = i;
 431             break;
 432         }
 433     }
 434     if (i == env->nb_tlb) {
 435         /* No match.  Discard any shadow entries, if any of them match.  */
 436         for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
 437             tlb = &env->mmu.r4k.tlb[i];
 438             /* 1k pages are not supported. */
 439             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 440             tag = env->CP0_EntryHi & ~mask;
 441             VPN = tlb->VPN & ~mask;
 442             /* Check ASID, virtual page number & size */
 443             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
 444                 r4k_mips_tlb_flush_extra (env, i);
 445                 break;
 446             }
 447         }
 448
 449         env->CP0_Index |= 0x80000000;
 450     }
 451 }
 452
 453 void r4k_do_tlbr (void)
 454 {
 455     r4k_tlb_t *tlb;
 456     uint8_t ASID;
 457
 458     ASID = env->CP0_EntryHi & 0xFF;
 459     tlb = &env->mmu.r4k.tlb[env->CP0_Index % env->nb_tlb];
 460
 461     /* If this will change the current ASID, flush qemu's TLB.  */
 462     if (ASID != tlb->ASID)
 463         cpu_mips_tlb_flush (env, 1);
 464
 465     r4k_mips_tlb_flush_extra(env, env->nb_tlb);
 466
 467     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
 468     env->CP0_PageMask = tlb->PageMask;
 469     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
 470                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
 471     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
 472                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
 473 }
 474
 475 #endif /* !CONFIG_USER_ONLY */
 476
 477 void dump_ldst (const unsigned char *func)
 478 {
 479     if (loglevel)
 480         fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
 481 }
 482
 483 void dump_sc (void)
 484 {
 485     if (loglevel) {
 486         fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
 487                 T1, T0, env->CP0_LLAddr);
 488     }
 489 }
 490
 491 void debug_pre_eret (void)
 492 {
 493     fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
 494             env->PC, env->CP0_EPC);
 495     if (env->CP0_Status & (1 << CP0St_ERL))
 496         fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
 497     if (env->hflags & MIPS_HFLAG_DM)
 498         fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
 499     fputs("\n", logfile);
 500 }
 501
 502 void debug_post_eret (void)
 503 {
 504     fprintf(logfile, "  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
 505             env->PC, env->CP0_EPC);
 506     if (env->CP0_Status & (1 << CP0St_ERL))
 507         fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
 508     if (env->hflags & MIPS_HFLAG_DM)
 509         fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
 510     if (env->hflags & MIPS_HFLAG_UM)
 511         fputs(", UM\n", logfile);
 512     else
 513         fputs("\n", logfile);
 514 }
 515
 516 void do_pmon (int function)
 517 {
 518     function /= 2;
 519     switch (function) {
 520     case 2: /* TODO: char inbyte(int waitflag); */
 521         if (env->gpr[4] == 0)
 522             env->gpr[2] = -1;
 523         /* Fall through */
 524     case 11: /* TODO: char inbyte (void); */
 525         env->gpr[2] = -1;
 526         break;
 527     case 3:
 528     case 12:
 529         printf("%c", (char)(env->gpr[4] & 0xFF));
 530         break;
 531     case 17:
 532         break;
 533     case 158:
 534         {
 535             unsigned char *fmt = (void *)(unsigned long)env->gpr[4];
 536             printf("%s", fmt);
 537         }
 538         break;
 539     }
 540 }
 541
 542 #if !defined(CONFIG_USER_ONLY)
 543
 544 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
 545
 546 #define MMUSUFFIX _mmu
 547 #define ALIGNED_ONLY
 548
 549 #define SHIFT 0
 550 #include "softmmu_template.h"
 551
 552 #define SHIFT 1
 553 #include "softmmu_template.h"
 554
 555 #define SHIFT 2
 556 #include "softmmu_template.h"
 557
 558 #define SHIFT 3
 559 #include "softmmu_template.h"
 560
 561 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
 562 {
 563     env->CP0_BadVAddr = addr;
 564     do_restore_state (retaddr);
 565     do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
 566 }
 567
 568 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
 569 {
 570     TranslationBlock *tb;
 571     CPUState *saved_env;
 572     unsigned long pc;
 573     int ret;
 574
 575     /* XXX: hack to restore env in all cases, even if not called from
 576        generated code */
 577     saved_env = env;
 578     env = cpu_single_env;
 579     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
 580     if (ret) {
 581         if (retaddr) {
 582             /* now we have a real cpu fault */
 583             pc = (unsigned long)retaddr;
 584             tb = tb_find_pc(pc);
 585             if (tb) {
 586                 /* the PC is inside the translated code. It means that we have
 587                    a virtual CPU fault */
 588                 cpu_restore_state(tb, env, pc, NULL);
 589             }
 590         }
 591         do_raise_exception_err(env->exception_index, env->error_code);
 592     }
 593     env = saved_env;
 594 }
 595
 596 #endif
 597
 598 /* Complex FPU operations which may need stack space. */
 599
 600 #define FLOAT_SIGN32 (1 << 31)
 601 #define FLOAT_SIGN64 (1ULL << 63)
 602 #define FLOAT_ONE32 (0x3f8 << 20)
 603 #define FLOAT_ONE64 (0x3ffULL << 52)
 604 #define FLOAT_TWO32 (1 << 30)
 605 #define FLOAT_TWO64 (1ULL << 62)
 606
 607 /* convert MIPS rounding mode in FCR31 to IEEE library */
 608 unsigned int ieee_rm[] = {
 609     float_round_nearest_even,
 610     float_round_to_zero,
 611     float_round_up,
 612     float_round_down
 613 };
 614
 615 #define RESTORE_ROUNDING_MODE \
 616     set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
 617
 618 void do_ctc1 (void)
 619 {
 620     switch(T1) {
 621     case 25:
 622         if (T0 & 0xffffff00)
 623             return;
 624         env->fcr31 = (env->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
 625                      ((T0 & 0x1) << 23);
 626         break;
 627     case 26:
 628         if (T0 & 0x007c0000)
 629             return;
 630         env->fcr31 = (env->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
 631         break;
 632     case 28:
 633         if (T0 & 0x007c0000)
 634             return;
 635         env->fcr31 = (env->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
 636                      ((T0 & 0x4) << 22);
 637         break;
 638     case 31:
 639         if (T0 & 0x007c0000)
 640             return;
 641         env->fcr31 = T0;
 642         break;
 643     default:
 644         return;
 645     }
 646     /* set rounding mode */
 647     RESTORE_ROUNDING_MODE;
 648     set_float_exception_flags(0, &env->fp_status);
 649     if ((GET_FP_ENABLE(env->fcr31) | 0x20) & GET_FP_CAUSE(env->fcr31))
 650         do_raise_exception(EXCP_FPE);
 651 }
 652
 653 inline char ieee_ex_to_mips(char xcpt)
 654 {
 655     return (xcpt & float_flag_inexact) >> 5 |
 656            (xcpt & float_flag_underflow) >> 3 |
 657            (xcpt & float_flag_overflow) >> 1 |
 658            (xcpt & float_flag_divbyzero) << 1 |
 659            (xcpt & float_flag_invalid) << 4;
 660 }
 661
 662 inline char mips_ex_to_ieee(char xcpt)
 663 {
 664     return (xcpt & FP_INEXACT) << 5 |
 665            (xcpt & FP_UNDERFLOW) << 3 |
 666            (xcpt & FP_OVERFLOW) << 1 |
 667            (xcpt & FP_DIV0) >> 1 |
 668            (xcpt & FP_INVALID) >> 4;
 669 }
 670
 671 inline void update_fcr31(void)
 672 {
 673     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fp_status));
 674
 675     SET_FP_CAUSE(env->fcr31, tmp);
 676     if (GET_FP_ENABLE(env->fcr31) & tmp)
 677         do_raise_exception(EXCP_FPE);
 678     else
 679         UPDATE_FP_FLAGS(env->fcr31, tmp);
 680 }
 681
 682 #define FLOAT_OP(name, p) void do_float_##name##_##p(void)
 683
 684 FLOAT_OP(cvtd, s)
 685 {
 686     set_float_exception_flags(0, &env->fp_status);
 687     FDT2 = float32_to_float64(FST0, &env->fp_status);
 688     update_fcr31();
 689 }
 690 FLOAT_OP(cvtd, w)
 691 {
 692     set_float_exception_flags(0, &env->fp_status);
 693     FDT2 = int32_to_float64(WT0, &env->fp_status);
 694     update_fcr31();
 695 }
 696 FLOAT_OP(cvtd, l)
 697 {
 698     set_float_exception_flags(0, &env->fp_status);
 699     FDT2 = int64_to_float64(DT0, &env->fp_status);
 700     update_fcr31();
 701 }
 702 FLOAT_OP(cvtl, d)
 703 {
 704     set_float_exception_flags(0, &env->fp_status);
 705     DT2 = float64_to_int64(FDT0, &env->fp_status);
 706     update_fcr31();
 707     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 708         DT2 = 0x7fffffffffffffffULL;
 709 }
 710 FLOAT_OP(cvtl, s)
 711 {
 712     set_float_exception_flags(0, &env->fp_status);
 713     DT2 = float32_to_int64(FST0, &env->fp_status);
 714     update_fcr31();
 715     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 716         DT2 = 0x7fffffffffffffffULL;
 717 }
 718
 719 FLOAT_OP(cvtps, pw)
 720 {
 721     set_float_exception_flags(0, &env->fp_status);
 722     FST2 = int32_to_float32(WT0, &env->fp_status);
 723     FSTH2 = int32_to_float32(WTH0, &env->fp_status);
 724     update_fcr31();
 725 }
 726 FLOAT_OP(cvtpw, ps)
 727 {
 728     set_float_exception_flags(0, &env->fp_status);
 729     WT2 = float32_to_int32(FST0, &env->fp_status);
 730     WTH2 = float32_to_int32(FSTH0, &env->fp_status);
 731     update_fcr31();
 732     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 733         WT2 = 0x7fffffff;
 734 }
 735 FLOAT_OP(cvts, d)
 736 {
 737     set_float_exception_flags(0, &env->fp_status);
 738     FST2 = float64_to_float32(FDT0, &env->fp_status);
 739     update_fcr31();
 740 }
 741 FLOAT_OP(cvts, w)
 742 {
 743     set_float_exception_flags(0, &env->fp_status);
 744     FST2 = int32_to_float32(WT0, &env->fp_status);
 745     update_fcr31();
 746 }
 747 FLOAT_OP(cvts, l)
 748 {
 749     set_float_exception_flags(0, &env->fp_status);
 750     FST2 = int64_to_float32(DT0, &env->fp_status);
 751     update_fcr31();
 752 }
 753 FLOAT_OP(cvts, pl)
 754 {
 755     set_float_exception_flags(0, &env->fp_status);
 756     WT2 = WT0;
 757     update_fcr31();
 758 }
 759 FLOAT_OP(cvts, pu)
 760 {
 761     set_float_exception_flags(0, &env->fp_status);
 762     WT2 = WTH0;
 763     update_fcr31();
 764 }
 765 FLOAT_OP(cvtw, s)
 766 {
 767     set_float_exception_flags(0, &env->fp_status);
 768     WT2 = float32_to_int32(FST0, &env->fp_status);
 769     update_fcr31();
 770     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 771         WT2 = 0x7fffffff;
 772 }
 773 FLOAT_OP(cvtw, d)
 774 {
 775     set_float_exception_flags(0, &env->fp_status);
 776     WT2 = float64_to_int32(FDT0, &env->fp_status);
 777     update_fcr31();
 778     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 779         WT2 = 0x7fffffff;
 780 }
 781
 782 FLOAT_OP(roundl, d)
 783 {
 784     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 785     DT2 = float64_round_to_int(FDT0, &env->fp_status);
 786     DT2 = float64_to_int64(DT2, &env->fp_status);
 787     RESTORE_ROUNDING_MODE;
 788     update_fcr31();
 789     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 790         DT2 = 0x7fffffffffffffffULL;
 791 }
 792 FLOAT_OP(roundl, s)
 793 {
 794     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 795     WT2 = float32_round_to_int(FST0, &env->fp_status);
 796     DT2 = float32_to_int64(WT2, &env->fp_status);
 797     RESTORE_ROUNDING_MODE;
 798     update_fcr31();
 799     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 800         DT2 = 0x7fffffffffffffffULL;
 801 }
 802 FLOAT_OP(roundw, d)
 803 {
 804     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 805     DT2 = float64_round_to_int(FDT0, &env->fp_status);
 806 // ???
 807     env->fp_status.float_exception_flags &= ~float_flag_inexact;
 808     WT2 = float64_to_int32(DT2, &env->fp_status);
 809     RESTORE_ROUNDING_MODE;
 810     update_fcr31();
 811     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 812         WT2 = 0x7fffffff;
 813 }
 814 FLOAT_OP(roundw, s)
 815 {
 816     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 817     WT2 = float32_round_to_int(FST0, &env->fp_status);
 818     WT2 = float32_to_int32(WT2, &env->fp_status);
 819     RESTORE_ROUNDING_MODE;
 820     update_fcr31();
 821     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 822         WT2 = 0x7fffffff;
 823 }
 824
 825 FLOAT_OP(truncl, d)
 826 {
 827     DT2 = float64_to_int64_round_to_zero(FDT0, &env->fp_status);
 828     update_fcr31();
 829     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 830         DT2 = 0x7fffffffffffffffULL;
 831 }
 832 FLOAT_OP(truncl, s)
 833 {
 834     DT2 = float32_to_int64_round_to_zero(FST0, &env->fp_status);
 835     update_fcr31();
 836     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 837         DT2 = 0x7fffffffffffffffULL;
 838 }
 839 FLOAT_OP(truncw, d)
 840 {
 841     WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
 842     update_fcr31();
 843     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 844         WT2 = 0x7fffffff;
 845 }
 846 FLOAT_OP(truncw, s)
 847 {
 848     WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
 849     update_fcr31();
 850     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 851         WT2 = 0x7fffffff;
 852 }
 853
 854 FLOAT_OP(ceill, d)
 855 {
 856     set_float_rounding_mode(float_round_up, &env->fp_status);
 857     DT2 = float64_round_to_int(FDT0, &env->fp_status);
 858     DT2 = float64_to_int64(DT2, &env->fp_status);
 859     RESTORE_ROUNDING_MODE;
 860     update_fcr31();
 861     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 862         DT2 = 0x7fffffffffffffffULL;
 863 }
 864 FLOAT_OP(ceill, s)
 865 {
 866     set_float_rounding_mode(float_round_up, &env->fp_status);
 867     WT2 = float32_round_to_int(FST0, &env->fp_status);
 868     DT2 = float32_to_int64(WT2, &env->fp_status);
 869     RESTORE_ROUNDING_MODE;
 870     update_fcr31();
 871     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 872         DT2 = 0x7fffffffffffffffULL;
 873 }
 874 FLOAT_OP(ceilw, d)
 875 {
 876     set_float_rounding_mode(float_round_up, &env->fp_status);
 877     DT2 = float64_round_to_int(FDT0, &env->fp_status);
 878 // ???
 879     env->fp_status.float_exception_flags &= ~float_flag_inexact;
 880     WT2 = float64_to_int32(DT2, &env->fp_status);
 881     RESTORE_ROUNDING_MODE;
 882     update_fcr31();
 883     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 884         WT2 = 0x7fffffff;
 885 }
 886 FLOAT_OP(ceilw, s)
 887 {
 888     set_float_rounding_mode(float_round_up, &env->fp_status);
 889     WT2 = float32_round_to_int(FST0, &env->fp_status);
 890     WT2 = float32_to_int32(WT2, &env->fp_status);
 891     RESTORE_ROUNDING_MODE;
 892     update_fcr31();
 893     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 894         WT2 = 0x7fffffff;
 895 }
 896
 897 FLOAT_OP(floorl, d)
 898 {
 899     set_float_rounding_mode(float_round_down, &env->fp_status);
 900     DT2 = float64_round_to_int(FDT0, &env->fp_status);
 901     DT2 = float64_to_int64(DT2, &env->fp_status);
 902     RESTORE_ROUNDING_MODE;
 903     update_fcr31();
 904     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 905         DT2 = 0x7fffffffffffffffULL;
 906 }
 907 FLOAT_OP(floorl, s)
 908 {
 909     set_float_rounding_mode(float_round_down, &env->fp_status);
 910     WT2 = float32_round_to_int(FST0, &env->fp_status);
 911     DT2 = float32_to_int64(WT2, &env->fp_status);
 912     RESTORE_ROUNDING_MODE;
 913     update_fcr31();
 914     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 915         DT2 = 0x7fffffffffffffffULL;
 916 }
 917 FLOAT_OP(floorw, d)
 918 {
 919     set_float_rounding_mode(float_round_down, &env->fp_status);
 920     DT2 = float64_round_to_int(FDT0, &env->fp_status);
 921 // ???
 922     env->fp_status.float_exception_flags &= ~float_flag_inexact;
 923     WT2 = float64_to_int32(DT2, &env->fp_status);
 924     RESTORE_ROUNDING_MODE;
 925     update_fcr31();
 926     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 927         WT2 = 0x7fffffff;
 928 }
 929 FLOAT_OP(floorw, s)
 930 {
 931     set_float_rounding_mode(float_round_down, &env->fp_status);
 932     WT2 = float32_round_to_int(FST0, &env->fp_status);
 933     WT2 = float32_to_int32(WT2, &env->fp_status);
 934     RESTORE_ROUNDING_MODE;
 935     update_fcr31();
 936     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
 937         WT2 = 0x7fffffff;
 938 }
 939
 940 /* MIPS specific unary operations */
 941 FLOAT_OP(recip, d)
 942 {
 943     set_float_exception_flags(0, &env->fp_status);
 944     FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fp_status);
 945     update_fcr31();
 946 }
 947 FLOAT_OP(recip, s)
 948 {
 949     set_float_exception_flags(0, &env->fp_status);
 950     FST2 = float32_div(FLOAT_ONE32, FST0, &env->fp_status);
 951     update_fcr31();
 952 }
 953
 954 FLOAT_OP(rsqrt, d)
 955 {
 956     set_float_exception_flags(0, &env->fp_status);
 957     FDT2 = float64_sqrt(FDT0, &env->fp_status);
 958     FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fp_status);
 959     update_fcr31();
 960 }
 961 FLOAT_OP(rsqrt, s)
 962 {
 963     set_float_exception_flags(0, &env->fp_status);
 964     FST2 = float32_sqrt(FST0, &env->fp_status);
 965     FST2 = float32_div(FLOAT_ONE32, FST2, &env->fp_status);
 966     update_fcr31();
 967 }
 968
 969 FLOAT_OP(recip1, d)
 970 {
 971     set_float_exception_flags(0, &env->fp_status);
 972     FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fp_status);
 973     update_fcr31();
 974 }
 975 FLOAT_OP(recip1, s)
 976 {
 977     set_float_exception_flags(0, &env->fp_status);
 978     FST2 = float32_div(FLOAT_ONE32, FST0, &env->fp_status);
 979     update_fcr31();
 980 }
 981 FLOAT_OP(recip1, ps)
 982 {
 983     set_float_exception_flags(0, &env->fp_status);
 984     FST2 = float32_div(FLOAT_ONE32, FST0, &env->fp_status);
 985     FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fp_status);
 986     update_fcr31();
 987 }
 988
 989 FLOAT_OP(rsqrt1, d)
 990 {
 991     set_float_exception_flags(0, &env->fp_status);
 992     FDT2 = float64_sqrt(FDT0, &env->fp_status);
 993     FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fp_status);
 994     update_fcr31();
 995 }
 996 FLOAT_OP(rsqrt1, s)
 997 {
 998     set_float_exception_flags(0, &env->fp_status);
 999     FST2 = float32_sqrt(FST0, &env->fp_status);
1000     FST2 = float32_div(FLOAT_ONE32, FST2, &env->fp_status);
1001     update_fcr31();
1002 }
1003 FLOAT_OP(rsqrt1, ps)
1004 {
1005     set_float_exception_flags(0, &env->fp_status);
1006     FST2 = float32_sqrt(FST0, &env->fp_status);
1007     FSTH2 = float32_sqrt(FSTH0, &env->fp_status);
1008     FST2 = float32_div(FLOAT_ONE32, FST2, &env->fp_status);
1009     FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fp_status);
1010     update_fcr31();
1011 }
1012
1013 /* binary operations */
1014 #define FLOAT_BINOP(name) \
1015 FLOAT_OP(name, d)         \
1016 {                         \
1017     set_float_exception_flags(0, &env->fp_status);            \
1018     FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status);    \
1019     update_fcr31();                                           \
1020     if (GET_FP_CAUSE(env->fcr31) & FP_INVALID)                \
1021         FDT2 = 0x7ff7ffffffffffffULL;                         \
1022     else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) {       \
1023         if ((env->fcr31 & 0x3) == 0)                          \
1024             FDT2 &= FLOAT_SIGN64;                             \
1025     }                     \
1026 }                         \
1027 FLOAT_OP(name, s)         \
1028 {                         \
1029     set_float_exception_flags(0, &env->fp_status);            \
1030     FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
1031     update_fcr31();                                           \
1032     if (GET_FP_CAUSE(env->fcr31) & FP_INVALID)                \
1033         FST2 = 0x7fbfffff;                                    \
1034     else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) {       \
1035         if ((env->fcr31 & 0x3) == 0)                          \
1036             FST2 &= FLOAT_SIGN32;                             \
1037     }                     \
1038 }                         \
1039 FLOAT_OP(name, ps)        \
1040 {                         \
1041     set_float_exception_flags(0, &env->fp_status);            \
1042     FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
1043     FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fp_status); \
1044     update_fcr31();       \
1045     if (GET_FP_CAUSE(env->fcr31) & FP_INVALID) {              \
1046         FST2 = 0x7fbfffff;                                    \
1047         FSTH2 = 0x7fbfffff;                                   \
1048     } else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) {     \
1049         if ((env->fcr31 & 0x3) == 0) {                        \
1050             FST2 &= FLOAT_SIGN32;                             \
1051             FSTH2 &= FLOAT_SIGN32;                            \
1052         }                 \
1053     }                     \
1054 }
1055 FLOAT_BINOP(add)
1056 FLOAT_BINOP(sub)
1057 FLOAT_BINOP(mul)
1058 FLOAT_BINOP(div)
1059 #undef FLOAT_BINOP
1060
1061 /* MIPS specific binary operations */
1062 FLOAT_OP(recip2, d)
1063 {
1064     set_float_exception_flags(0, &env->fp_status);
1065     FDT2 = float64_mul(FDT0, FDT2, &env->fp_status);
1066     FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fp_status) ^ FLOAT_SIGN64;
1067     update_fcr31();
1068 }
1069 FLOAT_OP(recip2, s)
1070 {
1071     set_float_exception_flags(0, &env->fp_status);
1072     FST2 = float32_mul(FST0, FST2, &env->fp_status);
1073     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fp_status) ^ FLOAT_SIGN32;
1074     update_fcr31();
1075 }
1076 FLOAT_OP(recip2, ps)
1077 {
1078     set_float_exception_flags(0, &env->fp_status);
1079     FST2 = float32_mul(FST0, FST2, &env->fp_status);
1080     FSTH2 = float32_mul(FSTH0, FSTH2, &env->fp_status);
1081     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fp_status) ^ FLOAT_SIGN32;
1082     FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fp_status) ^ FLOAT_SIGN32;
1083     update_fcr31();
1084 }
1085
1086 FLOAT_OP(rsqrt2, d)
1087 {
1088     set_float_exception_flags(0, &env->fp_status);
1089     FDT2 = float64_mul(FDT0, FDT2, &env->fp_status);
1090     FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fp_status);
1091     FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fp_status) ^ FLOAT_SIGN64;
1092     update_fcr31();
1093 }
1094 FLOAT_OP(rsqrt2, s)
1095 {
1096     set_float_exception_flags(0, &env->fp_status);
1097     FST2 = float32_mul(FST0, FST2, &env->fp_status);
1098     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fp_status);
1099     FST2 = float32_div(FST2, FLOAT_TWO32, &env->fp_status) ^ FLOAT_SIGN32;
1100     update_fcr31();
1101 }
1102 FLOAT_OP(rsqrt2, ps)
1103 {
1104     set_float_exception_flags(0, &env->fp_status);
1105     FST2 = float32_mul(FST0, FST2, &env->fp_status);
1106     FSTH2 = float32_mul(FSTH0, FSTH2, &env->fp_status);
1107     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fp_status);
1108     FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fp_status);
1109     FST2 = float32_div(FST2, FLOAT_TWO32, &env->fp_status) ^ FLOAT_SIGN32;
1110     FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fp_status) ^ FLOAT_SIGN32;
1111     update_fcr31();
1112 }
1113
1114 FLOAT_OP(addr, ps)
1115 {
1116     set_float_exception_flags(0, &env->fp_status);
1117     FST2 = float32_add (FST0, FSTH0, &env->fp_status);
1118     FSTH2 = float32_add (FST1, FSTH1, &env->fp_status);
1119     update_fcr31();
1120 }
1121
1122 FLOAT_OP(mulr, ps)
1123 {
1124     set_float_exception_flags(0, &env->fp_status);
1125     FST2 = float32_mul (FST0, FSTH0, &env->fp_status);
1126     FSTH2 = float32_mul (FST1, FSTH1, &env->fp_status);
1127     update_fcr31();
1128 }
1129
1130 /* compare operations */
1131 #define FOP_COND_D(op, cond)                   \
1132 void do_cmp_d_ ## op (long cc)                 \
1133 {                                              \
1134     int c = cond;                              \
1135     update_fcr31();                            \
1136     if (c)                                     \
1137         SET_FP_COND(cc, env);                  \
1138     else                                       \
1139         CLEAR_FP_COND(cc, env);                \
1140 }                                              \
1141 void do_cmpabs_d_ ## op (long cc)              \
1142 {                                              \
1143     int c;                                     \
1144     FDT0 &= ~FLOAT_SIGN64;                     \
1145     FDT1 &= ~FLOAT_SIGN64;                     \
1146     c = cond;                                  \
1147     update_fcr31();                            \
1148     if (c)                                     \
1149         SET_FP_COND(cc, env);                  \
1150     else                                       \
1151         CLEAR_FP_COND(cc, env);                \
1152 }
1153
1154 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1155 {
1156     if (float64_is_signaling_nan(a) ||
1157         float64_is_signaling_nan(b) ||
1158         (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1159         float_raise(float_flag_invalid, status);
1160         return 1;
1161     } else if (float64_is_nan(a) || float64_is_nan(b)) {
1162         return 1;
1163     } else {
1164         return 0;
1165     }
1166 }
1167
1168 /* NOTE: the comma operator will make "cond" to eval to false,
1169  * but float*_is_unordered() is still called. */
1170 FOP_COND_D(f,   (float64_is_unordered(0, FDT1, FDT0, &env->fp_status), 0))
1171 FOP_COND_D(un,  float64_is_unordered(0, FDT1, FDT0, &env->fp_status))
1172 FOP_COND_D(eq,  !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
1173 FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fp_status)  || float64_eq(FDT0, FDT1, &env->fp_status))
1174 FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
1175 FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fp_status)  || float64_lt(FDT0, FDT1, &env->fp_status))
1176 FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
1177 FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fp_status)  || float64_le(FDT0, FDT1, &env->fp_status))
1178 /* NOTE: the comma operator will make "cond" to eval to false,
1179  * but float*_is_unordered() is still called. */
1180 FOP_COND_D(sf,  (float64_is_unordered(1, FDT1, FDT0, &env->fp_status), 0))
1181 FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fp_status))
1182 FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
1183 FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fp_status)  || float64_eq(FDT0, FDT1, &env->fp_status))
1184 FOP_COND_D(lt,  !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
1185 FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fp_status)  || float64_lt(FDT0, FDT1, &env->fp_status))
1186 FOP_COND_D(le,  !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
1187 FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fp_status)  || float64_le(FDT0, FDT1, &env->fp_status))
1188
1189 #define FOP_COND_S(op, cond)                   \
1190 void do_cmp_s_ ## op (long cc)                 \
1191 {                                              \
1192     int c = cond;                              \
1193     update_fcr31();                            \
1194     if (c)                                     \
1195         SET_FP_COND(cc, env);                  \
1196     else                                       \
1197         CLEAR_FP_COND(cc, env);                \
1198 }                                              \
1199 void do_cmpabs_s_ ## op (long cc)              \
1200 {                                              \
1201     int c;                                     \
1202     FST0 &= ~FLOAT_SIGN32;                     \
1203     FST1 &= ~FLOAT_SIGN32;                     \
1204     c = cond;                                  \
1205     update_fcr31();                            \
1206     if (c)                                     \
1207         SET_FP_COND(cc, env);                  \
1208     else                                       \
1209         CLEAR_FP_COND(cc, env);                \
1210 }
1211
1212 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1213 {
1214     if (float32_is_signaling_nan(a) ||
1215         float32_is_signaling_nan(b) ||
1216         (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1217         float_raise(float_flag_invalid, status);
1218         return 1;
1219     } else if (float32_is_nan(a) || float32_is_nan(b)) {
1220         return 1;
1221     } else {
1222         return 0;
1223     }
1224 }
1225
1226 /* NOTE: the comma operator will make "cond" to eval to false,
1227  * but float*_is_unordered() is still called. */
1228 FOP_COND_S(f,   (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0))
1229 FOP_COND_S(un,  float32_is_unordered(0, FST1, FST0, &env->fp_status))
1230 FOP_COND_S(eq,  !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
1231 FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status)  || float32_eq(FST0, FST1, &env->fp_status))
1232 FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
1233 FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status)  || float32_lt(FST0, FST1, &env->fp_status))
1234 FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
1235 FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status)  || float32_le(FST0, FST1, &env->fp_status))
1236 /* NOTE: the comma operator will make "cond" to eval to false,
1237  * but float*_is_unordered() is still called. */
1238 FOP_COND_S(sf,  (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0))
1239 FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status))
1240 FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
1241 FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status)  || float32_eq(FST0, FST1, &env->fp_status))
1242 FOP_COND_S(lt,  !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
1243 FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status)  || float32_lt(FST0, FST1, &env->fp_status))
1244 FOP_COND_S(le,  !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
1245 FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status)  || float32_le(FST0, FST1, &env->fp_status))
1246
1247 #define FOP_COND_PS(op, condl, condh)          \
1248 void do_cmp_ps_ ## op (long cc)                \
1249 {                                              \
1250     int cl = condl;                            \
1251     int ch = condh;                            \
1252     update_fcr31();                            \
1253     if (cl)                                    \
1254         SET_FP_COND(cc, env);                  \
1255     else                                       \
1256         CLEAR_FP_COND(cc, env);                \
1257     if (ch)                                    \
1258         SET_FP_COND(cc + 1, env);              \
1259     else                                       \
1260         CLEAR_FP_COND(cc + 1, env);            \
1261 }                                              \
1262 void do_cmpabs_ps_ ## op (long cc)             \
1263 {                                              \
1264     int cl, ch;                                \
1265     FST0 &= ~FLOAT_SIGN32;                     \
1266     FSTH0 &= ~FLOAT_SIGN32;                    \
1267     FST1 &= ~FLOAT_SIGN32;                     \
1268     FSTH1 &= ~FLOAT_SIGN32;                    \
1269     cl = condl;                                \
1270     ch = condh;                                \
1271     update_fcr31();                            \
1272     if (cl)                                    \
1273         SET_FP_COND(cc, env);                  \
1274     else                                       \
1275         CLEAR_FP_COND(cc, env);                \
1276     if (ch)                                    \
1277         SET_FP_COND(cc + 1, env);              \
1278     else                                       \
1279         CLEAR_FP_COND(cc + 1, env);            \
1280 }
1281
1282 /* NOTE: the comma operator will make "cond" to eval to false,
1283  * but float*_is_unordered() is still called. */
1284 FOP_COND_PS(f,   (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0),
1285                  (float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status), 0))
1286 FOP_COND_PS(un,  float32_is_unordered(0, FST1, FST0, &env->fp_status),
1287                  float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status))
1288 FOP_COND_PS(eq,  !float32_is_unordered(0, FST1, FST0, &env->fp_status)   && float32_eq(FST0, FST1, &env->fp_status),
1289                  !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status))
1290 FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status)    || float32_eq(FST0, FST1, &env->fp_status),
1291                  float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status)  || float32_eq(FSTH0, FSTH1, &env->fp_status))
1292 FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status)   && float32_lt(FST0, FST1, &env->fp_status),
1293                  !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status))
1294 FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status)    || float32_lt(FST0, FST1, &env->fp_status),
1295                  float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status)  || float32_lt(FSTH0, FSTH1, &env->fp_status))
1296 FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status)   && float32_le(FST0, FST1, &env->fp_status),
1297                  !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status))
1298 FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status)    || float32_le(FST0, FST1, &env->fp_status),
1299                  float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status)  || float32_le(FSTH0, FSTH1, &env->fp_status))
1300 /* NOTE: the comma operator will make "cond" to eval to false,
1301  * but float*_is_unordered() is still called. */
1302 FOP_COND_PS(sf,  (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0),
1303                  (float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status), 0))
1304 FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status),
1305                  float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status))
1306 FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status)   && float32_eq(FST0, FST1, &env->fp_status),
1307                  !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status))
1308 FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status)    || float32_eq(FST0, FST1, &env->fp_status),
1309                  float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status)  || float32_eq(FSTH0, FSTH1, &env->fp_status))
1310 FOP_COND_PS(lt,  !float32_is_unordered(1, FST1, FST0, &env->fp_status)   && float32_lt(FST0, FST1, &env->fp_status),
1311                  !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status))
1312 FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status)    || float32_lt(FST0, FST1, &env->fp_status),
1313                  float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status)  || float32_lt(FSTH0, FSTH1, &env->fp_status))
1314 FOP_COND_PS(le,  !float32_is_unordered(1, FST1, FST0, &env->fp_status)   && float32_le(FST0, FST1, &env->fp_status),
1315                  !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status))
1316 FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status)    || float32_le(FST0, FST1, &env->fp_status),
1317                  float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status)  || float32_le(FSTH0, FSTH1, &env->fp_status))