2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 /* Include definitions for instructions classes and implementations flags */
31 //#define DO_SINGLE_STEP
32 //#define PPC_DEBUG_DISAS
33 //#define DEBUG_MEMORY_ACCESSES
34 //#define DO_PPC_STATISTICS
35 //#define OPTIMIZE_FPRF_UPDATE
37 /*****************************************************************************/
38 /* Code translation helpers */
39 #if defined(USE_DIRECT_JUMP)
42 #define TBPARAM(x) (long)(x)
46 #define DEF(s, n, copy_size) INDEX_op_ ## s,
52 static uint16_t *gen_opc_ptr
;
53 static uint32_t *gen_opparam_ptr
;
54 #if defined(OPTIMIZE_FPRF_UPDATE)
55 static uint16_t *gen_fprf_buf
[OPC_BUF_SIZE
];
56 static uint16_t **gen_fprf_ptr
;
61 static always_inline
void gen_set_T0 (target_ulong val
)
63 #if defined(TARGET_PPC64)
65 gen_op_set_T0_64(val
>> 32, val
);
71 static always_inline
void gen_set_T1 (target_ulong val
)
73 #if defined(TARGET_PPC64)
75 gen_op_set_T1_64(val
>> 32, val
);
81 #define GEN8(func, NAME) \
82 static GenOpFunc *NAME ## _table [8] = { \
83 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
84 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
86 static always_inline void func (int n) \
88 NAME ## _table[n](); \
91 #define GEN16(func, NAME) \
92 static GenOpFunc *NAME ## _table [16] = { \
93 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
94 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
95 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
96 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
98 static always_inline void func (int n) \
100 NAME ## _table[n](); \
103 #define GEN32(func, NAME) \
104 static GenOpFunc *NAME ## _table [32] = { \
105 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
106 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
107 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
108 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
109 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
110 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
111 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
112 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
114 static always_inline void func (int n) \
116 NAME ## _table[n](); \
119 /* Condition register moves */
120 GEN8(gen_op_load_crf_T0
, gen_op_load_crf_T0_crf
);
121 GEN8(gen_op_load_crf_T1
, gen_op_load_crf_T1_crf
);
122 GEN8(gen_op_store_T0_crf
, gen_op_store_T0_crf_crf
);
124 GEN8(gen_op_store_T1_crf
, gen_op_store_T1_crf_crf
);
127 /* General purpose registers moves */
128 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
129 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
130 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
132 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
133 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
135 GEN32(gen_op_store_T2_gpr
, gen_op_store_T2_gpr_gpr
);
138 /* floating point registers moves */
139 GEN32(gen_op_load_fpr_FT0
, gen_op_load_fpr_FT0_fpr
);
140 GEN32(gen_op_load_fpr_FT1
, gen_op_load_fpr_FT1_fpr
);
141 GEN32(gen_op_load_fpr_FT2
, gen_op_load_fpr_FT2_fpr
);
142 GEN32(gen_op_store_FT0_fpr
, gen_op_store_FT0_fpr_fpr
);
143 GEN32(gen_op_store_FT1_fpr
, gen_op_store_FT1_fpr_fpr
);
145 GEN32(gen_op_store_FT2_fpr
, gen_op_store_FT2_fpr_fpr
);
148 /* internal defines */
149 typedef struct DisasContext
{
150 struct TranslationBlock
*tb
;
154 /* Routine used to access memory */
156 /* Translation flags */
157 #if !defined(CONFIG_USER_ONLY)
160 #if defined(TARGET_PPC64)
166 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
167 int singlestep_enabled
;
168 int dcache_line_size
;
171 struct opc_handler_t
{
174 /* instruction type */
177 void (*handler
)(DisasContext
*ctx
);
178 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
179 const unsigned char *oname
;
181 #if defined(DO_PPC_STATISTICS)
186 static always_inline
void gen_set_Rc0 (DisasContext
*ctx
)
188 #if defined(TARGET_PPC64)
197 static always_inline
void gen_reset_fpstatus (void)
199 #ifdef CONFIG_SOFTFLOAT
200 gen_op_reset_fpstatus();
204 static always_inline
void gen_compute_fprf (int set_fprf
, int set_rc
)
207 /* This case might be optimized later */
208 #if defined(OPTIMIZE_FPRF_UPDATE)
209 *gen_fprf_ptr
++ = gen_opc_ptr
;
211 gen_op_compute_fprf(1);
212 if (unlikely(set_rc
))
213 gen_op_store_T0_crf(1);
214 gen_op_float_check_status();
215 } else if (unlikely(set_rc
)) {
216 /* We always need to compute fpcc */
217 gen_op_compute_fprf(0);
218 gen_op_store_T0_crf(1);
220 gen_op_float_check_status();
224 static always_inline
void gen_optimize_fprf (void)
226 #if defined(OPTIMIZE_FPRF_UPDATE)
229 for (ptr
= gen_fprf_buf
; ptr
!= (gen_fprf_ptr
- 1); ptr
++)
230 *ptr
= INDEX_op_nop1
;
231 gen_fprf_ptr
= gen_fprf_buf
;
235 static always_inline
void gen_update_nip (DisasContext
*ctx
, target_ulong nip
)
237 #if defined(TARGET_PPC64)
239 gen_op_update_nip_64(nip
>> 32, nip
);
242 gen_op_update_nip(nip
);
245 #define GEN_EXCP(ctx, excp, error) \
247 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
248 gen_update_nip(ctx, (ctx)->nip); \
250 gen_op_raise_exception_err((excp), (error)); \
251 ctx->exception = (excp); \
254 #define GEN_EXCP_INVAL(ctx) \
255 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
256 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
258 #define GEN_EXCP_PRIVOPC(ctx) \
259 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
260 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
262 #define GEN_EXCP_PRIVREG(ctx) \
263 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
264 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
266 #define GEN_EXCP_NO_FP(ctx) \
267 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
269 #define GEN_EXCP_NO_AP(ctx) \
270 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
272 #define GEN_EXCP_NO_VR(ctx) \
273 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
275 /* Stop translation */
276 static always_inline
void GEN_STOP (DisasContext
*ctx
)
278 gen_update_nip(ctx
, ctx
->nip
);
279 ctx
->exception
= POWERPC_EXCP_STOP
;
282 /* No need to update nip here, as execution flow will change */
283 static always_inline
void GEN_SYNC (DisasContext
*ctx
)
285 ctx
->exception
= POWERPC_EXCP_SYNC
;
288 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
289 static void gen_##name (DisasContext *ctx); \
290 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
291 static void gen_##name (DisasContext *ctx)
293 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
294 static void gen_##name (DisasContext *ctx); \
295 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
296 static void gen_##name (DisasContext *ctx)
298 typedef struct opcode_t
{
299 unsigned char opc1
, opc2
, opc3
;
300 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
301 unsigned char pad
[5];
303 unsigned char pad
[1];
305 opc_handler_t handler
;
306 const unsigned char *oname
;
309 /*****************************************************************************/
310 /*** Instruction decoding ***/
311 #define EXTRACT_HELPER(name, shift, nb) \
312 static always_inline uint32_t name (uint32_t opcode) \
314 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
317 #define EXTRACT_SHELPER(name, shift, nb) \
318 static always_inline int32_t name (uint32_t opcode) \
320 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
324 EXTRACT_HELPER(opc1
, 26, 6);
326 EXTRACT_HELPER(opc2
, 1, 5);
328 EXTRACT_HELPER(opc3
, 6, 5);
329 /* Update Cr0 flags */
330 EXTRACT_HELPER(Rc
, 0, 1);
332 EXTRACT_HELPER(rD
, 21, 5);
334 EXTRACT_HELPER(rS
, 21, 5);
336 EXTRACT_HELPER(rA
, 16, 5);
338 EXTRACT_HELPER(rB
, 11, 5);
340 EXTRACT_HELPER(rC
, 6, 5);
342 EXTRACT_HELPER(crfD
, 23, 3);
343 EXTRACT_HELPER(crfS
, 18, 3);
344 EXTRACT_HELPER(crbD
, 21, 5);
345 EXTRACT_HELPER(crbA
, 16, 5);
346 EXTRACT_HELPER(crbB
, 11, 5);
348 EXTRACT_HELPER(_SPR
, 11, 10);
349 static always_inline
uint32_t SPR (uint32_t opcode
)
351 uint32_t sprn
= _SPR(opcode
);
353 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
355 /*** Get constants ***/
356 EXTRACT_HELPER(IMM
, 12, 8);
357 /* 16 bits signed immediate value */
358 EXTRACT_SHELPER(SIMM
, 0, 16);
359 /* 16 bits unsigned immediate value */
360 EXTRACT_HELPER(UIMM
, 0, 16);
362 EXTRACT_HELPER(NB
, 11, 5);
364 EXTRACT_HELPER(SH
, 11, 5);
366 EXTRACT_HELPER(MB
, 6, 5);
368 EXTRACT_HELPER(ME
, 1, 5);
370 EXTRACT_HELPER(TO
, 21, 5);
372 EXTRACT_HELPER(CRM
, 12, 8);
373 EXTRACT_HELPER(FM
, 17, 8);
374 EXTRACT_HELPER(SR
, 16, 4);
375 EXTRACT_HELPER(FPIMM
, 20, 4);
377 /*** Jump target decoding ***/
379 EXTRACT_SHELPER(d
, 0, 16);
380 /* Immediate address */
381 static always_inline target_ulong
LI (uint32_t opcode
)
383 return (opcode
>> 0) & 0x03FFFFFC;
386 static always_inline
uint32_t BD (uint32_t opcode
)
388 return (opcode
>> 0) & 0xFFFC;
391 EXTRACT_HELPER(BO
, 21, 5);
392 EXTRACT_HELPER(BI
, 16, 5);
393 /* Absolute/relative address */
394 EXTRACT_HELPER(AA
, 1, 1);
396 EXTRACT_HELPER(LK
, 0, 1);
398 /* Create a mask between <start> and <end> bits */
399 static always_inline target_ulong
MASK (uint32_t start
, uint32_t end
)
403 #if defined(TARGET_PPC64)
404 if (likely(start
== 0)) {
405 ret
= UINT64_MAX
<< (63 - end
);
406 } else if (likely(end
== 63)) {
407 ret
= UINT64_MAX
>> start
;
410 if (likely(start
== 0)) {
411 ret
= UINT32_MAX
<< (31 - end
);
412 } else if (likely(end
== 31)) {
413 ret
= UINT32_MAX
>> start
;
417 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
418 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
419 if (unlikely(start
> end
))
426 /*****************************************************************************/
427 /* PowerPC Instructions types definitions */
429 PPC_NONE
= 0x0000000000000000ULL
,
430 /* PowerPC base instructions set */
431 PPC_INSNS_BASE
= 0x0000000000000001ULL
,
432 /* integer operations instructions */
433 #define PPC_INTEGER PPC_INSNS_BASE
434 /* flow control instructions */
435 #define PPC_FLOW PPC_INSNS_BASE
436 /* virtual memory instructions */
437 #define PPC_MEM PPC_INSNS_BASE
438 /* ld/st with reservation instructions */
439 #define PPC_RES PPC_INSNS_BASE
440 /* spr/msr access instructions */
441 #define PPC_MISC PPC_INSNS_BASE
442 /* Deprecated instruction sets */
443 /* Original POWER instruction set */
444 PPC_POWER
= 0x0000000000000002ULL
,
445 /* POWER2 instruction set extension */
446 PPC_POWER2
= 0x0000000000000004ULL
,
447 /* Power RTC support */
448 PPC_POWER_RTC
= 0x0000000000000008ULL
,
449 /* Power-to-PowerPC bridge (601) */
450 PPC_POWER_BR
= 0x0000000000000010ULL
,
451 /* 64 bits PowerPC instruction set */
452 PPC_64B
= 0x0000000000000020ULL
,
453 /* New 64 bits extensions (PowerPC 2.0x) */
454 PPC_64BX
= 0x0000000000000040ULL
,
455 /* 64 bits hypervisor extensions */
456 PPC_64H
= 0x0000000000000080ULL
,
457 /* New wait instruction (PowerPC 2.0x) */
458 PPC_WAIT
= 0x0000000000000100ULL
,
459 /* Time base mftb instruction */
460 PPC_MFTB
= 0x0000000000000200ULL
,
462 /* Fixed-point unit extensions */
463 /* PowerPC 602 specific */
464 PPC_602_SPEC
= 0x0000000000000400ULL
,
465 /* isel instruction */
466 PPC_ISEL
= 0x0000000000000800ULL
,
467 /* popcntb instruction */
468 PPC_POPCNTB
= 0x0000000000001000ULL
,
469 /* string load / store */
470 PPC_STRING
= 0x0000000000002000ULL
,
472 /* Floating-point unit extensions */
473 /* Optional floating point instructions */
474 PPC_FLOAT
= 0x0000000000010000ULL
,
475 /* New floating-point extensions (PowerPC 2.0x) */
476 PPC_FLOAT_EXT
= 0x0000000000020000ULL
,
477 PPC_FLOAT_FSQRT
= 0x0000000000040000ULL
,
478 PPC_FLOAT_FRES
= 0x0000000000080000ULL
,
479 PPC_FLOAT_FRSQRTE
= 0x0000000000100000ULL
,
480 PPC_FLOAT_FRSQRTES
= 0x0000000000200000ULL
,
481 PPC_FLOAT_FSEL
= 0x0000000000400000ULL
,
482 PPC_FLOAT_STFIWX
= 0x0000000000800000ULL
,
484 /* Vector/SIMD extensions */
485 /* Altivec support */
486 PPC_ALTIVEC
= 0x0000000001000000ULL
,
487 /* PowerPC 2.03 SPE extension */
488 PPC_SPE
= 0x0000000002000000ULL
,
489 /* PowerPC 2.03 SPE floating-point extension */
490 PPC_SPEFPU
= 0x0000000004000000ULL
,
492 /* Optional memory control instructions */
493 PPC_MEM_TLBIA
= 0x0000000010000000ULL
,
494 PPC_MEM_TLBIE
= 0x0000000020000000ULL
,
495 PPC_MEM_TLBSYNC
= 0x0000000040000000ULL
,
496 /* sync instruction */
497 PPC_MEM_SYNC
= 0x0000000080000000ULL
,
498 /* eieio instruction */
499 PPC_MEM_EIEIO
= 0x0000000100000000ULL
,
501 /* Cache control instructions */
502 PPC_CACHE
= 0x0000000200000000ULL
,
503 /* icbi instruction */
504 PPC_CACHE_ICBI
= 0x0000000400000000ULL
,
505 /* dcbz instruction with fixed cache line size */
506 PPC_CACHE_DCBZ
= 0x0000000800000000ULL
,
507 /* dcbz instruction with tunable cache line size */
508 PPC_CACHE_DCBZT
= 0x0000001000000000ULL
,
509 /* dcba instruction */
510 PPC_CACHE_DCBA
= 0x0000002000000000ULL
,
511 /* Freescale cache locking instructions */
512 PPC_CACHE_LOCK
= 0x0000004000000000ULL
,
514 /* MMU related extensions */
515 /* external control instructions */
516 PPC_EXTERN
= 0x0000010000000000ULL
,
517 /* segment register access instructions */
518 PPC_SEGMENT
= 0x0000020000000000ULL
,
519 /* PowerPC 6xx TLB management instructions */
520 PPC_6xx_TLB
= 0x0000040000000000ULL
,
521 /* PowerPC 74xx TLB management instructions */
522 PPC_74xx_TLB
= 0x0000080000000000ULL
,
523 /* PowerPC 40x TLB management instructions */
524 PPC_40x_TLB
= 0x0000100000000000ULL
,
525 /* segment register access instructions for PowerPC 64 "bridge" */
526 PPC_SEGMENT_64B
= 0x0000200000000000ULL
,
528 PPC_SLBI
= 0x0000400000000000ULL
,
530 /* Embedded PowerPC dedicated instructions */
531 PPC_WRTEE
= 0x0001000000000000ULL
,
532 /* PowerPC 40x exception model */
533 PPC_40x_EXCP
= 0x0002000000000000ULL
,
534 /* PowerPC 405 Mac instructions */
535 PPC_405_MAC
= 0x0004000000000000ULL
,
536 /* PowerPC 440 specific instructions */
537 PPC_440_SPEC
= 0x0008000000000000ULL
,
538 /* BookE (embedded) PowerPC specification */
539 PPC_BOOKE
= 0x0010000000000000ULL
,
540 /* mfapidi instruction */
541 PPC_MFAPIDI
= 0x0020000000000000ULL
,
542 /* tlbiva instruction */
543 PPC_TLBIVA
= 0x0040000000000000ULL
,
544 /* tlbivax instruction */
545 PPC_TLBIVAX
= 0x0080000000000000ULL
,
546 /* PowerPC 4xx dedicated instructions */
547 PPC_4xx_COMMON
= 0x0100000000000000ULL
,
548 /* PowerPC 40x ibct instructions */
549 PPC_40x_ICBT
= 0x0200000000000000ULL
,
550 /* rfmci is not implemented in all BookE PowerPC */
551 PPC_RFMCI
= 0x0400000000000000ULL
,
552 /* rfdi instruction */
553 PPC_RFDI
= 0x0800000000000000ULL
,
555 PPC_DCR
= 0x1000000000000000ULL
,
556 /* DCR extended accesse */
557 PPC_DCRX
= 0x2000000000000000ULL
,
558 /* user-mode DCR access, implemented in PowerPC 460 */
559 PPC_DCRUX
= 0x4000000000000000ULL
,
562 /*****************************************************************************/
563 /* PowerPC instructions table */
564 #if HOST_LONG_BITS == 64
569 #if defined(__APPLE__)
570 #define OPCODES_SECTION \
571 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
573 #define OPCODES_SECTION \
574 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
577 #if defined(DO_PPC_STATISTICS)
578 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
579 OPCODES_SECTION opcode_t opc_##name = { \
587 .handler = &gen_##name, \
588 .oname = stringify(name), \
590 .oname = stringify(name), \
592 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
593 OPCODES_SECTION opcode_t opc_##name = { \
601 .handler = &gen_##name, \
607 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
608 OPCODES_SECTION opcode_t opc_##name = { \
616 .handler = &gen_##name, \
618 .oname = stringify(name), \
620 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
621 OPCODES_SECTION opcode_t opc_##name = { \
629 .handler = &gen_##name, \
635 #define GEN_OPCODE_MARK(name) \
636 OPCODES_SECTION opcode_t opc_##name = { \
642 .inval = 0x00000000, \
646 .oname = stringify(name), \
649 /* Start opcode list */
650 GEN_OPCODE_MARK(start
);
652 /* Invalid instruction */
653 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
)
658 static opc_handler_t invalid_handler
= {
661 .handler
= gen_invalid
,
664 /*** Integer arithmetic ***/
665 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
666 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
668 gen_op_load_gpr_T0(rA(ctx->opcode)); \
669 gen_op_load_gpr_T1(rB(ctx->opcode)); \
671 gen_op_store_T0_gpr(rD(ctx->opcode)); \
672 if (unlikely(Rc(ctx->opcode) != 0)) \
676 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
677 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
679 gen_op_load_gpr_T0(rA(ctx->opcode)); \
680 gen_op_load_gpr_T1(rB(ctx->opcode)); \
682 gen_op_store_T0_gpr(rD(ctx->opcode)); \
683 if (unlikely(Rc(ctx->opcode) != 0)) \
687 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
688 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
690 gen_op_load_gpr_T0(rA(ctx->opcode)); \
692 gen_op_store_T0_gpr(rD(ctx->opcode)); \
693 if (unlikely(Rc(ctx->opcode) != 0)) \
696 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
697 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
699 gen_op_load_gpr_T0(rA(ctx->opcode)); \
701 gen_op_store_T0_gpr(rD(ctx->opcode)); \
702 if (unlikely(Rc(ctx->opcode) != 0)) \
706 /* Two operands arithmetic functions */
707 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
708 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
709 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
711 /* Two operands arithmetic functions with no overflow allowed */
712 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
713 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
715 /* One operand arithmetic functions */
716 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
717 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
718 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
720 #if defined(TARGET_PPC64)
721 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
722 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
724 gen_op_load_gpr_T0(rA(ctx->opcode)); \
725 gen_op_load_gpr_T1(rB(ctx->opcode)); \
727 gen_op_##name##_64(); \
730 gen_op_store_T0_gpr(rD(ctx->opcode)); \
731 if (unlikely(Rc(ctx->opcode) != 0)) \
735 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
736 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
738 gen_op_load_gpr_T0(rA(ctx->opcode)); \
739 gen_op_load_gpr_T1(rB(ctx->opcode)); \
741 gen_op_##name##_64(); \
744 gen_op_store_T0_gpr(rD(ctx->opcode)); \
745 if (unlikely(Rc(ctx->opcode) != 0)) \
749 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
750 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
752 gen_op_load_gpr_T0(rA(ctx->opcode)); \
754 gen_op_##name##_64(); \
757 gen_op_store_T0_gpr(rD(ctx->opcode)); \
758 if (unlikely(Rc(ctx->opcode) != 0)) \
761 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
762 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
764 gen_op_load_gpr_T0(rA(ctx->opcode)); \
766 gen_op_##name##_64(); \
769 gen_op_store_T0_gpr(rD(ctx->opcode)); \
770 if (unlikely(Rc(ctx->opcode) != 0)) \
774 /* Two operands arithmetic functions */
775 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
776 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
777 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
779 /* Two operands arithmetic functions with no overflow allowed */
780 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
781 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
783 /* One operand arithmetic functions */
784 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
785 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
786 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
788 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
789 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
790 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
793 /* add add. addo addo. */
794 static always_inline
void gen_op_addo (void)
800 #if defined(TARGET_PPC64)
801 #define gen_op_add_64 gen_op_add
802 static always_inline
void gen_op_addo_64 (void)
806 gen_op_check_addo_64();
809 GEN_INT_ARITH2_64 (add
, 0x1F, 0x0A, 0x08, PPC_INTEGER
);
810 /* addc addc. addco addco. */
811 static always_inline
void gen_op_addc (void)
817 static always_inline
void gen_op_addco (void)
824 #if defined(TARGET_PPC64)
825 static always_inline
void gen_op_addc_64 (void)
829 gen_op_check_addc_64();
831 static always_inline
void gen_op_addco_64 (void)
835 gen_op_check_addc_64();
836 gen_op_check_addo_64();
839 GEN_INT_ARITH2_64 (addc
, 0x1F, 0x0A, 0x00, PPC_INTEGER
);
840 /* adde adde. addeo addeo. */
841 static always_inline
void gen_op_addeo (void)
847 #if defined(TARGET_PPC64)
848 static always_inline
void gen_op_addeo_64 (void)
852 gen_op_check_addo_64();
855 GEN_INT_ARITH2_64 (adde
, 0x1F, 0x0A, 0x04, PPC_INTEGER
);
856 /* addme addme. addmeo addmeo. */
857 static always_inline
void gen_op_addme (void)
862 #if defined(TARGET_PPC64)
863 static always_inline
void gen_op_addme_64 (void)
869 GEN_INT_ARITH1_64 (addme
, 0x1F, 0x0A, 0x07, PPC_INTEGER
);
870 /* addze addze. addzeo addzeo. */
871 static always_inline
void gen_op_addze (void)
877 static always_inline
void gen_op_addzeo (void)
884 #if defined(TARGET_PPC64)
885 static always_inline
void gen_op_addze_64 (void)
889 gen_op_check_addc_64();
891 static always_inline
void gen_op_addzeo_64 (void)
895 gen_op_check_addc_64();
896 gen_op_check_addo_64();
899 GEN_INT_ARITH1_64 (addze
, 0x1F, 0x0A, 0x06, PPC_INTEGER
);
900 /* divw divw. divwo divwo. */
901 GEN_INT_ARITH2 (divw
, 0x1F, 0x0B, 0x0F, PPC_INTEGER
);
902 /* divwu divwu. divwuo divwuo. */
903 GEN_INT_ARITH2 (divwu
, 0x1F, 0x0B, 0x0E, PPC_INTEGER
);
905 GEN_INT_ARITHN (mulhw
, 0x1F, 0x0B, 0x02, PPC_INTEGER
);
907 GEN_INT_ARITHN (mulhwu
, 0x1F, 0x0B, 0x00, PPC_INTEGER
);
908 /* mullw mullw. mullwo mullwo. */
909 GEN_INT_ARITH2 (mullw
, 0x1F, 0x0B, 0x07, PPC_INTEGER
);
910 /* neg neg. nego nego. */
911 GEN_INT_ARITH1_64 (neg
, 0x1F, 0x08, 0x03, PPC_INTEGER
);
912 /* subf subf. subfo subfo. */
913 static always_inline
void gen_op_subfo (void)
915 gen_op_moven_T2_T0();
919 #if defined(TARGET_PPC64)
920 #define gen_op_subf_64 gen_op_subf
921 static always_inline
void gen_op_subfo_64 (void)
923 gen_op_moven_T2_T0();
925 gen_op_check_addo_64();
928 GEN_INT_ARITH2_64 (subf
, 0x1F, 0x08, 0x01, PPC_INTEGER
);
929 /* subfc subfc. subfco subfco. */
930 static always_inline
void gen_op_subfc (void)
933 gen_op_check_subfc();
935 static always_inline
void gen_op_subfco (void)
937 gen_op_moven_T2_T0();
939 gen_op_check_subfc();
942 #if defined(TARGET_PPC64)
943 static always_inline
void gen_op_subfc_64 (void)
946 gen_op_check_subfc_64();
948 static always_inline
void gen_op_subfco_64 (void)
950 gen_op_moven_T2_T0();
952 gen_op_check_subfc_64();
953 gen_op_check_addo_64();
956 GEN_INT_ARITH2_64 (subfc
, 0x1F, 0x08, 0x00, PPC_INTEGER
);
957 /* subfe subfe. subfeo subfeo. */
958 static always_inline
void gen_op_subfeo (void)
960 gen_op_moven_T2_T0();
964 #if defined(TARGET_PPC64)
965 #define gen_op_subfe_64 gen_op_subfe
966 static always_inline
void gen_op_subfeo_64 (void)
968 gen_op_moven_T2_T0();
970 gen_op_check_addo_64();
973 GEN_INT_ARITH2_64 (subfe
, 0x1F, 0x08, 0x04, PPC_INTEGER
);
974 /* subfme subfme. subfmeo subfmeo. */
975 GEN_INT_ARITH1_64 (subfme
, 0x1F, 0x08, 0x07, PPC_INTEGER
);
976 /* subfze subfze. subfzeo subfzeo. */
977 GEN_INT_ARITH1_64 (subfze
, 0x1F, 0x08, 0x06, PPC_INTEGER
);
979 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
981 target_long simm
= SIMM(ctx
->opcode
);
983 if (rA(ctx
->opcode
) == 0) {
987 gen_op_load_gpr_T0(rA(ctx
->opcode
));
988 if (likely(simm
!= 0))
991 gen_op_store_T0_gpr(rD(ctx
->opcode
));
994 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
996 target_long simm
= SIMM(ctx
->opcode
);
998 gen_op_load_gpr_T0(rA(ctx
->opcode
));
999 if (likely(simm
!= 0)) {
1000 gen_op_move_T2_T0();
1002 #if defined(TARGET_PPC64)
1004 gen_op_check_addc_64();
1007 gen_op_check_addc();
1009 gen_op_clear_xer_ca();
1011 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1014 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1016 target_long simm
= SIMM(ctx
->opcode
);
1018 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1019 if (likely(simm
!= 0)) {
1020 gen_op_move_T2_T0();
1022 #if defined(TARGET_PPC64)
1024 gen_op_check_addc_64();
1027 gen_op_check_addc();
1029 gen_op_clear_xer_ca();
1031 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1035 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1037 target_long simm
= SIMM(ctx
->opcode
);
1039 if (rA(ctx
->opcode
) == 0) {
1041 gen_set_T0(simm
<< 16);
1043 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1044 if (likely(simm
!= 0))
1045 gen_op_addi(simm
<< 16);
1047 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1050 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1052 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1053 gen_op_mulli(SIMM(ctx
->opcode
));
1054 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1057 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1059 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1060 #if defined(TARGET_PPC64)
1062 gen_op_subfic_64(SIMM(ctx
->opcode
));
1065 gen_op_subfic(SIMM(ctx
->opcode
));
1066 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1069 #if defined(TARGET_PPC64)
1071 GEN_INT_ARITHN (mulhd
, 0x1F, 0x09, 0x02, PPC_64B
);
1072 /* mulhdu mulhdu. */
1073 GEN_INT_ARITHN (mulhdu
, 0x1F, 0x09, 0x00, PPC_64B
);
1074 /* mulld mulld. mulldo mulldo. */
1075 GEN_INT_ARITH2 (mulld
, 0x1F, 0x09, 0x07, PPC_64B
);
1076 /* divd divd. divdo divdo. */
1077 GEN_INT_ARITH2 (divd
, 0x1F, 0x09, 0x0F, PPC_64B
);
1078 /* divdu divdu. divduo divduo. */
1079 GEN_INT_ARITH2 (divdu
, 0x1F, 0x09, 0x0E, PPC_64B
);
1082 /*** Integer comparison ***/
1083 #if defined(TARGET_PPC64)
1084 #define GEN_CMP(name, opc, type) \
1085 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1087 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1088 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1089 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
1090 gen_op_##name##_64(); \
1093 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1096 #define GEN_CMP(name, opc, type) \
1097 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1099 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1100 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1102 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1107 GEN_CMP(cmp
, 0x00, PPC_INTEGER
);
1109 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
1111 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1112 #if defined(TARGET_PPC64)
1113 if (ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000))
1114 gen_op_cmpi_64(SIMM(ctx
->opcode
));
1117 gen_op_cmpi(SIMM(ctx
->opcode
));
1118 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1121 GEN_CMP(cmpl
, 0x01, PPC_INTEGER
);
1123 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
1125 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1126 #if defined(TARGET_PPC64)
1127 if (ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000))
1128 gen_op_cmpli_64(UIMM(ctx
->opcode
));
1131 gen_op_cmpli(UIMM(ctx
->opcode
));
1132 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1135 /* isel (PowerPC 2.03 specification) */
1136 GEN_HANDLER(isel
, 0x1F, 0x0F, 0x00, 0x00000001, PPC_ISEL
)
1138 uint32_t bi
= rC(ctx
->opcode
);
1141 if (rA(ctx
->opcode
) == 0) {
1144 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1146 gen_op_load_gpr_T2(rB(ctx
->opcode
));
1147 mask
= 1 << (3 - (bi
& 0x03));
1148 gen_op_load_crf_T0(bi
>> 2);
1149 gen_op_test_true(mask
);
1151 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1154 /*** Integer logical ***/
1155 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1156 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1158 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1159 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1161 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1162 if (unlikely(Rc(ctx->opcode) != 0)) \
1165 #define GEN_LOGICAL2(name, opc, type) \
1166 __GEN_LOGICAL2(name, 0x1C, opc, type)
1168 #define GEN_LOGICAL1(name, opc, type) \
1169 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1171 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1173 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1174 if (unlikely(Rc(ctx->opcode) != 0)) \
1179 GEN_LOGICAL2(and, 0x00, PPC_INTEGER
);
1181 GEN_LOGICAL2(andc
, 0x01, PPC_INTEGER
);
1183 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1185 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1186 gen_op_andi_T0(UIMM(ctx
->opcode
));
1187 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1191 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1193 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1194 gen_op_andi_T0(UIMM(ctx
->opcode
) << 16);
1195 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1200 GEN_LOGICAL1(cntlzw
, 0x00, PPC_INTEGER
);
1202 GEN_LOGICAL2(eqv
, 0x08, PPC_INTEGER
);
1203 /* extsb & extsb. */
1204 GEN_LOGICAL1(extsb
, 0x1D, PPC_INTEGER
);
1205 /* extsh & extsh. */
1206 GEN_LOGICAL1(extsh
, 0x1C, PPC_INTEGER
);
1208 GEN_LOGICAL2(nand
, 0x0E, PPC_INTEGER
);
1210 GEN_LOGICAL2(nor
, 0x03, PPC_INTEGER
);
1213 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
)
1217 rs
= rS(ctx
->opcode
);
1218 ra
= rA(ctx
->opcode
);
1219 rb
= rB(ctx
->opcode
);
1220 /* Optimisation for mr. ri case */
1221 if (rs
!= ra
|| rs
!= rb
) {
1222 gen_op_load_gpr_T0(rs
);
1224 gen_op_load_gpr_T1(rb
);
1227 gen_op_store_T0_gpr(ra
);
1228 if (unlikely(Rc(ctx
->opcode
) != 0))
1230 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1231 gen_op_load_gpr_T0(rs
);
1233 #if defined(TARGET_PPC64)
1237 /* Set process priority to low */
1238 gen_op_store_pri(2);
1241 /* Set process priority to medium-low */
1242 gen_op_store_pri(3);
1245 /* Set process priority to normal */
1246 gen_op_store_pri(4);
1248 #if !defined(CONFIG_USER_ONLY)
1250 if (ctx
->supervisor
> 0) {
1251 /* Set process priority to very low */
1252 gen_op_store_pri(1);
1256 if (ctx
->supervisor
> 0) {
1257 /* Set process priority to medium-hight */
1258 gen_op_store_pri(5);
1262 if (ctx
->supervisor
> 0) {
1263 /* Set process priority to high */
1264 gen_op_store_pri(6);
1268 if (ctx
->supervisor
> 1) {
1269 /* Set process priority to very high */
1270 gen_op_store_pri(7);
1283 GEN_LOGICAL2(orc
, 0x0C, PPC_INTEGER
);
1285 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
)
1287 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1288 /* Optimisation for "set to zero" case */
1289 if (rS(ctx
->opcode
) != rB(ctx
->opcode
)) {
1290 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1295 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1296 if (unlikely(Rc(ctx
->opcode
) != 0))
1300 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1302 target_ulong uimm
= UIMM(ctx
->opcode
);
1304 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1306 /* XXX: should handle special NOPs for POWER series */
1309 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1310 if (likely(uimm
!= 0))
1312 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1315 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1317 target_ulong uimm
= UIMM(ctx
->opcode
);
1319 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1323 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1324 if (likely(uimm
!= 0))
1325 gen_op_ori(uimm
<< 16);
1326 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1329 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1331 target_ulong uimm
= UIMM(ctx
->opcode
);
1333 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1337 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1338 if (likely(uimm
!= 0))
1340 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1344 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1346 target_ulong uimm
= UIMM(ctx
->opcode
);
1348 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1352 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1353 if (likely(uimm
!= 0))
1354 gen_op_xori(uimm
<< 16);
1355 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1358 /* popcntb : PowerPC 2.03 specification */
1359 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB
)
1361 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1362 #if defined(TARGET_PPC64)
1364 gen_op_popcntb_64();
1368 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1371 #if defined(TARGET_PPC64)
1372 /* extsw & extsw. */
1373 GEN_LOGICAL1(extsw
, 0x1E, PPC_64B
);
1375 GEN_LOGICAL1(cntlzd
, 0x01, PPC_64B
);
1378 /*** Integer rotate ***/
1379 /* rlwimi & rlwimi. */
1380 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1383 uint32_t mb
, me
, sh
;
1385 mb
= MB(ctx
->opcode
);
1386 me
= ME(ctx
->opcode
);
1387 sh
= SH(ctx
->opcode
);
1388 if (likely(sh
== 0)) {
1389 if (likely(mb
== 0 && me
== 31)) {
1390 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1392 } else if (likely(mb
== 31 && me
== 0)) {
1393 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1396 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1397 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1400 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1401 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1402 gen_op_rotli32_T0(SH(ctx
->opcode
));
1404 #if defined(TARGET_PPC64)
1408 mask
= MASK(mb
, me
);
1409 gen_op_andi_T0(mask
);
1410 gen_op_andi_T1(~mask
);
1413 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1414 if (unlikely(Rc(ctx
->opcode
) != 0))
1417 /* rlwinm & rlwinm. */
1418 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1420 uint32_t mb
, me
, sh
;
1422 sh
= SH(ctx
->opcode
);
1423 mb
= MB(ctx
->opcode
);
1424 me
= ME(ctx
->opcode
);
1425 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1426 if (likely(sh
== 0)) {
1429 if (likely(mb
== 0)) {
1430 if (likely(me
== 31)) {
1431 gen_op_rotli32_T0(sh
);
1433 } else if (likely(me
== (31 - sh
))) {
1437 } else if (likely(me
== 31)) {
1438 if (likely(sh
== (32 - mb
))) {
1443 gen_op_rotli32_T0(sh
);
1445 #if defined(TARGET_PPC64)
1449 gen_op_andi_T0(MASK(mb
, me
));
1451 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1452 if (unlikely(Rc(ctx
->opcode
) != 0))
1455 /* rlwnm & rlwnm. */
1456 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1460 mb
= MB(ctx
->opcode
);
1461 me
= ME(ctx
->opcode
);
1462 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1463 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1464 gen_op_rotl32_T0_T1();
1465 if (unlikely(mb
!= 0 || me
!= 31)) {
1466 #if defined(TARGET_PPC64)
1470 gen_op_andi_T0(MASK(mb
, me
));
1472 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1473 if (unlikely(Rc(ctx
->opcode
) != 0))
1477 #if defined(TARGET_PPC64)
1478 #define GEN_PPC64_R2(name, opc1, opc2) \
1479 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1481 gen_##name(ctx, 0); \
1483 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1486 gen_##name(ctx, 1); \
1488 #define GEN_PPC64_R4(name, opc1, opc2) \
1489 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1491 gen_##name(ctx, 0, 0); \
1493 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1496 gen_##name(ctx, 0, 1); \
1498 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1501 gen_##name(ctx, 1, 0); \
1503 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1506 gen_##name(ctx, 1, 1); \
1509 static always_inline
void gen_andi_T0_64 (DisasContext
*ctx
, uint64_t mask
)
1512 gen_op_andi_T0_64(mask
>> 32, mask
& 0xFFFFFFFF);
1514 gen_op_andi_T0(mask
);
1517 static always_inline
void gen_andi_T1_64 (DisasContext
*ctx
, uint64_t mask
)
1520 gen_op_andi_T1_64(mask
>> 32, mask
& 0xFFFFFFFF);
1522 gen_op_andi_T1(mask
);
1525 static always_inline
void gen_rldinm (DisasContext
*ctx
, uint32_t mb
,
1526 uint32_t me
, uint32_t sh
)
1528 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1529 if (likely(sh
== 0)) {
1532 if (likely(mb
== 0)) {
1533 if (likely(me
== 63)) {
1534 gen_op_rotli64_T0(sh
);
1536 } else if (likely(me
== (63 - sh
))) {
1540 } else if (likely(me
== 63)) {
1541 if (likely(sh
== (64 - mb
))) {
1542 gen_op_srli_T0_64(mb
);
1546 gen_op_rotli64_T0(sh
);
1548 gen_andi_T0_64(ctx
, MASK(mb
, me
));
1550 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1551 if (unlikely(Rc(ctx
->opcode
) != 0))
1554 /* rldicl - rldicl. */
1555 static always_inline
void gen_rldicl (DisasContext
*ctx
, int mbn
, int shn
)
1559 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1560 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1561 gen_rldinm(ctx
, mb
, 63, sh
);
1563 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1564 /* rldicr - rldicr. */
1565 static always_inline
void gen_rldicr (DisasContext
*ctx
, int men
, int shn
)
1569 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1570 me
= MB(ctx
->opcode
) | (men
<< 5);
1571 gen_rldinm(ctx
, 0, me
, sh
);
1573 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1574 /* rldic - rldic. */
1575 static always_inline
void gen_rldic (DisasContext
*ctx
, int mbn
, int shn
)
1579 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1580 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1581 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1583 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1585 static always_inline
void gen_rldnm (DisasContext
*ctx
, uint32_t mb
,
1588 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1589 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1590 gen_op_rotl64_T0_T1();
1591 if (unlikely(mb
!= 0 || me
!= 63)) {
1592 gen_andi_T0_64(ctx
, MASK(mb
, me
));
1594 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1595 if (unlikely(Rc(ctx
->opcode
) != 0))
1599 /* rldcl - rldcl. */
1600 static always_inline
void gen_rldcl (DisasContext
*ctx
, int mbn
)
1604 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1605 gen_rldnm(ctx
, mb
, 63);
1607 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1608 /* rldcr - rldcr. */
1609 static always_inline
void gen_rldcr (DisasContext
*ctx
, int men
)
1613 me
= MB(ctx
->opcode
) | (men
<< 5);
1614 gen_rldnm(ctx
, 0, me
);
1616 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1617 /* rldimi - rldimi. */
1618 static always_inline
void gen_rldimi (DisasContext
*ctx
, int mbn
, int shn
)
1621 uint32_t sh
, mb
, me
;
1623 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1624 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1626 if (likely(sh
== 0)) {
1627 if (likely(mb
== 0)) {
1628 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1631 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1632 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1635 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1636 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1637 gen_op_rotli64_T0(sh
);
1639 mask
= MASK(mb
, me
);
1640 gen_andi_T0_64(ctx
, mask
);
1641 gen_andi_T1_64(ctx
, ~mask
);
1644 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1645 if (unlikely(Rc(ctx
->opcode
) != 0))
1648 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1651 /*** Integer shift ***/
1653 __GEN_LOGICAL2(slw
, 0x18, 0x00, PPC_INTEGER
);
1655 __GEN_LOGICAL2(sraw
, 0x18, 0x18, PPC_INTEGER
);
1656 /* srawi & srawi. */
1657 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
)
1660 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1661 if (SH(ctx
->opcode
) != 0) {
1662 gen_op_move_T1_T0();
1663 mb
= 32 - SH(ctx
->opcode
);
1665 #if defined(TARGET_PPC64)
1669 gen_op_srawi(SH(ctx
->opcode
), MASK(mb
, me
));
1671 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1672 if (unlikely(Rc(ctx
->opcode
) != 0))
1676 __GEN_LOGICAL2(srw
, 0x18, 0x10, PPC_INTEGER
);
1678 #if defined(TARGET_PPC64)
1680 __GEN_LOGICAL2(sld
, 0x1B, 0x00, PPC_64B
);
1682 __GEN_LOGICAL2(srad
, 0x1A, 0x18, PPC_64B
);
1683 /* sradi & sradi. */
1684 static always_inline
void gen_sradi (DisasContext
*ctx
, int n
)
1689 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1690 sh
= SH(ctx
->opcode
) + (n
<< 5);
1692 gen_op_move_T1_T0();
1693 mb
= 64 - SH(ctx
->opcode
);
1695 mask
= MASK(mb
, me
);
1696 gen_op_sradi(sh
, mask
>> 32, mask
);
1698 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1699 if (unlikely(Rc(ctx
->opcode
) != 0))
1702 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
)
1706 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
)
1711 __GEN_LOGICAL2(srd
, 0x1B, 0x10, PPC_64B
);
1714 /*** Floating-Point arithmetic ***/
1715 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1716 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1718 if (unlikely(!ctx->fpu_enabled)) { \
1719 GEN_EXCP_NO_FP(ctx); \
1722 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1723 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1724 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1725 gen_reset_fpstatus(); \
1730 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1731 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1734 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1735 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1736 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1738 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1739 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1741 if (unlikely(!ctx->fpu_enabled)) { \
1742 GEN_EXCP_NO_FP(ctx); \
1745 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1746 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1747 gen_reset_fpstatus(); \
1752 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1753 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1755 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1756 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1757 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1759 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1760 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1762 if (unlikely(!ctx->fpu_enabled)) { \
1763 GEN_EXCP_NO_FP(ctx); \
1766 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1767 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1768 gen_reset_fpstatus(); \
1773 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1774 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1776 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1777 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1778 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1780 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1781 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1783 if (unlikely(!ctx->fpu_enabled)) { \
1784 GEN_EXCP_NO_FP(ctx); \
1787 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1788 gen_reset_fpstatus(); \
1790 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1791 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1794 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1795 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1797 if (unlikely(!ctx->fpu_enabled)) { \
1798 GEN_EXCP_NO_FP(ctx); \
1801 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1802 gen_reset_fpstatus(); \
1804 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1805 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1809 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
1811 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
1813 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
1816 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
1819 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
1822 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
1825 static always_inline
void gen_op_frsqrtes (void)
1830 GEN_FLOAT_BS(rsqrtes
, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES
);
1833 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
1835 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
1838 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
1840 if (unlikely(!ctx
->fpu_enabled
)) {
1841 GEN_EXCP_NO_FP(ctx
);
1844 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1845 gen_reset_fpstatus();
1847 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1848 gen_compute_fprf(1, Rc(ctx
->opcode
) != 0);
1851 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
1853 if (unlikely(!ctx
->fpu_enabled
)) {
1854 GEN_EXCP_NO_FP(ctx
);
1857 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1858 gen_reset_fpstatus();
1861 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1862 gen_compute_fprf(1, Rc(ctx
->opcode
) != 0);
1865 /*** Floating-Point multiply-and-add ***/
1866 /* fmadd - fmadds */
1867 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
1868 /* fmsub - fmsubs */
1869 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
1870 /* fnmadd - fnmadds */
1871 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
1872 /* fnmsub - fnmsubs */
1873 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
1875 /*** Floating-Point round & convert ***/
1877 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
1879 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
1881 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
1882 #if defined(TARGET_PPC64)
1884 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
1886 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
1888 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
1892 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
1894 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
1896 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
1898 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
1900 /*** Floating-Point compare ***/
1902 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
)
1904 if (unlikely(!ctx
->fpu_enabled
)) {
1905 GEN_EXCP_NO_FP(ctx
);
1908 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
1909 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
1910 gen_reset_fpstatus();
1912 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1913 gen_op_float_check_status();
1917 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
)
1919 if (unlikely(!ctx
->fpu_enabled
)) {
1920 GEN_EXCP_NO_FP(ctx
);
1923 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
1924 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
1925 gen_reset_fpstatus();
1927 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1928 gen_op_float_check_status();
1931 /*** Floating-point move ***/
1933 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1934 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
);
1937 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1938 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
)
1940 if (unlikely(!ctx
->fpu_enabled
)) {
1941 GEN_EXCP_NO_FP(ctx
);
1944 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1945 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1946 gen_compute_fprf(0, Rc(ctx
->opcode
) != 0);
1950 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1951 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
);
1953 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1954 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
);
1956 /*** Floating-Point status & ctrl register ***/
1958 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
)
1962 if (unlikely(!ctx
->fpu_enabled
)) {
1963 GEN_EXCP_NO_FP(ctx
);
1966 gen_optimize_fprf();
1967 bfa
= 4 * (7 - crfS(ctx
->opcode
));
1968 gen_op_load_fpscr_T0(bfa
);
1969 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1970 gen_op_fpscr_resetbit(~(0xF << bfa
));
1974 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
)
1976 if (unlikely(!ctx
->fpu_enabled
)) {
1977 GEN_EXCP_NO_FP(ctx
);
1980 gen_optimize_fprf();
1981 gen_reset_fpstatus();
1982 gen_op_load_fpscr_FT0();
1983 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1984 gen_compute_fprf(0, Rc(ctx
->opcode
) != 0);
1988 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
)
1992 if (unlikely(!ctx
->fpu_enabled
)) {
1993 GEN_EXCP_NO_FP(ctx
);
1996 crb
= 32 - (crbD(ctx
->opcode
) >> 2);
1997 gen_optimize_fprf();
1998 gen_reset_fpstatus();
1999 if (likely(crb
!= 30 && crb
!= 29))
2000 gen_op_fpscr_resetbit(~(1 << crb
));
2001 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2008 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
)
2012 if (unlikely(!ctx
->fpu_enabled
)) {
2013 GEN_EXCP_NO_FP(ctx
);
2016 crb
= 32 - (crbD(ctx
->opcode
) >> 2);
2017 gen_optimize_fprf();
2018 gen_reset_fpstatus();
2019 /* XXX: we pretend we can only do IEEE floating-point computations */
2020 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
))
2021 gen_op_fpscr_setbit(crb
);
2022 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2026 /* We can raise a differed exception */
2027 gen_op_float_check_status();
2031 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT
)
2033 if (unlikely(!ctx
->fpu_enabled
)) {
2034 GEN_EXCP_NO_FP(ctx
);
2037 gen_optimize_fprf();
2038 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
2039 gen_reset_fpstatus();
2040 gen_op_store_fpscr(FM(ctx
->opcode
));
2041 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2045 /* We can raise a differed exception */
2046 gen_op_float_check_status();
2050 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
)
2054 if (unlikely(!ctx
->fpu_enabled
)) {
2055 GEN_EXCP_NO_FP(ctx
);
2058 bf
= crbD(ctx
->opcode
) >> 2;
2060 gen_optimize_fprf();
2061 gen_op_set_FT0(FPIMM(ctx
->opcode
) << (4 * sh
));
2062 gen_reset_fpstatus();
2063 gen_op_store_fpscr(1 << sh
);
2064 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2068 /* We can raise a differed exception */
2069 gen_op_float_check_status();
2072 /*** Addressing modes ***/
2073 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2074 static always_inline
void gen_addr_imm_index (DisasContext
*ctx
,
2077 target_long simm
= SIMM(ctx
->opcode
);
2080 if (rA(ctx
->opcode
) == 0) {
2083 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2084 if (likely(simm
!= 0))
2087 #ifdef DEBUG_MEMORY_ACCESSES
2088 gen_op_print_mem_EA();
2092 static always_inline
void gen_addr_reg_index (DisasContext
*ctx
)
2094 if (rA(ctx
->opcode
) == 0) {
2095 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2097 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2098 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2101 #ifdef DEBUG_MEMORY_ACCESSES
2102 gen_op_print_mem_EA();
2106 static always_inline
void gen_addr_register (DisasContext
*ctx
)
2108 if (rA(ctx
->opcode
) == 0) {
2111 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2113 #ifdef DEBUG_MEMORY_ACCESSES
2114 gen_op_print_mem_EA();
2118 #if defined(TARGET_PPC64)
2119 #define _GEN_MEM_FUNCS(name, mode) \
2120 &gen_op_##name##_##mode, \
2121 &gen_op_##name##_le_##mode, \
2122 &gen_op_##name##_64_##mode, \
2123 &gen_op_##name##_le_64_##mode
2125 #define _GEN_MEM_FUNCS(name, mode) \
2126 &gen_op_##name##_##mode, \
2127 &gen_op_##name##_le_##mode
2129 #if defined(CONFIG_USER_ONLY)
2130 #if defined(TARGET_PPC64)
2131 #define NB_MEM_FUNCS 4
2133 #define NB_MEM_FUNCS 2
2135 #define GEN_MEM_FUNCS(name) \
2136 _GEN_MEM_FUNCS(name, raw)
2138 #if defined(TARGET_PPC64)
2139 #define NB_MEM_FUNCS 12
2141 #define NB_MEM_FUNCS 6
2143 #define GEN_MEM_FUNCS(name) \
2144 _GEN_MEM_FUNCS(name, user), \
2145 _GEN_MEM_FUNCS(name, kernel), \
2146 _GEN_MEM_FUNCS(name, hypv)
2149 /*** Integer load ***/
2150 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2151 /* Byte access routine are endian safe */
2152 #define gen_op_lbz_le_raw gen_op_lbz_raw
2153 #define gen_op_lbz_le_user gen_op_lbz_user
2154 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2155 #define gen_op_lbz_le_hypv gen_op_lbz_hypv
2156 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2157 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2158 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2159 #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2160 #define gen_op_stb_le_raw gen_op_stb_raw
2161 #define gen_op_stb_le_user gen_op_stb_user
2162 #define gen_op_stb_le_kernel gen_op_stb_kernel
2163 #define gen_op_stb_le_hypv gen_op_stb_hypv
2164 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
2165 #define gen_op_stb_le_64_user gen_op_stb_64_user
2166 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2167 #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2168 #define OP_LD_TABLE(width) \
2169 static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2170 GEN_MEM_FUNCS(l##width), \
2172 #define OP_ST_TABLE(width) \
2173 static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2174 GEN_MEM_FUNCS(st##width), \
2177 #define GEN_LD(width, opc, type) \
2178 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2180 gen_addr_imm_index(ctx, 0); \
2181 op_ldst(l##width); \
2182 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2185 #define GEN_LDU(width, opc, type) \
2186 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2188 if (unlikely(rA(ctx->opcode) == 0 || \
2189 rA(ctx->opcode) == rD(ctx->opcode))) { \
2190 GEN_EXCP_INVAL(ctx); \
2193 if (type == PPC_64B) \
2194 gen_addr_imm_index(ctx, 0x03); \
2196 gen_addr_imm_index(ctx, 0); \
2197 op_ldst(l##width); \
2198 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2199 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2202 #define GEN_LDUX(width, opc2, opc3, type) \
2203 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2205 if (unlikely(rA(ctx->opcode) == 0 || \
2206 rA(ctx->opcode) == rD(ctx->opcode))) { \
2207 GEN_EXCP_INVAL(ctx); \
2210 gen_addr_reg_index(ctx); \
2211 op_ldst(l##width); \
2212 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2213 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2216 #define GEN_LDX(width, opc2, opc3, type) \
2217 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2219 gen_addr_reg_index(ctx); \
2220 op_ldst(l##width); \
2221 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2224 #define GEN_LDS(width, op, type) \
2225 OP_LD_TABLE(width); \
2226 GEN_LD(width, op | 0x20, type); \
2227 GEN_LDU(width, op | 0x21, type); \
2228 GEN_LDUX(width, 0x17, op | 0x01, type); \
2229 GEN_LDX(width, 0x17, op | 0x00, type)
2231 /* lbz lbzu lbzux lbzx */
2232 GEN_LDS(bz
, 0x02, PPC_INTEGER
);
2233 /* lha lhau lhaux lhax */
2234 GEN_LDS(ha
, 0x0A, PPC_INTEGER
);
2235 /* lhz lhzu lhzux lhzx */
2236 GEN_LDS(hz
, 0x08, PPC_INTEGER
);
2237 /* lwz lwzu lwzux lwzx */
2238 GEN_LDS(wz
, 0x00, PPC_INTEGER
);
2239 #if defined(TARGET_PPC64)
2243 GEN_LDUX(wa
, 0x15, 0x0B, PPC_64B
);
2245 GEN_LDX(wa
, 0x15, 0x0A, PPC_64B
);
2247 GEN_LDUX(d
, 0x15, 0x01, PPC_64B
);
2249 GEN_LDX(d
, 0x15, 0x00, PPC_64B
);
2250 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2252 if (Rc(ctx
->opcode
)) {
2253 if (unlikely(rA(ctx
->opcode
) == 0 ||
2254 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2255 GEN_EXCP_INVAL(ctx
);
2259 gen_addr_imm_index(ctx
, 0x03);
2260 if (ctx
->opcode
& 0x02) {
2261 /* lwa (lwau is undefined) */
2267 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2268 if (Rc(ctx
->opcode
))
2269 gen_op_store_T0_gpr(rA(ctx
->opcode
));
2272 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
)
2274 #if defined(CONFIG_USER_ONLY)
2275 GEN_EXCP_PRIVOPC(ctx
);
2279 /* Restore CPU state */
2280 if (unlikely(ctx
->supervisor
== 0)) {
2281 GEN_EXCP_PRIVOPC(ctx
);
2284 ra
= rA(ctx
->opcode
);
2285 rd
= rD(ctx
->opcode
);
2286 if (unlikely((rd
& 1) || rd
== ra
)) {
2287 GEN_EXCP_INVAL(ctx
);
2290 if (unlikely(ctx
->mem_idx
& 1)) {
2291 /* Little-endian mode is not handled */
2292 GEN_EXCP(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2295 gen_addr_imm_index(ctx
, 0x0F);
2297 gen_op_store_T1_gpr(rd
);
2300 gen_op_store_T1_gpr(rd
+ 1);
2305 /*** Integer store ***/
2306 #define GEN_ST(width, opc, type) \
2307 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2309 gen_addr_imm_index(ctx, 0); \
2310 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2311 op_ldst(st##width); \
2314 #define GEN_STU(width, opc, type) \
2315 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2317 if (unlikely(rA(ctx->opcode) == 0)) { \
2318 GEN_EXCP_INVAL(ctx); \
2321 if (type == PPC_64B) \
2322 gen_addr_imm_index(ctx, 0x03); \
2324 gen_addr_imm_index(ctx, 0); \
2325 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2326 op_ldst(st##width); \
2327 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2330 #define GEN_STUX(width, opc2, opc3, type) \
2331 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2333 if (unlikely(rA(ctx->opcode) == 0)) { \
2334 GEN_EXCP_INVAL(ctx); \
2337 gen_addr_reg_index(ctx); \
2338 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2339 op_ldst(st##width); \
2340 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2343 #define GEN_STX(width, opc2, opc3, type) \
2344 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2346 gen_addr_reg_index(ctx); \
2347 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2348 op_ldst(st##width); \
2351 #define GEN_STS(width, op, type) \
2352 OP_ST_TABLE(width); \
2353 GEN_ST(width, op | 0x20, type); \
2354 GEN_STU(width, op | 0x21, type); \
2355 GEN_STUX(width, 0x17, op | 0x01, type); \
2356 GEN_STX(width, 0x17, op | 0x00, type)
2358 /* stb stbu stbux stbx */
2359 GEN_STS(b
, 0x06, PPC_INTEGER
);
2360 /* sth sthu sthux sthx */
2361 GEN_STS(h
, 0x0C, PPC_INTEGER
);
2362 /* stw stwu stwux stwx */
2363 GEN_STS(w
, 0x04, PPC_INTEGER
);
2364 #if defined(TARGET_PPC64)
2366 GEN_STUX(d
, 0x15, 0x05, PPC_64B
);
2367 GEN_STX(d
, 0x15, 0x04, PPC_64B
);
2368 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2372 rs
= rS(ctx
->opcode
);
2373 if ((ctx
->opcode
& 0x3) == 0x2) {
2374 #if defined(CONFIG_USER_ONLY)
2375 GEN_EXCP_PRIVOPC(ctx
);
2378 if (unlikely(ctx
->supervisor
== 0)) {
2379 GEN_EXCP_PRIVOPC(ctx
);
2382 if (unlikely(rs
& 1)) {
2383 GEN_EXCP_INVAL(ctx
);
2386 if (unlikely(ctx
->mem_idx
& 1)) {
2387 /* Little-endian mode is not handled */
2388 GEN_EXCP(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2391 gen_addr_imm_index(ctx
, 0x03);
2392 gen_op_load_gpr_T1(rs
);
2395 gen_op_load_gpr_T1(rs
+ 1);
2400 if (Rc(ctx
->opcode
)) {
2401 if (unlikely(rA(ctx
->opcode
) == 0)) {
2402 GEN_EXCP_INVAL(ctx
);
2406 gen_addr_imm_index(ctx
, 0x03);
2407 gen_op_load_gpr_T1(rs
);
2409 if (Rc(ctx
->opcode
))
2410 gen_op_store_T0_gpr(rA(ctx
->opcode
));
2414 /*** Integer load and store with byte reverse ***/
2417 GEN_LDX(hbr
, 0x16, 0x18, PPC_INTEGER
);
2420 GEN_LDX(wbr
, 0x16, 0x10, PPC_INTEGER
);
2423 GEN_STX(hbr
, 0x16, 0x1C, PPC_INTEGER
);
2426 GEN_STX(wbr
, 0x16, 0x14, PPC_INTEGER
);
2428 /*** Integer load and store multiple ***/
2429 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2430 static GenOpFunc1
*gen_op_lmw
[NB_MEM_FUNCS
] = {
2433 static GenOpFunc1
*gen_op_stmw
[NB_MEM_FUNCS
] = {
2434 GEN_MEM_FUNCS(stmw
),
2438 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
2440 /* NIP cannot be restored if the memory exception comes from an helper */
2441 gen_update_nip(ctx
, ctx
->nip
- 4);
2442 gen_addr_imm_index(ctx
, 0);
2443 op_ldstm(lmw
, rD(ctx
->opcode
));
2447 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
2449 /* NIP cannot be restored if the memory exception comes from an helper */
2450 gen_update_nip(ctx
, ctx
->nip
- 4);
2451 gen_addr_imm_index(ctx
, 0);
2452 op_ldstm(stmw
, rS(ctx
->opcode
));
2455 /*** Integer load and store strings ***/
2456 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2457 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2458 /* string load & stores are by definition endian-safe */
2459 #define gen_op_lswi_le_raw gen_op_lswi_raw
2460 #define gen_op_lswi_le_user gen_op_lswi_user
2461 #define gen_op_lswi_le_kernel gen_op_lswi_kernel
2462 #define gen_op_lswi_le_hypv gen_op_lswi_hypv
2463 #define gen_op_lswi_le_64_raw gen_op_lswi_raw
2464 #define gen_op_lswi_le_64_user gen_op_lswi_user
2465 #define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2466 #define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
2467 static GenOpFunc1
*gen_op_lswi
[NB_MEM_FUNCS
] = {
2468 GEN_MEM_FUNCS(lswi
),
2470 #define gen_op_lswx_le_raw gen_op_lswx_raw
2471 #define gen_op_lswx_le_user gen_op_lswx_user
2472 #define gen_op_lswx_le_kernel gen_op_lswx_kernel
2473 #define gen_op_lswx_le_hypv gen_op_lswx_hypv
2474 #define gen_op_lswx_le_64_raw gen_op_lswx_raw
2475 #define gen_op_lswx_le_64_user gen_op_lswx_user
2476 #define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2477 #define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
2478 static GenOpFunc3
*gen_op_lswx
[NB_MEM_FUNCS
] = {
2479 GEN_MEM_FUNCS(lswx
),
2481 #define gen_op_stsw_le_raw gen_op_stsw_raw
2482 #define gen_op_stsw_le_user gen_op_stsw_user
2483 #define gen_op_stsw_le_kernel gen_op_stsw_kernel
2484 #define gen_op_stsw_le_hypv gen_op_stsw_hypv
2485 #define gen_op_stsw_le_64_raw gen_op_stsw_raw
2486 #define gen_op_stsw_le_64_user gen_op_stsw_user
2487 #define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2488 #define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
2489 static GenOpFunc1
*gen_op_stsw
[NB_MEM_FUNCS
] = {
2490 GEN_MEM_FUNCS(stsw
),
2494 /* PowerPC32 specification says we must generate an exception if
2495 * rA is in the range of registers to be loaded.
2496 * In an other hand, IBM says this is valid, but rA won't be loaded.
2497 * For now, I'll follow the spec...
2499 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
)
2501 int nb
= NB(ctx
->opcode
);
2502 int start
= rD(ctx
->opcode
);
2503 int ra
= rA(ctx
->opcode
);
2509 if (unlikely(((start
+ nr
) > 32 &&
2510 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
2511 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
2512 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
2513 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_LSWX
);
2516 /* NIP cannot be restored if the memory exception comes from an helper */
2517 gen_update_nip(ctx
, ctx
->nip
- 4);
2518 gen_addr_register(ctx
);
2520 op_ldsts(lswi
, start
);
2524 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
)
2526 int ra
= rA(ctx
->opcode
);
2527 int rb
= rB(ctx
->opcode
);
2529 /* NIP cannot be restored if the memory exception comes from an helper */
2530 gen_update_nip(ctx
, ctx
->nip
- 4);
2531 gen_addr_reg_index(ctx
);
2535 gen_op_load_xer_bc();
2536 op_ldstsx(lswx
, rD(ctx
->opcode
), ra
, rb
);
2540 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
)
2542 int nb
= NB(ctx
->opcode
);
2544 /* NIP cannot be restored if the memory exception comes from an helper */
2545 gen_update_nip(ctx
, ctx
->nip
- 4);
2546 gen_addr_register(ctx
);
2550 op_ldsts(stsw
, rS(ctx
->opcode
));
2554 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
)
2556 /* NIP cannot be restored if the memory exception comes from an helper */
2557 gen_update_nip(ctx
, ctx
->nip
- 4);
2558 gen_addr_reg_index(ctx
);
2559 gen_op_load_xer_bc();
2560 op_ldsts(stsw
, rS(ctx
->opcode
));
2563 /*** Memory synchronisation ***/
2565 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
)
2570 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
)
2575 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2576 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2577 static GenOpFunc
*gen_op_lwarx
[NB_MEM_FUNCS
] = {
2578 GEN_MEM_FUNCS(lwarx
),
2580 static GenOpFunc
*gen_op_stwcx
[NB_MEM_FUNCS
] = {
2581 GEN_MEM_FUNCS(stwcx
),
2585 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES
)
2587 /* NIP cannot be restored if the memory exception comes from an helper */
2588 gen_update_nip(ctx
, ctx
->nip
- 4);
2589 gen_addr_reg_index(ctx
);
2591 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2595 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
)
2597 /* NIP cannot be restored if the memory exception comes from an helper */
2598 gen_update_nip(ctx
, ctx
->nip
- 4);
2599 gen_addr_reg_index(ctx
);
2600 gen_op_load_gpr_T1(rS(ctx
->opcode
));
2604 #if defined(TARGET_PPC64)
2605 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2606 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2607 static GenOpFunc
*gen_op_ldarx
[NB_MEM_FUNCS
] = {
2608 GEN_MEM_FUNCS(ldarx
),
2610 static GenOpFunc
*gen_op_stdcx
[NB_MEM_FUNCS
] = {
2611 GEN_MEM_FUNCS(stdcx
),
2615 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B
)
2617 /* NIP cannot be restored if the memory exception comes from an helper */
2618 gen_update_nip(ctx
, ctx
->nip
- 4);
2619 gen_addr_reg_index(ctx
);
2621 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2625 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
)
2627 /* NIP cannot be restored if the memory exception comes from an helper */
2628 gen_update_nip(ctx
, ctx
->nip
- 4);
2629 gen_addr_reg_index(ctx
);
2630 gen_op_load_gpr_T1(rS(ctx
->opcode
));
2633 #endif /* defined(TARGET_PPC64) */
2636 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
)
2641 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
)
2643 /* Stop translation, as the CPU is supposed to sleep from now */
2645 GEN_EXCP(ctx
, EXCP_HLT
, 1);
2648 /*** Floating-point load ***/
2649 #define GEN_LDF(width, opc, type) \
2650 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2652 if (unlikely(!ctx->fpu_enabled)) { \
2653 GEN_EXCP_NO_FP(ctx); \
2656 gen_addr_imm_index(ctx, 0); \
2657 op_ldst(l##width); \
2658 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2661 #define GEN_LDUF(width, opc, type) \
2662 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2664 if (unlikely(!ctx->fpu_enabled)) { \
2665 GEN_EXCP_NO_FP(ctx); \
2668 if (unlikely(rA(ctx->opcode) == 0)) { \
2669 GEN_EXCP_INVAL(ctx); \
2672 gen_addr_imm_index(ctx, 0); \
2673 op_ldst(l##width); \
2674 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2675 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2678 #define GEN_LDUXF(width, opc, type) \
2679 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2681 if (unlikely(!ctx->fpu_enabled)) { \
2682 GEN_EXCP_NO_FP(ctx); \
2685 if (unlikely(rA(ctx->opcode) == 0)) { \
2686 GEN_EXCP_INVAL(ctx); \
2689 gen_addr_reg_index(ctx); \
2690 op_ldst(l##width); \
2691 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2692 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2695 #define GEN_LDXF(width, opc2, opc3, type) \
2696 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2698 if (unlikely(!ctx->fpu_enabled)) { \
2699 GEN_EXCP_NO_FP(ctx); \
2702 gen_addr_reg_index(ctx); \
2703 op_ldst(l##width); \
2704 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2707 #define GEN_LDFS(width, op, type) \
2708 OP_LD_TABLE(width); \
2709 GEN_LDF(width, op | 0x20, type); \
2710 GEN_LDUF(width, op | 0x21, type); \
2711 GEN_LDUXF(width, op | 0x01, type); \
2712 GEN_LDXF(width, 0x17, op | 0x00, type)
2714 /* lfd lfdu lfdux lfdx */
2715 GEN_LDFS(fd
, 0x12, PPC_FLOAT
);
2716 /* lfs lfsu lfsux lfsx */
2717 GEN_LDFS(fs
, 0x10, PPC_FLOAT
);
2719 /*** Floating-point store ***/
2720 #define GEN_STF(width, opc, type) \
2721 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2723 if (unlikely(!ctx->fpu_enabled)) { \
2724 GEN_EXCP_NO_FP(ctx); \
2727 gen_addr_imm_index(ctx, 0); \
2728 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2729 op_ldst(st##width); \
2732 #define GEN_STUF(width, opc, type) \
2733 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2735 if (unlikely(!ctx->fpu_enabled)) { \
2736 GEN_EXCP_NO_FP(ctx); \
2739 if (unlikely(rA(ctx->opcode) == 0)) { \
2740 GEN_EXCP_INVAL(ctx); \
2743 gen_addr_imm_index(ctx, 0); \
2744 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2745 op_ldst(st##width); \
2746 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2749 #define GEN_STUXF(width, opc, type) \
2750 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2752 if (unlikely(!ctx->fpu_enabled)) { \
2753 GEN_EXCP_NO_FP(ctx); \
2756 if (unlikely(rA(ctx->opcode) == 0)) { \
2757 GEN_EXCP_INVAL(ctx); \
2760 gen_addr_reg_index(ctx); \
2761 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2762 op_ldst(st##width); \
2763 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2766 #define GEN_STXF(width, opc2, opc3, type) \
2767 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2769 if (unlikely(!ctx->fpu_enabled)) { \
2770 GEN_EXCP_NO_FP(ctx); \
2773 gen_addr_reg_index(ctx); \
2774 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2775 op_ldst(st##width); \
2778 #define GEN_STFS(width, op, type) \
2779 OP_ST_TABLE(width); \
2780 GEN_STF(width, op | 0x20, type); \
2781 GEN_STUF(width, op | 0x21, type); \
2782 GEN_STUXF(width, op | 0x01, type); \
2783 GEN_STXF(width, 0x17, op | 0x00, type)
2785 /* stfd stfdu stfdux stfdx */
2786 GEN_STFS(fd
, 0x16, PPC_FLOAT
);
2787 /* stfs stfsu stfsux stfsx */
2788 GEN_STFS(fs
, 0x14, PPC_FLOAT
);
2793 GEN_STXF(fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
2796 static always_inline
void gen_goto_tb (DisasContext
*ctx
, int n
,
2799 TranslationBlock
*tb
;
2801 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
2803 gen_op_goto_tb0(TBPARAM(tb
));
2805 gen_op_goto_tb1(TBPARAM(tb
));
2807 #if defined(TARGET_PPC64)
2813 gen_op_set_T0((long)tb
+ n
);
2814 if (ctx
->singlestep_enabled
)
2819 #if defined(TARGET_PPC64)
2826 if (ctx
->singlestep_enabled
)
2832 static always_inline
void gen_setlr (DisasContext
*ctx
, target_ulong nip
)
2834 #if defined(TARGET_PPC64)
2835 if (ctx
->sf_mode
!= 0 && (nip
>> 32))
2836 gen_op_setlr_64(ctx
->nip
>> 32, ctx
->nip
);
2839 gen_op_setlr(ctx
->nip
);
2843 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
2845 target_ulong li
, target
;
2847 /* sign extend LI */
2848 #if defined(TARGET_PPC64)
2850 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
2853 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
2854 if (likely(AA(ctx
->opcode
) == 0))
2855 target
= ctx
->nip
+ li
- 4;
2858 #if defined(TARGET_PPC64)
2860 target
= (uint32_t)target
;
2862 if (LK(ctx
->opcode
))
2863 gen_setlr(ctx
, ctx
->nip
);
2864 gen_goto_tb(ctx
, 0, target
);
2865 ctx
->exception
= POWERPC_EXCP_BRANCH
;
2872 static always_inline
void gen_bcond (DisasContext
*ctx
, int type
)
2874 target_ulong target
= 0;
2876 uint32_t bo
= BO(ctx
->opcode
);
2877 uint32_t bi
= BI(ctx
->opcode
);
2880 if ((bo
& 0x4) == 0)
2884 li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
2885 if (likely(AA(ctx
->opcode
) == 0)) {
2886 target
= ctx
->nip
+ li
- 4;
2890 #if defined(TARGET_PPC64)
2892 target
= (uint32_t)target
;
2896 gen_op_movl_T1_ctr();
2900 gen_op_movl_T1_lr();
2903 if (LK(ctx
->opcode
))
2904 gen_setlr(ctx
, ctx
->nip
);
2906 /* No CR condition */
2909 #if defined(TARGET_PPC64)
2911 gen_op_test_ctr_64();
2917 #if defined(TARGET_PPC64)
2919 gen_op_test_ctrz_64();
2927 if (type
== BCOND_IM
) {
2928 gen_goto_tb(ctx
, 0, target
);
2931 #if defined(TARGET_PPC64)
2943 mask
= 1 << (3 - (bi
& 0x03));
2944 gen_op_load_crf_T0(bi
>> 2);
2948 #if defined(TARGET_PPC64)
2950 gen_op_test_ctr_true_64(mask
);
2953 gen_op_test_ctr_true(mask
);
2956 #if defined(TARGET_PPC64)
2958 gen_op_test_ctrz_true_64(mask
);
2961 gen_op_test_ctrz_true(mask
);
2966 gen_op_test_true(mask
);
2972 #if defined(TARGET_PPC64)
2974 gen_op_test_ctr_false_64(mask
);
2977 gen_op_test_ctr_false(mask
);
2980 #if defined(TARGET_PPC64)
2982 gen_op_test_ctrz_false_64(mask
);
2985 gen_op_test_ctrz_false(mask
);
2990 gen_op_test_false(mask
);
2995 if (type
== BCOND_IM
) {
2996 int l1
= gen_new_label();
2998 gen_goto_tb(ctx
, 0, target
);
3000 gen_goto_tb(ctx
, 1, ctx
->nip
);
3002 #if defined(TARGET_PPC64)
3004 gen_op_btest_T1_64(ctx
->nip
>> 32, ctx
->nip
);
3007 gen_op_btest_T1(ctx
->nip
);
3010 if (ctx
->singlestep_enabled
)
3015 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3018 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3020 gen_bcond(ctx
, BCOND_IM
);
3023 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
)
3025 gen_bcond(ctx
, BCOND_CTR
);
3028 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
)
3030 gen_bcond(ctx
, BCOND_LR
);
3033 /*** Condition register logical ***/
3034 #define GEN_CRLOGIC(op, opc) \
3035 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3039 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3040 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3042 gen_op_srli_T0(sh); \
3044 gen_op_sli_T0(-sh); \
3045 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3046 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3048 gen_op_srli_T1(sh); \
3050 gen_op_sli_T1(-sh); \
3052 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3053 gen_op_andi_T0(bitmask); \
3054 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3055 gen_op_andi_T1(~bitmask); \
3057 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
3061 GEN_CRLOGIC(and, 0x08);
3063 GEN_CRLOGIC(andc
, 0x04);
3065 GEN_CRLOGIC(eqv
, 0x09);
3067 GEN_CRLOGIC(nand
, 0x07);
3069 GEN_CRLOGIC(nor
, 0x01);
3071 GEN_CRLOGIC(or, 0x0E);
3073 GEN_CRLOGIC(orc
, 0x0D);
3075 GEN_CRLOGIC(xor, 0x06);
3077 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
)
3079 gen_op_load_crf_T0(crfS(ctx
->opcode
));
3080 gen_op_store_T0_crf(crfD(ctx
->opcode
));
3083 /*** System linkage ***/
3084 /* rfi (supervisor only) */
3085 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
)
3087 #if defined(CONFIG_USER_ONLY)
3088 GEN_EXCP_PRIVOPC(ctx
);
3090 /* Restore CPU state */
3091 if (unlikely(!ctx
->supervisor
)) {
3092 GEN_EXCP_PRIVOPC(ctx
);
3100 #if defined(TARGET_PPC64)
3101 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
)
3103 #if defined(CONFIG_USER_ONLY)
3104 GEN_EXCP_PRIVOPC(ctx
);
3106 /* Restore CPU state */
3107 if (unlikely(!ctx
->supervisor
)) {
3108 GEN_EXCP_PRIVOPC(ctx
);
3116 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
)
3118 #if defined(CONFIG_USER_ONLY)
3119 GEN_EXCP_PRIVOPC(ctx
);
3121 /* Restore CPU state */
3122 if (unlikely(ctx
->supervisor
<= 1)) {
3123 GEN_EXCP_PRIVOPC(ctx
);
3133 #if defined(CONFIG_USER_ONLY)
3134 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3136 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3138 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
)
3142 lev
= (ctx
->opcode
>> 5) & 0x7F;
3143 GEN_EXCP(ctx
, POWERPC_SYSCALL
, lev
);
3148 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
)
3150 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3151 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3152 /* Update the nip since this might generate a trap exception */
3153 gen_update_nip(ctx
, ctx
->nip
);
3154 gen_op_tw(TO(ctx
->opcode
));
3158 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3160 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3161 gen_set_T1(SIMM(ctx
->opcode
));
3162 /* Update the nip since this might generate a trap exception */
3163 gen_update_nip(ctx
, ctx
->nip
);
3164 gen_op_tw(TO(ctx
->opcode
));
3167 #if defined(TARGET_PPC64)
3169 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
)
3171 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3172 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3173 /* Update the nip since this might generate a trap exception */
3174 gen_update_nip(ctx
, ctx
->nip
);
3175 gen_op_td(TO(ctx
->opcode
));
3179 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
)
3181 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3182 gen_set_T1(SIMM(ctx
->opcode
));
3183 /* Update the nip since this might generate a trap exception */
3184 gen_update_nip(ctx
, ctx
->nip
);
3185 gen_op_td(TO(ctx
->opcode
));
3189 /*** Processor control ***/
3191 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
)
3193 gen_op_load_xer_cr();
3194 gen_op_store_T0_crf(crfD(ctx
->opcode
));
3195 gen_op_clear_xer_ov();
3196 gen_op_clear_xer_ca();
3200 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
)
3204 if (likely(ctx
->opcode
& 0x00100000)) {
3205 crm
= CRM(ctx
->opcode
);
3206 if (likely((crm
^ (crm
- 1)) == 0)) {
3208 gen_op_load_cro(7 - crn
);
3213 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3217 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
)
3219 #if defined(CONFIG_USER_ONLY)
3220 GEN_EXCP_PRIVREG(ctx
);
3222 if (unlikely(!ctx
->supervisor
)) {
3223 GEN_EXCP_PRIVREG(ctx
);
3227 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3232 #define SPR_NOACCESS ((void *)(-1UL))
3234 static void spr_noaccess (void *opaque
, int sprn
)
3236 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3237 printf("ERROR: try to access SPR %d !\n", sprn
);
3239 #define SPR_NOACCESS (&spr_noaccess)
3243 static always_inline
void gen_op_mfspr (DisasContext
*ctx
)
3245 void (*read_cb
)(void *opaque
, int sprn
);
3246 uint32_t sprn
= SPR(ctx
->opcode
);
3248 #if !defined(CONFIG_USER_ONLY)
3249 if (ctx
->supervisor
== 2)
3250 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3251 else if (ctx
->supervisor
)
3252 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3255 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3256 if (likely(read_cb
!= NULL
)) {
3257 if (likely(read_cb
!= SPR_NOACCESS
)) {
3258 (*read_cb
)(ctx
, sprn
);
3259 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3261 /* Privilege exception */
3262 /* This is a hack to avoid warnings when running Linux:
3263 * this OS breaks the PowerPC virtualisation model,
3264 * allowing userland application to read the PVR
3266 if (sprn
!= SPR_PVR
) {
3267 if (loglevel
!= 0) {
3268 fprintf(logfile
, "Trying to read privileged spr %d %03x at "
3269 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3271 printf("Trying to read privileged spr %d %03x at " ADDRX
"\n",
3272 sprn
, sprn
, ctx
->nip
);
3274 GEN_EXCP_PRIVREG(ctx
);
3278 if (loglevel
!= 0) {
3279 fprintf(logfile
, "Trying to read invalid spr %d %03x at "
3280 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3282 printf("Trying to read invalid spr %d %03x at " ADDRX
"\n",
3283 sprn
, sprn
, ctx
->nip
);
3284 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
3285 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_SPR
);
3289 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
)
3295 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
)
3301 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
)
3305 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3306 crm
= CRM(ctx
->opcode
);
3307 if (likely((ctx
->opcode
& 0x00100000) || (crm
^ (crm
- 1)) == 0)) {
3309 gen_op_srli_T0(crn
* 4);
3310 gen_op_andi_T0(0xF);
3311 gen_op_store_cro(7 - crn
);
3313 gen_op_store_cr(crm
);
3318 #if defined(TARGET_PPC64)
3319 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
)
3321 #if defined(CONFIG_USER_ONLY)
3322 GEN_EXCP_PRIVREG(ctx
);
3324 if (unlikely(!ctx
->supervisor
)) {
3325 GEN_EXCP_PRIVREG(ctx
);
3328 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3329 if (ctx
->opcode
& 0x00010000) {
3330 /* Special form that does not need any synchronisation */
3331 gen_op_update_riee();
3333 /* XXX: we need to update nip before the store
3334 * if we enter power saving mode, we will exit the loop
3335 * directly from ppc_store_msr
3337 gen_update_nip(ctx
, ctx
->nip
);
3339 /* Must stop the translation as machine state (may have) changed */
3340 /* Note that mtmsr is not always defined as context-synchronizing */
3341 ctx
->exception
= POWERPC_EXCP_STOP
;
3347 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
)
3349 #if defined(CONFIG_USER_ONLY)
3350 GEN_EXCP_PRIVREG(ctx
);
3352 if (unlikely(!ctx
->supervisor
)) {
3353 GEN_EXCP_PRIVREG(ctx
);
3356 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3357 if (ctx
->opcode
& 0x00010000) {
3358 /* Special form that does not need any synchronisation */
3359 gen_op_update_riee();
3361 /* XXX: we need to update nip before the store
3362 * if we enter power saving mode, we will exit the loop
3363 * directly from ppc_store_msr
3365 gen_update_nip(ctx
, ctx
->nip
);
3366 #if defined(TARGET_PPC64)
3368 gen_op_store_msr_32();
3372 /* Must stop the translation as machine state (may have) changed */
3373 /* Note that mtmsrd is not always defined as context-synchronizing */
3374 ctx
->exception
= POWERPC_EXCP_STOP
;
3380 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
)
3382 void (*write_cb
)(void *opaque
, int sprn
);
3383 uint32_t sprn
= SPR(ctx
->opcode
);
3385 #if !defined(CONFIG_USER_ONLY)
3386 if (ctx
->supervisor
== 2)
3387 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
3388 else if (ctx
->supervisor
)
3389 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
3392 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
3393 if (likely(write_cb
!= NULL
)) {
3394 if (likely(write_cb
!= SPR_NOACCESS
)) {
3395 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3396 (*write_cb
)(ctx
, sprn
);
3398 /* Privilege exception */
3399 if (loglevel
!= 0) {
3400 fprintf(logfile
, "Trying to write privileged spr %d %03x at "
3401 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3403 printf("Trying to write privileged spr %d %03x at " ADDRX
"\n",
3404 sprn
, sprn
, ctx
->nip
);
3405 GEN_EXCP_PRIVREG(ctx
);
3409 if (loglevel
!= 0) {
3410 fprintf(logfile
, "Trying to write invalid spr %d %03x at "
3411 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3413 printf("Trying to write invalid spr %d %03x at " ADDRX
"\n",
3414 sprn
, sprn
, ctx
->nip
);
3415 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
3416 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_SPR
);
3420 /*** Cache management ***/
3422 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
)
3424 /* XXX: specification says this is treated as a load by the MMU */
3425 gen_addr_reg_index(ctx
);
3429 /* dcbi (Supervisor only) */
3430 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
)
3432 #if defined(CONFIG_USER_ONLY)
3433 GEN_EXCP_PRIVOPC(ctx
);
3435 if (unlikely(!ctx
->supervisor
)) {
3436 GEN_EXCP_PRIVOPC(ctx
);
3439 gen_addr_reg_index(ctx
);
3440 /* XXX: specification says this should be treated as a store by the MMU */
3447 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
)
3449 /* XXX: specification say this is treated as a load by the MMU */
3450 gen_addr_reg_index(ctx
);
3455 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
)
3457 /* interpreted as no-op */
3458 /* XXX: specification say this is treated as a load by the MMU
3459 * but does not generate any exception
3464 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
)
3466 /* interpreted as no-op */
3467 /* XXX: specification say this is treated as a load by the MMU
3468 * but does not generate any exception
3473 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3474 static GenOpFunc
*gen_op_dcbz
[4][NB_MEM_FUNCS
] = {
3475 /* 32 bytes cache line size */
3477 #define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3478 #define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3479 #define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3480 #define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3481 #define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3482 #define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3483 #define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3484 #define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3485 GEN_MEM_FUNCS(dcbz_l32
),
3487 /* 64 bytes cache line size */
3489 #define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3490 #define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3491 #define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3492 #define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3493 #define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3494 #define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3495 #define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3496 #define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3497 GEN_MEM_FUNCS(dcbz_l64
),
3499 /* 128 bytes cache line size */
3501 #define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3502 #define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3503 #define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3504 #define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3505 #define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3506 #define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3507 #define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3508 #define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3509 GEN_MEM_FUNCS(dcbz_l128
),
3511 /* tunable cache line size */
3513 #define gen_op_dcbz_le_raw gen_op_dcbz_raw
3514 #define gen_op_dcbz_le_user gen_op_dcbz_user
3515 #define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3516 #define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3517 #define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3518 #define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3519 #define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3520 #define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3521 GEN_MEM_FUNCS(dcbz
),
3525 static always_inline
void handler_dcbz (DisasContext
*ctx
,
3526 int dcache_line_size
)
3530 switch (dcache_line_size
) {
3547 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ
)
3549 gen_addr_reg_index(ctx
);
3550 handler_dcbz(ctx
, ctx
->dcache_line_size
);
3551 gen_op_check_reservation();
3554 GEN_HANDLER2(dcbz_970
, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT
)
3556 gen_addr_reg_index(ctx
);
3557 if (ctx
->opcode
& 0x00200000)
3558 handler_dcbz(ctx
, ctx
->dcache_line_size
);
3560 handler_dcbz(ctx
, -1);
3561 gen_op_check_reservation();
3565 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3566 #define gen_op_icbi_le_raw gen_op_icbi_raw
3567 #define gen_op_icbi_le_user gen_op_icbi_user
3568 #define gen_op_icbi_le_kernel gen_op_icbi_kernel
3569 #define gen_op_icbi_le_hypv gen_op_icbi_hypv
3570 #define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3571 #define gen_op_icbi_le_64_user gen_op_icbi_64_user
3572 #define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3573 #define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3574 static GenOpFunc
*gen_op_icbi
[NB_MEM_FUNCS
] = {
3575 GEN_MEM_FUNCS(icbi
),
3578 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
)
3580 /* NIP cannot be restored if the memory exception comes from an helper */
3581 gen_update_nip(ctx
, ctx
->nip
- 4);
3582 gen_addr_reg_index(ctx
);
3588 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
)
3590 /* interpreted as no-op */
3591 /* XXX: specification say this is treated as a store by the MMU
3592 * but does not generate any exception
3596 /*** Segment register manipulation ***/
3597 /* Supervisor only: */
3599 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
)
3601 #if defined(CONFIG_USER_ONLY)
3602 GEN_EXCP_PRIVREG(ctx
);
3604 if (unlikely(!ctx
->supervisor
)) {
3605 GEN_EXCP_PRIVREG(ctx
);
3608 gen_op_set_T1(SR(ctx
->opcode
));
3610 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3615 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
)
3617 #if defined(CONFIG_USER_ONLY)
3618 GEN_EXCP_PRIVREG(ctx
);
3620 if (unlikely(!ctx
->supervisor
)) {
3621 GEN_EXCP_PRIVREG(ctx
);
3624 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3627 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3632 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
)
3634 #if defined(CONFIG_USER_ONLY)
3635 GEN_EXCP_PRIVREG(ctx
);
3637 if (unlikely(!ctx
->supervisor
)) {
3638 GEN_EXCP_PRIVREG(ctx
);
3641 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3642 gen_op_set_T1(SR(ctx
->opcode
));
3648 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
)
3650 #if defined(CONFIG_USER_ONLY)
3651 GEN_EXCP_PRIVREG(ctx
);
3653 if (unlikely(!ctx
->supervisor
)) {
3654 GEN_EXCP_PRIVREG(ctx
);
3657 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3658 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3664 #if defined(TARGET_PPC64)
3665 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3667 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
)
3669 #if defined(CONFIG_USER_ONLY)
3670 GEN_EXCP_PRIVREG(ctx
);
3672 if (unlikely(!ctx
->supervisor
)) {
3673 GEN_EXCP_PRIVREG(ctx
);
3676 gen_op_set_T1(SR(ctx
->opcode
));
3678 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3683 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3686 #if defined(CONFIG_USER_ONLY)
3687 GEN_EXCP_PRIVREG(ctx
);
3689 if (unlikely(!ctx
->supervisor
)) {
3690 GEN_EXCP_PRIVREG(ctx
);
3693 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3696 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3701 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
)
3703 #if defined(CONFIG_USER_ONLY)
3704 GEN_EXCP_PRIVREG(ctx
);
3706 if (unlikely(!ctx
->supervisor
)) {
3707 GEN_EXCP_PRIVREG(ctx
);
3710 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3711 gen_op_set_T1(SR(ctx
->opcode
));
3717 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3720 #if defined(CONFIG_USER_ONLY)
3721 GEN_EXCP_PRIVREG(ctx
);
3723 if (unlikely(!ctx
->supervisor
)) {
3724 GEN_EXCP_PRIVREG(ctx
);
3727 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3728 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3733 #endif /* defined(TARGET_PPC64) */
3735 /*** Lookaside buffer management ***/
3736 /* Optional & supervisor only: */
3738 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
)
3740 #if defined(CONFIG_USER_ONLY)
3741 GEN_EXCP_PRIVOPC(ctx
);
3743 if (unlikely(!ctx
->supervisor
)) {
3744 GEN_EXCP_PRIVOPC(ctx
);
3752 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
)
3754 #if defined(CONFIG_USER_ONLY)
3755 GEN_EXCP_PRIVOPC(ctx
);
3757 if (unlikely(!ctx
->supervisor
)) {
3758 GEN_EXCP_PRIVOPC(ctx
);
3761 gen_op_load_gpr_T0(rB(ctx
->opcode
));
3762 #if defined(TARGET_PPC64)
3772 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
)
3774 #if defined(CONFIG_USER_ONLY)
3775 GEN_EXCP_PRIVOPC(ctx
);
3777 if (unlikely(!ctx
->supervisor
)) {
3778 GEN_EXCP_PRIVOPC(ctx
);
3781 /* This has no effect: it should ensure that all previous
3782 * tlbie have completed
3788 #if defined(TARGET_PPC64)
3790 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
)
3792 #if defined(CONFIG_USER_ONLY)
3793 GEN_EXCP_PRIVOPC(ctx
);
3795 if (unlikely(!ctx
->supervisor
)) {
3796 GEN_EXCP_PRIVOPC(ctx
);
3804 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
)
3806 #if defined(CONFIG_USER_ONLY)
3807 GEN_EXCP_PRIVOPC(ctx
);
3809 if (unlikely(!ctx
->supervisor
)) {
3810 GEN_EXCP_PRIVOPC(ctx
);
3813 gen_op_load_gpr_T0(rB(ctx
->opcode
));
3819 /*** External control ***/
3821 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3822 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
3823 static GenOpFunc
*gen_op_eciwx
[NB_MEM_FUNCS
] = {
3824 GEN_MEM_FUNCS(eciwx
),
3826 static GenOpFunc
*gen_op_ecowx
[NB_MEM_FUNCS
] = {
3827 GEN_MEM_FUNCS(ecowx
),
3831 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
)
3833 /* Should check EAR[E] & alignment ! */
3834 gen_addr_reg_index(ctx
);
3836 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3840 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
)
3842 /* Should check EAR[E] & alignment ! */
3843 gen_addr_reg_index(ctx
);
3844 gen_op_load_gpr_T1(rS(ctx
->opcode
));
3848 /* PowerPC 601 specific instructions */
3850 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
)
3852 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3854 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3855 if (unlikely(Rc(ctx
->opcode
) != 0))
3860 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
)
3862 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3863 gen_op_POWER_abso();
3864 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3865 if (unlikely(Rc(ctx
->opcode
) != 0))
3870 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
)
3872 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3873 gen_op_POWER_clcs();
3874 /* Rc=1 sets CR0 to an undefined state */
3875 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3879 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
)
3881 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3882 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3884 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3885 if (unlikely(Rc(ctx
->opcode
) != 0))
3890 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
)
3892 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3893 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3894 gen_op_POWER_divo();
3895 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3896 if (unlikely(Rc(ctx
->opcode
) != 0))
3901 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
)
3903 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3904 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3905 gen_op_POWER_divs();
3906 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3907 if (unlikely(Rc(ctx
->opcode
) != 0))
3911 /* divso - divso. */
3912 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
)
3914 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3915 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3916 gen_op_POWER_divso();
3917 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3918 if (unlikely(Rc(ctx
->opcode
) != 0))
3923 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
)
3925 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3926 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3928 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3929 if (unlikely(Rc(ctx
->opcode
) != 0))
3934 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
)
3936 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3937 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3938 gen_op_POWER_dozo();
3939 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3940 if (unlikely(Rc(ctx
->opcode
) != 0))
3945 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
3947 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3948 gen_op_set_T1(SIMM(ctx
->opcode
));
3950 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3953 /* As lscbx load from memory byte after byte, it's always endian safe.
3954 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3956 #define op_POWER_lscbx(start, ra, rb) \
3957 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
3958 #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
3959 #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
3960 #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
3961 #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
3962 #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
3963 #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
3964 #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
3965 #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
3966 #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
3967 #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
3968 #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
3969 #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
3970 static GenOpFunc3
*gen_op_POWER_lscbx
[NB_MEM_FUNCS
] = {
3971 GEN_MEM_FUNCS(POWER_lscbx
),
3974 /* lscbx - lscbx. */
3975 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
)
3977 int ra
= rA(ctx
->opcode
);
3978 int rb
= rB(ctx
->opcode
);
3980 gen_addr_reg_index(ctx
);
3984 /* NIP cannot be restored if the memory exception comes from an helper */
3985 gen_update_nip(ctx
, ctx
->nip
- 4);
3986 gen_op_load_xer_bc();
3987 gen_op_load_xer_cmp();
3988 op_POWER_lscbx(rD(ctx
->opcode
), ra
, rb
);
3989 gen_op_store_xer_bc();
3990 if (unlikely(Rc(ctx
->opcode
) != 0))
3994 /* maskg - maskg. */
3995 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
)
3997 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3998 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3999 gen_op_POWER_maskg();
4000 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4001 if (unlikely(Rc(ctx
->opcode
) != 0))
4005 /* maskir - maskir. */
4006 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
)
4008 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4009 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4010 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4011 gen_op_POWER_maskir();
4012 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4013 if (unlikely(Rc(ctx
->opcode
) != 0))
4018 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
)
4020 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4021 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4023 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4024 if (unlikely(Rc(ctx
->opcode
) != 0))
4029 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
)
4031 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4032 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4033 gen_op_POWER_mulo();
4034 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4035 if (unlikely(Rc(ctx
->opcode
) != 0))
4040 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
)
4042 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4043 gen_op_POWER_nabs();
4044 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4045 if (unlikely(Rc(ctx
->opcode
) != 0))
4049 /* nabso - nabso. */
4050 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
)
4052 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4053 gen_op_POWER_nabso();
4054 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4055 if (unlikely(Rc(ctx
->opcode
) != 0))
4060 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
4064 mb
= MB(ctx
->opcode
);
4065 me
= ME(ctx
->opcode
);
4066 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4067 gen_op_load_gpr_T1(rA(ctx
->opcode
));
4068 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4069 gen_op_POWER_rlmi(MASK(mb
, me
), ~MASK(mb
, me
));
4070 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4071 if (unlikely(Rc(ctx
->opcode
) != 0))
4076 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
)
4078 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4079 gen_op_load_gpr_T1(rA(ctx
->opcode
));
4080 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4081 gen_op_POWER_rrib();
4082 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4083 if (unlikely(Rc(ctx
->opcode
) != 0))
4088 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
)
4090 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4091 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4093 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4094 if (unlikely(Rc(ctx
->opcode
) != 0))
4099 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
)
4101 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4102 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4103 gen_op_POWER_sleq();
4104 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4105 if (unlikely(Rc(ctx
->opcode
) != 0))
4110 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
)
4112 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4113 gen_op_set_T1(SH(ctx
->opcode
));
4115 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4116 if (unlikely(Rc(ctx
->opcode
) != 0))
4120 /* slliq - slliq. */
4121 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
)
4123 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4124 gen_op_set_T1(SH(ctx
->opcode
));
4125 gen_op_POWER_sleq();
4126 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4127 if (unlikely(Rc(ctx
->opcode
) != 0))
4132 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
)
4134 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4135 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4136 gen_op_POWER_sllq();
4137 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4138 if (unlikely(Rc(ctx
->opcode
) != 0))
4143 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
)
4145 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4146 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4148 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4149 if (unlikely(Rc(ctx
->opcode
) != 0))
4153 /* sraiq - sraiq. */
4154 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
)
4156 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4157 gen_op_set_T1(SH(ctx
->opcode
));
4158 gen_op_POWER_sraq();
4159 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4160 if (unlikely(Rc(ctx
->opcode
) != 0))
4165 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
)
4167 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4168 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4169 gen_op_POWER_sraq();
4170 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4171 if (unlikely(Rc(ctx
->opcode
) != 0))
4176 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
)
4178 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4179 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4181 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4182 if (unlikely(Rc(ctx
->opcode
) != 0))
4187 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
)
4189 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4190 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4191 gen_op_POWER_srea();
4192 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4193 if (unlikely(Rc(ctx
->opcode
) != 0))
4198 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
)
4200 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4201 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4202 gen_op_POWER_sreq();
4203 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4204 if (unlikely(Rc(ctx
->opcode
) != 0))
4209 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
)
4211 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4212 gen_op_set_T1(SH(ctx
->opcode
));
4214 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4215 if (unlikely(Rc(ctx
->opcode
) != 0))
4220 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
)
4222 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4223 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4224 gen_op_set_T1(SH(ctx
->opcode
));
4225 gen_op_POWER_srlq();
4226 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4227 if (unlikely(Rc(ctx
->opcode
) != 0))
4232 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
)
4234 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4235 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4236 gen_op_POWER_srlq();
4237 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4238 if (unlikely(Rc(ctx
->opcode
) != 0))
4243 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
)
4245 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4246 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4248 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4249 if (unlikely(Rc(ctx
->opcode
) != 0))
4253 /* PowerPC 602 specific instructions */
4255 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
)
4258 GEN_EXCP_INVAL(ctx
);
4262 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
)
4265 GEN_EXCP_INVAL(ctx
);
4269 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
)
4271 #if defined(CONFIG_USER_ONLY)
4272 GEN_EXCP_PRIVOPC(ctx
);
4274 if (unlikely(!ctx
->supervisor
)) {
4275 GEN_EXCP_PRIVOPC(ctx
);
4278 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4280 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4284 /* 602 - 603 - G2 TLB management */
4286 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
)
4288 #if defined(CONFIG_USER_ONLY)
4289 GEN_EXCP_PRIVOPC(ctx
);
4291 if (unlikely(!ctx
->supervisor
)) {
4292 GEN_EXCP_PRIVOPC(ctx
);
4295 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4301 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
)
4303 #if defined(CONFIG_USER_ONLY)
4304 GEN_EXCP_PRIVOPC(ctx
);
4306 if (unlikely(!ctx
->supervisor
)) {
4307 GEN_EXCP_PRIVOPC(ctx
);
4310 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4315 /* 74xx TLB management */
4317 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
)
4319 #if defined(CONFIG_USER_ONLY)
4320 GEN_EXCP_PRIVOPC(ctx
);
4322 if (unlikely(!ctx
->supervisor
)) {
4323 GEN_EXCP_PRIVOPC(ctx
);
4326 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4327 gen_op_74xx_tlbld();
4332 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
)
4334 #if defined(CONFIG_USER_ONLY)
4335 GEN_EXCP_PRIVOPC(ctx
);
4337 if (unlikely(!ctx
->supervisor
)) {
4338 GEN_EXCP_PRIVOPC(ctx
);
4341 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4342 gen_op_74xx_tlbli();
4346 /* POWER instructions not in PowerPC 601 */
4348 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
)
4350 /* Cache line flush: implemented as no-op */
4354 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
)
4356 /* Cache line invalidate: privileged and treated as no-op */
4357 #if defined(CONFIG_USER_ONLY)
4358 GEN_EXCP_PRIVOPC(ctx
);
4360 if (unlikely(!ctx
->supervisor
)) {
4361 GEN_EXCP_PRIVOPC(ctx
);
4368 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
)
4370 /* Data cache line store: treated as no-op */
4373 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
)
4375 #if defined(CONFIG_USER_ONLY)
4376 GEN_EXCP_PRIVOPC(ctx
);
4378 if (unlikely(!ctx
->supervisor
)) {
4379 GEN_EXCP_PRIVOPC(ctx
);
4382 int ra
= rA(ctx
->opcode
);
4383 int rd
= rD(ctx
->opcode
);
4385 gen_addr_reg_index(ctx
);
4386 gen_op_POWER_mfsri();
4387 gen_op_store_T0_gpr(rd
);
4388 if (ra
!= 0 && ra
!= rd
)
4389 gen_op_store_T1_gpr(ra
);
4393 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
)
4395 #if defined(CONFIG_USER_ONLY)
4396 GEN_EXCP_PRIVOPC(ctx
);
4398 if (unlikely(!ctx
->supervisor
)) {
4399 GEN_EXCP_PRIVOPC(ctx
);
4402 gen_addr_reg_index(ctx
);
4404 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4408 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
)
4410 #if defined(CONFIG_USER_ONLY)
4411 GEN_EXCP_PRIVOPC(ctx
);
4413 if (unlikely(!ctx
->supervisor
)) {
4414 GEN_EXCP_PRIVOPC(ctx
);
4417 gen_op_POWER_rfsvc();
4422 /* svc is not implemented for now */
4424 /* POWER2 specific instructions */
4425 /* Quad manipulation (load/store two floats at a time) */
4426 /* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
4427 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4428 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4429 #define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4430 #define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4431 #define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4432 #define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4433 #define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4434 #define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4435 #define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4436 #define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4437 #define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4438 #define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4439 #define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4440 #define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4441 #define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4442 #define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4443 #define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4444 #define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4445 static GenOpFunc
*gen_op_POWER2_lfq
[NB_MEM_FUNCS
] = {
4446 GEN_MEM_FUNCS(POWER2_lfq
),
4448 static GenOpFunc
*gen_op_POWER2_stfq
[NB_MEM_FUNCS
] = {
4449 GEN_MEM_FUNCS(POWER2_stfq
),
4453 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4455 /* NIP cannot be restored if the memory exception comes from an helper */
4456 gen_update_nip(ctx
, ctx
->nip
- 4);
4457 gen_addr_imm_index(ctx
, 0);
4459 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4460 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4464 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4466 int ra
= rA(ctx
->opcode
);
4468 /* NIP cannot be restored if the memory exception comes from an helper */
4469 gen_update_nip(ctx
, ctx
->nip
- 4);
4470 gen_addr_imm_index(ctx
, 0);
4472 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4473 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4475 gen_op_store_T0_gpr(ra
);
4479 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
)
4481 int ra
= rA(ctx
->opcode
);
4483 /* NIP cannot be restored if the memory exception comes from an helper */
4484 gen_update_nip(ctx
, ctx
->nip
- 4);
4485 gen_addr_reg_index(ctx
);
4487 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4488 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4490 gen_op_store_T0_gpr(ra
);
4494 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
)
4496 /* NIP cannot be restored if the memory exception comes from an helper */
4497 gen_update_nip(ctx
, ctx
->nip
- 4);
4498 gen_addr_reg_index(ctx
);
4500 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4501 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4505 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4507 /* NIP cannot be restored if the memory exception comes from an helper */
4508 gen_update_nip(ctx
, ctx
->nip
- 4);
4509 gen_addr_imm_index(ctx
, 0);
4510 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4511 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4516 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4518 int ra
= rA(ctx
->opcode
);
4520 /* NIP cannot be restored if the memory exception comes from an helper */
4521 gen_update_nip(ctx
, ctx
->nip
- 4);
4522 gen_addr_imm_index(ctx
, 0);
4523 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4524 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4527 gen_op_store_T0_gpr(ra
);
4531 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
)
4533 int ra
= rA(ctx
->opcode
);
4535 /* NIP cannot be restored if the memory exception comes from an helper */
4536 gen_update_nip(ctx
, ctx
->nip
- 4);
4537 gen_addr_reg_index(ctx
);
4538 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4539 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4542 gen_op_store_T0_gpr(ra
);
4546 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
)
4548 /* NIP cannot be restored if the memory exception comes from an helper */
4549 gen_update_nip(ctx
, ctx
->nip
- 4);
4550 gen_addr_reg_index(ctx
);
4551 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4552 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4556 /* BookE specific instructions */
4557 /* XXX: not implemented on 440 ? */
4558 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
)
4561 GEN_EXCP_INVAL(ctx
);
4564 /* XXX: not implemented on 440 ? */
4565 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
)
4567 #if defined(CONFIG_USER_ONLY)
4568 GEN_EXCP_PRIVOPC(ctx
);
4570 if (unlikely(!ctx
->supervisor
)) {
4571 GEN_EXCP_PRIVOPC(ctx
);
4574 gen_addr_reg_index(ctx
);
4575 /* Use the same micro-ops as for tlbie */
4576 #if defined(TARGET_PPC64)
4585 /* All 405 MAC instructions are translated here */
4586 static always_inline
void gen_405_mulladd_insn (DisasContext
*ctx
,
4588 int ra
, int rb
, int rt
, int Rc
)
4590 gen_op_load_gpr_T0(ra
);
4591 gen_op_load_gpr_T1(rb
);
4592 switch (opc3
& 0x0D) {
4594 /* macchw - macchw. - macchwo - macchwo. */
4595 /* macchws - macchws. - macchwso - macchwso. */
4596 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4597 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4598 /* mulchw - mulchw. */
4599 gen_op_405_mulchw();
4602 /* macchwu - macchwu. - macchwuo - macchwuo. */
4603 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4604 /* mulchwu - mulchwu. */
4605 gen_op_405_mulchwu();
4608 /* machhw - machhw. - machhwo - machhwo. */
4609 /* machhws - machhws. - machhwso - machhwso. */
4610 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4611 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4612 /* mulhhw - mulhhw. */
4613 gen_op_405_mulhhw();
4616 /* machhwu - machhwu. - machhwuo - machhwuo. */
4617 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4618 /* mulhhwu - mulhhwu. */
4619 gen_op_405_mulhhwu();
4622 /* maclhw - maclhw. - maclhwo - maclhwo. */
4623 /* maclhws - maclhws. - maclhwso - maclhwso. */
4624 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4625 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4626 /* mullhw - mullhw. */
4627 gen_op_405_mullhw();
4630 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4631 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4632 /* mullhwu - mullhwu. */
4633 gen_op_405_mullhwu();
4637 /* nmultiply-and-accumulate (0x0E) */
4641 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4642 gen_op_load_gpr_T2(rt
);
4643 gen_op_move_T1_T0();
4644 gen_op_405_add_T0_T2();
4647 /* Check overflow */
4649 gen_op_check_addo();
4651 gen_op_405_check_ovu();
4656 gen_op_405_check_sat();
4658 gen_op_405_check_satu();
4660 gen_op_store_T0_gpr(rt
);
4661 if (unlikely(Rc
) != 0) {
4667 #define GEN_MAC_HANDLER(name, opc2, opc3) \
4668 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
4670 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4671 rD(ctx->opcode), Rc(ctx->opcode)); \
4674 /* macchw - macchw. */
4675 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
4676 /* macchwo - macchwo. */
4677 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
4678 /* macchws - macchws. */
4679 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
4680 /* macchwso - macchwso. */
4681 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
4682 /* macchwsu - macchwsu. */
4683 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
4684 /* macchwsuo - macchwsuo. */
4685 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
4686 /* macchwu - macchwu. */
4687 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
4688 /* macchwuo - macchwuo. */
4689 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
4690 /* machhw - machhw. */
4691 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
4692 /* machhwo - machhwo. */
4693 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
4694 /* machhws - machhws. */
4695 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
4696 /* machhwso - machhwso. */
4697 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
4698 /* machhwsu - machhwsu. */
4699 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
4700 /* machhwsuo - machhwsuo. */
4701 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
4702 /* machhwu - machhwu. */
4703 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
4704 /* machhwuo - machhwuo. */
4705 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
4706 /* maclhw - maclhw. */
4707 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
4708 /* maclhwo - maclhwo. */
4709 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
4710 /* maclhws - maclhws. */
4711 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
4712 /* maclhwso - maclhwso. */
4713 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
4714 /* maclhwu - maclhwu. */
4715 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
4716 /* maclhwuo - maclhwuo. */
4717 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
4718 /* maclhwsu - maclhwsu. */
4719 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
4720 /* maclhwsuo - maclhwsuo. */
4721 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
4722 /* nmacchw - nmacchw. */
4723 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
4724 /* nmacchwo - nmacchwo. */
4725 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
4726 /* nmacchws - nmacchws. */
4727 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
4728 /* nmacchwso - nmacchwso. */
4729 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
4730 /* nmachhw - nmachhw. */
4731 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
4732 /* nmachhwo - nmachhwo. */
4733 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
4734 /* nmachhws - nmachhws. */
4735 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
4736 /* nmachhwso - nmachhwso. */
4737 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
4738 /* nmaclhw - nmaclhw. */
4739 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
4740 /* nmaclhwo - nmaclhwo. */
4741 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
4742 /* nmaclhws - nmaclhws. */
4743 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
4744 /* nmaclhwso - nmaclhwso. */
4745 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
4747 /* mulchw - mulchw. */
4748 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
4749 /* mulchwu - mulchwu. */
4750 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
4751 /* mulhhw - mulhhw. */
4752 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
4753 /* mulhhwu - mulhhwu. */
4754 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
4755 /* mullhw - mullhw. */
4756 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
4757 /* mullhwu - mullhwu. */
4758 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
4761 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
)
4763 #if defined(CONFIG_USER_ONLY)
4764 GEN_EXCP_PRIVREG(ctx
);
4766 uint32_t dcrn
= SPR(ctx
->opcode
);
4768 if (unlikely(!ctx
->supervisor
)) {
4769 GEN_EXCP_PRIVREG(ctx
);
4772 gen_op_set_T0(dcrn
);
4774 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4779 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
)
4781 #if defined(CONFIG_USER_ONLY)
4782 GEN_EXCP_PRIVREG(ctx
);
4784 uint32_t dcrn
= SPR(ctx
->opcode
);
4786 if (unlikely(!ctx
->supervisor
)) {
4787 GEN_EXCP_PRIVREG(ctx
);
4790 gen_op_set_T0(dcrn
);
4791 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4797 /* XXX: not implemented on 440 ? */
4798 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
)
4800 #if defined(CONFIG_USER_ONLY)
4801 GEN_EXCP_PRIVREG(ctx
);
4803 if (unlikely(!ctx
->supervisor
)) {
4804 GEN_EXCP_PRIVREG(ctx
);
4807 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4809 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4810 /* Note: Rc update flag set leads to undefined state of Rc0 */
4815 /* XXX: not implemented on 440 ? */
4816 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
)
4818 #if defined(CONFIG_USER_ONLY)
4819 GEN_EXCP_PRIVREG(ctx
);
4821 if (unlikely(!ctx
->supervisor
)) {
4822 GEN_EXCP_PRIVREG(ctx
);
4825 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4826 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4828 /* Note: Rc update flag set leads to undefined state of Rc0 */
4832 /* mfdcrux (PPC 460) : user-mode access to DCR */
4833 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
)
4835 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4837 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4838 /* Note: Rc update flag set leads to undefined state of Rc0 */
4841 /* mtdcrux (PPC 460) : user-mode access to DCR */
4842 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
)
4844 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4845 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4847 /* Note: Rc update flag set leads to undefined state of Rc0 */
4851 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
)
4853 #if defined(CONFIG_USER_ONLY)
4854 GEN_EXCP_PRIVOPC(ctx
);
4856 if (unlikely(!ctx
->supervisor
)) {
4857 GEN_EXCP_PRIVOPC(ctx
);
4860 /* interpreted as no-op */
4865 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
)
4867 #if defined(CONFIG_USER_ONLY)
4868 GEN_EXCP_PRIVOPC(ctx
);
4870 if (unlikely(!ctx
->supervisor
)) {
4871 GEN_EXCP_PRIVOPC(ctx
);
4874 gen_addr_reg_index(ctx
);
4876 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4881 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
)
4883 /* interpreted as no-op */
4884 /* XXX: specification say this is treated as a load by the MMU
4885 * but does not generate any exception
4890 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
)
4892 #if defined(CONFIG_USER_ONLY)
4893 GEN_EXCP_PRIVOPC(ctx
);
4895 if (unlikely(!ctx
->supervisor
)) {
4896 GEN_EXCP_PRIVOPC(ctx
);
4899 /* interpreted as no-op */
4904 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
)
4906 #if defined(CONFIG_USER_ONLY)
4907 GEN_EXCP_PRIVOPC(ctx
);
4909 if (unlikely(!ctx
->supervisor
)) {
4910 GEN_EXCP_PRIVOPC(ctx
);
4913 /* interpreted as no-op */
4917 /* rfci (supervisor only) */
4918 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
)
4920 #if defined(CONFIG_USER_ONLY)
4921 GEN_EXCP_PRIVOPC(ctx
);
4923 if (unlikely(!ctx
->supervisor
)) {
4924 GEN_EXCP_PRIVOPC(ctx
);
4927 /* Restore CPU state */
4933 GEN_HANDLER(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
)
4935 #if defined(CONFIG_USER_ONLY)
4936 GEN_EXCP_PRIVOPC(ctx
);
4938 if (unlikely(!ctx
->supervisor
)) {
4939 GEN_EXCP_PRIVOPC(ctx
);
4942 /* Restore CPU state */
4948 /* BookE specific */
4949 /* XXX: not implemented on 440 ? */
4950 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
)
4952 #if defined(CONFIG_USER_ONLY)
4953 GEN_EXCP_PRIVOPC(ctx
);
4955 if (unlikely(!ctx
->supervisor
)) {
4956 GEN_EXCP_PRIVOPC(ctx
);
4959 /* Restore CPU state */
4965 /* XXX: not implemented on 440 ? */
4966 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
)
4968 #if defined(CONFIG_USER_ONLY)
4969 GEN_EXCP_PRIVOPC(ctx
);
4971 if (unlikely(!ctx
->supervisor
)) {
4972 GEN_EXCP_PRIVOPC(ctx
);
4975 /* Restore CPU state */
4981 /* TLB management - PowerPC 405 implementation */
4983 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
)
4985 #if defined(CONFIG_USER_ONLY)
4986 GEN_EXCP_PRIVOPC(ctx
);
4988 if (unlikely(!ctx
->supervisor
)) {
4989 GEN_EXCP_PRIVOPC(ctx
);
4992 switch (rB(ctx
->opcode
)) {
4994 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4995 gen_op_4xx_tlbre_hi();
4996 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4999 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5000 gen_op_4xx_tlbre_lo();
5001 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5004 GEN_EXCP_INVAL(ctx
);
5010 /* tlbsx - tlbsx. */
5011 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
)
5013 #if defined(CONFIG_USER_ONLY)
5014 GEN_EXCP_PRIVOPC(ctx
);
5016 if (unlikely(!ctx
->supervisor
)) {
5017 GEN_EXCP_PRIVOPC(ctx
);
5020 gen_addr_reg_index(ctx
);
5022 if (Rc(ctx
->opcode
))
5023 gen_op_4xx_tlbsx_check();
5024 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5029 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
)
5031 #if defined(CONFIG_USER_ONLY)
5032 GEN_EXCP_PRIVOPC(ctx
);
5034 if (unlikely(!ctx
->supervisor
)) {
5035 GEN_EXCP_PRIVOPC(ctx
);
5038 switch (rB(ctx
->opcode
)) {
5040 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5041 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5042 gen_op_4xx_tlbwe_hi();
5045 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5046 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5047 gen_op_4xx_tlbwe_lo();
5050 GEN_EXCP_INVAL(ctx
);
5056 /* TLB management - PowerPC 440 implementation */
5058 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
)
5060 #if defined(CONFIG_USER_ONLY)
5061 GEN_EXCP_PRIVOPC(ctx
);
5063 if (unlikely(!ctx
->supervisor
)) {
5064 GEN_EXCP_PRIVOPC(ctx
);
5067 switch (rB(ctx
->opcode
)) {
5071 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5072 gen_op_440_tlbre(rB(ctx
->opcode
));
5073 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5076 GEN_EXCP_INVAL(ctx
);
5082 /* tlbsx - tlbsx. */
5083 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
)
5085 #if defined(CONFIG_USER_ONLY)
5086 GEN_EXCP_PRIVOPC(ctx
);
5088 if (unlikely(!ctx
->supervisor
)) {
5089 GEN_EXCP_PRIVOPC(ctx
);
5092 gen_addr_reg_index(ctx
);
5094 if (Rc(ctx
->opcode
))
5095 gen_op_4xx_tlbsx_check();
5096 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5101 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
)
5103 #if defined(CONFIG_USER_ONLY)
5104 GEN_EXCP_PRIVOPC(ctx
);
5106 if (unlikely(!ctx
->supervisor
)) {
5107 GEN_EXCP_PRIVOPC(ctx
);
5110 switch (rB(ctx
->opcode
)) {
5114 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5115 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5116 gen_op_440_tlbwe(rB(ctx
->opcode
));
5119 GEN_EXCP_INVAL(ctx
);
5126 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
)
5128 #if defined(CONFIG_USER_ONLY)
5129 GEN_EXCP_PRIVOPC(ctx
);
5131 if (unlikely(!ctx
->supervisor
)) {
5132 GEN_EXCP_PRIVOPC(ctx
);
5135 gen_op_load_gpr_T0(rD(ctx
->opcode
));
5137 /* Stop translation to have a chance to raise an exception
5138 * if we just set msr_ee to 1
5145 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE
)
5147 #if defined(CONFIG_USER_ONLY)
5148 GEN_EXCP_PRIVOPC(ctx
);
5150 if (unlikely(!ctx
->supervisor
)) {
5151 GEN_EXCP_PRIVOPC(ctx
);
5154 gen_op_set_T0(ctx
->opcode
& 0x00010000);
5156 /* Stop translation to have a chance to raise an exception
5157 * if we just set msr_ee to 1
5163 /* PowerPC 440 specific instructions */
5165 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
)
5167 gen_op_load_gpr_T0(rS(ctx
->opcode
));
5168 gen_op_load_gpr_T1(rB(ctx
->opcode
));
5170 gen_op_store_T0_gpr(rA(ctx
->opcode
));
5171 gen_op_store_xer_bc();
5172 if (Rc(ctx
->opcode
)) {
5173 gen_op_440_dlmzb_update_Rc();
5174 gen_op_store_T0_crf(0);
5178 /* mbar replaces eieio on 440 */
5179 GEN_HANDLER(mbar
, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE
)
5181 /* interpreted as no-op */
5184 /* msync replaces sync on 440 */
5185 GEN_HANDLER(msync
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
)
5187 /* interpreted as no-op */
5191 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE
)
5193 /* interpreted as no-op */
5194 /* XXX: specification say this is treated as a load by the MMU
5195 * but does not generate any exception
5199 /*** Altivec vector extension ***/
5200 /* Altivec registers moves */
5201 GEN32(gen_op_load_avr_A0
, gen_op_load_avr_A0_avr
);
5202 GEN32(gen_op_load_avr_A1
, gen_op_load_avr_A1_avr
);
5203 GEN32(gen_op_load_avr_A2
, gen_op_load_avr_A2_avr
);
5205 GEN32(gen_op_store_A0_avr
, gen_op_store_A0_avr_avr
);
5206 GEN32(gen_op_store_A1_avr
, gen_op_store_A1_avr_avr
);
5208 GEN32(gen_op_store_A2_avr
, gen_op_store_A2_avr_avr
);
5211 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5212 #define OP_VR_LD_TABLE(name) \
5213 static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5214 GEN_MEM_FUNCS(vr_l##name), \
5216 #define OP_VR_ST_TABLE(name) \
5217 static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5218 GEN_MEM_FUNCS(vr_st##name), \
5221 #define GEN_VR_LDX(name, opc2, opc3) \
5222 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5224 if (unlikely(!ctx->altivec_enabled)) { \
5225 GEN_EXCP_NO_VR(ctx); \
5228 gen_addr_reg_index(ctx); \
5229 op_vr_ldst(vr_l##name); \
5230 gen_op_store_A0_avr(rD(ctx->opcode)); \
5233 #define GEN_VR_STX(name, opc2, opc3) \
5234 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5236 if (unlikely(!ctx->altivec_enabled)) { \
5237 GEN_EXCP_NO_VR(ctx); \
5240 gen_addr_reg_index(ctx); \
5241 gen_op_load_avr_A0(rS(ctx->opcode)); \
5242 op_vr_ldst(vr_st##name); \
5246 GEN_VR_LDX(vx
, 0x07, 0x03);
5247 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5248 #define gen_op_vr_lvxl gen_op_vr_lvx
5249 GEN_VR_LDX(vxl
, 0x07, 0x0B);
5252 GEN_VR_STX(vx
, 0x07, 0x07);
5253 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5254 #define gen_op_vr_stvxl gen_op_vr_stvx
5255 GEN_VR_STX(vxl
, 0x07, 0x0F);
5257 /*** SPE extension ***/
5258 /* Register moves */
5259 #if !defined(TARGET_PPC64)
5261 GEN32(gen_op_load_gpr64_T0
, gen_op_load_gpr64_T0_gpr
);
5262 GEN32(gen_op_load_gpr64_T1
, gen_op_load_gpr64_T1_gpr
);
5264 GEN32(gen_op_load_gpr64_T2
, gen_op_load_gpr64_T2_gpr
);
5267 GEN32(gen_op_store_T0_gpr64
, gen_op_store_T0_gpr64_gpr
);
5268 GEN32(gen_op_store_T1_gpr64
, gen_op_store_T1_gpr64_gpr
);
5270 GEN32(gen_op_store_T2_gpr64
, gen_op_store_T2_gpr64_gpr
);
5273 #else /* !defined(TARGET_PPC64) */
5275 /* No specific load/store functions: GPRs are already 64 bits */
5276 #define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
5277 #define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
5279 #define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
5282 #define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
5283 #define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
5285 #define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
5288 #endif /* !defined(TARGET_PPC64) */
5290 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5291 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5293 if (Rc(ctx->opcode)) \
5299 /* Handler for undefined SPE opcodes */
5300 static always_inline
void gen_speundef (DisasContext
*ctx
)
5302 GEN_EXCP_INVAL(ctx
);
5305 /* SPE load and stores */
5306 static always_inline
void gen_addr_spe_imm_index (DisasContext
*ctx
, int sh
)
5308 target_long simm
= rB(ctx
->opcode
);
5310 if (rA(ctx
->opcode
) == 0) {
5311 gen_set_T0(simm
<< sh
);
5313 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5314 if (likely(simm
!= 0))
5315 gen_op_addi(simm
<< sh
);
5319 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5320 #define OP_SPE_LD_TABLE(name) \
5321 static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5322 GEN_MEM_FUNCS(spe_l##name), \
5324 #define OP_SPE_ST_TABLE(name) \
5325 static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5326 GEN_MEM_FUNCS(spe_st##name), \
5329 #define GEN_SPE_LD(name, sh) \
5330 static always_inline void gen_evl##name (DisasContext *ctx) \
5332 if (unlikely(!ctx->spe_enabled)) { \
5333 GEN_EXCP_NO_AP(ctx); \
5336 gen_addr_spe_imm_index(ctx, sh); \
5337 op_spe_ldst(spe_l##name); \
5338 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5341 #define GEN_SPE_LDX(name) \
5342 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5344 if (unlikely(!ctx->spe_enabled)) { \
5345 GEN_EXCP_NO_AP(ctx); \
5348 gen_addr_reg_index(ctx); \
5349 op_spe_ldst(spe_l##name); \
5350 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5353 #define GEN_SPEOP_LD(name, sh) \
5354 OP_SPE_LD_TABLE(name); \
5355 GEN_SPE_LD(name, sh); \
5358 #define GEN_SPE_ST(name, sh) \
5359 static always_inline void gen_evst##name (DisasContext *ctx) \
5361 if (unlikely(!ctx->spe_enabled)) { \
5362 GEN_EXCP_NO_AP(ctx); \
5365 gen_addr_spe_imm_index(ctx, sh); \
5366 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5367 op_spe_ldst(spe_st##name); \
5370 #define GEN_SPE_STX(name) \
5371 static always_inline void gen_evst##name##x (DisasContext *ctx) \
5373 if (unlikely(!ctx->spe_enabled)) { \
5374 GEN_EXCP_NO_AP(ctx); \
5377 gen_addr_reg_index(ctx); \
5378 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5379 op_spe_ldst(spe_st##name); \
5382 #define GEN_SPEOP_ST(name, sh) \
5383 OP_SPE_ST_TABLE(name); \
5384 GEN_SPE_ST(name, sh); \
5387 #define GEN_SPEOP_LDST(name, sh) \
5388 GEN_SPEOP_LD(name, sh); \
5389 GEN_SPEOP_ST(name, sh)
5391 /* SPE arithmetic and logic */
5392 #define GEN_SPEOP_ARITH2(name) \
5393 static always_inline void gen_##name (DisasContext *ctx) \
5395 if (unlikely(!ctx->spe_enabled)) { \
5396 GEN_EXCP_NO_AP(ctx); \
5399 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5400 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5402 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5405 #define GEN_SPEOP_ARITH1(name) \
5406 static always_inline void gen_##name (DisasContext *ctx) \
5408 if (unlikely(!ctx->spe_enabled)) { \
5409 GEN_EXCP_NO_AP(ctx); \
5412 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5414 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5417 #define GEN_SPEOP_COMP(name) \
5418 static always_inline void gen_##name (DisasContext *ctx) \
5420 if (unlikely(!ctx->spe_enabled)) { \
5421 GEN_EXCP_NO_AP(ctx); \
5424 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5425 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5427 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5431 GEN_SPEOP_ARITH2(evand
);
5432 GEN_SPEOP_ARITH2(evandc
);
5433 GEN_SPEOP_ARITH2(evxor
);
5434 GEN_SPEOP_ARITH2(evor
);
5435 GEN_SPEOP_ARITH2(evnor
);
5436 GEN_SPEOP_ARITH2(eveqv
);
5437 GEN_SPEOP_ARITH2(evorc
);
5438 GEN_SPEOP_ARITH2(evnand
);
5439 GEN_SPEOP_ARITH2(evsrwu
);
5440 GEN_SPEOP_ARITH2(evsrws
);
5441 GEN_SPEOP_ARITH2(evslw
);
5442 GEN_SPEOP_ARITH2(evrlw
);
5443 GEN_SPEOP_ARITH2(evmergehi
);
5444 GEN_SPEOP_ARITH2(evmergelo
);
5445 GEN_SPEOP_ARITH2(evmergehilo
);
5446 GEN_SPEOP_ARITH2(evmergelohi
);
5449 GEN_SPEOP_ARITH2(evaddw
);
5450 GEN_SPEOP_ARITH2(evsubfw
);
5451 GEN_SPEOP_ARITH1(evabs
);
5452 GEN_SPEOP_ARITH1(evneg
);
5453 GEN_SPEOP_ARITH1(evextsb
);
5454 GEN_SPEOP_ARITH1(evextsh
);
5455 GEN_SPEOP_ARITH1(evrndw
);
5456 GEN_SPEOP_ARITH1(evcntlzw
);
5457 GEN_SPEOP_ARITH1(evcntlsw
);
5458 static always_inline
void gen_brinc (DisasContext
*ctx
)
5460 /* Note: brinc is usable even if SPE is disabled */
5461 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5462 gen_op_load_gpr_T1(rB(ctx
->opcode
));
5464 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5467 #define GEN_SPEOP_ARITH_IMM2(name) \
5468 static always_inline void gen_##name##i (DisasContext *ctx) \
5470 if (unlikely(!ctx->spe_enabled)) { \
5471 GEN_EXCP_NO_AP(ctx); \
5474 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5475 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5477 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5480 #define GEN_SPEOP_LOGIC_IMM2(name) \
5481 static always_inline void gen_##name##i (DisasContext *ctx) \
5483 if (unlikely(!ctx->spe_enabled)) { \
5484 GEN_EXCP_NO_AP(ctx); \
5487 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5488 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5490 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5493 GEN_SPEOP_ARITH_IMM2(evaddw
);
5494 #define gen_evaddiw gen_evaddwi
5495 GEN_SPEOP_ARITH_IMM2(evsubfw
);
5496 #define gen_evsubifw gen_evsubfwi
5497 GEN_SPEOP_LOGIC_IMM2(evslw
);
5498 GEN_SPEOP_LOGIC_IMM2(evsrwu
);
5499 #define gen_evsrwis gen_evsrwsi
5500 GEN_SPEOP_LOGIC_IMM2(evsrws
);
5501 #define gen_evsrwiu gen_evsrwui
5502 GEN_SPEOP_LOGIC_IMM2(evrlw
);
5504 static always_inline
void gen_evsplati (DisasContext
*ctx
)
5506 int32_t imm
= (int32_t)(rA(ctx
->opcode
) << 27) >> 27;
5508 gen_op_splatwi_T0_64(imm
);
5509 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5512 static always_inline
void gen_evsplatfi (DisasContext
*ctx
)
5514 uint32_t imm
= rA(ctx
->opcode
) << 27;
5516 gen_op_splatwi_T0_64(imm
);
5517 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5521 GEN_SPEOP_COMP(evcmpgtu
);
5522 GEN_SPEOP_COMP(evcmpgts
);
5523 GEN_SPEOP_COMP(evcmpltu
);
5524 GEN_SPEOP_COMP(evcmplts
);
5525 GEN_SPEOP_COMP(evcmpeq
);
5527 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, PPC_SPE
); ////
5528 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, PPC_SPE
);
5529 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, PPC_SPE
); ////
5530 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, PPC_SPE
);
5531 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, PPC_SPE
); ////
5532 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, PPC_SPE
); ////
5533 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, PPC_SPE
); ////
5534 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x00000000, PPC_SPE
); //
5535 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0x00000000, PPC_SPE
); ////
5536 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, PPC_SPE
); ////
5537 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, PPC_SPE
); ////
5538 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, PPC_SPE
); ////
5539 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0x00000000, PPC_SPE
); ////
5540 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, PPC_SPE
); ////
5541 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, PPC_SPE
); ////
5542 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, PPC_SPE
);
5543 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, PPC_SPE
); ////
5544 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, PPC_SPE
);
5545 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, PPC_SPE
); //
5546 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, PPC_SPE
);
5547 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, PPC_SPE
); ////
5548 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, PPC_SPE
); ////
5549 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, PPC_SPE
); ////
5550 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, PPC_SPE
); ////
5551 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, PPC_SPE
); ////
5553 static always_inline
void gen_evsel (DisasContext
*ctx
)
5555 if (unlikely(!ctx
->spe_enabled
)) {
5556 GEN_EXCP_NO_AP(ctx
);
5559 gen_op_load_crf_T0(ctx
->opcode
& 0x7);
5560 gen_op_load_gpr64_T0(rA(ctx
->opcode
));
5561 gen_op_load_gpr64_T1(rB(ctx
->opcode
));
5563 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5566 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
)
5570 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
)
5574 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
)
5578 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
)
5583 /* Load and stores */
5584 #if defined(TARGET_PPC64)
5585 /* In that case, we already have 64 bits load & stores
5586 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5588 #define gen_op_spe_ldd_raw gen_op_ld_raw
5589 #define gen_op_spe_ldd_user gen_op_ld_user
5590 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
5591 #define gen_op_spe_ldd_hypv gen_op_ld_hypv
5592 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5593 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
5594 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5595 #define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
5596 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5597 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
5598 #define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
5599 #define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
5600 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5601 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5602 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
5603 #define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
5604 #define gen_op_spe_stdd_raw gen_op_std_raw
5605 #define gen_op_spe_stdd_user gen_op_std_user
5606 #define gen_op_spe_stdd_kernel gen_op_std_kernel
5607 #define gen_op_spe_stdd_hypv gen_op_std_hypv
5608 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5609 #define gen_op_spe_stdd_64_user gen_op_std_64_user
5610 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5611 #define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
5612 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5613 #define gen_op_spe_stdd_le_user gen_op_std_le_user
5614 #define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
5615 #define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
5616 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5617 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5618 #define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
5619 #define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
5620 #endif /* defined(TARGET_PPC64) */
5621 GEN_SPEOP_LDST(dd
, 3);
5622 GEN_SPEOP_LDST(dw
, 3);
5623 GEN_SPEOP_LDST(dh
, 3);
5624 GEN_SPEOP_LDST(whe
, 2);
5625 GEN_SPEOP_LD(whou
, 2);
5626 GEN_SPEOP_LD(whos
, 2);
5627 GEN_SPEOP_ST(who
, 2);
5629 #if defined(TARGET_PPC64)
5630 /* In that case, spe_stwwo is equivalent to stw */
5631 #define gen_op_spe_stwwo_raw gen_op_stw_raw
5632 #define gen_op_spe_stwwo_user gen_op_stw_user
5633 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5634 #define gen_op_spe_stwwo_hypv gen_op_stw_hypv
5635 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5636 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5637 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5638 #define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
5639 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5640 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5641 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5642 #define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
5643 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5644 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
5645 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
5646 #define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
5648 #define _GEN_OP_SPE_STWWE(suffix) \
5649 static always_inline void gen_op_spe_stwwe_##suffix (void) \
5651 gen_op_srli32_T1_64(); \
5652 gen_op_spe_stwwo_##suffix(); \
5654 #define _GEN_OP_SPE_STWWE_LE(suffix) \
5655 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
5657 gen_op_srli32_T1_64(); \
5658 gen_op_spe_stwwo_le_##suffix(); \
5660 #if defined(TARGET_PPC64)
5661 #define GEN_OP_SPE_STWWE(suffix) \
5662 _GEN_OP_SPE_STWWE(suffix); \
5663 _GEN_OP_SPE_STWWE_LE(suffix); \
5664 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
5666 gen_op_srli32_T1_64(); \
5667 gen_op_spe_stwwo_64_##suffix(); \
5669 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
5671 gen_op_srli32_T1_64(); \
5672 gen_op_spe_stwwo_le_64_##suffix(); \
5675 #define GEN_OP_SPE_STWWE(suffix) \
5676 _GEN_OP_SPE_STWWE(suffix); \
5677 _GEN_OP_SPE_STWWE_LE(suffix)
5679 #if defined(CONFIG_USER_ONLY)
5680 GEN_OP_SPE_STWWE(raw
);
5681 #else /* defined(CONFIG_USER_ONLY) */
5682 GEN_OP_SPE_STWWE(user
);
5683 GEN_OP_SPE_STWWE(kernel
);
5684 GEN_OP_SPE_STWWE(hypv
);
5685 #endif /* defined(CONFIG_USER_ONLY) */
5686 GEN_SPEOP_ST(wwe
, 2);
5687 GEN_SPEOP_ST(wwo
, 2);
5689 #define GEN_SPE_LDSPLAT(name, op, suffix) \
5690 static always_inline void gen_op_spe_l##name##_##suffix (void) \
5692 gen_op_##op##_##suffix(); \
5693 gen_op_splatw_T1_64(); \
5696 #define GEN_OP_SPE_LHE(suffix) \
5697 static always_inline void gen_op_spe_lhe_##suffix (void) \
5699 gen_op_spe_lh_##suffix(); \
5700 gen_op_sli16_T1_64(); \
5703 #define GEN_OP_SPE_LHX(suffix) \
5704 static always_inline void gen_op_spe_lhx_##suffix (void) \
5706 gen_op_spe_lh_##suffix(); \
5707 gen_op_extsh_T1_64(); \
5710 #if defined(CONFIG_USER_ONLY)
5711 GEN_OP_SPE_LHE(raw
);
5712 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, raw
);
5713 GEN_OP_SPE_LHE(le_raw
);
5714 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_raw
);
5715 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, raw
);
5716 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_raw
);
5717 GEN_OP_SPE_LHX(raw
);
5718 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, raw
);
5719 GEN_OP_SPE_LHX(le_raw
);
5720 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_raw
);
5721 #if defined(TARGET_PPC64)
5722 GEN_OP_SPE_LHE(64_raw
);
5723 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_raw
);
5724 GEN_OP_SPE_LHE(le_64_raw
);
5725 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_raw
);
5726 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_raw
);
5727 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_raw
);
5728 GEN_OP_SPE_LHX(64_raw
);
5729 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_raw
);
5730 GEN_OP_SPE_LHX(le_64_raw
);
5731 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_raw
);
5734 GEN_OP_SPE_LHE(user
);
5735 GEN_OP_SPE_LHE(kernel
);
5736 GEN_OP_SPE_LHE(hypv
);
5737 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, user
);
5738 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, kernel
);
5739 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, hypv
);
5740 GEN_OP_SPE_LHE(le_user
);
5741 GEN_OP_SPE_LHE(le_kernel
);
5742 GEN_OP_SPE_LHE(le_hypv
);
5743 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_user
);
5744 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_kernel
);
5745 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_hypv
);
5746 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, user
);
5747 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, kernel
);
5748 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, hypv
);
5749 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_user
);
5750 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_kernel
);
5751 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_hypv
);
5752 GEN_OP_SPE_LHX(user
);
5753 GEN_OP_SPE_LHX(kernel
);
5754 GEN_OP_SPE_LHX(hypv
);
5755 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, user
);
5756 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, kernel
);
5757 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, hypv
);
5758 GEN_OP_SPE_LHX(le_user
);
5759 GEN_OP_SPE_LHX(le_kernel
);
5760 GEN_OP_SPE_LHX(le_hypv
);
5761 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_user
);
5762 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_kernel
);
5763 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_hypv
);
5764 #if defined(TARGET_PPC64)
5765 GEN_OP_SPE_LHE(64_user
);
5766 GEN_OP_SPE_LHE(64_kernel
);
5767 GEN_OP_SPE_LHE(64_hypv
);
5768 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_user
);
5769 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_kernel
);
5770 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_hypv
);
5771 GEN_OP_SPE_LHE(le_64_user
);
5772 GEN_OP_SPE_LHE(le_64_kernel
);
5773 GEN_OP_SPE_LHE(le_64_hypv
);
5774 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_user
);
5775 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_kernel
);
5776 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_hypv
);
5777 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_user
);
5778 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_kernel
);
5779 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_hypv
);
5780 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_user
);
5781 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_kernel
);
5782 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_hypv
);
5783 GEN_OP_SPE_LHX(64_user
);
5784 GEN_OP_SPE_LHX(64_kernel
);
5785 GEN_OP_SPE_LHX(64_hypv
);
5786 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_user
);
5787 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_kernel
);
5788 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_hypv
);
5789 GEN_OP_SPE_LHX(le_64_user
);
5790 GEN_OP_SPE_LHX(le_64_kernel
);
5791 GEN_OP_SPE_LHX(le_64_hypv
);
5792 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_user
);
5793 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_kernel
);
5794 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_hypv
);
5797 GEN_SPEOP_LD(hhesplat
, 1);
5798 GEN_SPEOP_LD(hhousplat
, 1);
5799 GEN_SPEOP_LD(hhossplat
, 1);
5800 GEN_SPEOP_LD(wwsplat
, 2);
5801 GEN_SPEOP_LD(whsplat
, 2);
5803 GEN_SPE(evlddx
, evldd
, 0x00, 0x0C, 0x00000000, PPC_SPE
); //
5804 GEN_SPE(evldwx
, evldw
, 0x01, 0x0C, 0x00000000, PPC_SPE
); //
5805 GEN_SPE(evldhx
, evldh
, 0x02, 0x0C, 0x00000000, PPC_SPE
); //
5806 GEN_SPE(evlhhesplatx
, evlhhesplat
, 0x04, 0x0C, 0x00000000, PPC_SPE
); //
5807 GEN_SPE(evlhhousplatx
, evlhhousplat
, 0x06, 0x0C, 0x00000000, PPC_SPE
); //
5808 GEN_SPE(evlhhossplatx
, evlhhossplat
, 0x07, 0x0C, 0x00000000, PPC_SPE
); //
5809 GEN_SPE(evlwhex
, evlwhe
, 0x08, 0x0C, 0x00000000, PPC_SPE
); //
5810 GEN_SPE(evlwhoux
, evlwhou
, 0x0A, 0x0C, 0x00000000, PPC_SPE
); //
5811 GEN_SPE(evlwhosx
, evlwhos
, 0x0B, 0x0C, 0x00000000, PPC_SPE
); //
5812 GEN_SPE(evlwwsplatx
, evlwwsplat
, 0x0C, 0x0C, 0x00000000, PPC_SPE
); //
5813 GEN_SPE(evlwhsplatx
, evlwhsplat
, 0x0E, 0x0C, 0x00000000, PPC_SPE
); //
5814 GEN_SPE(evstddx
, evstdd
, 0x10, 0x0C, 0x00000000, PPC_SPE
); //
5815 GEN_SPE(evstdwx
, evstdw
, 0x11, 0x0C, 0x00000000, PPC_SPE
); //
5816 GEN_SPE(evstdhx
, evstdh
, 0x12, 0x0C, 0x00000000, PPC_SPE
); //
5817 GEN_SPE(evstwhex
, evstwhe
, 0x18, 0x0C, 0x00000000, PPC_SPE
); //
5818 GEN_SPE(evstwhox
, evstwho
, 0x1A, 0x0C, 0x00000000, PPC_SPE
); //
5819 GEN_SPE(evstwwex
, evstwwe
, 0x1C, 0x0C, 0x00000000, PPC_SPE
); //
5820 GEN_SPE(evstwwox
, evstwwo
, 0x1E, 0x0C, 0x00000000, PPC_SPE
); //
5822 /* Multiply and add - TODO */
5824 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0x00000000, PPC_SPE
);
5825 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0x00000000, PPC_SPE
);
5826 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, PPC_SPE
);
5827 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0x00000000, PPC_SPE
);
5828 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, PPC_SPE
);
5829 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0x00000000, PPC_SPE
);
5830 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0x00000000, PPC_SPE
);
5831 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0x00000000, PPC_SPE
);
5832 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, PPC_SPE
);
5833 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0x00000000, PPC_SPE
);
5834 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, PPC_SPE
);
5835 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0x00000000, PPC_SPE
);
5837 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0x00000000, PPC_SPE
);
5838 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, PPC_SPE
);
5839 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, PPC_SPE
);
5840 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0x00000000, PPC_SPE
);
5841 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0x00000000, PPC_SPE
);
5842 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, PPC_SPE
);
5843 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0x00000000, PPC_SPE
);
5844 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0x00000000, PPC_SPE
);
5845 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, PPC_SPE
);
5846 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, PPC_SPE
);
5847 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0x00000000, PPC_SPE
);
5848 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0x00000000, PPC_SPE
);
5849 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, PPC_SPE
);
5850 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0x00000000, PPC_SPE
);
5852 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, PPC_SPE
);
5853 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, PPC_SPE
);
5854 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, PPC_SPE
);
5855 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, PPC_SPE
);
5856 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, PPC_SPE
);
5857 GEN_SPE(evmra
, speundef
, 0x07, 0x13, 0x0000F800, PPC_SPE
);
5859 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, PPC_SPE
);
5860 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0x00000000, PPC_SPE
);
5861 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, PPC_SPE
);
5862 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0x00000000, PPC_SPE
);
5863 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, PPC_SPE
);
5864 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0x00000000, PPC_SPE
);
5865 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, PPC_SPE
);
5866 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0x00000000, PPC_SPE
);
5867 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, PPC_SPE
);
5868 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0x00000000, PPC_SPE
);
5869 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, PPC_SPE
);
5870 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0x00000000, PPC_SPE
);
5872 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, PPC_SPE
);
5873 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, PPC_SPE
);
5874 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0x00000000, PPC_SPE
);
5875 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, PPC_SPE
);
5876 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0x00000000, PPC_SPE
);
5878 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, PPC_SPE
);
5879 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0x00000000, PPC_SPE
);
5880 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, PPC_SPE
);
5881 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0x00000000, PPC_SPE
);
5882 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, PPC_SPE
);
5883 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0x00000000, PPC_SPE
);
5884 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, PPC_SPE
);
5885 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0x00000000, PPC_SPE
);
5886 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, PPC_SPE
);
5887 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0x00000000, PPC_SPE
);
5888 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, PPC_SPE
);
5889 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0x00000000, PPC_SPE
);
5891 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, PPC_SPE
);
5892 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, PPC_SPE
);
5893 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0x00000000, PPC_SPE
);
5894 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, PPC_SPE
);
5895 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0x00000000, PPC_SPE
);
5898 /*** SPE floating-point extension ***/
5899 #define GEN_SPEFPUOP_CONV(name) \
5900 static always_inline void gen_##name (DisasContext *ctx) \
5902 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5904 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5907 /* Single precision floating-point vectors operations */
5909 GEN_SPEOP_ARITH2(evfsadd
);
5910 GEN_SPEOP_ARITH2(evfssub
);
5911 GEN_SPEOP_ARITH2(evfsmul
);
5912 GEN_SPEOP_ARITH2(evfsdiv
);
5913 GEN_SPEOP_ARITH1(evfsabs
);
5914 GEN_SPEOP_ARITH1(evfsnabs
);
5915 GEN_SPEOP_ARITH1(evfsneg
);
5917 GEN_SPEFPUOP_CONV(evfscfui
);
5918 GEN_SPEFPUOP_CONV(evfscfsi
);
5919 GEN_SPEFPUOP_CONV(evfscfuf
);
5920 GEN_SPEFPUOP_CONV(evfscfsf
);
5921 GEN_SPEFPUOP_CONV(evfsctui
);
5922 GEN_SPEFPUOP_CONV(evfsctsi
);
5923 GEN_SPEFPUOP_CONV(evfsctuf
);
5924 GEN_SPEFPUOP_CONV(evfsctsf
);
5925 GEN_SPEFPUOP_CONV(evfsctuiz
);
5926 GEN_SPEFPUOP_CONV(evfsctsiz
);
5928 GEN_SPEOP_COMP(evfscmpgt
);
5929 GEN_SPEOP_COMP(evfscmplt
);
5930 GEN_SPEOP_COMP(evfscmpeq
);
5931 GEN_SPEOP_COMP(evfststgt
);
5932 GEN_SPEOP_COMP(evfststlt
);
5933 GEN_SPEOP_COMP(evfststeq
);
5935 /* Opcodes definitions */
5936 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, PPC_SPEFPU
); //
5937 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU
); //
5938 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU
); //
5939 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, PPC_SPEFPU
); //
5940 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, PPC_SPEFPU
); //
5941 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, PPC_SPEFPU
); //
5942 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, PPC_SPEFPU
); //
5943 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, PPC_SPEFPU
); //
5944 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU
); //
5945 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU
); //
5946 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU
); //
5947 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU
); //
5948 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU
); //
5949 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU
); //
5951 /* Single precision floating-point operations */
5953 GEN_SPEOP_ARITH2(efsadd
);
5954 GEN_SPEOP_ARITH2(efssub
);
5955 GEN_SPEOP_ARITH2(efsmul
);
5956 GEN_SPEOP_ARITH2(efsdiv
);
5957 GEN_SPEOP_ARITH1(efsabs
);
5958 GEN_SPEOP_ARITH1(efsnabs
);
5959 GEN_SPEOP_ARITH1(efsneg
);
5961 GEN_SPEFPUOP_CONV(efscfui
);
5962 GEN_SPEFPUOP_CONV(efscfsi
);
5963 GEN_SPEFPUOP_CONV(efscfuf
);
5964 GEN_SPEFPUOP_CONV(efscfsf
);
5965 GEN_SPEFPUOP_CONV(efsctui
);
5966 GEN_SPEFPUOP_CONV(efsctsi
);
5967 GEN_SPEFPUOP_CONV(efsctuf
);
5968 GEN_SPEFPUOP_CONV(efsctsf
);
5969 GEN_SPEFPUOP_CONV(efsctuiz
);
5970 GEN_SPEFPUOP_CONV(efsctsiz
);
5971 GEN_SPEFPUOP_CONV(efscfd
);
5973 GEN_SPEOP_COMP(efscmpgt
);
5974 GEN_SPEOP_COMP(efscmplt
);
5975 GEN_SPEOP_COMP(efscmpeq
);
5976 GEN_SPEOP_COMP(efststgt
);
5977 GEN_SPEOP_COMP(efststlt
);
5978 GEN_SPEOP_COMP(efststeq
);
5980 /* Opcodes definitions */
5981 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, PPC_SPEFPU
); //
5982 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU
); //
5983 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU
); //
5984 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, PPC_SPEFPU
); //
5985 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, PPC_SPEFPU
); //
5986 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, PPC_SPEFPU
); //
5987 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, PPC_SPEFPU
); //
5988 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, PPC_SPEFPU
); //
5989 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU
); //
5990 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU
); //
5991 GEN_SPE(efsctuiz
, efsctsiz
, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU
); //
5992 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU
); //
5993 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU
); //
5995 /* Double precision floating-point operations */
5997 GEN_SPEOP_ARITH2(efdadd
);
5998 GEN_SPEOP_ARITH2(efdsub
);
5999 GEN_SPEOP_ARITH2(efdmul
);
6000 GEN_SPEOP_ARITH2(efddiv
);
6001 GEN_SPEOP_ARITH1(efdabs
);
6002 GEN_SPEOP_ARITH1(efdnabs
);
6003 GEN_SPEOP_ARITH1(efdneg
);
6006 GEN_SPEFPUOP_CONV(efdcfui
);
6007 GEN_SPEFPUOP_CONV(efdcfsi
);
6008 GEN_SPEFPUOP_CONV(efdcfuf
);
6009 GEN_SPEFPUOP_CONV(efdcfsf
);
6010 GEN_SPEFPUOP_CONV(efdctui
);
6011 GEN_SPEFPUOP_CONV(efdctsi
);
6012 GEN_SPEFPUOP_CONV(efdctuf
);
6013 GEN_SPEFPUOP_CONV(efdctsf
);
6014 GEN_SPEFPUOP_CONV(efdctuiz
);
6015 GEN_SPEFPUOP_CONV(efdctsiz
);
6016 GEN_SPEFPUOP_CONV(efdcfs
);
6017 GEN_SPEFPUOP_CONV(efdcfuid
);
6018 GEN_SPEFPUOP_CONV(efdcfsid
);
6019 GEN_SPEFPUOP_CONV(efdctuidz
);
6020 GEN_SPEFPUOP_CONV(efdctsidz
);
6022 GEN_SPEOP_COMP(efdcmpgt
);
6023 GEN_SPEOP_COMP(efdcmplt
);
6024 GEN_SPEOP_COMP(efdcmpeq
);
6025 GEN_SPEOP_COMP(efdtstgt
);
6026 GEN_SPEOP_COMP(efdtstlt
);
6027 GEN_SPEOP_COMP(efdtsteq
);
6029 /* Opcodes definitions */
6030 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, PPC_SPEFPU
); //
6031 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, PPC_SPEFPU
); //
6032 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU
); //
6033 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU
); //
6034 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, PPC_SPEFPU
); //
6035 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, PPC_SPEFPU
); //
6036 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, PPC_SPEFPU
); //
6037 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, PPC_SPEFPU
); //
6038 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, PPC_SPEFPU
); //
6039 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, PPC_SPEFPU
); //
6040 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU
); //
6041 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU
); //
6042 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU
); //
6043 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU
); //
6044 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU
); //
6045 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU
); //
6047 /* End opcode list */
6048 GEN_OPCODE_MARK(end
);
6050 #include "translate_init.c"
6051 #include "helper_regs.h"
6053 /*****************************************************************************/
6054 /* Misc PowerPC helpers */
6055 void cpu_dump_state (CPUState
*env
, FILE *f
,
6056 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6064 cpu_fprintf(f
, "NIP " ADDRX
" LR " ADDRX
" CTR " ADDRX
" XER %08x\n",
6065 env
->nip
, env
->lr
, env
->ctr
, hreg_load_xer(env
));
6066 cpu_fprintf(f
, "MSR " ADDRX
" HID0 " ADDRX
" HF " ADDRX
" idx %d\n",
6067 env
->msr
, env
->spr
[SPR_HID0
], env
->hflags
, env
->mmu_idx
);
6068 #if !defined(NO_TIMER_DUMP)
6069 cpu_fprintf(f
, "TB %08x %08x "
6070 #if !defined(CONFIG_USER_ONLY)
6074 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
6075 #if !defined(CONFIG_USER_ONLY)
6076 , cpu_ppc_load_decr(env
)
6080 for (i
= 0; i
< 32; i
++) {
6081 if ((i
& (RGPL
- 1)) == 0)
6082 cpu_fprintf(f
, "GPR%02d", i
);
6083 cpu_fprintf(f
, " " REGX
, ppc_dump_gpr(env
, i
));
6084 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
6085 cpu_fprintf(f
, "\n");
6087 cpu_fprintf(f
, "CR ");
6088 for (i
= 0; i
< 8; i
++)
6089 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
6090 cpu_fprintf(f
, " [");
6091 for (i
= 0; i
< 8; i
++) {
6093 if (env
->crf
[i
] & 0x08)
6095 else if (env
->crf
[i
] & 0x04)
6097 else if (env
->crf
[i
] & 0x02)
6099 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
6101 cpu_fprintf(f
, " ] RES " ADDRX
"\n", env
->reserve
);
6102 for (i
= 0; i
< 32; i
++) {
6103 if ((i
& (RFPL
- 1)) == 0)
6104 cpu_fprintf(f
, "FPR%02d", i
);
6105 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
6106 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
6107 cpu_fprintf(f
, "\n");
6109 #if !defined(CONFIG_USER_ONLY)
6110 cpu_fprintf(f
, "SRR0 " ADDRX
" SRR1 " ADDRX
" SDR1 " ADDRX
"\n",
6111 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
], env
->sdr1
);
6118 void cpu_dump_statistics (CPUState
*env
, FILE*f
,
6119 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6122 #if defined(DO_PPC_STATISTICS)
6123 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
6127 for (op1
= 0; op1
< 64; op1
++) {
6129 if (is_indirect_opcode(handler
)) {
6130 t2
= ind_table(handler
);
6131 for (op2
= 0; op2
< 32; op2
++) {
6133 if (is_indirect_opcode(handler
)) {
6134 t3
= ind_table(handler
);
6135 for (op3
= 0; op3
< 32; op3
++) {
6137 if (handler
->count
== 0)
6139 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
6141 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
6143 handler
->count
, handler
->count
);
6146 if (handler
->count
== 0)
6148 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
6150 op1
, op2
, op1
, op2
, handler
->oname
,
6151 handler
->count
, handler
->count
);
6155 if (handler
->count
== 0)
6157 cpu_fprintf(f
, "%02x (%02x ) %16s: %016llx %lld\n",
6158 op1
, op1
, handler
->oname
,
6159 handler
->count
, handler
->count
);
6165 /*****************************************************************************/
6166 static always_inline
int gen_intermediate_code_internal (CPUState
*env
,
6167 TranslationBlock
*tb
,
6170 DisasContext ctx
, *ctxp
= &ctx
;
6171 opc_handler_t
**table
, *handler
;
6172 target_ulong pc_start
;
6173 uint16_t *gen_opc_end
;
6174 int supervisor
, little_endian
;
6175 int single_step
, branch_step
;
6179 gen_opc_ptr
= gen_opc_buf
;
6180 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
6181 gen_opparam_ptr
= gen_opparam_buf
;
6182 #if defined(OPTIMIZE_FPRF_UPDATE)
6183 gen_fprf_ptr
= gen_fprf_buf
;
6188 ctx
.exception
= POWERPC_EXCP_NONE
;
6189 ctx
.spr_cb
= env
->spr_cb
;
6190 supervisor
= env
->mmu_idx
;
6191 #if !defined(CONFIG_USER_ONLY)
6192 ctx
.supervisor
= supervisor
;
6194 little_endian
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
6195 #if defined(TARGET_PPC64)
6196 ctx
.sf_mode
= msr_sf
;
6197 ctx
.mem_idx
= (supervisor
<< 2) | (msr_sf
<< 1) | little_endian
;
6199 ctx
.mem_idx
= (supervisor
<< 1) | little_endian
;
6201 ctx
.dcache_line_size
= env
->dcache_line_size
;
6202 ctx
.fpu_enabled
= msr_fp
;
6203 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
6204 ctx
.spe_enabled
= msr_spe
;
6206 ctx
.spe_enabled
= 0;
6207 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
6208 ctx
.altivec_enabled
= msr_vr
;
6210 ctx
.altivec_enabled
= 0;
6211 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
6215 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
6219 ctx
.singlestep_enabled
= env
->singlestep_enabled
|| single_step
== 1;
6220 #if defined (DO_SINGLE_STEP) && 0
6221 /* Single step trace mode */
6224 /* Set env in case of segfault during code fetch */
6225 while (ctx
.exception
== POWERPC_EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
6226 if (unlikely(env
->nb_breakpoints
> 0)) {
6227 for (j
= 0; j
< env
->nb_breakpoints
; j
++) {
6228 if (env
->breakpoints
[j
] == ctx
.nip
) {
6229 gen_update_nip(&ctx
, ctx
.nip
);
6235 if (unlikely(search_pc
)) {
6236 j
= gen_opc_ptr
- gen_opc_buf
;
6240 gen_opc_instr_start
[lj
++] = 0;
6241 gen_opc_pc
[lj
] = ctx
.nip
;
6242 gen_opc_instr_start
[lj
] = 1;
6245 #if defined PPC_DEBUG_DISAS
6246 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6247 fprintf(logfile
, "----------------\n");
6248 fprintf(logfile
, "nip=" ADDRX
" super=%d ir=%d\n",
6249 ctx
.nip
, supervisor
, (int)msr_ir
);
6252 if (unlikely(little_endian
)) {
6253 ctx
.opcode
= bswap32(ldl_code(ctx
.nip
));
6255 ctx
.opcode
= ldl_code(ctx
.nip
);
6257 #if defined PPC_DEBUG_DISAS
6258 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6259 fprintf(logfile
, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6260 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6261 opc3(ctx
.opcode
), little_endian
? "little" : "big");
6265 table
= env
->opcodes
;
6266 handler
= table
[opc1(ctx
.opcode
)];
6267 if (is_indirect_opcode(handler
)) {
6268 table
= ind_table(handler
);
6269 handler
= table
[opc2(ctx
.opcode
)];
6270 if (is_indirect_opcode(handler
)) {
6271 table
= ind_table(handler
);
6272 handler
= table
[opc3(ctx
.opcode
)];
6275 /* Is opcode *REALLY* valid ? */
6276 if (unlikely(handler
->handler
== &gen_invalid
)) {
6277 if (loglevel
!= 0) {
6278 fprintf(logfile
, "invalid/unsupported opcode: "
6279 "%02x - %02x - %02x (%08x) " ADDRX
" %d\n",
6280 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6281 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
6283 printf("invalid/unsupported opcode: "
6284 "%02x - %02x - %02x (%08x) " ADDRX
" %d\n",
6285 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6286 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
6289 if (unlikely((ctx
.opcode
& handler
->inval
) != 0)) {
6290 if (loglevel
!= 0) {
6291 fprintf(logfile
, "invalid bits: %08x for opcode: "
6292 "%02x - %02x - %02x (%08x) " ADDRX
"\n",
6293 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
6294 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
6295 ctx
.opcode
, ctx
.nip
- 4);
6297 printf("invalid bits: %08x for opcode: "
6298 "%02x - %02x - %02x (%08x) " ADDRX
"\n",
6299 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
6300 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
6301 ctx
.opcode
, ctx
.nip
- 4);
6303 GEN_EXCP_INVAL(ctxp
);
6307 (*(handler
->handler
))(&ctx
);
6308 #if defined(DO_PPC_STATISTICS)
6311 /* Check trace mode exceptions */
6312 if (unlikely(branch_step
!= 0 &&
6313 ctx
.exception
== POWERPC_EXCP_BRANCH
)) {
6314 GEN_EXCP(ctxp
, POWERPC_EXCP_TRACE
, 0);
6315 } else if (unlikely(single_step
!= 0 &&
6316 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00 ||
6317 (ctx
.nip
& 0xFC) != 0x04) &&
6318 ctx
.exception
!= POWERPC_SYSCALL
&&
6319 ctx
.exception
!= POWERPC_EXCP_TRAP
)) {
6320 GEN_EXCP(ctxp
, POWERPC_EXCP_TRACE
, 0);
6321 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
6322 (env
->singlestep_enabled
))) {
6323 /* if we reach a page boundary or are single stepping, stop
6328 #if defined (DO_SINGLE_STEP)
6332 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
6333 gen_goto_tb(&ctx
, 0, ctx
.nip
);
6334 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
6336 /* Generate the return instruction */
6339 *gen_opc_ptr
= INDEX_op_end
;
6340 if (unlikely(search_pc
)) {
6341 j
= gen_opc_ptr
- gen_opc_buf
;
6344 gen_opc_instr_start
[lj
++] = 0;
6346 tb
->size
= ctx
.nip
- pc_start
;
6348 #if defined(DEBUG_DISAS)
6349 if (loglevel
& CPU_LOG_TB_CPU
) {
6350 fprintf(logfile
, "---------------- excp: %04x\n", ctx
.exception
);
6351 cpu_dump_state(env
, logfile
, fprintf
, 0);
6353 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6355 flags
= env
->bfd_mach
;
6356 flags
|= little_endian
<< 16;
6357 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
6358 target_disas(logfile
, pc_start
, ctx
.nip
- pc_start
, flags
);
6359 fprintf(logfile
, "\n");
6361 if (loglevel
& CPU_LOG_TB_OP
) {
6362 fprintf(logfile
, "OP:\n");
6363 dump_ops(gen_opc_buf
, gen_opparam_buf
);
6364 fprintf(logfile
, "\n");
6370 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
6372 return gen_intermediate_code_internal(env
, tb
, 0);
6375 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
6377 return gen_intermediate_code_internal(env
, tb
, 1);