target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdlib.h>
  21 #include "exec.h"
  22
  23 #define GETPC() (__builtin_return_address(0))
  24
  25 /*****************************************************************************/
  26 /* Exceptions processing helpers */
  27
  28 void do_raise_exception_err (uint32_t exception, int error_code)
  29 {
  30 #if 1
  31     if (logfile && exception < 0x100)
  32         fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
  33 #endif
  34     env->exception_index = exception;
  35     env->error_code = error_code;
  36     T0 = 0;
  37     cpu_loop_exit();
  38 }
  39
  40 void do_raise_exception (uint32_t exception)
  41 {
  42     do_raise_exception_err(exception, 0);
  43 }
  44
  45 void do_restore_state (void *pc_ptr)
  46 {
  47   TranslationBlock *tb;
  48   unsigned long pc = (unsigned long) pc_ptr;
  49
  50   tb = tb_find_pc (pc);
  51   cpu_restore_state (tb, env, pc, NULL);
  52 }
  53
  54 void do_raise_exception_direct_err (uint32_t exception, int error_code)
  55 {
  56     do_restore_state (GETPC ());
  57     do_raise_exception_err (exception, error_code);
  58 }
  59
  60 void do_raise_exception_direct (uint32_t exception)
  61 {
  62     do_raise_exception_direct_err (exception, 0);
  63 }
  64
  65 #define MEMSUFFIX _raw
  66 #include "op_helper_mem.c"
  67 #undef MEMSUFFIX
  68 #if !defined(CONFIG_USER_ONLY)
  69 #define MEMSUFFIX _user
  70 #include "op_helper_mem.c"
  71 #undef MEMSUFFIX
  72 #define MEMSUFFIX _kernel
  73 #include "op_helper_mem.c"
  74 #undef MEMSUFFIX
  75 #endif
  76
  77 #ifdef TARGET_MIPS64
  78 #if TARGET_LONG_BITS > HOST_LONG_BITS
  79 /* Those might call libgcc functions.  */
  80 void do_dsll (void)
  81 {
  82     T0 = T0 << T1;
  83 }
  84
  85 void do_dsll32 (void)
  86 {
  87     T0 = T0 << (T1 + 32);
  88 }
  89
  90 void do_dsra (void)
  91 {
  92     T0 = (int64_t)T0 >> T1;
  93 }
  94
  95 void do_dsra32 (void)
  96 {
  97     T0 = (int64_t)T0 >> (T1 + 32);
  98 }
  99
 100 void do_dsrl (void)
 101 {
 102     T0 = T0 >> T1;
 103 }
 104
 105 void do_dsrl32 (void)
 106 {
 107     T0 = T0 >> (T1 + 32);
 108 }
 109
 110 void do_drotr (void)
 111 {
 112     target_ulong tmp;
 113
 114     if (T1) {
 115        tmp = T0 << (0x40 - T1);
 116        T0 = (T0 >> T1) | tmp;
 117     }
 118 }
 119
 120 void do_drotr32 (void)
 121 {
 122     target_ulong tmp;
 123
 124     if (T1) {
 125        tmp = T0 << (0x40 - (32 + T1));
 126        T0 = (T0 >> (32 + T1)) | tmp;
 127     }
 128 }
 129
 130 void do_dsllv (void)
 131 {
 132     T0 = T1 << (T0 & 0x3F);
 133 }
 134
 135 void do_dsrav (void)
 136 {
 137     T0 = (int64_t)T1 >> (T0 & 0x3F);
 138 }
 139
 140 void do_dsrlv (void)
 141 {
 142     T0 = T1 >> (T0 & 0x3F);
 143 }
 144
 145 void do_drotrv (void)
 146 {
 147     target_ulong tmp;
 148
 149     T0 &= 0x3F;
 150     if (T0) {
 151        tmp = T1 << (0x40 - T0);
 152        T0 = (T1 >> T0) | tmp;
 153     } else
 154        T0 = T1;
 155 }
 156 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 157 #endif /* TARGET_MIPS64 */
 158
 159 /* 64 bits arithmetic for 32 bits hosts */
 160 #if TARGET_LONG_BITS > HOST_LONG_BITS
 161 static inline uint64_t get_HILO (void)
 162 {
 163     return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
 164 }
 165
 166 static inline void set_HILO (uint64_t HILO)
 167 {
 168     env->LO[0][env->current_tc] = (int32_t)HILO;
 169     env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
 170 }
 171
 172 void do_mult (void)
 173 {
 174     set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 175 }
 176
 177 void do_multu (void)
 178 {
 179     set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 180 }
 181
 182 void do_madd (void)
 183 {
 184     int64_t tmp;
 185
 186     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 187     set_HILO((int64_t)get_HILO() + tmp);
 188 }
 189
 190 void do_maddu (void)
 191 {
 192     uint64_t tmp;
 193
 194     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 195     set_HILO(get_HILO() + tmp);
 196 }
 197
 198 void do_msub (void)
 199 {
 200     int64_t tmp;
 201
 202     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 203     set_HILO((int64_t)get_HILO() - tmp);
 204 }
 205
 206 void do_msubu (void)
 207 {
 208     uint64_t tmp;
 209
 210     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 211     set_HILO(get_HILO() - tmp);
 212 }
 213 #endif
 214
 215 #if HOST_LONG_BITS < 64
 216 void do_div (void)
 217 {
 218     /* 64bit datatypes because we may see overflow/underflow. */
 219     if (T1 != 0) {
 220         env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
 221         env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
 222     }
 223 }
 224 #endif
 225
 226 #ifdef TARGET_MIPS64
 227 void do_ddiv (void)
 228 {
 229     if (T1 != 0) {
 230         lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
 231         env->LO[0][env->current_tc] = res.quot;
 232         env->HI[0][env->current_tc] = res.rem;
 233     }
 234 }
 235
 236 #if TARGET_LONG_BITS > HOST_LONG_BITS
 237 void do_ddivu (void)
 238 {
 239     if (T1 != 0) {
 240         env->LO[0][env->current_tc] = T0 / T1;
 241         env->HI[0][env->current_tc] = T0 % T1;
 242     }
 243 }
 244 #endif
 245 #endif /* TARGET_MIPS64 */
 246
 247 #if defined(CONFIG_USER_ONLY)
 248 void do_mfc0_random (void)
 249 {
 250     cpu_abort(env, "mfc0 random\n");
 251 }
 252
 253 void do_mfc0_count (void)
 254 {
 255     cpu_abort(env, "mfc0 count\n");
 256 }
 257
 258 void cpu_mips_store_count(CPUState *env, uint32_t value)
 259 {
 260     cpu_abort(env, "mtc0 count\n");
 261 }
 262
 263 void cpu_mips_store_compare(CPUState *env, uint32_t value)
 264 {
 265     cpu_abort(env, "mtc0 compare\n");
 266 }
 267
 268 void cpu_mips_start_count(CPUState *env)
 269 {
 270     cpu_abort(env, "start count\n");
 271 }
 272
 273 void cpu_mips_stop_count(CPUState *env)
 274 {
 275     cpu_abort(env, "stop count\n");
 276 }
 277
 278 void cpu_mips_update_irq(CPUState *env)
 279 {
 280     cpu_abort(env, "mtc0 status / mtc0 cause\n");
 281 }
 282
 283 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 284 {
 285     cpu_abort(env, "mtc0 status debug\n");
 286 }
 287
 288 void do_mtc0_status_irqraise_debug (void)
 289 {
 290     cpu_abort(env, "mtc0 status irqraise debug\n");
 291 }
 292
 293 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 294 {
 295     cpu_abort(env, "mips_tlb_flush\n");
 296 }
 297
 298 #else
 299
 300 /* CP0 helpers */
 301 void do_mfc0_random (void)
 302 {
 303     T0 = (int32_t)cpu_mips_get_random(env);
 304 }
 305
 306 void do_mfc0_count (void)
 307 {
 308     T0 = (int32_t)cpu_mips_get_count(env);
 309 }
 310
 311 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 312 {
 313     fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
 314             old, old & env->CP0_Cause & CP0Ca_IP_mask,
 315             val, val & env->CP0_Cause & CP0Ca_IP_mask,
 316             env->CP0_Cause);
 317     (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
 318                                   : fputs("\n", logfile);
 319 }
 320
 321 void do_mtc0_status_irqraise_debug(void)
 322 {
 323     fprintf(logfile, "Raise pending IRQs\n");
 324 }
 325
 326 void fpu_handle_exception(void)
 327 {
 328 #ifdef CONFIG_SOFTFLOAT
 329     int flags = get_float_exception_flags(&env->fpu->fp_status);
 330     unsigned int cpuflags = 0, enable, cause = 0;
 331
 332     enable = GET_FP_ENABLE(env->fpu->fcr31);
 333
 334     /* determine current flags */
 335     if (flags & float_flag_invalid) {
 336         cpuflags |= FP_INVALID;
 337         cause |= FP_INVALID & enable;
 338     }
 339     if (flags & float_flag_divbyzero) {
 340         cpuflags |= FP_DIV0;
 341         cause |= FP_DIV0 & enable;
 342     }
 343     if (flags & float_flag_overflow) {
 344         cpuflags |= FP_OVERFLOW;
 345         cause |= FP_OVERFLOW & enable;
 346     }
 347     if (flags & float_flag_underflow) {
 348         cpuflags |= FP_UNDERFLOW;
 349         cause |= FP_UNDERFLOW & enable;
 350     }
 351     if (flags & float_flag_inexact) {
 352         cpuflags |= FP_INEXACT;
 353         cause |= FP_INEXACT & enable;
 354     }
 355     SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
 356     SET_FP_CAUSE(env->fpu->fcr31, cause);
 357 #else
 358     SET_FP_FLAGS(env->fpu->fcr31, 0);
 359     SET_FP_CAUSE(env->fpu->fcr31, 0);
 360 #endif
 361 }
 362
 363 /* TLB management */
 364 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 365 {
 366     /* Flush qemu's TLB and discard all shadowed entries.  */
 367     tlb_flush (env, flush_global);
 368     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 369 }
 370
 371 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
 372 {
 373     /* Discard entries from env->tlb[first] onwards.  */
 374     while (env->tlb->tlb_in_use > first) {
 375         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
 376     }
 377 }
 378
 379 static void r4k_fill_tlb (int idx)
 380 {
 381     r4k_tlb_t *tlb;
 382
 383     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
 384     tlb = &env->tlb->mmu.r4k.tlb[idx];
 385     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
 386 #ifdef TARGET_MIPS64
 387     tlb->VPN &= env->SEGMask;
 388 #endif
 389     tlb->ASID = env->CP0_EntryHi & 0xFF;
 390     tlb->PageMask = env->CP0_PageMask;
 391     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
 392     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
 393     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
 394     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
 395     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
 396     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
 397     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
 398     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
 399     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
 400 }
 401
 402 void r4k_do_tlbwi (void)
 403 {
 404     /* Discard cached TLB entries.  We could avoid doing this if the
 405        tlbwi is just upgrading access permissions on the current entry;
 406        that might be a further win.  */
 407     r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
 408
 409     r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
 410     r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
 411 }
 412
 413 void r4k_do_tlbwr (void)
 414 {
 415     int r = cpu_mips_get_random(env);
 416
 417     r4k_invalidate_tlb(env, r, 1);
 418     r4k_fill_tlb(r);
 419 }
 420
 421 void r4k_do_tlbp (void)
 422 {
 423     r4k_tlb_t *tlb;
 424     target_ulong mask;
 425     target_ulong tag;
 426     target_ulong VPN;
 427     uint8_t ASID;
 428     int i;
 429
 430     ASID = env->CP0_EntryHi & 0xFF;
 431     for (i = 0; i < env->tlb->nb_tlb; i++) {
 432         tlb = &env->tlb->mmu.r4k.tlb[i];
 433         /* 1k pages are not supported. */
 434         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 435         tag = env->CP0_EntryHi & ~mask;
 436         VPN = tlb->VPN & ~mask;
 437         /* Check ASID, virtual page number & size */
 438         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
 439             /* TLB match */
 440             env->CP0_Index = i;
 441             break;
 442         }
 443     }
 444     if (i == env->tlb->nb_tlb) {
 445         /* No match.  Discard any shadow entries, if any of them match.  */
 446         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
 447             tlb = &env->tlb->mmu.r4k.tlb[i];
 448             /* 1k pages are not supported. */
 449             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 450             tag = env->CP0_EntryHi & ~mask;
 451             VPN = tlb->VPN & ~mask;
 452             /* Check ASID, virtual page number & size */
 453             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
 454                 r4k_mips_tlb_flush_extra (env, i);
 455                 break;
 456             }
 457         }
 458
 459         env->CP0_Index |= 0x80000000;
 460     }
 461 }
 462
 463 void r4k_do_tlbr (void)
 464 {
 465     r4k_tlb_t *tlb;
 466     uint8_t ASID;
 467
 468     ASID = env->CP0_EntryHi & 0xFF;
 469     tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
 470
 471     /* If this will change the current ASID, flush qemu's TLB.  */
 472     if (ASID != tlb->ASID)
 473         cpu_mips_tlb_flush (env, 1);
 474
 475     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
 476
 477     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
 478     env->CP0_PageMask = tlb->PageMask;
 479     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
 480                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
 481     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
 482                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
 483 }
 484
 485 #endif /* !CONFIG_USER_ONLY */
 486
 487 void dump_ldst (const unsigned char *func)
 488 {
 489     if (loglevel)
 490         fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
 491 }
 492
 493 void dump_sc (void)
 494 {
 495     if (loglevel) {
 496         fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
 497                 T1, T0, env->CP0_LLAddr);
 498     }
 499 }
 500
 501 void debug_pre_eret (void)
 502 {
 503     fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
 504             env->PC[env->current_tc], env->CP0_EPC);
 505     if (env->CP0_Status & (1 << CP0St_ERL))
 506         fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
 507     if (env->hflags & MIPS_HFLAG_DM)
 508         fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
 509     fputs("\n", logfile);
 510 }
 511
 512 void debug_post_eret (void)
 513 {
 514     fprintf(logfile, "  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
 515             env->PC[env->current_tc], env->CP0_EPC);
 516     if (env->CP0_Status & (1 << CP0St_ERL))
 517         fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
 518     if (env->hflags & MIPS_HFLAG_DM)
 519         fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
 520     if (env->hflags & MIPS_HFLAG_UM)
 521         fputs(", UM\n", logfile);
 522     else
 523         fputs("\n", logfile);
 524 }
 525
 526 void do_pmon (int function)
 527 {
 528     function /= 2;
 529     switch (function) {
 530     case 2: /* TODO: char inbyte(int waitflag); */
 531         if (env->gpr[4][env->current_tc] == 0)
 532             env->gpr[2][env->current_tc] = -1;
 533         /* Fall through */
 534     case 11: /* TODO: char inbyte (void); */
 535         env->gpr[2][env->current_tc] = -1;
 536         break;
 537     case 3:
 538     case 12:
 539         printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF));
 540         break;
 541     case 17:
 542         break;
 543     case 158:
 544         {
 545             unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc];
 546             printf("%s", fmt);
 547         }
 548         break;
 549     }
 550 }
 551
 552 #if !defined(CONFIG_USER_ONLY)
 553
 554 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
 555
 556 #define MMUSUFFIX _mmu
 557 #define ALIGNED_ONLY
 558
 559 #define SHIFT 0
 560 #include "softmmu_template.h"
 561
 562 #define SHIFT 1
 563 #include "softmmu_template.h"
 564
 565 #define SHIFT 2
 566 #include "softmmu_template.h"
 567
 568 #define SHIFT 3
 569 #include "softmmu_template.h"
 570
 571 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
 572 {
 573     env->CP0_BadVAddr = addr;
 574     do_restore_state (retaddr);
 575     do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
 576 }
 577
 578 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
 579 {
 580     TranslationBlock *tb;
 581     CPUState *saved_env;
 582     unsigned long pc;
 583     int ret;
 584
 585     /* XXX: hack to restore env in all cases, even if not called from
 586        generated code */
 587     saved_env = env;
 588     env = cpu_single_env;
 589     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
 590     if (ret) {
 591         if (retaddr) {
 592             /* now we have a real cpu fault */
 593             pc = (unsigned long)retaddr;
 594             tb = tb_find_pc(pc);
 595             if (tb) {
 596                 /* the PC is inside the translated code. It means that we have
 597                    a virtual CPU fault */
 598                 cpu_restore_state(tb, env, pc, NULL);
 599             }
 600         }
 601         do_raise_exception_err(env->exception_index, env->error_code);
 602     }
 603     env = saved_env;
 604 }
 605
 606 #endif
 607
 608 /* Complex FPU operations which may need stack space. */
 609
 610 #define FLOAT_SIGN32 (1 << 31)
 611 #define FLOAT_SIGN64 (1ULL << 63)
 612 #define FLOAT_ONE32 (0x3f8 << 20)
 613 #define FLOAT_ONE64 (0x3ffULL << 52)
 614 #define FLOAT_TWO32 (1 << 30)
 615 #define FLOAT_TWO64 (1ULL << 62)
 616
 617 /* convert MIPS rounding mode in FCR31 to IEEE library */
 618 unsigned int ieee_rm[] = {
 619     float_round_nearest_even,
 620     float_round_to_zero,
 621     float_round_up,
 622     float_round_down
 623 };
 624
 625 #define RESTORE_ROUNDING_MODE \
 626     set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
 627
 628 void do_cfc1 (int reg)
 629 {
 630     switch (reg) {
 631     case 0:
 632         T0 = (int32_t)env->fpu->fcr0;
 633         break;
 634     case 25:
 635         T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
 636         break;
 637     case 26:
 638         T0 = env->fpu->fcr31 & 0x0003f07c;
 639         break;
 640     case 28:
 641         T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
 642         break;
 643     default:
 644         T0 = (int32_t)env->fpu->fcr31;
 645         break;
 646     }
 647 }
 648
 649 void do_ctc1 (int reg)
 650 {
 651     switch(reg) {
 652     case 25:
 653         if (T0 & 0xffffff00)
 654             return;
 655         env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
 656                      ((T0 & 0x1) << 23);
 657         break;
 658     case 26:
 659         if (T0 & 0x007c0000)
 660             return;
 661         env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
 662         break;
 663     case 28:
 664         if (T0 & 0x007c0000)
 665             return;
 666         env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
 667                      ((T0 & 0x4) << 22);
 668         break;
 669     case 31:
 670         if (T0 & 0x007c0000)
 671             return;
 672         env->fpu->fcr31 = T0;
 673         break;
 674     default:
 675         return;
 676     }
 677     /* set rounding mode */
 678     RESTORE_ROUNDING_MODE;
 679     set_float_exception_flags(0, &env->fpu->fp_status);
 680     if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
 681         do_raise_exception(EXCP_FPE);
 682 }
 683
 684 inline char ieee_ex_to_mips(char xcpt)
 685 {
 686     return (xcpt & float_flag_inexact) >> 5 |
 687            (xcpt & float_flag_underflow) >> 3 |
 688            (xcpt & float_flag_overflow) >> 1 |
 689            (xcpt & float_flag_divbyzero) << 1 |
 690            (xcpt & float_flag_invalid) << 4;
 691 }
 692
 693 inline char mips_ex_to_ieee(char xcpt)
 694 {
 695     return (xcpt & FP_INEXACT) << 5 |
 696            (xcpt & FP_UNDERFLOW) << 3 |
 697            (xcpt & FP_OVERFLOW) << 1 |
 698            (xcpt & FP_DIV0) >> 1 |
 699            (xcpt & FP_INVALID) >> 4;
 700 }
 701
 702 inline void update_fcr31(void)
 703 {
 704     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
 705
 706     SET_FP_CAUSE(env->fpu->fcr31, tmp);
 707     if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
 708         do_raise_exception(EXCP_FPE);
 709     else
 710         UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
 711 }
 712
 713 #define FLOAT_OP(name, p) void do_float_##name##_##p(void)
 714
 715 FLOAT_OP(cvtd, s)
 716 {
 717     set_float_exception_flags(0, &env->fpu->fp_status);
 718     FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
 719     update_fcr31();
 720 }
 721 FLOAT_OP(cvtd, w)
 722 {
 723     set_float_exception_flags(0, &env->fpu->fp_status);
 724     FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
 725     update_fcr31();
 726 }
 727 FLOAT_OP(cvtd, l)
 728 {
 729     set_float_exception_flags(0, &env->fpu->fp_status);
 730     FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
 731     update_fcr31();
 732 }
 733 FLOAT_OP(cvtl, d)
 734 {
 735     set_float_exception_flags(0, &env->fpu->fp_status);
 736     DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
 737     update_fcr31();
 738     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 739         DT2 = 0x7fffffffffffffffULL;
 740 }
 741 FLOAT_OP(cvtl, s)
 742 {
 743     set_float_exception_flags(0, &env->fpu->fp_status);
 744     DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
 745     update_fcr31();
 746     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 747         DT2 = 0x7fffffffffffffffULL;
 748 }
 749
 750 FLOAT_OP(cvtps, pw)
 751 {
 752     set_float_exception_flags(0, &env->fpu->fp_status);
 753     FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
 754     FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
 755     update_fcr31();
 756 }
 757 FLOAT_OP(cvtpw, ps)
 758 {
 759     set_float_exception_flags(0, &env->fpu->fp_status);
 760     WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
 761     WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
 762     update_fcr31();
 763     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 764         WT2 = 0x7fffffff;
 765 }
 766 FLOAT_OP(cvts, d)
 767 {
 768     set_float_exception_flags(0, &env->fpu->fp_status);
 769     FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
 770     update_fcr31();
 771 }
 772 FLOAT_OP(cvts, w)
 773 {
 774     set_float_exception_flags(0, &env->fpu->fp_status);
 775     FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
 776     update_fcr31();
 777 }
 778 FLOAT_OP(cvts, l)
 779 {
 780     set_float_exception_flags(0, &env->fpu->fp_status);
 781     FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
 782     update_fcr31();
 783 }
 784 FLOAT_OP(cvts, pl)
 785 {
 786     set_float_exception_flags(0, &env->fpu->fp_status);
 787     WT2 = WT0;
 788     update_fcr31();
 789 }
 790 FLOAT_OP(cvts, pu)
 791 {
 792     set_float_exception_flags(0, &env->fpu->fp_status);
 793     WT2 = WTH0;
 794     update_fcr31();
 795 }
 796 FLOAT_OP(cvtw, s)
 797 {
 798     set_float_exception_flags(0, &env->fpu->fp_status);
 799     WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
 800     update_fcr31();
 801     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 802         WT2 = 0x7fffffff;
 803 }
 804 FLOAT_OP(cvtw, d)
 805 {
 806     set_float_exception_flags(0, &env->fpu->fp_status);
 807     WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
 808     update_fcr31();
 809     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 810         WT2 = 0x7fffffff;
 811 }
 812
 813 FLOAT_OP(roundl, d)
 814 {
 815     set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
 816     DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
 817     RESTORE_ROUNDING_MODE;
 818     update_fcr31();
 819     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 820         DT2 = 0x7fffffffffffffffULL;
 821 }
 822 FLOAT_OP(roundl, s)
 823 {
 824     set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
 825     DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
 826     RESTORE_ROUNDING_MODE;
 827     update_fcr31();
 828     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 829         DT2 = 0x7fffffffffffffffULL;
 830 }
 831 FLOAT_OP(roundw, d)
 832 {
 833     set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
 834     WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
 835     RESTORE_ROUNDING_MODE;
 836     update_fcr31();
 837     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 838         WT2 = 0x7fffffff;
 839 }
 840 FLOAT_OP(roundw, s)
 841 {
 842     set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
 843     WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
 844     RESTORE_ROUNDING_MODE;
 845     update_fcr31();
 846     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 847         WT2 = 0x7fffffff;
 848 }
 849
 850 FLOAT_OP(truncl, d)
 851 {
 852     DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
 853     update_fcr31();
 854     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 855         DT2 = 0x7fffffffffffffffULL;
 856 }
 857 FLOAT_OP(truncl, s)
 858 {
 859     DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
 860     update_fcr31();
 861     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 862         DT2 = 0x7fffffffffffffffULL;
 863 }
 864 FLOAT_OP(truncw, d)
 865 {
 866     WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
 867     update_fcr31();
 868     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 869         WT2 = 0x7fffffff;
 870 }
 871 FLOAT_OP(truncw, s)
 872 {
 873     WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
 874     update_fcr31();
 875     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 876         WT2 = 0x7fffffff;
 877 }
 878
 879 FLOAT_OP(ceill, d)
 880 {
 881     set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
 882     DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
 883     RESTORE_ROUNDING_MODE;
 884     update_fcr31();
 885     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 886         DT2 = 0x7fffffffffffffffULL;
 887 }
 888 FLOAT_OP(ceill, s)
 889 {
 890     set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
 891     DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
 892     RESTORE_ROUNDING_MODE;
 893     update_fcr31();
 894     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 895         DT2 = 0x7fffffffffffffffULL;
 896 }
 897 FLOAT_OP(ceilw, d)
 898 {
 899     set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
 900     WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
 901     RESTORE_ROUNDING_MODE;
 902     update_fcr31();
 903     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 904         WT2 = 0x7fffffff;
 905 }
 906 FLOAT_OP(ceilw, s)
 907 {
 908     set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
 909     WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
 910     RESTORE_ROUNDING_MODE;
 911     update_fcr31();
 912     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 913         WT2 = 0x7fffffff;
 914 }
 915
 916 FLOAT_OP(floorl, d)
 917 {
 918     set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
 919     DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
 920     RESTORE_ROUNDING_MODE;
 921     update_fcr31();
 922     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 923         DT2 = 0x7fffffffffffffffULL;
 924 }
 925 FLOAT_OP(floorl, s)
 926 {
 927     set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
 928     DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
 929     RESTORE_ROUNDING_MODE;
 930     update_fcr31();
 931     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 932         DT2 = 0x7fffffffffffffffULL;
 933 }
 934 FLOAT_OP(floorw, d)
 935 {
 936     set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
 937     WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
 938     RESTORE_ROUNDING_MODE;
 939     update_fcr31();
 940     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 941         WT2 = 0x7fffffff;
 942 }
 943 FLOAT_OP(floorw, s)
 944 {
 945     set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
 946     WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
 947     RESTORE_ROUNDING_MODE;
 948     update_fcr31();
 949     if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
 950         WT2 = 0x7fffffff;
 951 }
 952
 953 /* MIPS specific unary operations */
 954 FLOAT_OP(recip, d)
 955 {
 956     set_float_exception_flags(0, &env->fpu->fp_status);
 957     FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
 958     update_fcr31();
 959 }
 960 FLOAT_OP(recip, s)
 961 {
 962     set_float_exception_flags(0, &env->fpu->fp_status);
 963     FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
 964     update_fcr31();
 965 }
 966
 967 FLOAT_OP(rsqrt, d)
 968 {
 969     set_float_exception_flags(0, &env->fpu->fp_status);
 970     FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
 971     FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
 972     update_fcr31();
 973 }
 974 FLOAT_OP(rsqrt, s)
 975 {
 976     set_float_exception_flags(0, &env->fpu->fp_status);
 977     FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
 978     FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
 979     update_fcr31();
 980 }
 981
 982 FLOAT_OP(recip1, d)
 983 {
 984     set_float_exception_flags(0, &env->fpu->fp_status);
 985     FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
 986     update_fcr31();
 987 }
 988 FLOAT_OP(recip1, s)
 989 {
 990     set_float_exception_flags(0, &env->fpu->fp_status);
 991     FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
 992     update_fcr31();
 993 }
 994 FLOAT_OP(recip1, ps)
 995 {
 996     set_float_exception_flags(0, &env->fpu->fp_status);
 997     FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
 998     FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
 999     update_fcr31();
1000 }
1001
1002 FLOAT_OP(rsqrt1, d)
1003 {
1004     set_float_exception_flags(0, &env->fpu->fp_status);
1005     FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1006     FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
1007     update_fcr31();
1008 }
1009 FLOAT_OP(rsqrt1, s)
1010 {
1011     set_float_exception_flags(0, &env->fpu->fp_status);
1012     FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1013     FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1014     update_fcr31();
1015 }
1016 FLOAT_OP(rsqrt1, ps)
1017 {
1018     set_float_exception_flags(0, &env->fpu->fp_status);
1019     FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1020     FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1021     FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1022     FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
1023     update_fcr31();
1024 }
1025
1026 /* binary operations */
1027 #define FLOAT_BINOP(name) \
1028 FLOAT_OP(name, d)         \
1029 {                         \
1030     set_float_exception_flags(0, &env->fpu->fp_status);            \
1031     FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status);    \
1032     update_fcr31();                                                \
1033     if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID)                \
1034         FDT2 = 0x7ff7ffffffffffffULL;                              \
1035     else if (GET_FP_CAUSE(env->fpu->fcr31) & FP_UNDERFLOW) {       \
1036         if ((env->fpu->fcr31 & 0x3) == 0)                          \
1037             FDT2 &= FLOAT_SIGN64;                                  \
1038     }                     \
1039 }                         \
1040 FLOAT_OP(name, s)         \
1041 {                         \
1042     set_float_exception_flags(0, &env->fpu->fp_status);            \
1043     FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status);    \
1044     update_fcr31();                                                \
1045     if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID)                \
1046         FST2 = 0x7fbfffff;                                         \
1047     else if (GET_FP_CAUSE(env->fpu->fcr31) & FP_UNDERFLOW) {       \
1048         if ((env->fpu->fcr31 & 0x3) == 0)                          \
1049             FST2 &= FLOAT_SIGN32;                                  \
1050     }                     \
1051 }                         \
1052 FLOAT_OP(name, ps)        \
1053 {                         \
1054     set_float_exception_flags(0, &env->fpu->fp_status);            \
1055     FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status);    \
1056     FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
1057     update_fcr31();       \
1058     if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) {              \
1059         FST2 = 0x7fbfffff;                                         \
1060         FSTH2 = 0x7fbfffff;                                        \
1061     } else if (GET_FP_CAUSE(env->fpu->fcr31) & FP_UNDERFLOW) {     \
1062         if ((env->fpu->fcr31 & 0x3) == 0) {                        \
1063             FST2 &= FLOAT_SIGN32;                                  \
1064             FSTH2 &= FLOAT_SIGN32;                                 \
1065         }                 \
1066     }                     \
1067 }
1068 FLOAT_BINOP(add)
1069 FLOAT_BINOP(sub)
1070 FLOAT_BINOP(mul)
1071 FLOAT_BINOP(div)
1072 #undef FLOAT_BINOP
1073
1074 /* MIPS specific binary operations */
1075 FLOAT_OP(recip2, d)
1076 {
1077     set_float_exception_flags(0, &env->fpu->fp_status);
1078     FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1079     FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
1080     update_fcr31();
1081 }
1082 FLOAT_OP(recip2, s)
1083 {
1084     set_float_exception_flags(0, &env->fpu->fp_status);
1085     FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1086     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1087     update_fcr31();
1088 }
1089 FLOAT_OP(recip2, ps)
1090 {
1091     set_float_exception_flags(0, &env->fpu->fp_status);
1092     FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1093     FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1094     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1095     FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1096     update_fcr31();
1097 }
1098
1099 FLOAT_OP(rsqrt2, d)
1100 {
1101     set_float_exception_flags(0, &env->fpu->fp_status);
1102     FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1103     FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
1104     FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
1105     update_fcr31();
1106 }
1107 FLOAT_OP(rsqrt2, s)
1108 {
1109     set_float_exception_flags(0, &env->fpu->fp_status);
1110     FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1111     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1112     FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1113     update_fcr31();
1114 }
1115 FLOAT_OP(rsqrt2, ps)
1116 {
1117     set_float_exception_flags(0, &env->fpu->fp_status);
1118     FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1119     FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1120     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1121     FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
1122     FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1123     FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1124     update_fcr31();
1125 }
1126
1127 FLOAT_OP(addr, ps)
1128 {
1129     set_float_exception_flags(0, &env->fpu->fp_status);
1130     FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1131     FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
1132     update_fcr31();
1133 }
1134
1135 FLOAT_OP(mulr, ps)
1136 {
1137     set_float_exception_flags(0, &env->fpu->fp_status);
1138     FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1139     FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
1140     update_fcr31();
1141 }
1142
1143 /* compare operations */
1144 #define FOP_COND_D(op, cond)                   \
1145 void do_cmp_d_ ## op (long cc)                 \
1146 {                                              \
1147     int c = cond;                              \
1148     update_fcr31();                            \
1149     if (c)                                     \
1150         SET_FP_COND(cc, env->fpu);             \
1151     else                                       \
1152         CLEAR_FP_COND(cc, env->fpu);           \
1153 }                                              \
1154 void do_cmpabs_d_ ## op (long cc)              \
1155 {                                              \
1156     int c;                                     \
1157     FDT0 &= ~FLOAT_SIGN64;                     \
1158     FDT1 &= ~FLOAT_SIGN64;                     \
1159     c = cond;                                  \
1160     update_fcr31();                            \
1161     if (c)                                     \
1162         SET_FP_COND(cc, env->fpu);             \
1163     else                                       \
1164         CLEAR_FP_COND(cc, env->fpu);           \
1165 }
1166
1167 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1168 {
1169     if (float64_is_signaling_nan(a) ||
1170         float64_is_signaling_nan(b) ||
1171         (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1172         float_raise(float_flag_invalid, status);
1173         return 1;
1174     } else if (float64_is_nan(a) || float64_is_nan(b)) {
1175         return 1;
1176     } else {
1177         return 0;
1178     }
1179 }
1180
1181 /* NOTE: the comma operator will make "cond" to eval to false,
1182  * but float*_is_unordered() is still called. */
1183 FOP_COND_D(f,   (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
1184 FOP_COND_D(un,  float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
1185 FOP_COND_D(eq,  !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1186 FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status)  || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1187 FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1188 FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status)  || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1189 FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1190 FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status)  || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1191 /* NOTE: the comma operator will make "cond" to eval to false,
1192  * but float*_is_unordered() is still called. */
1193 FOP_COND_D(sf,  (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
1194 FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
1195 FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1196 FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status)  || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1197 FOP_COND_D(lt,  !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1198 FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status)  || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1199 FOP_COND_D(le,  !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1200 FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status)  || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1201
1202 #define FOP_COND_S(op, cond)                   \
1203 void do_cmp_s_ ## op (long cc)                 \
1204 {                                              \
1205     int c = cond;                              \
1206     update_fcr31();                            \
1207     if (c)                                     \
1208         SET_FP_COND(cc, env->fpu);             \
1209     else                                       \
1210         CLEAR_FP_COND(cc, env->fpu);           \
1211 }                                              \
1212 void do_cmpabs_s_ ## op (long cc)              \
1213 {                                              \
1214     int c;                                     \
1215     FST0 &= ~FLOAT_SIGN32;                     \
1216     FST1 &= ~FLOAT_SIGN32;                     \
1217     c = cond;                                  \
1218     update_fcr31();                            \
1219     if (c)                                     \
1220         SET_FP_COND(cc, env->fpu);             \
1221     else                                       \
1222         CLEAR_FP_COND(cc, env->fpu);           \
1223 }
1224
1225 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1226 {
1227     if (float32_is_signaling_nan(a) ||
1228         float32_is_signaling_nan(b) ||
1229         (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1230         float_raise(float_flag_invalid, status);
1231         return 1;
1232     } else if (float32_is_nan(a) || float32_is_nan(b)) {
1233         return 1;
1234     } else {
1235         return 0;
1236     }
1237 }
1238
1239 /* NOTE: the comma operator will make "cond" to eval to false,
1240  * but float*_is_unordered() is still called. */
1241 FOP_COND_S(f,   (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
1242 FOP_COND_S(un,  float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
1243 FOP_COND_S(eq,  !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1244 FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status)  || float32_eq(FST0, FST1, &env->fpu->fp_status))
1245 FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1246 FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status)  || float32_lt(FST0, FST1, &env->fpu->fp_status))
1247 FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1248 FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status)  || float32_le(FST0, FST1, &env->fpu->fp_status))
1249 /* NOTE: the comma operator will make "cond" to eval to false,
1250  * but float*_is_unordered() is still called. */
1251 FOP_COND_S(sf,  (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
1252 FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
1253 FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1254 FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status)  || float32_eq(FST0, FST1, &env->fpu->fp_status))
1255 FOP_COND_S(lt,  !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1256 FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status)  || float32_lt(FST0, FST1, &env->fpu->fp_status))
1257 FOP_COND_S(le,  !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1258 FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status)  || float32_le(FST0, FST1, &env->fpu->fp_status))
1259
1260 #define FOP_COND_PS(op, condl, condh)          \
1261 void do_cmp_ps_ ## op (long cc)                \
1262 {                                              \
1263     int cl = condl;                            \
1264     int ch = condh;                            \
1265     update_fcr31();                            \
1266     if (cl)                                    \
1267         SET_FP_COND(cc, env->fpu);             \
1268     else                                       \
1269         CLEAR_FP_COND(cc, env->fpu);           \
1270     if (ch)                                    \
1271         SET_FP_COND(cc + 1, env->fpu);         \
1272     else                                       \
1273         CLEAR_FP_COND(cc + 1, env->fpu);       \
1274 }                                              \
1275 void do_cmpabs_ps_ ## op (long cc)             \
1276 {                                              \
1277     int cl, ch;                                \
1278     FST0 &= ~FLOAT_SIGN32;                     \
1279     FSTH0 &= ~FLOAT_SIGN32;                    \
1280     FST1 &= ~FLOAT_SIGN32;                     \
1281     FSTH1 &= ~FLOAT_SIGN32;                    \
1282     cl = condl;                                \
1283     ch = condh;                                \
1284     update_fcr31();                            \
1285     if (cl)                                    \
1286         SET_FP_COND(cc, env->fpu);             \
1287     else                                       \
1288         CLEAR_FP_COND(cc, env->fpu);           \
1289     if (ch)                                    \
1290         SET_FP_COND(cc + 1, env->fpu);         \
1291     else                                       \
1292         CLEAR_FP_COND(cc + 1, env->fpu);       \
1293 }
1294
1295 /* NOTE: the comma operator will make "cond" to eval to false,
1296  * but float*_is_unordered() is still called. */
1297 FOP_COND_PS(f,   (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
1298                  (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1299 FOP_COND_PS(un,  float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
1300                  float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
1301 FOP_COND_PS(eq,  !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status)   && float32_eq(FST0, FST1, &env->fpu->fp_status),
1302                  !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1303 FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status)    || float32_eq(FST0, FST1, &env->fpu->fp_status),
1304                  float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status)  || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1305 FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status)   && float32_lt(FST0, FST1, &env->fpu->fp_status),
1306                  !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1307 FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status)    || float32_lt(FST0, FST1, &env->fpu->fp_status),
1308                  float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status)  || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1309 FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status)   && float32_le(FST0, FST1, &env->fpu->fp_status),
1310                  !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1311 FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status)    || float32_le(FST0, FST1, &env->fpu->fp_status),
1312                  float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status)  || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1313 /* NOTE: the comma operator will make "cond" to eval to false,
1314  * but float*_is_unordered() is still called. */
1315 FOP_COND_PS(sf,  (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
1316                  (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1317 FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
1318                  float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
1319 FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status)   && float32_eq(FST0, FST1, &env->fpu->fp_status),
1320                  !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1321 FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status)    || float32_eq(FST0, FST1, &env->fpu->fp_status),
1322                  float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status)  || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1323 FOP_COND_PS(lt,  !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status)   && float32_lt(FST0, FST1, &env->fpu->fp_status),
1324                  !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1325 FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status)    || float32_lt(FST0, FST1, &env->fpu->fp_status),
1326                  float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status)  || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1327 FOP_COND_PS(le,  !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status)   && float32_le(FST0, FST1, &env->fpu->fp_status),
1328                  !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1329 FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status)    || float32_le(FST0, FST1, &env->fpu->fp_status),
1330                  float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status)  || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))