2 * Arm PrimeCell PL011 UART
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
11 #include "qemu-char.h"
12 #include "primecell.h"
23 uint32_t read_fifo
[16];
36 #define PL011_INT_TX 0x20
37 #define PL011_INT_RX 0x10
39 #define PL011_FLAG_TXFE 0x80
40 #define PL011_FLAG_RXFF 0x40
41 #define PL011_FLAG_TXFF 0x20
42 #define PL011_FLAG_RXFE 0x10
44 static const unsigned char pl011_id
[2][8] = {
45 { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_ARM */
46 { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_LUMINARY */
49 static void pl011_update(pl011_state
*s
)
53 flags
= s
->int_level
& s
->int_enabled
;
54 qemu_set_irq(s
->irq
, flags
!= 0);
57 static uint32_t pl011_read(void *opaque
, target_phys_addr_t offset
)
59 pl011_state
*s
= (pl011_state
*)opaque
;
63 if (offset
>= 0xfe0 && offset
< 0x1000) {
64 return pl011_id
[s
->type
][(offset
- 0xfe0) >> 2];
66 switch (offset
>> 2) {
68 s
->flags
&= ~PL011_FLAG_RXFF
;
69 c
= s
->read_fifo
[s
->read_pos
];
70 if (s
->read_count
> 0) {
72 if (++s
->read_pos
== 16)
75 if (s
->read_count
== 0) {
76 s
->flags
|= PL011_FLAG_RXFE
;
78 if (s
->read_count
== s
->read_trigger
- 1)
79 s
->int_level
&= ~ PL011_INT_RX
;
86 case 8: /* UARTILPR */
88 case 9: /* UARTIBRD */
90 case 10: /* UARTFBRD */
92 case 11: /* UARTLCR_H */
96 case 13: /* UARTIFLS */
98 case 14: /* UARTIMSC */
99 return s
->int_enabled
;
100 case 15: /* UARTRIS */
102 case 16: /* UARTMIS */
103 return s
->int_level
& s
->int_enabled
;
104 case 18: /* UARTDMACR */
107 cpu_abort (cpu_single_env
, "pl011_read: Bad offset %x\n", (int)offset
);
112 static void pl011_set_read_trigger(pl011_state
*s
)
115 /* The docs say the RX interrupt is triggered when the FIFO exceeds
116 the threshold. However linux only reads the FIFO in response to an
117 interrupt. Triggering the interrupt when the FIFO is non-empty seems
118 to make things work. */
120 s
->read_trigger
= (s
->ifl
>> 1) & 0x1c;
126 static void pl011_write(void *opaque
, target_phys_addr_t offset
,
129 pl011_state
*s
= (pl011_state
*)opaque
;
133 switch (offset
>> 2) {
135 /* ??? Check if transmitter is enabled. */
138 qemu_chr_write(s
->chr
, &ch
, 1);
139 s
->int_level
|= PL011_INT_TX
;
146 /* Writes to Flag register are ignored. */
148 case 8: /* UARTUARTILPR */
151 case 9: /* UARTIBRD */
154 case 10: /* UARTFBRD */
157 case 11: /* UARTLCR_H */
159 pl011_set_read_trigger(s
);
161 case 12: /* UARTCR */
162 /* ??? Need to implement the enable and loopback bits. */
165 case 13: /* UARTIFS */
167 pl011_set_read_trigger(s
);
169 case 14: /* UARTIMSC */
170 s
->int_enabled
= value
;
173 case 17: /* UARTICR */
174 s
->int_level
&= ~value
;
177 case 18: /* UARTDMACR */
180 cpu_abort(cpu_single_env
, "PL011: DMA not implemented\n");
183 cpu_abort (cpu_single_env
, "pl011_write: Bad offset %x\n", (int)offset
);
187 static int pl011_can_receive(void *opaque
)
189 pl011_state
*s
= (pl011_state
*)opaque
;
192 return s
->read_count
< 16;
194 return s
->read_count
< 1;
197 static void pl011_receive(void *opaque
, const uint8_t *buf
, int size
)
199 pl011_state
*s
= (pl011_state
*)opaque
;
202 slot
= s
->read_pos
+ s
->read_count
;
205 s
->read_fifo
[slot
] = *buf
;
207 s
->flags
&= ~PL011_FLAG_RXFE
;
208 if (s
->cr
& 0x10 || s
->read_count
== 16) {
209 s
->flags
|= PL011_FLAG_RXFF
;
211 if (s
->read_count
== s
->read_trigger
) {
212 s
->int_level
|= PL011_INT_RX
;
217 static void pl011_event(void *opaque
, int event
)
219 /* ??? Should probably implement break. */
222 static CPUReadMemoryFunc
*pl011_readfn
[] = {
228 static CPUWriteMemoryFunc
*pl011_writefn
[] = {
234 void pl011_init(uint32_t base
, qemu_irq irq
,
235 CharDriverState
*chr
, enum pl011_type type
)
240 s
= (pl011_state
*)qemu_mallocz(sizeof(pl011_state
));
241 iomemtype
= cpu_register_io_memory(0, pl011_readfn
,
243 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
253 qemu_chr_add_handlers(chr
, pl011_can_receive
, pl011_receive
,
256 /* ??? Save/restore. */