2 * MIPS emulation micro-operations for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #define CALL_FROM_TB0(func) func()
30 #define CALL_FROM_TB1(func, arg0) func(arg0)
32 #ifndef CALL_FROM_TB1_CONST16
33 #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
36 #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
38 #ifndef CALL_FROM_TB2_CONST16
39 #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
40 CALL_FROM_TB2(func, arg0, arg1)
43 #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
46 #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
47 func(arg0, arg1, arg2, arg3)
51 #include "op_template.c"
54 #include "op_template.c"
57 #include "op_template.c"
60 #include "op_template.c"
63 #include "op_template.c"
66 #include "op_template.c"
69 #include "op_template.c"
72 #include "op_template.c"
75 #include "op_template.c"
78 #include "op_template.c"
81 #include "op_template.c"
84 #include "op_template.c"
87 #include "op_template.c"
90 #include "op_template.c"
93 #include "op_template.c"
96 #include "op_template.c"
99 #include "op_template.c"
102 #include "op_template.c"
105 #include "op_template.c"
108 #include "op_template.c"
111 #include "op_template.c"
114 #include "op_template.c"
117 #include "op_template.c"
120 #include "op_template.c"
123 #include "op_template.c"
126 #include "op_template.c"
129 #include "op_template.c"
132 #include "op_template.c"
135 #include "op_template.c"
138 #include "op_template.c"
141 #include "op_template.c"
145 #include "op_template.c"
149 #include "fop_template.c"
152 #include "fop_template.c"
155 #include "fop_template.c"
158 #include "fop_template.c"
161 #include "fop_template.c"
164 #include "fop_template.c"
167 #include "fop_template.c"
170 #include "fop_template.c"
173 #include "fop_template.c"
176 #include "fop_template.c"
179 #include "fop_template.c"
182 #include "fop_template.c"
185 #include "fop_template.c"
188 #include "fop_template.c"
191 #include "fop_template.c"
194 #include "fop_template.c"
197 #include "fop_template.c"
200 #include "fop_template.c"
203 #include "fop_template.c"
206 #include "fop_template.c"
209 #include "fop_template.c"
212 #include "fop_template.c"
215 #include "fop_template.c"
218 #include "fop_template.c"
221 #include "fop_template.c"
224 #include "fop_template.c"
227 #include "fop_template.c"
230 #include "fop_template.c"
233 #include "fop_template.c"
236 #include "fop_template.c"
239 #include "fop_template.c"
242 #include "fop_template.c"
246 #include "fop_template.c"
249 void op_dup_T0 (void)
255 void op_load_HI (void)
261 void op_store_HI (void)
267 void op_load_LO (void)
273 void op_store_LO (void)
280 #define MEMSUFFIX _raw
283 #if !defined(CONFIG_USER_ONLY)
284 #define MEMSUFFIX _user
288 #define MEMSUFFIX _kernel
293 /* Addresses computation */
294 void op_addr_add (void)
296 /* For compatibility with 32-bit code, data reference in user mode
297 with Status_UX = 0 should be casted to 32-bit and sign extended.
298 See the MIPS64 PRA manual, section 4.10. */
300 if ((env
->CP0_Status
& (1 << CP0St_UM
)) &&
301 !(env
->CP0_Status
& (1 << CP0St_UX
)))
302 T0
= (int64_t)(int32_t)(T0
+ T1
);
312 T0
= (int32_t)((int32_t)T0
+ (int32_t)T1
);
321 T0
= (int32_t)T0
+ (int32_t)T1
;
322 if (((tmp
^ T1
^ (-1)) & (T0
^ T1
)) >> 31) {
323 /* operands of same sign, result different sign */
324 CALL_FROM_TB1(do_raise_exception
, EXCP_OVERFLOW
);
332 T0
= (int32_t)((int32_t)T0
- (int32_t)T1
);
341 T0
= (int32_t)T0
- (int32_t)T1
;
342 if (((tmp
^ T1
) & (tmp
^ T0
)) >> 31) {
343 /* operands of different sign, first operand and result different sign */
344 CALL_FROM_TB1(do_raise_exception
, EXCP_OVERFLOW
);
352 T0
= (int32_t)((int32_t)T0
* (int32_t)T1
);
356 #if HOST_LONG_BITS < 64
359 CALL_FROM_TB0(do_div
);
366 env
->LO
= (int32_t)((int64_t)(int32_t)T0
/ (int32_t)T1
);
367 env
->HI
= (int32_t)((int64_t)(int32_t)T0
% (int32_t)T1
);
376 env
->LO
= (int32_t)((uint32_t)T0
/ (uint32_t)T1
);
377 env
->HI
= (int32_t)((uint32_t)T0
% (uint32_t)T1
);
396 if (((tmp
^ T1
^ (-1)) & (T0
^ T1
)) >> 63) {
397 /* operands of same sign, result different sign */
398 CALL_FROM_TB1(do_raise_exception
, EXCP_OVERFLOW
);
414 T0
= (int64_t)T0
- (int64_t)T1
;
415 if (((tmp
^ T1
) & (tmp
^ T0
)) >> 63) {
416 /* operands of different sign, first operand and result different sign */
417 CALL_FROM_TB1(do_raise_exception
, EXCP_OVERFLOW
);
424 T0
= (int64_t)T0
* (int64_t)T1
;
428 /* Those might call libgcc functions. */
435 #if TARGET_LONG_BITS > HOST_LONG_BITS
451 #endif /* TARGET_MIPS64 */
480 T0
= (int32_t)((uint32_t)T0
<< T1
);
486 T0
= (int32_t)((int32_t)T0
>> T1
);
492 T0
= (int32_t)((uint32_t)T0
>> T1
);
501 tmp
= (int32_t)((uint32_t)T0
<< (0x20 - T1
));
502 T0
= (int32_t)((uint32_t)T0
>> T1
) | tmp
;
509 T0
= (int32_t)((uint32_t)T1
<< ((uint32_t)T0
& 0x1F));
515 T0
= (int32_t)((int32_t)T1
>> (T0
& 0x1F));
521 T0
= (int32_t)((uint32_t)T1
>> (T0
& 0x1F));
531 tmp
= (int32_t)((uint32_t)T1
<< (0x20 - T0
));
532 T0
= (int32_t)((uint32_t)T1
>> T0
) | tmp
;
542 if (T0
== ~((target_ulong
)0)) {
545 for (n
= 0; n
< 32; n
++) {
546 if (!(T0
& (1 << 31)))
562 for (n
= 0; n
< 32; n
++) {
574 #if TARGET_LONG_BITS > HOST_LONG_BITS
575 /* Those might call libgcc functions. */
578 CALL_FROM_TB0(do_dsll
);
582 void op_dsll32 (void)
584 CALL_FROM_TB0(do_dsll32
);
590 CALL_FROM_TB0(do_dsra
);
594 void op_dsra32 (void)
596 CALL_FROM_TB0(do_dsra32
);
602 CALL_FROM_TB0(do_dsrl
);
606 void op_dsrl32 (void)
608 CALL_FROM_TB0(do_dsrl32
);
614 CALL_FROM_TB0(do_drotr
);
618 void op_drotr32 (void)
620 CALL_FROM_TB0(do_drotr32
);
626 CALL_FROM_TB0(do_dsllv
);
632 CALL_FROM_TB0(do_dsrav
);
638 CALL_FROM_TB0(do_dsrlv
);
642 void op_drotrv (void)
644 CALL_FROM_TB0(do_drotrv
);
648 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
656 void op_dsll32 (void)
658 T0
= T0
<< (T1
+ 32);
664 T0
= (int64_t)T0
>> T1
;
668 void op_dsra32 (void)
670 T0
= (int64_t)T0
>> (T1
+ 32);
680 void op_dsrl32 (void)
682 T0
= T0
>> (T1
+ 32);
691 tmp
= T0
<< (0x40 - T1
);
692 T0
= (T0
>> T1
) | tmp
;
697 void op_drotr32 (void)
702 tmp
= T0
<< (0x40 - (32 + T1
));
703 T0
= (T0
>> (32 + T1
)) | tmp
;
710 T0
= T1
<< (T0
& 0x3F);
716 T0
= (int64_t)T1
>> (T0
& 0x3F);
722 T0
= T1
>> (T0
& 0x3F);
726 void op_drotrv (void)
732 tmp
= T1
<< (0x40 - T0
);
733 T0
= (T1
>> T0
) | tmp
;
738 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
744 if (T0
== ~((target_ulong
)0)) {
747 for (n
= 0; n
< 64; n
++) {
748 if (!(T0
& (1ULL << 63)))
764 for (n
= 0; n
< 64; n
++) {
765 if (T0
& (1ULL << 63))
775 /* 64 bits arithmetic */
776 #if TARGET_LONG_BITS > HOST_LONG_BITS
779 CALL_FROM_TB0(do_mult
);
785 CALL_FROM_TB0(do_multu
);
791 CALL_FROM_TB0(do_madd
);
797 CALL_FROM_TB0(do_maddu
);
803 CALL_FROM_TB0(do_msub
);
809 CALL_FROM_TB0(do_msubu
);
813 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
815 static inline uint64_t get_HILO (void)
817 return ((uint64_t)env
->HI
<< 32) | ((uint64_t)(uint32_t)env
->LO
);
820 static inline void set_HILO (uint64_t HILO
)
822 env
->LO
= (int32_t)(HILO
& 0xFFFFFFFF);
823 env
->HI
= (int32_t)(HILO
>> 32);
828 set_HILO((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
834 set_HILO((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
842 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
843 set_HILO((int64_t)get_HILO() + tmp
);
851 tmp
= ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
852 set_HILO(get_HILO() + tmp
);
860 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
861 set_HILO((int64_t)get_HILO() - tmp
);
869 tmp
= ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
870 set_HILO(get_HILO() - tmp
);
873 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
878 CALL_FROM_TB4(muls64
, &(env
->HI
), &(env
->LO
), T0
, T1
);
882 void op_dmultu (void)
884 CALL_FROM_TB4(mulu64
, &(env
->HI
), &(env
->LO
), T0
, T1
);
889 /* Conditional moves */
893 env
->gpr
[PARAM1
] = T0
;
900 env
->gpr
[PARAM1
] = T0
;
906 if (!(env
->fcr31
& PARAM1
))
913 if (env
->fcr31
& PARAM1
)
919 #define OP_COND(name, cond) \
920 void glue(op_, name) (void) \
930 OP_COND(eq
, T0
== T1
);
931 OP_COND(ne
, T0
!= T1
);
932 OP_COND(ge
, (target_long
)T0
>= (target_long
)T1
);
933 OP_COND(geu
, T0
>= T1
);
934 OP_COND(lt
, (target_long
)T0
< (target_long
)T1
);
935 OP_COND(ltu
, T0
< T1
);
936 OP_COND(gez
, (target_long
)T0
>= 0);
937 OP_COND(gtz
, (target_long
)T0
> 0);
938 OP_COND(lez
, (target_long
)T0
<= 0);
939 OP_COND(ltz
, (target_long
)T0
< 0);
942 void OPPROTO
op_goto_tb0(void)
944 GOTO_TB(op_goto_tb0
, PARAM1
, 0);
948 void OPPROTO
op_goto_tb1(void)
950 GOTO_TB(op_goto_tb1
, PARAM1
, 1);
954 /* Branch to register */
955 void op_save_breg_target (void)
961 void op_restore_breg_target (void)
973 void op_save_btarget (void)
975 env
->btarget
= PARAM1
;
980 void op_save_btarget64 (void)
982 env
->btarget
= ((uint64_t)PARAM1
<< 32) | (uint32_t)PARAM2
;
987 /* Conditional branch */
988 void op_set_bcond (void)
994 void op_save_bcond (void)
1000 void op_restore_bcond (void)
1006 void op_jnz_T2 (void)
1009 GOTO_LABEL_PARAM(1);
1014 void op_mfc0_index (void)
1016 T0
= env
->CP0_Index
;
1020 void op_mfc0_random (void)
1022 CALL_FROM_TB0(do_mfc0_random
);
1026 void op_mfc0_entrylo0 (void)
1028 T0
= (int32_t)env
->CP0_EntryLo0
;
1032 void op_mfc0_entrylo1 (void)
1034 T0
= (int32_t)env
->CP0_EntryLo1
;
1038 void op_mfc0_context (void)
1040 T0
= (int32_t)env
->CP0_Context
;
1044 void op_mfc0_pagemask (void)
1046 T0
= env
->CP0_PageMask
;
1050 void op_mfc0_pagegrain (void)
1052 T0
= env
->CP0_PageGrain
;
1056 void op_mfc0_wired (void)
1058 T0
= env
->CP0_Wired
;
1062 void op_mfc0_hwrena (void)
1064 T0
= env
->CP0_HWREna
;
1068 void op_mfc0_badvaddr (void)
1070 T0
= (int32_t)env
->CP0_BadVAddr
;
1074 void op_mfc0_count (void)
1076 CALL_FROM_TB0(do_mfc0_count
);
1080 void op_mfc0_entryhi (void)
1082 T0
= (int32_t)env
->CP0_EntryHi
;
1086 void op_mfc0_compare (void)
1088 T0
= env
->CP0_Compare
;
1092 void op_mfc0_status (void)
1094 T0
= env
->CP0_Status
;
1098 void op_mfc0_intctl (void)
1100 T0
= env
->CP0_IntCtl
;
1104 void op_mfc0_srsctl (void)
1106 T0
= env
->CP0_SRSCtl
;
1110 void op_mfc0_srsmap (void)
1112 T0
= env
->CP0_SRSMap
;
1116 void op_mfc0_cause (void)
1118 T0
= env
->CP0_Cause
;
1122 void op_mfc0_epc (void)
1124 T0
= (int32_t)env
->CP0_EPC
;
1128 void op_mfc0_prid (void)
1134 void op_mfc0_ebase (void)
1136 T0
= env
->CP0_EBase
;
1140 void op_mfc0_config0 (void)
1142 T0
= env
->CP0_Config0
;
1146 void op_mfc0_config1 (void)
1148 T0
= env
->CP0_Config1
;
1152 void op_mfc0_config2 (void)
1154 T0
= env
->CP0_Config2
;
1158 void op_mfc0_config3 (void)
1160 T0
= env
->CP0_Config3
;
1164 void op_mfc0_config6 (void)
1166 T0
= env
->CP0_Config6
;
1170 void op_mfc0_config7 (void)
1172 T0
= env
->CP0_Config7
;
1176 void op_mfc0_lladdr (void)
1178 T0
= (int32_t)env
->CP0_LLAddr
>> 4;
1182 void op_mfc0_watchlo (void)
1184 T0
= (int32_t)env
->CP0_WatchLo
[PARAM1
];
1188 void op_mfc0_watchhi (void)
1190 T0
= env
->CP0_WatchHi
[PARAM1
];
1194 void op_mfc0_xcontext (void)
1196 T0
= (int32_t)env
->CP0_XContext
;
1200 void op_mfc0_framemask (void)
1202 T0
= env
->CP0_Framemask
;
1206 void op_mfc0_debug (void)
1208 T0
= env
->CP0_Debug
;
1209 if (env
->hflags
& MIPS_HFLAG_DM
)
1210 T0
|= 1 << CP0DB_DM
;
1214 void op_mfc0_depc (void)
1216 T0
= (int32_t)env
->CP0_DEPC
;
1220 void op_mfc0_performance0 (void)
1222 T0
= env
->CP0_Performance0
;
1226 void op_mfc0_taglo (void)
1228 T0
= env
->CP0_TagLo
;
1232 void op_mfc0_datalo (void)
1234 T0
= env
->CP0_DataLo
;
1238 void op_mfc0_taghi (void)
1240 T0
= env
->CP0_TagHi
;
1244 void op_mfc0_datahi (void)
1246 T0
= env
->CP0_DataHi
;
1250 void op_mfc0_errorepc (void)
1252 T0
= (int32_t)env
->CP0_ErrorEPC
;
1256 void op_mfc0_desave (void)
1258 T0
= env
->CP0_DESAVE
;
1262 void op_mtc0_index (void)
1264 env
->CP0_Index
= (env
->CP0_Index
& 0x80000000) | (T0
% env
->nb_tlb
);
1268 void op_mtc0_entrylo0 (void)
1270 /* Large physaddr not implemented */
1271 /* 1k pages not implemented */
1272 env
->CP0_EntryLo0
= T0
& 0x3FFFFFFF;
1276 void op_mtc0_entrylo1 (void)
1278 /* Large physaddr not implemented */
1279 /* 1k pages not implemented */
1280 env
->CP0_EntryLo1
= T0
& 0x3FFFFFFF;
1284 void op_mtc0_context (void)
1286 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (T0
& ~0x007FFFFF);
1290 void op_mtc0_pagemask (void)
1292 /* 1k pages not implemented */
1293 env
->CP0_PageMask
= T0
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1297 void op_mtc0_pagegrain (void)
1299 /* SmartMIPS not implemented */
1300 /* Large physaddr not implemented */
1301 /* 1k pages not implemented */
1302 env
->CP0_PageGrain
= 0;
1306 void op_mtc0_wired (void)
1308 env
->CP0_Wired
= T0
% env
->nb_tlb
;
1312 void op_mtc0_hwrena (void)
1314 env
->CP0_HWREna
= T0
& 0x0000000F;
1318 void op_mtc0_count (void)
1320 CALL_FROM_TB2(cpu_mips_store_count
, env
, T0
);
1324 void op_mtc0_entryhi (void)
1326 target_ulong old
, val
;
1328 /* 1k pages not implemented */
1329 val
= T0
& ((TARGET_PAGE_MASK
<< 1) | 0xFF);
1330 #ifdef TARGET_MIPS64
1331 val
= T0
& 0xC00000FFFFFFFFFFULL
;
1333 old
= env
->CP0_EntryHi
;
1334 env
->CP0_EntryHi
= val
;
1335 /* If the ASID changes, flush qemu's TLB. */
1336 if ((old
& 0xFF) != (val
& 0xFF))
1337 CALL_FROM_TB2(cpu_mips_tlb_flush
, env
, 1);
1341 void op_mtc0_compare (void)
1343 CALL_FROM_TB2(cpu_mips_store_compare
, env
, T0
);
1347 void op_mtc0_status (void)
1350 uint32_t mask
= env
->Status_rw_bitmask
;
1352 /* No reverse endianness, no MDMX/DSP implemented. */
1354 old
= env
->CP0_Status
;
1355 if (!(val
& (1 << CP0St_EXL
)) &&
1356 !(val
& (1 << CP0St_ERL
)) &&
1357 !(env
->hflags
& MIPS_HFLAG_DM
) &&
1358 (val
& (1 << CP0St_UM
)))
1359 env
->hflags
|= MIPS_HFLAG_UM
;
1360 #ifdef TARGET_MIPS64
1361 if ((env
->hflags
& MIPS_HFLAG_UM
) &&
1362 !(val
& (1 << CP0St_PX
)) &&
1363 !(val
& (1 << CP0St_UX
)))
1364 env
->hflags
&= ~MIPS_HFLAG_64
;
1366 if (val
& (1 << CP0St_CU1
))
1367 env
->hflags
|= MIPS_HFLAG_FPU
;
1369 env
->hflags
&= ~MIPS_HFLAG_FPU
;
1370 if (val
& (1 << CP0St_FR
))
1371 env
->hflags
|= MIPS_HFLAG_F64
;
1373 env
->hflags
&= ~MIPS_HFLAG_F64
;
1374 env
->CP0_Status
= (env
->CP0_Status
& ~mask
) | val
;
1375 if (loglevel
& CPU_LOG_EXEC
)
1376 CALL_FROM_TB2(do_mtc0_status_debug
, old
, val
);
1377 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
1381 void op_mtc0_intctl (void)
1383 /* vectored interrupts not implemented, timer on int 7,
1384 no performance counters. */
1385 env
->CP0_IntCtl
|= T0
& 0x000002e0;
1389 void op_mtc0_srsctl (void)
1391 /* shadow registers not implemented */
1392 env
->CP0_SRSCtl
= 0;
1396 void op_mtc0_srsmap (void)
1398 /* shadow registers not implemented */
1399 env
->CP0_SRSMap
= 0;
1403 void op_mtc0_cause (void)
1405 uint32_t mask
= 0x00C00300;
1407 if ((env
->CP0_Config0
& (0x7 << CP0C0_AR
)) == (1 << CP0C0_AR
))
1408 mask
|= 1 << CP0Ca_DC
;
1410 env
->CP0_Cause
= (env
->CP0_Cause
& ~mask
) | (T0
& mask
);
1412 /* Handle the software interrupt as an hardware one, as they
1414 if (T0
& CP0Ca_IP_mask
) {
1415 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
1420 void op_mtc0_epc (void)
1426 void op_mtc0_ebase (void)
1428 /* vectored interrupts not implemented */
1429 /* Multi-CPU not implemented */
1430 env
->CP0_EBase
= 0x80000000 | (T0
& 0x3FFFF000);
1434 void op_mtc0_config0 (void)
1436 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (T0
& 0x00000001);
1440 void op_mtc0_config2 (void)
1442 /* tertiary/secondary caches not implemented */
1443 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1447 void op_mtc0_watchlo (void)
1449 /* Watch exceptions for instructions, data loads, data stores
1451 env
->CP0_WatchLo
[PARAM1
] = (T0
& ~0x7);
1455 void op_mtc0_watchhi (void)
1457 env
->CP0_WatchHi
[PARAM1
] = (T0
& 0x40FF0FF8);
1458 env
->CP0_WatchHi
[PARAM1
] &= ~(env
->CP0_WatchHi
[PARAM1
] & T0
& 0x7);
1462 void op_mtc0_framemask (void)
1464 env
->CP0_Framemask
= T0
; /* XXX */
1468 void op_mtc0_debug (void)
1470 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (T0
& 0x13300120);
1471 if (T0
& (1 << CP0DB_DM
))
1472 env
->hflags
|= MIPS_HFLAG_DM
;
1474 env
->hflags
&= ~MIPS_HFLAG_DM
;
1478 void op_mtc0_depc (void)
1484 void op_mtc0_performance0 (void)
1486 env
->CP0_Performance0
= T0
; /* XXX */
1490 void op_mtc0_taglo (void)
1492 env
->CP0_TagLo
= T0
& 0xFFFFFCF6;
1496 void op_mtc0_datalo (void)
1498 env
->CP0_DataLo
= T0
; /* XXX */
1502 void op_mtc0_taghi (void)
1504 env
->CP0_TagHi
= T0
; /* XXX */
1508 void op_mtc0_datahi (void)
1510 env
->CP0_DataHi
= T0
; /* XXX */
1514 void op_mtc0_errorepc (void)
1516 env
->CP0_ErrorEPC
= T0
;
1520 void op_mtc0_desave (void)
1522 env
->CP0_DESAVE
= T0
;
1526 #ifdef TARGET_MIPS64
1527 void op_mtc0_xcontext (void)
1529 env
->CP0_XContext
= (env
->CP0_XContext
& 0x1ffffffffULL
) | (T0
& ~0x1ffffffffULL
);
1533 void op_dmfc0_entrylo0 (void)
1535 T0
= env
->CP0_EntryLo0
;
1539 void op_dmfc0_entrylo1 (void)
1541 T0
= env
->CP0_EntryLo1
;
1545 void op_dmfc0_context (void)
1547 T0
= env
->CP0_Context
;
1551 void op_dmfc0_badvaddr (void)
1553 T0
= env
->CP0_BadVAddr
;
1557 void op_dmfc0_entryhi (void)
1559 T0
= env
->CP0_EntryHi
;
1563 void op_dmfc0_epc (void)
1569 void op_dmfc0_lladdr (void)
1571 T0
= env
->CP0_LLAddr
>> 4;
1575 void op_dmfc0_watchlo (void)
1577 T0
= env
->CP0_WatchLo
[PARAM1
];
1581 void op_dmfc0_xcontext (void)
1583 T0
= env
->CP0_XContext
;
1587 void op_dmfc0_depc (void)
1593 void op_dmfc0_errorepc (void)
1595 T0
= env
->CP0_ErrorEPC
;
1598 #endif /* TARGET_MIPS64 */
1602 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1604 # define DEBUG_FPU_STATE() do { } while(0)
1607 void op_cp0_enabled(void)
1609 if (!(env
->CP0_Status
& (1 << CP0St_CU0
)) &&
1610 (env
->hflags
& MIPS_HFLAG_UM
)) {
1611 CALL_FROM_TB2(do_raise_exception_err
, EXCP_CpU
, 0);
1620 T0
= (int32_t)env
->fcr0
;
1623 T0
= ((env
->fcr31
>> 24) & 0xfe) | ((env
->fcr31
>> 23) & 0x1);
1626 T0
= env
->fcr31
& 0x0003f07c;
1629 T0
= (env
->fcr31
& 0x00000f83) | ((env
->fcr31
>> 22) & 0x4);
1632 T0
= (int32_t)env
->fcr31
;
1641 CALL_FROM_TB0(do_ctc1
);
1660 void op_dmfc1 (void)
1667 void op_dmtc1 (void)
1674 void op_mfhc1 (void)
1681 void op_mthc1 (void)
1689 Single precition routines have a "s" suffix, double precision a
1690 "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
1691 paired single lowwer "pl", paired single upper "pu". */
1693 #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1697 CALL_FROM_TB0(do_float_cvtd_s
);
1703 CALL_FROM_TB0(do_float_cvtd_w
);
1709 CALL_FROM_TB0(do_float_cvtd_l
);
1715 CALL_FROM_TB0(do_float_cvtl_d
);
1721 CALL_FROM_TB0(do_float_cvtl_s
);
1734 CALL_FROM_TB0(do_float_cvtps_pw
);
1740 CALL_FROM_TB0(do_float_cvtpw_ps
);
1746 CALL_FROM_TB0(do_float_cvts_d
);
1752 CALL_FROM_TB0(do_float_cvts_w
);
1758 CALL_FROM_TB0(do_float_cvts_l
);
1764 CALL_FROM_TB0(do_float_cvts_pl
);
1770 CALL_FROM_TB0(do_float_cvts_pu
);
1776 CALL_FROM_TB0(do_float_cvtw_s
);
1782 CALL_FROM_TB0(do_float_cvtw_d
);
1789 DT2
= ((uint64_t)WT0
<< 32) | WT1
;
1795 DT2
= ((uint64_t)WT0
<< 32) | WTH1
;
1801 DT2
= ((uint64_t)WTH0
<< 32) | WT1
;
1807 DT2
= ((uint64_t)WTH0
<< 32) | WTH1
;
1812 #define FLOAT_ROUNDOP(op, ttype, stype) \
1813 FLOAT_OP(op ## ttype, stype) \
1815 CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \
1816 DEBUG_FPU_STATE(); \
1820 FLOAT_ROUNDOP(round
, l
, d
)
1821 FLOAT_ROUNDOP(round
, l
, s
)
1822 FLOAT_ROUNDOP(round
, w
, d
)
1823 FLOAT_ROUNDOP(round
, w
, s
)
1825 FLOAT_ROUNDOP(trunc
, l
, d
)
1826 FLOAT_ROUNDOP(trunc
, l
, s
)
1827 FLOAT_ROUNDOP(trunc
, w
, d
)
1828 FLOAT_ROUNDOP(trunc
, w
, s
)
1830 FLOAT_ROUNDOP(ceil
, l
, d
)
1831 FLOAT_ROUNDOP(ceil
, l
, s
)
1832 FLOAT_ROUNDOP(ceil
, w
, d
)
1833 FLOAT_ROUNDOP(ceil
, w
, s
)
1835 FLOAT_ROUNDOP(floor
, l
, d
)
1836 FLOAT_ROUNDOP(floor
, l
, s
)
1837 FLOAT_ROUNDOP(floor
, w
, d
)
1838 FLOAT_ROUNDOP(floor
, w
, s
)
1839 #undef FLOAR_ROUNDOP
1843 if (!(env
->fcr31
& PARAM1
))
1850 if (!(env
->fcr31
& PARAM1
))
1857 if (!(env
->fcr31
& PARAM1
)) {
1866 if (env
->fcr31
& PARAM1
)
1873 if (env
->fcr31
& PARAM1
)
1880 if (env
->fcr31
& PARAM1
) {
1934 /* operations calling helpers, for s, d and ps */
1935 #define FLOAT_HOP(name) \
1938 CALL_FROM_TB0(do_float_ ## name ## _d); \
1939 DEBUG_FPU_STATE(); \
1944 CALL_FROM_TB0(do_float_ ## name ## _s); \
1945 DEBUG_FPU_STATE(); \
1948 FLOAT_OP(name, ps) \
1950 CALL_FROM_TB0(do_float_ ## name ## _ps); \
1951 DEBUG_FPU_STATE(); \
1964 /* operations calling helpers, for s and d */
1965 #define FLOAT_HOP(name) \
1968 CALL_FROM_TB0(do_float_ ## name ## _d); \
1969 DEBUG_FPU_STATE(); \
1974 CALL_FROM_TB0(do_float_ ## name ## _s); \
1975 DEBUG_FPU_STATE(); \
1982 /* operations calling helpers, for ps */
1983 #define FLOAT_HOP(name) \
1984 FLOAT_OP(name, ps) \
1986 CALL_FROM_TB0(do_float_ ## name ## _ps); \
1987 DEBUG_FPU_STATE(); \
1994 /* ternary operations */
1995 #define FLOAT_TERNOP(name1, name2) \
1996 FLOAT_OP(name1 ## name2, d) \
1998 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status); \
1999 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status); \
2000 DEBUG_FPU_STATE(); \
2003 FLOAT_OP(name1 ## name2, s) \
2005 FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \
2006 FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \
2007 DEBUG_FPU_STATE(); \
2010 FLOAT_OP(name1 ## name2, ps) \
2012 FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \
2013 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \
2014 FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \
2015 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \
2016 DEBUG_FPU_STATE(); \
2019 FLOAT_TERNOP(mul
, add
)
2020 FLOAT_TERNOP(mul
, sub
)
2023 /* negated ternary operations */
2024 #define FLOAT_NTERNOP(name1, name2) \
2025 FLOAT_OP(n ## name1 ## name2, d) \
2027 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status); \
2028 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status); \
2029 FDT2 ^= 1ULL << 63; \
2030 DEBUG_FPU_STATE(); \
2033 FLOAT_OP(n ## name1 ## name2, s) \
2035 FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \
2036 FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \
2038 DEBUG_FPU_STATE(); \
2041 FLOAT_OP(n ## name1 ## name2, ps) \
2043 FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \
2044 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \
2045 FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \
2046 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \
2049 DEBUG_FPU_STATE(); \
2052 FLOAT_NTERNOP(mul
, add
)
2053 FLOAT_NTERNOP(mul
, sub
)
2054 #undef FLOAT_NTERNOP
2056 /* unary operations, modifying fp status */
2057 #define FLOAT_UNOP(name) \
2060 FDT2 = float64_ ## name(FDT0, &env->fp_status); \
2061 DEBUG_FPU_STATE(); \
2066 FST2 = float32_ ## name(FST0, &env->fp_status); \
2067 DEBUG_FPU_STATE(); \
2073 /* unary operations, not modifying fp status */
2074 #define FLOAT_UNOP(name) \
2077 FDT2 = float64_ ## name(FDT0); \
2078 DEBUG_FPU_STATE(); \
2083 FST2 = float32_ ## name(FST0); \
2084 DEBUG_FPU_STATE(); \
2087 FLOAT_OP(name, ps) \
2089 FST2 = float32_ ## name(FST0); \
2090 FSTH2 = float32_ ## name(FSTH0); \
2091 DEBUG_FPU_STATE(); \
2125 #ifdef TARGET_WORDS_BIGENDIAN
2133 default: /* unpredictable */
2140 #ifdef CONFIG_SOFTFLOAT
2141 #define clear_invalid() do { \
2142 int flags = get_float_exception_flags(&env->fp_status); \
2143 flags &= ~float_flag_invalid; \
2144 set_float_exception_flags(flags, &env->fp_status); \
2147 #define clear_invalid() do { } while(0)
2150 extern void dump_fpu_s(CPUState
*env
);
2152 #define CMP_OP(fmt, op) \
2153 void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void) \
2155 CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \
2156 DEBUG_FPU_STATE(); \
2159 void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void) \
2161 CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \
2162 DEBUG_FPU_STATE(); \
2165 #define CMP_OPS(op) \
2191 T0
= !!(~GET_FP_COND(env
) & (0x1 << PARAM1
));
2195 void op_bc1any2f (void)
2197 T0
= !!(~GET_FP_COND(env
) & (0x3 << PARAM1
));
2201 void op_bc1any4f (void)
2203 T0
= !!(~GET_FP_COND(env
) & (0xf << PARAM1
));
2210 T0
= !!(GET_FP_COND(env
) & (0x1 << PARAM1
));
2214 void op_bc1any2t (void)
2216 T0
= !!(GET_FP_COND(env
) & (0x3 << PARAM1
));
2220 void op_bc1any4t (void)
2222 T0
= !!(GET_FP_COND(env
) & (0xf << PARAM1
));
2227 void op_tlbwi (void)
2229 CALL_FROM_TB0(env
->do_tlbwi
);
2233 void op_tlbwr (void)
2235 CALL_FROM_TB0(env
->do_tlbwr
);
2241 CALL_FROM_TB0(env
->do_tlbp
);
2247 CALL_FROM_TB0(env
->do_tlbr
);
2252 #if defined (CONFIG_USER_ONLY)
2253 void op_tls_value (void)
2255 T0
= env
->tls_value
;
2261 CALL_FROM_TB1(do_pmon
, PARAM1
);
2267 T0
= env
->CP0_Status
;
2268 env
->CP0_Status
= T0
& ~(1 << CP0St_IE
);
2269 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
2275 T0
= env
->CP0_Status
;
2276 env
->CP0_Status
= T0
| (1 << CP0St_IE
);
2277 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
2284 CALL_FROM_TB1(do_raise_exception
, EXCP_TRAP
);
2289 void op_debug (void)
2291 CALL_FROM_TB1(do_raise_exception
, EXCP_DEBUG
);
2295 void op_set_lladdr (void)
2297 env
->CP0_LLAddr
= T2
;
2301 void debug_pre_eret (void);
2302 void debug_post_eret (void);
2305 if (loglevel
& CPU_LOG_EXEC
)
2306 CALL_FROM_TB0(debug_pre_eret
);
2307 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2308 env
->PC
= env
->CP0_ErrorEPC
;
2309 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2311 env
->PC
= env
->CP0_EPC
;
2312 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2314 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
2315 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
2316 !(env
->hflags
& MIPS_HFLAG_DM
) &&
2317 (env
->CP0_Status
& (1 << CP0St_UM
)))
2318 env
->hflags
|= MIPS_HFLAG_UM
;
2319 #ifdef TARGET_MIPS64
2320 if ((env
->hflags
& MIPS_HFLAG_UM
) &&
2321 !(env
->CP0_Status
& (1 << CP0St_PX
)) &&
2322 !(env
->CP0_Status
& (1 << CP0St_UX
)))
2323 env
->hflags
&= ~MIPS_HFLAG_64
;
2325 if (loglevel
& CPU_LOG_EXEC
)
2326 CALL_FROM_TB0(debug_post_eret
);
2327 env
->CP0_LLAddr
= 1;
2331 void op_deret (void)
2333 if (loglevel
& CPU_LOG_EXEC
)
2334 CALL_FROM_TB0(debug_pre_eret
);
2335 env
->PC
= env
->CP0_DEPC
;
2336 env
->hflags
|= MIPS_HFLAG_DM
;
2337 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
2338 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
2339 !(env
->hflags
& MIPS_HFLAG_DM
) &&
2340 (env
->CP0_Status
& (1 << CP0St_UM
)))
2341 env
->hflags
|= MIPS_HFLAG_UM
;
2342 #ifdef TARGET_MIPS64
2343 if ((env
->hflags
& MIPS_HFLAG_UM
) &&
2344 !(env
->CP0_Status
& (1 << CP0St_PX
)) &&
2345 !(env
->CP0_Status
& (1 << CP0St_UX
)))
2346 env
->hflags
&= ~MIPS_HFLAG_64
;
2348 if (loglevel
& CPU_LOG_EXEC
)
2349 CALL_FROM_TB0(debug_post_eret
);
2350 env
->CP0_LLAddr
= 1;
2354 void op_rdhwr_cpunum(void)
2356 if (!(env
->hflags
& MIPS_HFLAG_UM
) ||
2357 (env
->CP0_HWREna
& (1 << 0)) ||
2358 (env
->CP0_Status
& (1 << CP0St_CU0
)))
2359 T0
= env
->CP0_EBase
& 0x3ff;
2361 CALL_FROM_TB1(do_raise_exception
, EXCP_RI
);
2365 void op_rdhwr_synci_step(void)
2367 if (!(env
->hflags
& MIPS_HFLAG_UM
) ||
2368 (env
->CP0_HWREna
& (1 << 1)) ||
2369 (env
->CP0_Status
& (1 << CP0St_CU0
)))
2370 T0
= env
->SYNCI_Step
;
2372 CALL_FROM_TB1(do_raise_exception
, EXCP_RI
);
2376 void op_rdhwr_cc(void)
2378 if (!(env
->hflags
& MIPS_HFLAG_UM
) ||
2379 (env
->CP0_HWREna
& (1 << 2)) ||
2380 (env
->CP0_Status
& (1 << CP0St_CU0
)))
2381 T0
= env
->CP0_Count
;
2383 CALL_FROM_TB1(do_raise_exception
, EXCP_RI
);
2387 void op_rdhwr_ccres(void)
2389 if (!(env
->hflags
& MIPS_HFLAG_UM
) ||
2390 (env
->CP0_HWREna
& (1 << 3)) ||
2391 (env
->CP0_Status
& (1 << CP0St_CU0
)))
2394 CALL_FROM_TB1(do_raise_exception
, EXCP_RI
);
2398 void op_save_state (void)
2400 env
->hflags
= PARAM1
;
2404 void op_save_pc (void)
2410 #ifdef TARGET_MIPS64
2411 void op_save_pc64 (void)
2413 env
->PC
= ((uint64_t)PARAM1
<< 32) | (uint32_t)PARAM2
;
2418 void op_interrupt_restart (void)
2420 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
2421 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
2422 !(env
->hflags
& MIPS_HFLAG_DM
) &&
2423 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
2424 (env
->CP0_Status
& env
->CP0_Cause
& CP0Ca_IP_mask
)) {
2425 env
->CP0_Cause
&= ~(0x1f << CP0Ca_EC
);
2426 CALL_FROM_TB1(do_raise_exception
, EXCP_EXT_INTERRUPT
);
2431 void op_raise_exception (void)
2433 CALL_FROM_TB1(do_raise_exception
, PARAM1
);
2437 void op_raise_exception_err (void)
2439 CALL_FROM_TB2(do_raise_exception_err
, PARAM1
, PARAM2
);
2443 void op_exit_tb (void)
2452 CALL_FROM_TB1(do_raise_exception
, EXCP_HLT
);
2456 /* Bitfield operations. */
2459 unsigned int pos
= PARAM1
;
2460 unsigned int size
= PARAM2
;
2462 T0
= ((uint32_t)T1
>> pos
) & ((size
< 32) ? ((1 << size
) - 1) : ~0);
2468 unsigned int pos
= PARAM1
;
2469 unsigned int size
= PARAM2
;
2470 target_ulong mask
= ((size
< 32) ? ((1 << size
) - 1) : ~0) << pos
;
2472 T0
= (T0
& ~mask
) | (((uint32_t)T1
<< pos
) & mask
);
2478 T0
= ((T1
<< 8) & ~0x00FF00FF) | ((T1
>> 8) & 0x00FF00FF);
2482 #ifdef TARGET_MIPS64
2485 unsigned int pos
= PARAM1
;
2486 unsigned int size
= PARAM2
;
2488 T0
= (T1
>> pos
) & ((size
< 32) ? ((1 << size
) - 1) : ~0);
2494 unsigned int pos
= PARAM1
;
2495 unsigned int size
= PARAM2
;
2496 target_ulong mask
= ((size
< 32) ? ((1 << size
) - 1) : ~0) << pos
;
2498 T0
= (T0
& ~mask
) | ((T1
<< pos
) & mask
);
2504 T0
= ((T1
<< 8) & ~0x00FF00FF00FF00FFULL
) | ((T1
>> 8) & 0x00FF00FF00FF00FFULL
);
2510 T0
= ((T1
<< 16) & ~0x0000FFFF0000FFFFULL
) | ((T1
>> 16) & 0x0000FFFF0000FFFFULL
);
2517 T0
= ((T1
& 0xFF) ^ 0x80) - 0x80;
2523 T0
= ((T1
& 0xFFFF) ^ 0x8000) - 0x8000;