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More user timer fixes (Robert Reif)
[qemu/qemu_0_9_1_stable.git] / cpu-exec.c
blob55758faef299e8439d8bfa267f0f6f75a764eb36
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 void cpu_loop_exit(void)
44 {
45 /* NOTE: the register at this point must be saved by hand because
46 longjmp restore them */
47 regs_to_env();
48 longjmp(env->jmp_env, 1);
49 }
50
51 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
52 #define reg_T2
53 #endif
54
55 /* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
57 */
58 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 {
60 #if !defined(CONFIG_SOFTMMU)
61 struct ucontext *uc = puc;
62 #endif
63
64 env = env1;
65
66 /* XXX: restore cpu registers saved in host registers */
67
68 #if !defined(CONFIG_SOFTMMU)
69 if (puc) {
70 /* XXX: use siglongjmp ? */
71 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
72 }
73 #endif
74 longjmp(env->jmp_env, 1);
75 }
76
77
78 static TranslationBlock *tb_find_slow(target_ulong pc,
79 target_ulong cs_base,
80 uint64_t flags)
81 {
82 TranslationBlock *tb, **ptb1;
83 int code_gen_size;
84 unsigned int h;
85 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
86 uint8_t *tc_ptr;
87
88 spin_lock(&tb_lock);
89
90 tb_invalidated_flag = 0;
91
92 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93
94 /* find translated block using physical mappings */
95 phys_pc = get_phys_addr_code(env, pc);
96 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 phys_page2 = -1;
98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
104 if (tb->pc == pc &&
105 tb->page_addr[0] == phys_page1 &&
106 tb->cs_base == cs_base &&
107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
110 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 TARGET_PAGE_SIZE;
112 phys_page2 = get_phys_addr_code(env, virt_page2);
113 if (tb->page_addr[1] == phys_page2)
114 goto found;
115 } else {
116 goto found;
117 }
118 }
119 ptb1 = &tb->phys_hash_next;
120 }
121 not_found:
122 /* if no translated code available, then translate it now */
123 tb = tb_alloc(pc);
124 if (!tb) {
125 /* flush must be done */
126 tb_flush(env);
127 /* cannot fail at this point */
128 tb = tb_alloc(pc);
129 /* don't forget to invalidate previous TB info */
130 tb_invalidated_flag = 1;
131 }
132 tc_ptr = code_gen_ptr;
133 tb->tc_ptr = tc_ptr;
134 tb->cs_base = cs_base;
135 tb->flags = flags;
136 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
137 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138
139 /* check next page if needed */
140 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
143 phys_page2 = get_phys_addr_code(env, virt_page2);
144 }
145 tb_link_phys(tb, phys_pc, phys_page2);
146
147 found:
148 /* we add the TB in the virtual pc hash table */
149 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
150 spin_unlock(&tb_lock);
151 return tb;
152 }
153
154 static inline TranslationBlock *tb_find_fast(void)
155 {
156 TranslationBlock *tb;
157 target_ulong cs_base, pc;
158 uint64_t flags;
159
160 /* we record a subset of the CPU state. It will
161 always be the same before a given translated block
162 is executed. */
163 #if defined(TARGET_I386)
164 flags = env->hflags;
165 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
166 flags |= env->intercept;
167 cs_base = env->segs[R_CS].base;
168 pc = cs_base + env->eip;
169 #elif defined(TARGET_ARM)
170 flags = env->thumb | (env->vfp.vec_len << 1)
171 | (env->vfp.vec_stride << 4);
172 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
173 flags |= (1 << 6);
174 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
175 flags |= (1 << 7);
176 cs_base = 0;
177 pc = env->regs[15];
178 #elif defined(TARGET_SPARC)
179 #ifdef TARGET_SPARC64
180 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
181 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
182 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183 #else
184 // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor
185 flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3)
186 | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
187 | env->psrs;
188 #endif
189 cs_base = env->npc;
190 pc = env->pc;
191 #elif defined(TARGET_PPC)
192 flags = env->hflags;
193 cs_base = 0;
194 pc = env->nip;
195 #elif defined(TARGET_MIPS)
196 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
197 cs_base = 0;
198 pc = env->PC[env->current_tc];
199 #elif defined(TARGET_M68K)
200 flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
201 | (env->sr & SR_S) /* Bit 13 */
202 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
203 cs_base = 0;
204 pc = env->pc;
205 #elif defined(TARGET_SH4)
206 flags = env->sr & (SR_MD | SR_RB);
207 cs_base = 0; /* XXXXX */
208 pc = env->pc;
209 #elif defined(TARGET_ALPHA)
210 flags = env->ps;
211 cs_base = 0;
212 pc = env->pc;
213 #else
214 #error unsupported CPU
215 #endif
216 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
217 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
218 tb->flags != flags, 0)) {
219 tb = tb_find_slow(pc, cs_base, flags);
220 /* Note: we do it here to avoid a gcc bug on Mac OS X when
221 doing it in tb_find_slow */
222 if (tb_invalidated_flag) {
223 /* as some TB could have been invalidated because
224 of memory exceptions while generating the code, we
225 must recompute the hash index here */
226 T0 = 0;
227 }
228 }
229 return tb;
230 }
231
232
233 /* main execution loop */
234
235 int cpu_exec(CPUState *env1)
236 {
237 #define DECLARE_HOST_REGS 1
238 #include "hostregs_helper.h"
239 #if defined(TARGET_SPARC)
240 #if defined(reg_REGWPTR)
241 uint32_t *saved_regwptr;
242 #endif
243 #endif
244 #if defined(__sparc__) && !defined(HOST_SOLARIS)
245 int saved_i7;
246 target_ulong tmp_T0;
247 #endif
248 int ret, interrupt_request;
249 void (*gen_func)(void);
250 TranslationBlock *tb;
251 uint8_t *tc_ptr;
252
253 if (cpu_halted(env1) == EXCP_HALTED)
254 return EXCP_HALTED;
255
256 cpu_single_env = env1;
257
258 /* first we save global registers */
259 #define SAVE_HOST_REGS 1
260 #include "hostregs_helper.h"
261 env = env1;
262 #if defined(__sparc__) && !defined(HOST_SOLARIS)
263 /* we also save i7 because longjmp may not restore it */
264 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
265 #endif
266
267 env_to_regs();
268 #if defined(TARGET_I386)
269 /* put eflags in CPU temporary format */
270 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
271 DF = 1 - (2 * ((env->eflags >> 10) & 1));
272 CC_OP = CC_OP_EFLAGS;
273 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
274 #elif defined(TARGET_SPARC)
275 #if defined(reg_REGWPTR)
276 saved_regwptr = REGWPTR;
277 #endif
278 #elif defined(TARGET_M68K)
279 env->cc_op = CC_OP_FLAGS;
280 env->cc_dest = env->sr & 0xf;
281 env->cc_x = (env->sr >> 4) & 1;
282 #elif defined(TARGET_ALPHA)
283 #elif defined(TARGET_ARM)
284 #elif defined(TARGET_PPC)
285 #elif defined(TARGET_MIPS)
286 #elif defined(TARGET_SH4)
287 /* XXXXX */
288 #else
289 #error unsupported target CPU
290 #endif
291 env->exception_index = -1;
292
293 /* prepare setjmp context for exception handling */
294 for(;;) {
295 if (setjmp(env->jmp_env) == 0) {
296 env->current_tb = NULL;
297 /* if an exception is pending, we execute it here */
298 if (env->exception_index >= 0) {
299 if (env->exception_index >= EXCP_INTERRUPT) {
300 /* exit request from the cpu execution loop */
301 ret = env->exception_index;
302 break;
303 } else if (env->user_mode_only) {
304 /* if user mode only, we simulate a fake exception
305 which will be handled outside the cpu execution
306 loop */
307 #if defined(TARGET_I386)
308 do_interrupt_user(env->exception_index,
309 env->exception_is_int,
310 env->error_code,
311 env->exception_next_eip);
312 #endif
313 ret = env->exception_index;
314 break;
315 } else {
316 #if defined(TARGET_I386)
317 /* simulate a real cpu exception. On i386, it can
318 trigger new exceptions, but we do not handle
319 double or triple faults yet. */
320 do_interrupt(env->exception_index,
321 env->exception_is_int,
322 env->error_code,
323 env->exception_next_eip, 0);
324 /* successfully delivered */
325 env->old_exception = -1;
326 #elif defined(TARGET_PPC)
327 do_interrupt(env);
328 #elif defined(TARGET_MIPS)
329 do_interrupt(env);
330 #elif defined(TARGET_SPARC)
331 do_interrupt(env->exception_index);
332 #elif defined(TARGET_ARM)
333 do_interrupt(env);
334 #elif defined(TARGET_SH4)
335 do_interrupt(env);
336 #elif defined(TARGET_ALPHA)
337 do_interrupt(env);
338 #elif defined(TARGET_M68K)
339 do_interrupt(0);
340 #endif
341 }
342 env->exception_index = -1;
343 }
344 #ifdef USE_KQEMU
345 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
346 int ret;
347 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
348 ret = kqemu_cpu_exec(env);
349 /* put eflags in CPU temporary format */
350 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
351 DF = 1 - (2 * ((env->eflags >> 10) & 1));
352 CC_OP = CC_OP_EFLAGS;
353 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
354 if (ret == 1) {
355 /* exception */
356 longjmp(env->jmp_env, 1);
357 } else if (ret == 2) {
358 /* softmmu execution needed */
359 } else {
360 if (env->interrupt_request != 0) {
361 /* hardware interrupt will be executed just after */
362 } else {
363 /* otherwise, we restart */
364 longjmp(env->jmp_env, 1);
365 }
366 }
367 }
368 #endif
369
370 T0 = 0; /* force lookup of first TB */
371 for(;;) {
372 #if defined(__sparc__) && !defined(HOST_SOLARIS)
373 /* g1 can be modified by some libc? functions */
374 tmp_T0 = T0;
375 #endif
376 interrupt_request = env->interrupt_request;
377 if (__builtin_expect(interrupt_request, 0)
378 #if defined(TARGET_I386)
379 && env->hflags & HF_GIF_MASK
380 #endif
381 ) {
382 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
383 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
384 env->exception_index = EXCP_DEBUG;
385 cpu_loop_exit();
386 }
387 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
388 defined(TARGET_PPC) || defined(TARGET_ALPHA)
389 if (interrupt_request & CPU_INTERRUPT_HALT) {
390 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
391 env->halted = 1;
392 env->exception_index = EXCP_HLT;
393 cpu_loop_exit();
394 }
395 #endif
396 #if defined(TARGET_I386)
397 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
398 !(env->hflags & HF_SMM_MASK)) {
399 svm_check_intercept(SVM_EXIT_SMI);
400 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
401 do_smm_enter();
402 #if defined(__sparc__) && !defined(HOST_SOLARIS)
403 tmp_T0 = 0;
404 #else
405 T0 = 0;
406 #endif
407 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
408 (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) &&
409 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
410 int intno;
411 svm_check_intercept(SVM_EXIT_INTR);
412 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
413 intno = cpu_get_pic_interrupt(env);
414 if (loglevel & CPU_LOG_TB_IN_ASM) {
415 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
416 }
417 do_interrupt(intno, 0, 0, 0, 1);
418 /* ensure that no TB jump will be modified as
419 the program flow was changed */
420 #if defined(__sparc__) && !defined(HOST_SOLARIS)
421 tmp_T0 = 0;
422 #else
423 T0 = 0;
424 #endif
425 #if !defined(CONFIG_USER_ONLY)
426 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
427 (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
428 int intno;
429 /* FIXME: this should respect TPR */
430 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
431 svm_check_intercept(SVM_EXIT_VINTR);
432 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
433 if (loglevel & CPU_LOG_TB_IN_ASM)
434 fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno);
435 do_interrupt(intno, 0, 0, -1, 1);
436 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
437 ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK);
438 #if defined(__sparc__) && !defined(HOST_SOLARIS)
439 tmp_T0 = 0;
440 #else
441 T0 = 0;
442 #endif
443 #endif
444 }
445 #elif defined(TARGET_PPC)
446 #if 0
447 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
448 cpu_ppc_reset(env);
449 }
450 #endif
451 if (interrupt_request & CPU_INTERRUPT_HARD) {
452 ppc_hw_interrupt(env);
453 if (env->pending_interrupts == 0)
454 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
455 #if defined(__sparc__) && !defined(HOST_SOLARIS)
456 tmp_T0 = 0;
457 #else
458 T0 = 0;
459 #endif
460 }
461 #elif defined(TARGET_MIPS)
462 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
463 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
464 (env->CP0_Status & (1 << CP0St_IE)) &&
465 !(env->CP0_Status & (1 << CP0St_EXL)) &&
466 !(env->CP0_Status & (1 << CP0St_ERL)) &&
467 !(env->hflags & MIPS_HFLAG_DM)) {
468 /* Raise it */
469 env->exception_index = EXCP_EXT_INTERRUPT;
470 env->error_code = 0;
471 do_interrupt(env);
472 #if defined(__sparc__) && !defined(HOST_SOLARIS)
473 tmp_T0 = 0;
474 #else
475 T0 = 0;
476 #endif
477 }
478 #elif defined(TARGET_SPARC)
479 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
480 (env->psret != 0)) {
481 int pil = env->interrupt_index & 15;
482 int type = env->interrupt_index & 0xf0;
483
484 if (((type == TT_EXTINT) &&
485 (pil == 15 || pil > env->psrpil)) ||
486 type != TT_EXTINT) {
487 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
488 do_interrupt(env->interrupt_index);
489 env->interrupt_index = 0;
490 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
491 cpu_check_irqs(env);
492 #endif
493 #if defined(__sparc__) && !defined(HOST_SOLARIS)
494 tmp_T0 = 0;
495 #else
496 T0 = 0;
497 #endif
498 }
499 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
500 //do_interrupt(0, 0, 0, 0, 0);
501 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
502 }
503 #elif defined(TARGET_ARM)
504 if (interrupt_request & CPU_INTERRUPT_FIQ
505 && !(env->uncached_cpsr & CPSR_F)) {
506 env->exception_index = EXCP_FIQ;
507 do_interrupt(env);
508 }
509 if (interrupt_request & CPU_INTERRUPT_HARD
510 && !(env->uncached_cpsr & CPSR_I)) {
511 env->exception_index = EXCP_IRQ;
512 do_interrupt(env);
513 }
514 #elif defined(TARGET_SH4)
515 /* XXXXX */
516 #elif defined(TARGET_ALPHA)
517 if (interrupt_request & CPU_INTERRUPT_HARD) {
518 do_interrupt(env);
519 }
520 #elif defined(TARGET_M68K)
521 if (interrupt_request & CPU_INTERRUPT_HARD
522 && ((env->sr & SR_I) >> SR_I_SHIFT)
523 < env->pending_level) {
524 /* Real hardware gets the interrupt vector via an
525 IACK cycle at this point. Current emulated
526 hardware doesn't rely on this, so we
527 provide/save the vector when the interrupt is
528 first signalled. */
529 env->exception_index = env->pending_vector;
530 do_interrupt(1);
531 }
532 #endif
533 /* Don't use the cached interupt_request value,
534 do_interrupt may have updated the EXITTB flag. */
535 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
536 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
537 /* ensure that no TB jump will be modified as
538 the program flow was changed */
539 #if defined(__sparc__) && !defined(HOST_SOLARIS)
540 tmp_T0 = 0;
541 #else
542 T0 = 0;
543 #endif
544 }
545 if (interrupt_request & CPU_INTERRUPT_EXIT) {
546 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
547 env->exception_index = EXCP_INTERRUPT;
548 cpu_loop_exit();
549 }
550 }
551 #ifdef DEBUG_EXEC
552 if ((loglevel & CPU_LOG_TB_CPU)) {
553 /* restore flags in standard format */
554 regs_to_env();
555 #if defined(TARGET_I386)
556 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
557 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
558 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
559 #elif defined(TARGET_ARM)
560 cpu_dump_state(env, logfile, fprintf, 0);
561 #elif defined(TARGET_SPARC)
562 REGWPTR = env->regbase + (env->cwp * 16);
563 env->regwptr = REGWPTR;
564 cpu_dump_state(env, logfile, fprintf, 0);
565 #elif defined(TARGET_PPC)
566 cpu_dump_state(env, logfile, fprintf, 0);
567 #elif defined(TARGET_M68K)
568 cpu_m68k_flush_flags(env, env->cc_op);
569 env->cc_op = CC_OP_FLAGS;
570 env->sr = (env->sr & 0xffe0)
571 | env->cc_dest | (env->cc_x << 4);
572 cpu_dump_state(env, logfile, fprintf, 0);
573 #elif defined(TARGET_MIPS)
574 cpu_dump_state(env, logfile, fprintf, 0);
575 #elif defined(TARGET_SH4)
576 cpu_dump_state(env, logfile, fprintf, 0);
577 #elif defined(TARGET_ALPHA)
578 cpu_dump_state(env, logfile, fprintf, 0);
579 #else
580 #error unsupported target CPU
581 #endif
582 }
583 #endif
584 tb = tb_find_fast();
585 #ifdef DEBUG_EXEC
586 if ((loglevel & CPU_LOG_EXEC)) {
587 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
588 (long)tb->tc_ptr, tb->pc,
589 lookup_symbol(tb->pc));
590 }
591 #endif
592 #if defined(__sparc__) && !defined(HOST_SOLARIS)
593 T0 = tmp_T0;
594 #endif
595 /* see if we can patch the calling TB. When the TB
596 spans two pages, we cannot safely do a direct
597 jump. */
598 {
599 if (T0 != 0 &&
600 #if USE_KQEMU
601 (env->kqemu_enabled != 2) &&
602 #endif
603 tb->page_addr[1] == -1
604 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
605 && (tb->cflags & CF_CODE_COPY) ==
606 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
607 #endif
608 ) {
609 spin_lock(&tb_lock);
610 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
611 #if defined(USE_CODE_COPY)
612 /* propagates the FP use info */
613 ((TranslationBlock *)(T0 & ~3))->cflags |=
614 (tb->cflags & CF_FP_USED);
615 #endif
616 spin_unlock(&tb_lock);
617 }
618 }
619 tc_ptr = tb->tc_ptr;
620 env->current_tb = tb;
621 /* execute the generated code */
622 gen_func = (void *)tc_ptr;
623 #if defined(__sparc__)
624 __asm__ __volatile__("call %0\n\t"
625 "mov %%o7,%%i0"
626 : /* no outputs */
627 : "r" (gen_func)
628 : "i0", "i1", "i2", "i3", "i4", "i5",
629 "o0", "o1", "o2", "o3", "o4", "o5",
630 "l0", "l1", "l2", "l3", "l4", "l5",
631 "l6", "l7");
632 #elif defined(__arm__)
633 asm volatile ("mov pc, %0\n\t"
634 ".global exec_loop\n\t"
635 "exec_loop:\n\t"
636 : /* no outputs */
637 : "r" (gen_func)
638 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
639 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
640 {
641 if (!(tb->cflags & CF_CODE_COPY)) {
642 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
643 save_native_fp_state(env);
644 }
645 gen_func();
646 } else {
647 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
648 restore_native_fp_state(env);
649 }
650 /* we work with native eflags */
651 CC_SRC = cc_table[CC_OP].compute_all();
652 CC_OP = CC_OP_EFLAGS;
653 asm(".globl exec_loop\n"
654 "\n"
655 "debug1:\n"
656 " pushl %%ebp\n"
657 " fs movl %10, %9\n"
658 " fs movl %11, %%eax\n"
659 " andl $0x400, %%eax\n"
660 " fs orl %8, %%eax\n"
661 " pushl %%eax\n"
662 " popf\n"
663 " fs movl %%esp, %12\n"
664 " fs movl %0, %%eax\n"
665 " fs movl %1, %%ecx\n"
666 " fs movl %2, %%edx\n"
667 " fs movl %3, %%ebx\n"
668 " fs movl %4, %%esp\n"
669 " fs movl %5, %%ebp\n"
670 " fs movl %6, %%esi\n"
671 " fs movl %7, %%edi\n"
672 " fs jmp *%9\n"
673 "exec_loop:\n"
674 " fs movl %%esp, %4\n"
675 " fs movl %12, %%esp\n"
676 " fs movl %%eax, %0\n"
677 " fs movl %%ecx, %1\n"
678 " fs movl %%edx, %2\n"
679 " fs movl %%ebx, %3\n"
680 " fs movl %%ebp, %5\n"
681 " fs movl %%esi, %6\n"
682 " fs movl %%edi, %7\n"
683 " pushf\n"
684 " popl %%eax\n"
685 " movl %%eax, %%ecx\n"
686 " andl $0x400, %%ecx\n"
687 " shrl $9, %%ecx\n"
688 " andl $0x8d5, %%eax\n"
689 " fs movl %%eax, %8\n"
690 " movl $1, %%eax\n"
691 " subl %%ecx, %%eax\n"
692 " fs movl %%eax, %11\n"
693 " fs movl %9, %%ebx\n" /* get T0 value */
694 " popl %%ebp\n"
695 :
696 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
697 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
698 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
699 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
700 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
701 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
702 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
703 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
704 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
705 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
706 "a" (gen_func),
707 "m" (*(uint8_t *)offsetof(CPUState, df)),
708 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
709 : "%ecx", "%edx"
710 );
711 }
712 }
713 #elif defined(__ia64)
714 struct fptr {
715 void *ip;
716 void *gp;
717 } fp;
718
719 fp.ip = tc_ptr;
720 fp.gp = code_gen_buffer + 2 * (1 << 20);
721 (*(void (*)(void)) &fp)();
722 #else
723 gen_func();
724 #endif
725 env->current_tb = NULL;
726 /* reset soft MMU for next block (it can currently
727 only be set by a memory fault) */
728 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
729 if (env->hflags & HF_SOFTMMU_MASK) {
730 env->hflags &= ~HF_SOFTMMU_MASK;
731 /* do not allow linking to another block */
732 T0 = 0;
733 }
734 #endif
735 #if defined(USE_KQEMU)
736 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
737 if (kqemu_is_ok(env) &&
738 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
739 cpu_loop_exit();
740 }
741 #endif
742 } /* for(;;) */
743 } else {
744 env_to_regs();
745 }
746 } /* for(;;) */
747
748
749 #if defined(TARGET_I386)
750 #if defined(USE_CODE_COPY)
751 if (env->native_fp_regs) {
752 save_native_fp_state(env);
753 }
754 #endif
755 /* restore flags in standard format */
756 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
757 #elif defined(TARGET_ARM)
758 /* XXX: Save/restore host fpu exception state?. */
759 #elif defined(TARGET_SPARC)
760 #if defined(reg_REGWPTR)
761 REGWPTR = saved_regwptr;
762 #endif
763 #elif defined(TARGET_PPC)
764 #elif defined(TARGET_M68K)
765 cpu_m68k_flush_flags(env, env->cc_op);
766 env->cc_op = CC_OP_FLAGS;
767 env->sr = (env->sr & 0xffe0)
768 | env->cc_dest | (env->cc_x << 4);
769 #elif defined(TARGET_MIPS)
770 #elif defined(TARGET_SH4)
771 #elif defined(TARGET_ALPHA)
772 /* XXXXX */
773 #else
774 #error unsupported target CPU
775 #endif
776
777 /* restore global registers */
778 #if defined(__sparc__) && !defined(HOST_SOLARIS)
779 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
780 #endif
781 #include "hostregs_helper.h"
782
783 /* fail safe : never use cpu_single_env outside cpu_exec() */
784 cpu_single_env = NULL;
785 return ret;
786 }
787
788 /* must only be called from the generated code as an exception can be
789 generated */
790 void tb_invalidate_page_range(target_ulong start, target_ulong end)
791 {
792 /* XXX: cannot enable it yet because it yields to MMU exception
793 where NIP != read address on PowerPC */
794 #if 0
795 target_ulong phys_addr;
796 phys_addr = get_phys_addr_code(env, start);
797 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
798 #endif
799 }
800
801 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
802
803 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
804 {
805 CPUX86State *saved_env;
806
807 saved_env = env;
808 env = s;
809 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
810 selector &= 0xffff;
811 cpu_x86_load_seg_cache(env, seg_reg, selector,
812 (selector << 4), 0xffff, 0);
813 } else {
814 load_seg(seg_reg, selector);
815 }
816 env = saved_env;
817 }
818
819 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
820 {
821 CPUX86State *saved_env;
822
823 saved_env = env;
824 env = s;
825
826 helper_fsave((target_ulong)ptr, data32);
827
828 env = saved_env;
829 }
830
831 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
832 {
833 CPUX86State *saved_env;
834
835 saved_env = env;
836 env = s;
837
838 helper_frstor((target_ulong)ptr, data32);
839
840 env = saved_env;
841 }
842
843 #endif /* TARGET_I386 */
844
845 #if !defined(CONFIG_SOFTMMU)
846
847 #if defined(TARGET_I386)
848
849 /* 'pc' is the host PC at which the exception was raised. 'address' is
850 the effective address of the memory exception. 'is_write' is 1 if a
851 write caused the exception and otherwise 0'. 'old_set' is the
852 signal set which should be restored */
853 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
854 int is_write, sigset_t *old_set,
855 void *puc)
856 {
857 TranslationBlock *tb;
858 int ret;
859
860 if (cpu_single_env)
861 env = cpu_single_env; /* XXX: find a correct solution for multithread */
862 #if defined(DEBUG_SIGNAL)
863 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
864 pc, address, is_write, *(unsigned long *)old_set);
865 #endif
866 /* XXX: locking issue */
867 if (is_write && page_unprotect(h2g(address), pc, puc)) {
868 return 1;
869 }
870
871 /* see if it is an MMU fault */
872 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
873 ((env->hflags & HF_CPL_MASK) == 3), 0);
874 if (ret < 0)
875 return 0; /* not an MMU fault */
876 if (ret == 0)
877 return 1; /* the MMU fault was handled without causing real CPU fault */
878 /* now we have a real cpu fault */
879 tb = tb_find_pc(pc);
880 if (tb) {
881 /* the PC is inside the translated code. It means that we have
882 a virtual CPU fault */
883 cpu_restore_state(tb, env, pc, puc);
884 }
885 if (ret == 1) {
886 #if 0
887 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
888 env->eip, env->cr[2], env->error_code);
889 #endif
890 /* we restore the process signal mask as the sigreturn should
891 do it (XXX: use sigsetjmp) */
892 sigprocmask(SIG_SETMASK, old_set, NULL);
893 raise_exception_err(env->exception_index, env->error_code);
894 } else {
895 /* activate soft MMU for this block */
896 env->hflags |= HF_SOFTMMU_MASK;
897 cpu_resume_from_signal(env, puc);
898 }
899 /* never comes here */
900 return 1;
901 }
902
903 #elif defined(TARGET_ARM)
904 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
905 int is_write, sigset_t *old_set,
906 void *puc)
907 {
908 TranslationBlock *tb;
909 int ret;
910
911 if (cpu_single_env)
912 env = cpu_single_env; /* XXX: find a correct solution for multithread */
913 #if defined(DEBUG_SIGNAL)
914 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
915 pc, address, is_write, *(unsigned long *)old_set);
916 #endif
917 /* XXX: locking issue */
918 if (is_write && page_unprotect(h2g(address), pc, puc)) {
919 return 1;
920 }
921 /* see if it is an MMU fault */
922 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
923 if (ret < 0)
924 return 0; /* not an MMU fault */
925 if (ret == 0)
926 return 1; /* the MMU fault was handled without causing real CPU fault */
927 /* now we have a real cpu fault */
928 tb = tb_find_pc(pc);
929 if (tb) {
930 /* the PC is inside the translated code. It means that we have
931 a virtual CPU fault */
932 cpu_restore_state(tb, env, pc, puc);
933 }
934 /* we restore the process signal mask as the sigreturn should
935 do it (XXX: use sigsetjmp) */
936 sigprocmask(SIG_SETMASK, old_set, NULL);
937 cpu_loop_exit();
938 }
939 #elif defined(TARGET_SPARC)
940 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
941 int is_write, sigset_t *old_set,
942 void *puc)
943 {
944 TranslationBlock *tb;
945 int ret;
946
947 if (cpu_single_env)
948 env = cpu_single_env; /* XXX: find a correct solution for multithread */
949 #if defined(DEBUG_SIGNAL)
950 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
951 pc, address, is_write, *(unsigned long *)old_set);
952 #endif
953 /* XXX: locking issue */
954 if (is_write && page_unprotect(h2g(address), pc, puc)) {
955 return 1;
956 }
957 /* see if it is an MMU fault */
958 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
959 if (ret < 0)
960 return 0; /* not an MMU fault */
961 if (ret == 0)
962 return 1; /* the MMU fault was handled without causing real CPU fault */
963 /* now we have a real cpu fault */
964 tb = tb_find_pc(pc);
965 if (tb) {
966 /* the PC is inside the translated code. It means that we have
967 a virtual CPU fault */
968 cpu_restore_state(tb, env, pc, puc);
969 }
970 /* we restore the process signal mask as the sigreturn should
971 do it (XXX: use sigsetjmp) */
972 sigprocmask(SIG_SETMASK, old_set, NULL);
973 cpu_loop_exit();
974 }
975 #elif defined (TARGET_PPC)
976 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
977 int is_write, sigset_t *old_set,
978 void *puc)
979 {
980 TranslationBlock *tb;
981 int ret;
982
983 if (cpu_single_env)
984 env = cpu_single_env; /* XXX: find a correct solution for multithread */
985 #if defined(DEBUG_SIGNAL)
986 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
987 pc, address, is_write, *(unsigned long *)old_set);
988 #endif
989 /* XXX: locking issue */
990 if (is_write && page_unprotect(h2g(address), pc, puc)) {
991 return 1;
992 }
993
994 /* see if it is an MMU fault */
995 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
996 if (ret < 0)
997 return 0; /* not an MMU fault */
998 if (ret == 0)
999 return 1; /* the MMU fault was handled without causing real CPU fault */
1000
1001 /* now we have a real cpu fault */
1002 tb = tb_find_pc(pc);
1003 if (tb) {
1004 /* the PC is inside the translated code. It means that we have
1005 a virtual CPU fault */
1006 cpu_restore_state(tb, env, pc, puc);
1007 }
1008 if (ret == 1) {
1009 #if 0
1010 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1011 env->nip, env->error_code, tb);
1012 #endif
1013 /* we restore the process signal mask as the sigreturn should
1014 do it (XXX: use sigsetjmp) */
1015 sigprocmask(SIG_SETMASK, old_set, NULL);
1016 do_raise_exception_err(env->exception_index, env->error_code);
1017 } else {
1018 /* activate soft MMU for this block */
1019 cpu_resume_from_signal(env, puc);
1020 }
1021 /* never comes here */
1022 return 1;
1023 }
1024
1025 #elif defined(TARGET_M68K)
1026 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1027 int is_write, sigset_t *old_set,
1028 void *puc)
1029 {
1030 TranslationBlock *tb;
1031 int ret;
1032
1033 if (cpu_single_env)
1034 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1035 #if defined(DEBUG_SIGNAL)
1036 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1037 pc, address, is_write, *(unsigned long *)old_set);
1038 #endif
1039 /* XXX: locking issue */
1040 if (is_write && page_unprotect(address, pc, puc)) {
1041 return 1;
1042 }
1043 /* see if it is an MMU fault */
1044 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1045 if (ret < 0)
1046 return 0; /* not an MMU fault */
1047 if (ret == 0)
1048 return 1; /* the MMU fault was handled without causing real CPU fault */
1049 /* now we have a real cpu fault */
1050 tb = tb_find_pc(pc);
1051 if (tb) {
1052 /* the PC is inside the translated code. It means that we have
1053 a virtual CPU fault */
1054 cpu_restore_state(tb, env, pc, puc);
1055 }
1056 /* we restore the process signal mask as the sigreturn should
1057 do it (XXX: use sigsetjmp) */
1058 sigprocmask(SIG_SETMASK, old_set, NULL);
1059 cpu_loop_exit();
1060 /* never comes here */
1061 return 1;
1062 }
1063
1064 #elif defined (TARGET_MIPS)
1065 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1066 int is_write, sigset_t *old_set,
1067 void *puc)
1068 {
1069 TranslationBlock *tb;
1070 int ret;
1071
1072 if (cpu_single_env)
1073 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1074 #if defined(DEBUG_SIGNAL)
1075 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1076 pc, address, is_write, *(unsigned long *)old_set);
1077 #endif
1078 /* XXX: locking issue */
1079 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1080 return 1;
1081 }
1082
1083 /* see if it is an MMU fault */
1084 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1085 if (ret < 0)
1086 return 0; /* not an MMU fault */
1087 if (ret == 0)
1088 return 1; /* the MMU fault was handled without causing real CPU fault */
1089
1090 /* now we have a real cpu fault */
1091 tb = tb_find_pc(pc);
1092 if (tb) {
1093 /* the PC is inside the translated code. It means that we have
1094 a virtual CPU fault */
1095 cpu_restore_state(tb, env, pc, puc);
1096 }
1097 if (ret == 1) {
1098 #if 0
1099 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1100 env->PC, env->error_code, tb);
1101 #endif
1102 /* we restore the process signal mask as the sigreturn should
1103 do it (XXX: use sigsetjmp) */
1104 sigprocmask(SIG_SETMASK, old_set, NULL);
1105 do_raise_exception_err(env->exception_index, env->error_code);
1106 } else {
1107 /* activate soft MMU for this block */
1108 cpu_resume_from_signal(env, puc);
1109 }
1110 /* never comes here */
1111 return 1;
1112 }
1113
1114 #elif defined (TARGET_SH4)
1115 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1116 int is_write, sigset_t *old_set,
1117 void *puc)
1118 {
1119 TranslationBlock *tb;
1120 int ret;
1121
1122 if (cpu_single_env)
1123 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1124 #if defined(DEBUG_SIGNAL)
1125 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1126 pc, address, is_write, *(unsigned long *)old_set);
1127 #endif
1128 /* XXX: locking issue */
1129 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1130 return 1;
1131 }
1132
1133 /* see if it is an MMU fault */
1134 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1135 if (ret < 0)
1136 return 0; /* not an MMU fault */
1137 if (ret == 0)
1138 return 1; /* the MMU fault was handled without causing real CPU fault */
1139
1140 /* now we have a real cpu fault */
1141 tb = tb_find_pc(pc);
1142 if (tb) {
1143 /* the PC is inside the translated code. It means that we have
1144 a virtual CPU fault */
1145 cpu_restore_state(tb, env, pc, puc);
1146 }
1147 #if 0
1148 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1149 env->nip, env->error_code, tb);
1150 #endif
1151 /* we restore the process signal mask as the sigreturn should
1152 do it (XXX: use sigsetjmp) */
1153 sigprocmask(SIG_SETMASK, old_set, NULL);
1154 cpu_loop_exit();
1155 /* never comes here */
1156 return 1;
1157 }
1158
1159 #elif defined (TARGET_ALPHA)
1160 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1161 int is_write, sigset_t *old_set,
1162 void *puc)
1163 {
1164 TranslationBlock *tb;
1165 int ret;
1166
1167 if (cpu_single_env)
1168 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1169 #if defined(DEBUG_SIGNAL)
1170 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1171 pc, address, is_write, *(unsigned long *)old_set);
1172 #endif
1173 /* XXX: locking issue */
1174 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1175 return 1;
1176 }
1177
1178 /* see if it is an MMU fault */
1179 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0);
1180 if (ret < 0)
1181 return 0; /* not an MMU fault */
1182 if (ret == 0)
1183 return 1; /* the MMU fault was handled without causing real CPU fault */
1184
1185 /* now we have a real cpu fault */
1186 tb = tb_find_pc(pc);
1187 if (tb) {
1188 /* the PC is inside the translated code. It means that we have
1189 a virtual CPU fault */
1190 cpu_restore_state(tb, env, pc, puc);
1191 }
1192 #if 0
1193 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1194 env->nip, env->error_code, tb);
1195 #endif
1196 /* we restore the process signal mask as the sigreturn should
1197 do it (XXX: use sigsetjmp) */
1198 sigprocmask(SIG_SETMASK, old_set, NULL);
1199 cpu_loop_exit();
1200 /* never comes here */
1201 return 1;
1202 }
1203 #else
1204 #error unsupported target CPU
1205 #endif
1206
1207 #if defined(__i386__)
1208
1209 #if defined(__APPLE__)
1210 # include <sys/ucontext.h>
1211
1212 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1213 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1214 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1215 #else
1216 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1217 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1218 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1219 #endif
1220
1221 #if defined(USE_CODE_COPY)
1222 static void cpu_send_trap(unsigned long pc, int trap,
1223 struct ucontext *uc)
1224 {
1225 TranslationBlock *tb;
1226
1227 if (cpu_single_env)
1228 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1229 /* now we have a real cpu fault */
1230 tb = tb_find_pc(pc);
1231 if (tb) {
1232 /* the PC is inside the translated code. It means that we have
1233 a virtual CPU fault */
1234 cpu_restore_state(tb, env, pc, uc);
1235 }
1236 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1237 raise_exception_err(trap, env->error_code);
1238 }
1239 #endif
1240
1241 int cpu_signal_handler(int host_signum, void *pinfo,
1242 void *puc)
1243 {
1244 siginfo_t *info = pinfo;
1245 struct ucontext *uc = puc;
1246 unsigned long pc;
1247 int trapno;
1248
1249 #ifndef REG_EIP
1250 /* for glibc 2.1 */
1251 #define REG_EIP EIP
1252 #define REG_ERR ERR
1253 #define REG_TRAPNO TRAPNO
1254 #endif
1255 pc = EIP_sig(uc);
1256 trapno = TRAP_sig(uc);
1257 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1258 if (trapno == 0x00 || trapno == 0x05) {
1259 /* send division by zero or bound exception */
1260 cpu_send_trap(pc, trapno, uc);
1261 return 1;
1262 } else
1263 #endif
1264 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1265 trapno == 0xe ?
1266 (ERROR_sig(uc) >> 1) & 1 : 0,
1267 &uc->uc_sigmask, puc);
1268 }
1269
1270 #elif defined(__x86_64__)
1271
1272 int cpu_signal_handler(int host_signum, void *pinfo,
1273 void *puc)
1274 {
1275 siginfo_t *info = pinfo;
1276 struct ucontext *uc = puc;
1277 unsigned long pc;
1278
1279 pc = uc->uc_mcontext.gregs[REG_RIP];
1280 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1281 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1282 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1283 &uc->uc_sigmask, puc);
1284 }
1285
1286 #elif defined(__powerpc__)
1287
1288 /***********************************************************************
1289 * signal context platform-specific definitions
1290 * From Wine
1291 */
1292 #ifdef linux
1293 /* All Registers access - only for local access */
1294 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1295 /* Gpr Registers access */
1296 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1297 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1298 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1299 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1300 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1301 # define LR_sig(context) REG_sig(link, context) /* Link register */
1302 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1303 /* Float Registers access */
1304 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1305 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1306 /* Exception Registers access */
1307 # define DAR_sig(context) REG_sig(dar, context)
1308 # define DSISR_sig(context) REG_sig(dsisr, context)
1309 # define TRAP_sig(context) REG_sig(trap, context)
1310 #endif /* linux */
1311
1312 #ifdef __APPLE__
1313 # include <sys/ucontext.h>
1314 typedef struct ucontext SIGCONTEXT;
1315 /* All Registers access - only for local access */
1316 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1317 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1318 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1319 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1320 /* Gpr Registers access */
1321 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1322 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1323 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1324 # define CTR_sig(context) REG_sig(ctr, context)
1325 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1326 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1327 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1328 /* Float Registers access */
1329 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1330 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1331 /* Exception Registers access */
1332 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1333 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1334 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1335 #endif /* __APPLE__ */
1336
1337 int cpu_signal_handler(int host_signum, void *pinfo,
1338 void *puc)
1339 {
1340 siginfo_t *info = pinfo;
1341 struct ucontext *uc = puc;
1342 unsigned long pc;
1343 int is_write;
1344
1345 pc = IAR_sig(uc);
1346 is_write = 0;
1347 #if 0
1348 /* ppc 4xx case */
1349 if (DSISR_sig(uc) & 0x00800000)
1350 is_write = 1;
1351 #else
1352 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1353 is_write = 1;
1354 #endif
1355 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1356 is_write, &uc->uc_sigmask, puc);
1357 }
1358
1359 #elif defined(__alpha__)
1360
1361 int cpu_signal_handler(int host_signum, void *pinfo,
1362 void *puc)
1363 {
1364 siginfo_t *info = pinfo;
1365 struct ucontext *uc = puc;
1366 uint32_t *pc = uc->uc_mcontext.sc_pc;
1367 uint32_t insn = *pc;
1368 int is_write = 0;
1369
1370 /* XXX: need kernel patch to get write flag faster */
1371 switch (insn >> 26) {
1372 case 0x0d: // stw
1373 case 0x0e: // stb
1374 case 0x0f: // stq_u
1375 case 0x24: // stf
1376 case 0x25: // stg
1377 case 0x26: // sts
1378 case 0x27: // stt
1379 case 0x2c: // stl
1380 case 0x2d: // stq
1381 case 0x2e: // stl_c
1382 case 0x2f: // stq_c
1383 is_write = 1;
1384 }
1385
1386 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1387 is_write, &uc->uc_sigmask, puc);
1388 }
1389 #elif defined(__sparc__)
1390
1391 int cpu_signal_handler(int host_signum, void *pinfo,
1392 void *puc)
1393 {
1394 siginfo_t *info = pinfo;
1395 uint32_t *regs = (uint32_t *)(info + 1);
1396 void *sigmask = (regs + 20);
1397 unsigned long pc;
1398 int is_write;
1399 uint32_t insn;
1400
1401 /* XXX: is there a standard glibc define ? */
1402 pc = regs[1];
1403 /* XXX: need kernel patch to get write flag faster */
1404 is_write = 0;
1405 insn = *(uint32_t *)pc;
1406 if ((insn >> 30) == 3) {
1407 switch((insn >> 19) & 0x3f) {
1408 case 0x05: // stb
1409 case 0x06: // sth
1410 case 0x04: // st
1411 case 0x07: // std
1412 case 0x24: // stf
1413 case 0x27: // stdf
1414 case 0x25: // stfsr
1415 is_write = 1;
1416 break;
1417 }
1418 }
1419 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1420 is_write, sigmask, NULL);
1421 }
1422
1423 #elif defined(__arm__)
1424
1425 int cpu_signal_handler(int host_signum, void *pinfo,
1426 void *puc)
1427 {
1428 siginfo_t *info = pinfo;
1429 struct ucontext *uc = puc;
1430 unsigned long pc;
1431 int is_write;
1432
1433 pc = uc->uc_mcontext.gregs[R15];
1434 /* XXX: compute is_write */
1435 is_write = 0;
1436 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1437 is_write,
1438 &uc->uc_sigmask, puc);
1439 }
1440
1441 #elif defined(__mc68000)
1442
1443 int cpu_signal_handler(int host_signum, void *pinfo,
1444 void *puc)
1445 {
1446 siginfo_t *info = pinfo;
1447 struct ucontext *uc = puc;
1448 unsigned long pc;
1449 int is_write;
1450
1451 pc = uc->uc_mcontext.gregs[16];
1452 /* XXX: compute is_write */
1453 is_write = 0;
1454 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1455 is_write,
1456 &uc->uc_sigmask, puc);
1457 }
1458
1459 #elif defined(__ia64)
1460
1461 #ifndef __ISR_VALID
1462 /* This ought to be in <bits/siginfo.h>... */
1463 # define __ISR_VALID 1
1464 #endif
1465
1466 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1467 {
1468 siginfo_t *info = pinfo;
1469 struct ucontext *uc = puc;
1470 unsigned long ip;
1471 int is_write = 0;
1472
1473 ip = uc->uc_mcontext.sc_ip;
1474 switch (host_signum) {
1475 case SIGILL:
1476 case SIGFPE:
1477 case SIGSEGV:
1478 case SIGBUS:
1479 case SIGTRAP:
1480 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1481 /* ISR.W (write-access) is bit 33: */
1482 is_write = (info->si_isr >> 33) & 1;
1483 break;
1484
1485 default:
1486 break;
1487 }
1488 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1489 is_write,
1490 &uc->uc_sigmask, puc);
1491 }
1492
1493 #elif defined(__s390__)
1494
1495 int cpu_signal_handler(int host_signum, void *pinfo,
1496 void *puc)
1497 {
1498 siginfo_t *info = pinfo;
1499 struct ucontext *uc = puc;
1500 unsigned long pc;
1501 int is_write;
1502
1503 pc = uc->uc_mcontext.psw.addr;
1504 /* XXX: compute is_write */
1505 is_write = 0;
1506 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1507 is_write, &uc->uc_sigmask, puc);
1508 }
1509
1510 #elif defined(__mips__)
1511
1512 int cpu_signal_handler(int host_signum, void *pinfo,
1513 void *puc)
1514 {
1515 siginfo_t *info = pinfo;
1516 struct ucontext *uc = puc;
1517 greg_t pc = uc->uc_mcontext.pc;
1518 int is_write;
1519
1520 /* XXX: compute is_write */
1521 is_write = 0;
1522 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1523 is_write, &uc->uc_sigmask, puc);
1524 }
1525
1526 #else
1527
1528 #error host CPU specific signal handler needed
1529
1530 #endif
1531
1532 #endif /* !defined(CONFIG_SOFTMMU) */
Stable branch of Qemu 0.9.1