hw/cuda.c

   1 /*
   2  * QEMU CUDA support
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_CUDA
  27 //#define DEBUG_CUDA_PACKET
  28
  29 /* Bits in B data register: all active low */
  30 #define TREQ            0x08            /* Transfer request (input) */
  31 #define TACK            0x10            /* Transfer acknowledge (output) */
  32 #define TIP             0x20            /* Transfer in progress (output) */
  33
  34 /* Bits in ACR */
  35 #define SR_CTRL         0x1c            /* Shift register control bits */
  36 #define SR_EXT          0x0c            /* Shift on external clock */
  37 #define SR_OUT          0x10            /* Shift out if 1 */
  38
  39 /* Bits in IFR and IER */
  40 #define IER_SET         0x80            /* set bits in IER */
  41 #define IER_CLR         0               /* clear bits in IER */
  42 #define SR_INT          0x04            /* Shift register full/empty */
  43 #define T1_INT          0x40            /* Timer 1 interrupt */
  44
  45 /* Bits in ACR */
  46 #define T1MODE          0xc0            /* Timer 1 mode */
  47 #define T1MODE_CONT     0x40            /*  continuous interrupts */
  48
  49 /* commands (1st byte) */
  50 #define ADB_PACKET      0
  51 #define CUDA_PACKET     1
  52 #define ERROR_PACKET    2
  53 #define TIMER_PACKET    3
  54 #define POWER_PACKET    4
  55 #define MACIIC_PACKET   5
  56 #define PMU_PACKET      6
  57
  58
  59 /* CUDA commands (2nd byte) */
  60 #define CUDA_WARM_START                 0x0
  61 #define CUDA_AUTOPOLL                   0x1
  62 #define CUDA_GET_6805_ADDR              0x2
  63 #define CUDA_GET_TIME                   0x3
  64 #define CUDA_GET_PRAM                   0x7
  65 #define CUDA_SET_6805_ADDR              0x8
  66 #define CUDA_SET_TIME                   0x9
  67 #define CUDA_POWERDOWN                  0xa
  68 #define CUDA_POWERUP_TIME               0xb
  69 #define CUDA_SET_PRAM                   0xc
  70 #define CUDA_MS_RESET                   0xd
  71 #define CUDA_SEND_DFAC                  0xe
  72 #define CUDA_BATTERY_SWAP_SENSE         0x10
  73 #define CUDA_RESET_SYSTEM               0x11
  74 #define CUDA_SET_IPL                    0x12
  75 #define CUDA_FILE_SERVER_FLAG           0x13
  76 #define CUDA_SET_AUTO_RATE              0x14
  77 #define CUDA_GET_AUTO_RATE              0x16
  78 #define CUDA_SET_DEVICE_LIST            0x19
  79 #define CUDA_GET_DEVICE_LIST            0x1a
  80 #define CUDA_SET_ONE_SECOND_MODE        0x1b
  81 #define CUDA_SET_POWER_MESSAGES         0x21
  82 #define CUDA_GET_SET_IIC                0x22
  83 #define CUDA_WAKEUP                     0x23
  84 #define CUDA_TIMER_TICKLE               0x24
  85 #define CUDA_COMBINED_FORMAT_IIC        0x25
  86
  87 #define CUDA_TIMER_FREQ (4700000 / 6)
  88 #define CUDA_ADB_POLL_FREQ 50
  89
  90 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
  91 #define RTC_OFFSET                      2082844800
  92
  93 typedef struct CUDATimer {
  94     unsigned int latch;
  95     uint16_t counter_value; /* counter value at load time */
  96     int64_t load_time;
  97     int64_t next_irq_time;
  98     QEMUTimer *timer;
  99 } CUDATimer;
 100
 101 typedef struct CUDAState {
 102     /* cuda registers */
 103     uint8_t b;      /* B-side data */
 104     uint8_t a;      /* A-side data */
 105     uint8_t dirb;   /* B-side direction (1=output) */
 106     uint8_t dira;   /* A-side direction (1=output) */
 107     uint8_t sr;     /* Shift register */
 108     uint8_t acr;    /* Auxiliary control register */
 109     uint8_t pcr;    /* Peripheral control register */
 110     uint8_t ifr;    /* Interrupt flag register */
 111     uint8_t ier;    /* Interrupt enable register */
 112     uint8_t anh;    /* A-side data, no handshake */
 113
 114     CUDATimer timers[2];
 115
 116     uint8_t last_b; /* last value of B register */
 117     uint8_t last_acr; /* last value of B register */
 118
 119     int data_in_size;
 120     int data_in_index;
 121     int data_out_index;
 122
 123     int irq;
 124     openpic_t *openpic;
 125     uint8_t autopoll;
 126     uint8_t data_in[128];
 127     uint8_t data_out[16];
 128     QEMUTimer *adb_poll_timer;
 129 } CUDAState;
 130
 131 static CUDAState cuda_state;
 132 ADBBusState adb_bus;
 133
 134 static void cuda_update(CUDAState *s);
 135 static void cuda_receive_packet_from_host(CUDAState *s,
 136                                           const uint8_t *data, int len);
 137 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 138                               int64_t current_time);
 139
 140 static void cuda_update_irq(CUDAState *s)
 141 {
 142     if (s->ifr & s->ier & (SR_INT | T1_INT)) {
 143         openpic_set_irq(s->openpic, s->irq, 1);
 144     } else {
 145         openpic_set_irq(s->openpic, s->irq, 0);
 146     }
 147 }
 148
 149 static unsigned int get_counter(CUDATimer *s)
 150 {
 151     int64_t d;
 152     unsigned int counter;
 153
 154     d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
 155                  CUDA_TIMER_FREQ, ticks_per_sec);
 156     if (d <= s->counter_value) {
 157         counter = d;
 158     } else {
 159         counter = s->latch - 1 - ((d - s->counter_value) % s->latch);
 160     }
 161     return counter;
 162 }
 163
 164 static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
 165 {
 166 #ifdef DEBUG_CUDA
 167     printf("cuda: T%d.counter=%d\n",
 168            1 + (ti->timer == NULL), val);
 169 #endif
 170     ti->load_time = qemu_get_clock(vm_clock);
 171     ti->counter_value = val;
 172     cuda_timer_update(s, ti, ti->load_time);
 173 }
 174
 175 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
 176 {
 177     int64_t d, next_time, base;
 178     /* current counter value */
 179     d = muldiv64(current_time - s->load_time,
 180                  CUDA_TIMER_FREQ, ticks_per_sec);
 181     if (d < s->counter_value) {
 182         next_time = s->counter_value + 1;
 183     } else
 184     {
 185         base = ((d - s->counter_value + 1) / s->latch);
 186         base = (base * s->latch) + s->counter_value;
 187         next_time = base + s->latch;
 188     }
 189 #if 0
 190 #ifdef DEBUG_CUDA
 191     printf("latch=%d counter=%lld delta_next=%lld\n",
 192            s->latch, d, next_time - d);
 193 #endif
 194 #endif
 195     next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
 196         s->load_time;
 197     if (next_time <= current_time)
 198         next_time = current_time + 1;
 199     return next_time;
 200 }
 201
 202 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 203                               int64_t current_time)
 204 {
 205     if (!ti->timer)
 206         return;
 207     if ((s->acr & T1MODE) != T1MODE_CONT) {
 208         qemu_del_timer(ti->timer);
 209     } else {
 210         ti->next_irq_time = get_next_irq_time(ti, current_time);
 211         qemu_mod_timer(ti->timer, ti->next_irq_time);
 212     }
 213 }
 214
 215 static void cuda_timer1(void *opaque)
 216 {
 217     CUDAState *s = opaque;
 218     CUDATimer *ti = &s->timers[0];
 219
 220     cuda_timer_update(s, ti, ti->next_irq_time);
 221     s->ifr |= T1_INT;
 222     cuda_update_irq(s);
 223 }
 224
 225 static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
 226 {
 227     CUDAState *s = opaque;
 228     uint32_t val;
 229
 230     addr = (addr >> 9) & 0xf;
 231     switch(addr) {
 232     case 0:
 233         val = s->b;
 234         break;
 235     case 1:
 236         val = s->a;
 237         break;
 238     case 2:
 239         val = s->dirb;
 240         break;
 241     case 3:
 242         val = s->dira;
 243         break;
 244     case 4:
 245         val = get_counter(&s->timers[0]) & 0xff;
 246         s->ifr &= ~T1_INT;
 247         cuda_update_irq(s);
 248         break;
 249     case 5:
 250         val = get_counter(&s->timers[0]) >> 8;
 251         s->ifr &= ~T1_INT;
 252         cuda_update_irq(s);
 253         break;
 254     case 6:
 255         val = s->timers[0].latch & 0xff;
 256         break;
 257     case 7:
 258         val = (s->timers[0].latch >> 8) & 0xff;
 259         break;
 260     case 8:
 261         val = get_counter(&s->timers[1]) & 0xff;
 262         break;
 263     case 9:
 264         val = get_counter(&s->timers[1]) >> 8;
 265         break;
 266     case 10:
 267         val = s->sr;
 268         s->ifr &= ~SR_INT;
 269         cuda_update_irq(s);
 270         break;
 271     case 11:
 272         val = s->acr;
 273         break;
 274     case 12:
 275         val = s->pcr;
 276         break;
 277     case 13:
 278         val = s->ifr;
 279         break;
 280     case 14:
 281         val = s->ier;
 282         break;
 283     default:
 284     case 15:
 285         val = s->anh;
 286         break;
 287     }
 288 #ifdef DEBUG_CUDA
 289     if (addr != 13 || val != 0)
 290         printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
 291 #endif
 292     return val;
 293 }
 294
 295 static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 296 {
 297     CUDAState *s = opaque;
 298
 299     addr = (addr >> 9) & 0xf;
 300 #ifdef DEBUG_CUDA
 301     printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
 302 #endif
 303
 304     switch(addr) {
 305     case 0:
 306         s->b = val;
 307         cuda_update(s);
 308         break;
 309     case 1:
 310         s->a = val;
 311         break;
 312     case 2:
 313         s->dirb = val;
 314         break;
 315     case 3:
 316         s->dira = val;
 317         break;
 318     case 4:
 319         val = val | (get_counter(&s->timers[0]) & 0xff00);
 320         set_counter(s, &s->timers[0], val);
 321         break;
 322     case 5:
 323         val = (val << 8) |  (get_counter(&s->timers[0]) & 0xff);
 324         set_counter(s, &s->timers[0], val);
 325         break;
 326     case 6:
 327         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 328         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 329         break;
 330     case 7:
 331         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 332         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 333         break;
 334     case 8:
 335         val = val | (get_counter(&s->timers[1]) & 0xff00);
 336         set_counter(s, &s->timers[1], val);
 337         break;
 338     case 9:
 339         val = (val << 8) |  (get_counter(&s->timers[1]) & 0xff);
 340         set_counter(s, &s->timers[1], val);
 341         break;
 342     case 10:
 343         s->sr = val;
 344         break;
 345     case 11:
 346         s->acr = val;
 347         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 348         cuda_update(s);
 349         break;
 350     case 12:
 351         s->pcr = val;
 352         break;
 353     case 13:
 354         /* reset bits */
 355         s->ifr &= ~val;
 356         cuda_update_irq(s);
 357         break;
 358     case 14:
 359         if (val & IER_SET) {
 360             /* set bits */
 361             s->ier |= val & 0x7f;
 362         } else {
 363             /* reset bits */
 364             s->ier &= ~val;
 365         }
 366         cuda_update_irq(s);
 367         break;
 368     default:
 369     case 15:
 370         s->anh = val;
 371         break;
 372     }
 373 }
 374
 375 /* NOTE: TIP and TREQ are negated */
 376 static void cuda_update(CUDAState *s)
 377 {
 378     int packet_received, len;
 379
 380     packet_received = 0;
 381     if (!(s->b & TIP)) {
 382         /* transfer requested from host */
 383
 384         if (s->acr & SR_OUT) {
 385             /* data output */
 386             if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 387                 if (s->data_out_index < sizeof(s->data_out)) {
 388 #ifdef DEBUG_CUDA
 389                     printf("cuda: send: %02x\n", s->sr);
 390 #endif
 391                     s->data_out[s->data_out_index++] = s->sr;
 392                     s->ifr |= SR_INT;
 393                     cuda_update_irq(s);
 394                 }
 395             }
 396         } else {
 397             if (s->data_in_index < s->data_in_size) {
 398                 /* data input */
 399                 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 400                     s->sr = s->data_in[s->data_in_index++];
 401 #ifdef DEBUG_CUDA
 402                     printf("cuda: recv: %02x\n", s->sr);
 403 #endif
 404                     /* indicate end of transfer */
 405                     if (s->data_in_index >= s->data_in_size) {
 406                         s->b = (s->b | TREQ);
 407                     }
 408                     s->ifr |= SR_INT;
 409                     cuda_update_irq(s);
 410                 }
 411             }
 412         }
 413     } else {
 414         /* no transfer requested: handle sync case */
 415         if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
 416             /* update TREQ state each time TACK change state */
 417             if (s->b & TACK)
 418                 s->b = (s->b | TREQ);
 419             else
 420                 s->b = (s->b & ~TREQ);
 421             s->ifr |= SR_INT;
 422             cuda_update_irq(s);
 423         } else {
 424             if (!(s->last_b & TIP)) {
 425                 /* handle end of host to cuda transfert */
 426                 packet_received = (s->data_out_index > 0);
 427                 /* always an IRQ at the end of transfert */
 428                 s->ifr |= SR_INT;
 429                 cuda_update_irq(s);
 430             }
 431             /* signal if there is data to read */
 432             if (s->data_in_index < s->data_in_size) {
 433                 s->b = (s->b & ~TREQ);
 434             }
 435         }
 436     }
 437
 438     s->last_acr = s->acr;
 439     s->last_b = s->b;
 440
 441     /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
 442        recursively */
 443     if (packet_received) {
 444         len = s->data_out_index;
 445         s->data_out_index = 0;
 446         cuda_receive_packet_from_host(s, s->data_out, len);
 447     }
 448 }
 449
 450 static void cuda_send_packet_to_host(CUDAState *s,
 451                                      const uint8_t *data, int len)
 452 {
 453 #ifdef DEBUG_CUDA_PACKET
 454     {
 455         int i;
 456         printf("cuda_send_packet_to_host:\n");
 457         for(i = 0; i < len; i++)
 458             printf(" %02x", data[i]);
 459         printf("\n");
 460     }
 461 #endif
 462     memcpy(s->data_in, data, len);
 463     s->data_in_size = len;
 464     s->data_in_index = 0;
 465     cuda_update(s);
 466     s->ifr |= SR_INT;
 467     cuda_update_irq(s);
 468 }
 469
 470 static void cuda_adb_poll(void *opaque)
 471 {
 472     CUDAState *s = opaque;
 473     uint8_t obuf[ADB_MAX_OUT_LEN + 2];
 474     int olen;
 475
 476     olen = adb_poll(&adb_bus, obuf + 2);
 477     if (olen > 0) {
 478         obuf[0] = ADB_PACKET;
 479         obuf[1] = 0x40; /* polled data */
 480         cuda_send_packet_to_host(s, obuf, olen + 2);
 481     }
 482     qemu_mod_timer(s->adb_poll_timer,
 483                    qemu_get_clock(vm_clock) +
 484                    (ticks_per_sec / CUDA_ADB_POLL_FREQ));
 485 }
 486
 487 static void cuda_receive_packet(CUDAState *s,
 488                                 const uint8_t *data, int len)
 489 {
 490     uint8_t obuf[16];
 491     int ti, autopoll;
 492
 493     switch(data[0]) {
 494     case CUDA_AUTOPOLL:
 495         autopoll = (data[1] != 0);
 496         if (autopoll != s->autopoll) {
 497             s->autopoll = autopoll;
 498             if (autopoll) {
 499                 qemu_mod_timer(s->adb_poll_timer,
 500                                qemu_get_clock(vm_clock) +
 501                                (ticks_per_sec / CUDA_ADB_POLL_FREQ));
 502             } else {
 503                 qemu_del_timer(s->adb_poll_timer);
 504             }
 505         }
 506         obuf[0] = CUDA_PACKET;
 507         obuf[1] = data[1];
 508         cuda_send_packet_to_host(s, obuf, 2);
 509         break;
 510     case CUDA_GET_TIME:
 511     case CUDA_SET_TIME:
 512         /* XXX: add time support ? */
 513         ti = time(NULL) + RTC_OFFSET;
 514         obuf[0] = CUDA_PACKET;
 515         obuf[1] = 0;
 516         obuf[2] = 0;
 517         obuf[3] = ti >> 24;
 518         obuf[4] = ti >> 16;
 519         obuf[5] = ti >> 8;
 520         obuf[6] = ti;
 521         cuda_send_packet_to_host(s, obuf, 7);
 522         break;
 523     case CUDA_FILE_SERVER_FLAG:
 524     case CUDA_SET_DEVICE_LIST:
 525     case CUDA_SET_AUTO_RATE:
 526     case CUDA_SET_POWER_MESSAGES:
 527         obuf[0] = CUDA_PACKET;
 528         obuf[1] = 0;
 529         cuda_send_packet_to_host(s, obuf, 2);
 530         break;
 531     case CUDA_POWERDOWN:
 532         obuf[0] = CUDA_PACKET;
 533         obuf[1] = 0;
 534         cuda_send_packet_to_host(s, obuf, 2);
 535         qemu_system_shutdown_request();
 536         break;
 537     default:
 538         break;
 539     }
 540 }
 541
 542 static void cuda_receive_packet_from_host(CUDAState *s,
 543                                           const uint8_t *data, int len)
 544 {
 545 #ifdef DEBUG_CUDA_PACKET
 546     {
 547         int i;
 548         printf("cuda_receive_packet_to_host:\n");
 549         for(i = 0; i < len; i++)
 550             printf(" %02x", data[i]);
 551         printf("\n");
 552     }
 553 #endif
 554     switch(data[0]) {
 555     case ADB_PACKET:
 556         {
 557             uint8_t obuf[ADB_MAX_OUT_LEN + 2];
 558             int olen;
 559             olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
 560             if (olen > 0) {
 561                 obuf[0] = ADB_PACKET;
 562                 obuf[1] = 0x00;
 563             } else {
 564                 /* error */
 565                 obuf[0] = ADB_PACKET;
 566                 obuf[1] = -olen;
 567                 olen = 0;
 568             }
 569             cuda_send_packet_to_host(s, obuf, olen + 2);
 570         }
 571         break;
 572     case CUDA_PACKET:
 573         cuda_receive_packet(s, data + 1, len - 1);
 574         break;
 575     }
 576 }
 577
 578 static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 579 {
 580 }
 581
 582 static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 583 {
 584 }
 585
 586 static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
 587 {
 588     return 0;
 589 }
 590
 591 static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
 592 {
 593     return 0;
 594 }
 595
 596 static CPUWriteMemoryFunc *cuda_write[] = {
 597     &cuda_writeb,
 598     &cuda_writew,
 599     &cuda_writel,
 600 };
 601
 602 static CPUReadMemoryFunc *cuda_read[] = {
 603     &cuda_readb,
 604     &cuda_readw,
 605     &cuda_readl,
 606 };
 607
 608 int cuda_init(openpic_t *openpic, int irq)
 609 {
 610     CUDAState *s = &cuda_state;
 611     int cuda_mem_index;
 612
 613     s->openpic = openpic;
 614     s->irq = irq;
 615
 616     s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
 617     s->timers[0].latch = 0x10000;
 618     set_counter(s, &s->timers[0], 0xffff);
 619     s->timers[1].latch = 0x10000;
 620     s->ier = T1_INT | SR_INT;
 621     set_counter(s, &s->timers[1], 0xffff);
 622
 623     s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
 624     cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
 625     return cuda_mem_index;
 626 }