2 * SuperH Timer modules.
4 * Copyright (c) 2007 Magnus Damm
5 * Based on arm_timer.c by Paul Brook
6 * Copyright (c) 2005-2006 CodeSourcery.
8 * This code is licenced under the GPL.
15 #define TIMER_TCR_TPSC (7 << 0)
16 #define TIMER_TCR_CKEG (3 << 3)
17 #define TIMER_TCR_UNIE (1 << 5)
18 #define TIMER_TCR_ICPE (3 << 6)
19 #define TIMER_TCR_UNF (1 << 8)
20 #define TIMER_TCR_ICPF (1 << 9)
21 #define TIMER_TCR_RESERVED (0x3f << 10)
23 #define TIMER_FEAT_CAPT (1 << 0)
24 #define TIMER_FEAT_EXTCLK (1 << 1)
39 /* Check all active timers, and schedule the next timer interrupt. */
41 static void sh_timer_update(sh_timer_state
*s
)
44 /* Update interrupts. */
45 if (s
->int_level
&& (s
->tcr
& TIMER_TCR_UNIE
)) {
46 qemu_irq_raise(s
->irq
);
48 qemu_irq_lower(s
->irq
);
53 uint32_t sh_timer_read(void *opaque
, target_phys_addr_t offset
)
55 sh_timer_state
*s
= (sh_timer_state
*)opaque
;
57 switch (offset
>> 2) {
61 return ptimer_get_count(s
->timer
);
63 return s
->tcr
| (s
->int_level
? TIMER_TCR_UNF
: 0);
65 if (s
->feat
& TIMER_FEAT_CAPT
)
68 cpu_abort (cpu_single_env
, "sh_timer_read: Bad offset %x\n",
74 static void sh_timer_write(void *opaque
, target_phys_addr_t offset
,
77 sh_timer_state
*s
= (sh_timer_state
*)opaque
;
80 switch (offset
>> 2) {
83 ptimer_set_limit(s
->timer
, s
->tcor
, 0);
87 ptimer_set_count(s
->timer
, s
->tcnt
);
91 /* Pause the timer if it is running. This may cause some
92 inaccuracy dure to rounding, but avoids a whole lot of other
94 ptimer_stop(s
->timer
);
97 /* ??? Need to recalculate expiry time after changing divisor. */
98 switch (value
& TIMER_TCR_TPSC
) {
99 case 0: freq
>>= 2; break;
100 case 1: freq
>>= 4; break;
101 case 2: freq
>>= 6; break;
102 case 3: freq
>>= 8; break;
103 case 4: freq
>>= 10; break;
105 case 7: if (s
->feat
& TIMER_FEAT_EXTCLK
) break;
106 default: cpu_abort (cpu_single_env
,
107 "sh_timer_write: Reserved TPSC value\n"); break;
109 switch ((value
& TIMER_TCR_CKEG
) >> 3) {
113 case 3: if (s
->feat
& TIMER_FEAT_EXTCLK
) break;
114 default: cpu_abort (cpu_single_env
,
115 "sh_timer_write: Reserved CKEG value\n"); break;
117 switch ((value
& TIMER_TCR_ICPE
) >> 6) {
120 case 3: if (s
->feat
& TIMER_FEAT_CAPT
) break;
121 default: cpu_abort (cpu_single_env
,
122 "sh_timer_write: Reserved ICPE value\n"); break;
124 if ((value
& TIMER_TCR_UNF
) == 0)
127 value
&= ~TIMER_TCR_UNF
;
129 if ((value
& TIMER_TCR_ICPF
) && (!(s
->feat
& TIMER_FEAT_CAPT
)))
130 cpu_abort (cpu_single_env
,
131 "sh_timer_write: Reserved ICPF value\n");
133 value
&= ~TIMER_TCR_ICPF
; /* capture not supported */
135 if (value
& TIMER_TCR_RESERVED
)
136 cpu_abort (cpu_single_env
,
137 "sh_timer_write: Reserved TCR bits set\n");
139 ptimer_set_limit(s
->timer
, s
->tcor
, 0);
140 ptimer_set_freq(s
->timer
, freq
);
142 /* Restart the timer if still enabled. */
143 ptimer_run(s
->timer
, 0);
147 if (s
->feat
& TIMER_FEAT_CAPT
) {
152 cpu_abort (cpu_single_env
, "sh_timer_write: Bad offset %x\n",
158 static void sh_timer_start_stop(void *opaque
, int enable
)
160 sh_timer_state
*s
= (sh_timer_state
*)opaque
;
163 printf("sh_timer_start_stop %d (%d)\n", enable
, s
->enabled
);
166 if (s
->enabled
&& !enable
) {
167 ptimer_stop(s
->timer
);
169 if (!s
->enabled
&& enable
) {
170 ptimer_run(s
->timer
, 0);
172 s
->enabled
= !!enable
;
175 printf("sh_timer_start_stop done %d\n", s
->enabled
);
179 static void sh_timer_tick(void *opaque
)
181 sh_timer_state
*s
= (sh_timer_state
*)opaque
;
182 s
->int_level
= s
->enabled
;
186 static void *sh_timer_init(uint32_t freq
, int feat
)
191 s
= (sh_timer_state
*)qemu_mallocz(sizeof(sh_timer_state
));
194 s
->tcor
= 0xffffffff;
195 s
->tcnt
= 0xffffffff;
196 s
->tcpr
= 0xdeadbeef;
200 bh
= qemu_bh_new(sh_timer_tick
, s
);
201 s
->timer
= ptimer_init(bh
);
202 /* ??? Save/restore. */
211 target_phys_addr_t base
;
215 static uint32_t tmu012_read(void *opaque
, target_phys_addr_t offset
)
217 tmu012_state
*s
= (tmu012_state
*)opaque
;
220 printf("tmu012_read 0x%lx\n", (unsigned long) offset
);
224 if (offset
>= 0x20) {
225 if (!(s
->feat
& TMU012_FEAT_3CHAN
))
226 cpu_abort (cpu_single_env
, "tmu012_write: Bad channel offset %x\n",
228 return sh_timer_read(s
->timer
[2], offset
- 0x20);
232 return sh_timer_read(s
->timer
[1], offset
- 0x14);
235 return sh_timer_read(s
->timer
[0], offset
- 0x08);
240 if ((s
->feat
& TMU012_FEAT_TOCR
) && offset
== 0)
243 cpu_abort (cpu_single_env
, "tmu012_write: Bad offset %x\n",
248 static void tmu012_write(void *opaque
, target_phys_addr_t offset
,
251 tmu012_state
*s
= (tmu012_state
*)opaque
;
254 printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset
, value
);
258 if (offset
>= 0x20) {
259 if (!(s
->feat
& TMU012_FEAT_3CHAN
))
260 cpu_abort (cpu_single_env
, "tmu012_write: Bad channel offset %x\n",
262 sh_timer_write(s
->timer
[2], offset
- 0x20, value
);
266 if (offset
>= 0x14) {
267 sh_timer_write(s
->timer
[1], offset
- 0x14, value
);
271 if (offset
>= 0x08) {
272 sh_timer_write(s
->timer
[0], offset
- 0x08, value
);
277 sh_timer_start_stop(s
->timer
[0], value
& (1 << 0));
278 sh_timer_start_stop(s
->timer
[1], value
& (1 << 1));
279 if (s
->feat
& TMU012_FEAT_3CHAN
)
280 sh_timer_start_stop(s
->timer
[2], value
& (1 << 2));
282 if (value
& (1 << 2))
283 cpu_abort (cpu_single_env
, "tmu012_write: Bad channel\n");
289 if ((s
->feat
& TMU012_FEAT_TOCR
) && offset
== 0) {
290 s
->tocr
= value
& (1 << 0);
294 static CPUReadMemoryFunc
*tmu012_readfn
[] = {
300 static CPUWriteMemoryFunc
*tmu012_writefn
[] = {
306 void tmu012_init(uint32_t base
, int feat
, uint32_t freq
)
310 int timer_feat
= (feat
& TMU012_FEAT_EXTCLK
) ? TIMER_FEAT_EXTCLK
: 0;
312 s
= (tmu012_state
*)qemu_mallocz(sizeof(tmu012_state
));
315 s
->timer
[0] = sh_timer_init(freq
, timer_feat
);
316 s
->timer
[1] = sh_timer_init(freq
, timer_feat
);
317 if (feat
& TMU012_FEAT_3CHAN
)
318 s
->timer
[2] = sh_timer_init(freq
, timer_feat
| TIMER_FEAT_CAPT
);
319 iomemtype
= cpu_register_io_memory(0, tmu012_readfn
,
321 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
322 /* ??? Save/restore. */