2 * QEMU 8253/8254 interval timer emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #define RW_STATE_LSB 1
29 #define RW_STATE_MSB 2
30 #define RW_STATE_WORD0 3
31 #define RW_STATE_WORD1 4
33 typedef struct PITChannelState
{
34 int count
; /* can be 65536 */
35 uint16_t latched_count
;
36 uint8_t count_latched
;
37 uint8_t status_latched
;
44 uint8_t bcd
; /* not supported */
45 uint8_t gate
; /* timer start */
46 int64_t count_load_time
;
48 int64_t next_transition_time
;
54 PITChannelState channels
[3];
57 static PITState pit_state
;
59 static void pit_irq_timer_update(PITChannelState
*s
, int64_t current_time
);
61 static int pit_get_count(PITChannelState
*s
)
66 d
= muldiv64(qemu_get_clock(vm_clock
) - s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
72 counter
= (s
->count
- d
) & 0xffff;
75 /* XXX: may be incorrect for odd counts */
76 counter
= s
->count
- ((2 * d
) % s
->count
);
79 counter
= s
->count
- (d
% s
->count
);
85 /* get pit output bit */
86 static int pit_get_out1(PITChannelState
*s
, int64_t current_time
)
91 d
= muldiv64(current_time
- s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
95 out
= (d
>= s
->count
);
101 if ((d
% s
->count
) == 0 && d
!= 0)
107 out
= (d
% s
->count
) < ((s
->count
+ 1) >> 1);
111 out
= (d
== s
->count
);
117 int pit_get_out(PITState
*pit
, int channel
, int64_t current_time
)
119 PITChannelState
*s
= &pit
->channels
[channel
];
120 return pit_get_out1(s
, current_time
);
123 /* return -1 if no transition will occur. */
124 static int64_t pit_get_next_transition_time(PITChannelState
*s
,
125 int64_t current_time
)
127 uint64_t d
, next_time
, base
;
130 d
= muldiv64(current_time
- s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
136 next_time
= s
->count
;
141 base
= (d
/ s
->count
) * s
->count
;
142 if ((d
- base
) == 0 && d
!= 0)
143 next_time
= base
+ s
->count
;
145 next_time
= base
+ s
->count
+ 1;
148 base
= (d
/ s
->count
) * s
->count
;
149 period2
= ((s
->count
+ 1) >> 1);
150 if ((d
- base
) < period2
)
151 next_time
= base
+ period2
;
153 next_time
= base
+ s
->count
;
158 next_time
= s
->count
;
159 else if (d
== s
->count
)
160 next_time
= s
->count
+ 1;
165 /* convert to timer units */
166 next_time
= s
->count_load_time
+ muldiv64(next_time
, ticks_per_sec
, PIT_FREQ
);
167 /* fix potential rounding problems */
168 /* XXX: better solution: use a clock at PIT_FREQ Hz */
169 if (next_time
<= current_time
)
170 next_time
= current_time
+ 1;
174 /* val must be 0 or 1 */
175 void pit_set_gate(PITState
*pit
, int channel
, int val
)
177 PITChannelState
*s
= &pit
->channels
[channel
];
183 /* XXX: just disable/enable counting */
188 /* restart counting on rising edge */
189 s
->count_load_time
= qemu_get_clock(vm_clock
);
190 pit_irq_timer_update(s
, s
->count_load_time
);
196 /* restart counting on rising edge */
197 s
->count_load_time
= qemu_get_clock(vm_clock
);
198 pit_irq_timer_update(s
, s
->count_load_time
);
200 /* XXX: disable/enable counting */
206 int pit_get_gate(PITState
*pit
, int channel
)
208 PITChannelState
*s
= &pit
->channels
[channel
];
212 int pit_get_initial_count(PITState
*pit
, int channel
)
214 PITChannelState
*s
= &pit
->channels
[channel
];
218 int pit_get_mode(PITState
*pit
, int channel
)
220 PITChannelState
*s
= &pit
->channels
[channel
];
224 static inline void pit_load_count(PITChannelState
*s
, int val
)
228 s
->count_load_time
= qemu_get_clock(vm_clock
);
230 pit_irq_timer_update(s
, s
->count_load_time
);
233 /* if already latched, do not latch again */
234 static void pit_latch_count(PITChannelState
*s
)
236 if (!s
->count_latched
) {
237 s
->latched_count
= pit_get_count(s
);
238 s
->count_latched
= s
->rw_mode
;
242 static void pit_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
244 PITState
*pit
= opaque
;
252 /* read back command */
253 for(channel
= 0; channel
< 3; channel
++) {
254 s
= &pit
->channels
[channel
];
255 if (val
& (2 << channel
)) {
259 if (!(val
& 0x10) && !s
->status_latched
) {
261 /* XXX: add BCD and null count */
262 s
->status
= (pit_get_out1(s
, qemu_get_clock(vm_clock
)) << 7) |
266 s
->status_latched
= 1;
271 s
= &pit
->channels
[channel
];
272 access
= (val
>> 4) & 3;
277 s
->read_state
= access
;
278 s
->write_state
= access
;
280 s
->mode
= (val
>> 1) & 7;
282 /* XXX: update irq timer ? */
286 s
= &pit
->channels
[addr
];
287 switch(s
->write_state
) {
290 pit_load_count(s
, val
);
293 pit_load_count(s
, val
<< 8);
296 s
->write_latch
= val
;
297 s
->write_state
= RW_STATE_WORD1
;
300 pit_load_count(s
, s
->write_latch
| (val
<< 8));
301 s
->write_state
= RW_STATE_WORD0
;
307 static uint32_t pit_ioport_read(void *opaque
, uint32_t addr
)
309 PITState
*pit
= opaque
;
314 s
= &pit
->channels
[addr
];
315 if (s
->status_latched
) {
316 s
->status_latched
= 0;
318 } else if (s
->count_latched
) {
319 switch(s
->count_latched
) {
322 ret
= s
->latched_count
& 0xff;
323 s
->count_latched
= 0;
326 ret
= s
->latched_count
>> 8;
327 s
->count_latched
= 0;
330 ret
= s
->latched_count
& 0xff;
331 s
->count_latched
= RW_STATE_MSB
;
335 switch(s
->read_state
) {
338 count
= pit_get_count(s
);
342 count
= pit_get_count(s
);
343 ret
= (count
>> 8) & 0xff;
346 count
= pit_get_count(s
);
348 s
->read_state
= RW_STATE_WORD1
;
351 count
= pit_get_count(s
);
352 ret
= (count
>> 8) & 0xff;
353 s
->read_state
= RW_STATE_WORD0
;
360 static void pit_irq_timer_update(PITChannelState
*s
, int64_t current_time
)
367 expire_time
= pit_get_next_transition_time(s
, current_time
);
368 irq_level
= pit_get_out1(s
, current_time
);
369 qemu_set_irq(s
->irq
, irq_level
);
371 printf("irq_level=%d next_delay=%f\n",
373 (double)(expire_time
- current_time
) / ticks_per_sec
);
375 s
->next_transition_time
= expire_time
;
376 if (expire_time
!= -1)
377 qemu_mod_timer(s
->irq_timer
, expire_time
);
379 qemu_del_timer(s
->irq_timer
);
382 static void pit_irq_timer(void *opaque
)
384 PITChannelState
*s
= opaque
;
386 pit_irq_timer_update(s
, s
->next_transition_time
);
389 static void pit_save(QEMUFile
*f
, void *opaque
)
391 PITState
*pit
= opaque
;
395 for(i
= 0; i
< 3; i
++) {
396 s
= &pit
->channels
[i
];
397 qemu_put_be32s(f
, &s
->count
);
398 qemu_put_be16s(f
, &s
->latched_count
);
399 qemu_put_8s(f
, &s
->count_latched
);
400 qemu_put_8s(f
, &s
->status_latched
);
401 qemu_put_8s(f
, &s
->status
);
402 qemu_put_8s(f
, &s
->read_state
);
403 qemu_put_8s(f
, &s
->write_state
);
404 qemu_put_8s(f
, &s
->write_latch
);
405 qemu_put_8s(f
, &s
->rw_mode
);
406 qemu_put_8s(f
, &s
->mode
);
407 qemu_put_8s(f
, &s
->bcd
);
408 qemu_put_8s(f
, &s
->gate
);
409 qemu_put_be64s(f
, &s
->count_load_time
);
411 qemu_put_be64s(f
, &s
->next_transition_time
);
412 qemu_put_timer(f
, s
->irq_timer
);
417 static int pit_load(QEMUFile
*f
, void *opaque
, int version_id
)
419 PITState
*pit
= opaque
;
426 for(i
= 0; i
< 3; i
++) {
427 s
= &pit
->channels
[i
];
428 qemu_get_be32s(f
, &s
->count
);
429 qemu_get_be16s(f
, &s
->latched_count
);
430 qemu_get_8s(f
, &s
->count_latched
);
431 qemu_get_8s(f
, &s
->status_latched
);
432 qemu_get_8s(f
, &s
->status
);
433 qemu_get_8s(f
, &s
->read_state
);
434 qemu_get_8s(f
, &s
->write_state
);
435 qemu_get_8s(f
, &s
->write_latch
);
436 qemu_get_8s(f
, &s
->rw_mode
);
437 qemu_get_8s(f
, &s
->mode
);
438 qemu_get_8s(f
, &s
->bcd
);
439 qemu_get_8s(f
, &s
->gate
);
440 qemu_get_be64s(f
, &s
->count_load_time
);
442 qemu_get_be64s(f
, &s
->next_transition_time
);
443 qemu_get_timer(f
, s
->irq_timer
);
449 static void pit_reset(void *opaque
)
451 PITState
*pit
= opaque
;
455 for(i
= 0;i
< 3; i
++) {
456 s
= &pit
->channels
[i
];
459 pit_load_count(s
, 0);
463 PITState
*pit_init(int base
, qemu_irq irq
)
465 PITState
*pit
= &pit_state
;
468 s
= &pit
->channels
[0];
469 /* the timer 0 is connected to an IRQ */
470 s
->irq_timer
= qemu_new_timer(vm_clock
, pit_irq_timer
, s
);
473 register_savevm("i8254", base
, 1, pit_save
, pit_load
, pit
);
475 qemu_register_reset(pit_reset
, pit
);
476 register_ioport_write(base
, 4, 1, pit_ioport_write
, pit
);
477 register_ioport_read(base
, 3, 1, pit_ioport_read
, pit
);