4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 //#define DEBUG_IOAPIC
25 /* APIC Local Vector Table */
26 #define APIC_LVT_TIMER 0
27 #define APIC_LVT_THERMAL 1
28 #define APIC_LVT_PERFORM 2
29 #define APIC_LVT_LINT0 3
30 #define APIC_LVT_LINT1 4
31 #define APIC_LVT_ERROR 5
34 /* APIC delivery modes */
35 #define APIC_DM_FIXED 0
36 #define APIC_DM_LOWPRI 1
39 #define APIC_DM_INIT 5
40 #define APIC_DM_SIPI 6
41 #define APIC_DM_EXTINT 7
43 /* APIC destination mode */
44 #define APIC_DESTMODE_FLAT 0xf
45 #define APIC_DESTMODE_CLUSTER 1
47 #define APIC_TRIGGER_EDGE 0
48 #define APIC_TRIGGER_LEVEL 1
50 #define APIC_LVT_TIMER_PERIODIC (1<<17)
51 #define APIC_LVT_MASKED (1<<16)
52 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
53 #define APIC_LVT_REMOTE_IRR (1<<14)
54 #define APIC_INPUT_POLARITY (1<<13)
55 #define APIC_SEND_PENDING (1<<12)
57 #define IOAPIC_NUM_PINS 0x18
59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
61 #define APIC_SV_ENABLE (1 << 8)
64 #define MAX_APIC_WORDS 8
66 typedef struct APICState
{
72 uint32_t spurious_vec
;
75 uint32_t isr
[8]; /* in service register */
76 uint32_t tmr
[8]; /* trigger mode register */
77 uint32_t irr
[8]; /* interrupt request register */
78 uint32_t lvt
[APIC_LVT_NB
];
79 uint32_t esr
; /* error register */
84 uint32_t initial_count
;
85 int64_t initial_count_load_time
, next_time
;
94 uint64_t ioredtbl
[IOAPIC_NUM_PINS
];
97 static int apic_io_memory
;
98 static APICState
*local_apics
[MAX_APICS
+ 1];
99 static int last_apic_id
= 0;
101 static void apic_init_ipi(APICState
*s
);
102 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
);
103 static void apic_update_irq(APICState
*s
);
105 /* Find first bit starting from msb. Return 0 if value = 0 */
106 static int fls_bit(uint32_t value
)
108 unsigned int ret
= 0;
110 #if defined(HOST_I386)
111 __asm__
__volatile__ ("bsr %1, %0\n" : "+r" (ret
) : "rm" (value
));
115 value
>>= 16, ret
= 16;
117 value
>>= 8, ret
+= 8;
119 value
>>= 4, ret
+= 4;
121 value
>>= 2, ret
+= 2;
122 return ret
+ (value
>> 1);
126 /* Find first bit starting from lsb. Return 0 if value = 0 */
127 static int ffs_bit(uint32_t value
)
129 unsigned int ret
= 0;
131 #if defined(HOST_I386)
132 __asm__
__volatile__ ("bsf %1, %0\n" : "+r" (ret
) : "rm" (value
));
137 if (!(value
& 0xffff))
138 value
>>= 16, ret
= 16;
140 value
>>= 8, ret
+= 8;
142 value
>>= 4, ret
+= 4;
144 value
>>= 2, ret
+= 2;
151 static inline void set_bit(uint32_t *tab
, int index
)
155 mask
= 1 << (index
& 0x1f);
159 static inline void reset_bit(uint32_t *tab
, int index
)
163 mask
= 1 << (index
& 0x1f);
167 #define foreach_apic(apic, deliver_bitmask, code) \
169 int __i, __j, __mask;\
170 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
171 __mask = deliver_bitmask[__i];\
173 for(__j = 0; __j < 32; __j++) {\
174 if (__mask & (1 << __j)) {\
175 apic = local_apics[__i * 32 + __j];\
185 static void apic_bus_deliver(const uint32_t *deliver_bitmask
,
186 uint8_t delivery_mode
,
187 uint8_t vector_num
, uint8_t polarity
,
188 uint8_t trigger_mode
)
190 APICState
*apic_iter
;
192 switch (delivery_mode
) {
194 /* XXX: search for focus processor, arbitration */
198 for(i
= 0; i
< MAX_APIC_WORDS
; i
++) {
199 if (deliver_bitmask
[i
]) {
200 d
= i
* 32 + ffs_bit(deliver_bitmask
[i
]);
205 apic_iter
= local_apics
[d
];
207 apic_set_irq(apic_iter
, vector_num
, trigger_mode
);
221 /* normal INIT IPI sent to processors */
222 foreach_apic(apic_iter
, deliver_bitmask
,
223 apic_init_ipi(apic_iter
) );
227 /* handled in I/O APIC code */
234 foreach_apic(apic_iter
, deliver_bitmask
,
235 apic_set_irq(apic_iter
, vector_num
, trigger_mode
) );
238 void cpu_set_apic_base(CPUState
*env
, uint64_t val
)
240 APICState
*s
= env
->apic_state
;
242 printf("cpu_set_apic_base: %016" PRIx64
"\n", val
);
244 s
->apicbase
= (val
& 0xfffff000) |
245 (s
->apicbase
& (MSR_IA32_APICBASE_BSP
| MSR_IA32_APICBASE_ENABLE
));
246 /* if disabled, cannot be enabled again */
247 if (!(val
& MSR_IA32_APICBASE_ENABLE
)) {
248 s
->apicbase
&= ~MSR_IA32_APICBASE_ENABLE
;
249 env
->cpuid_features
&= ~CPUID_APIC
;
250 s
->spurious_vec
&= ~APIC_SV_ENABLE
;
254 uint64_t cpu_get_apic_base(CPUState
*env
)
256 APICState
*s
= env
->apic_state
;
258 printf("cpu_get_apic_base: %016" PRIx64
"\n", (uint64_t)s
->apicbase
);
263 void cpu_set_apic_tpr(CPUX86State
*env
, uint8_t val
)
265 APICState
*s
= env
->apic_state
;
266 s
->tpr
= (val
& 0x0f) << 4;
270 uint8_t cpu_get_apic_tpr(CPUX86State
*env
)
272 APICState
*s
= env
->apic_state
;
276 /* return -1 if no bit is set */
277 static int get_highest_priority_int(uint32_t *tab
)
280 for(i
= 7; i
>= 0; i
--) {
282 return i
* 32 + fls_bit(tab
[i
]);
288 static int apic_get_ppr(APICState
*s
)
293 isrv
= get_highest_priority_int(s
->isr
);
304 static int apic_get_arb_pri(APICState
*s
)
306 /* XXX: arbitration */
310 /* signal the CPU if an irq is pending */
311 static void apic_update_irq(APICState
*s
)
314 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
316 irrv
= get_highest_priority_int(s
->irr
);
319 ppr
= apic_get_ppr(s
);
320 if (ppr
&& (irrv
& 0xf0) <= (ppr
& 0xf0))
322 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
325 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
)
327 set_bit(s
->irr
, vector_num
);
329 set_bit(s
->tmr
, vector_num
);
331 reset_bit(s
->tmr
, vector_num
);
335 static void apic_eoi(APICState
*s
)
338 isrv
= get_highest_priority_int(s
->isr
);
341 reset_bit(s
->isr
, isrv
);
342 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
343 set the remote IRR bit for level triggered interrupts. */
347 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
348 uint8_t dest
, uint8_t dest_mode
)
350 APICState
*apic_iter
;
353 if (dest_mode
== 0) {
355 memset(deliver_bitmask
, 0xff, MAX_APIC_WORDS
* sizeof(uint32_t));
357 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
358 set_bit(deliver_bitmask
, dest
);
361 /* XXX: cluster mode */
362 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
363 for(i
= 0; i
< MAX_APICS
; i
++) {
364 apic_iter
= local_apics
[i
];
366 if (apic_iter
->dest_mode
== 0xf) {
367 if (dest
& apic_iter
->log_dest
)
368 set_bit(deliver_bitmask
, i
);
369 } else if (apic_iter
->dest_mode
== 0x0) {
370 if ((dest
& 0xf0) == (apic_iter
->log_dest
& 0xf0) &&
371 (dest
& apic_iter
->log_dest
& 0x0f)) {
372 set_bit(deliver_bitmask
, i
);
381 static void apic_init_ipi(APICState
*s
)
386 s
->spurious_vec
= 0xff;
389 memset(s
->isr
, 0, sizeof(s
->isr
));
390 memset(s
->tmr
, 0, sizeof(s
->tmr
));
391 memset(s
->irr
, 0, sizeof(s
->irr
));
392 for(i
= 0; i
< APIC_LVT_NB
; i
++)
393 s
->lvt
[i
] = 1 << 16; /* mask LVT */
395 memset(s
->icr
, 0, sizeof(s
->icr
));
398 s
->initial_count
= 0;
399 s
->initial_count_load_time
= 0;
403 /* send a SIPI message to the CPU to start it */
404 static void apic_startup(APICState
*s
, int vector_num
)
406 CPUState
*env
= s
->cpu_env
;
407 if (!(env
->hflags
& HF_HALTED_MASK
))
410 cpu_x86_load_seg_cache(env
, R_CS
, vector_num
<< 8, vector_num
<< 12,
412 env
->hflags
&= ~HF_HALTED_MASK
;
415 static void apic_deliver(APICState
*s
, uint8_t dest
, uint8_t dest_mode
,
416 uint8_t delivery_mode
, uint8_t vector_num
,
417 uint8_t polarity
, uint8_t trigger_mode
)
419 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
420 int dest_shorthand
= (s
->icr
[0] >> 18) & 3;
421 APICState
*apic_iter
;
423 switch (dest_shorthand
) {
425 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
428 memset(deliver_bitmask
, 0x00, sizeof(deliver_bitmask
));
429 set_bit(deliver_bitmask
, s
->id
);
432 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
435 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
436 reset_bit(deliver_bitmask
, s
->id
);
440 switch (delivery_mode
) {
443 int trig_mode
= (s
->icr
[0] >> 15) & 1;
444 int level
= (s
->icr
[0] >> 14) & 1;
445 if (level
== 0 && trig_mode
== 1) {
446 foreach_apic(apic_iter
, deliver_bitmask
,
447 apic_iter
->arb_id
= apic_iter
->id
);
454 foreach_apic(apic_iter
, deliver_bitmask
,
455 apic_startup(apic_iter
, vector_num
) );
459 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, polarity
,
463 int apic_get_interrupt(CPUState
*env
)
465 APICState
*s
= env
->apic_state
;
468 /* if the APIC is installed or enabled, we let the 8259 handle the
472 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
475 /* XXX: spurious IRQ handling */
476 intno
= get_highest_priority_int(s
->irr
);
479 if (s
->tpr
&& intno
<= s
->tpr
)
480 return s
->spurious_vec
& 0xff;
481 reset_bit(s
->irr
, intno
);
482 set_bit(s
->isr
, intno
);
487 int apic_accept_pic_intr(CPUState
*env
)
489 APICState
*s
= env
->apic_state
;
495 lvt0
= s
->lvt
[APIC_LVT_LINT0
];
498 ((s
->apicbase
& MSR_IA32_APICBASE_ENABLE
) == 0 ||
499 ((lvt0
& APIC_LVT_MASKED
) == 0 &&
500 ((lvt0
>> 8) & 0x7) == APIC_DM_EXTINT
)))
506 static uint32_t apic_get_current_count(APICState
*s
)
510 d
= (qemu_get_clock(vm_clock
) - s
->initial_count_load_time
) >>
512 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
514 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
516 if (d
>= s
->initial_count
)
519 val
= s
->initial_count
- d
;
524 static void apic_timer_update(APICState
*s
, int64_t current_time
)
526 int64_t next_time
, d
;
528 if (!(s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
)) {
529 d
= (current_time
- s
->initial_count_load_time
) >>
531 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
532 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) * ((uint64_t)s
->initial_count
+ 1);
534 if (d
>= s
->initial_count
)
536 d
= (uint64_t)s
->initial_count
+ 1;
538 next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
539 qemu_mod_timer(s
->timer
, next_time
);
540 s
->next_time
= next_time
;
543 qemu_del_timer(s
->timer
);
547 static void apic_timer(void *opaque
)
549 APICState
*s
= opaque
;
551 if (!(s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
)) {
552 apic_set_irq(s
, s
->lvt
[APIC_LVT_TIMER
] & 0xff, APIC_TRIGGER_EDGE
);
554 apic_timer_update(s
, s
->next_time
);
557 static uint32_t apic_mem_readb(void *opaque
, target_phys_addr_t addr
)
562 static uint32_t apic_mem_readw(void *opaque
, target_phys_addr_t addr
)
567 static void apic_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
571 static void apic_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
575 static uint32_t apic_mem_readl(void *opaque
, target_phys_addr_t addr
)
582 env
= cpu_single_env
;
587 index
= (addr
>> 4) & 0xff;
592 case 0x03: /* version */
593 val
= 0x11 | ((APIC_LVT_NB
- 1) << 16); /* version 0x11 */
599 val
= apic_get_arb_pri(s
);
603 val
= apic_get_ppr(s
);
606 val
= s
->log_dest
<< 24;
609 val
= s
->dest_mode
<< 28;
612 val
= s
->spurious_vec
;
615 val
= s
->isr
[index
& 7];
618 val
= s
->tmr
[index
& 7];
621 val
= s
->irr
[index
& 7];
628 val
= s
->icr
[index
& 1];
631 val
= s
->lvt
[index
- 0x32];
634 val
= s
->initial_count
;
637 val
= apic_get_current_count(s
);
640 val
= s
->divide_conf
;
643 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
648 printf("APIC read: %08x = %08x\n", (uint32_t)addr
, val
);
653 static void apic_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
659 env
= cpu_single_env
;
665 printf("APIC write: %08x = %08x\n", (uint32_t)addr
, val
);
668 index
= (addr
>> 4) & 0xff;
686 s
->log_dest
= val
>> 24;
689 s
->dest_mode
= val
>> 28;
692 s
->spurious_vec
= val
& 0x1ff;
702 apic_deliver(s
, (s
->icr
[1] >> 24) & 0xff, (s
->icr
[0] >> 11) & 1,
703 (s
->icr
[0] >> 8) & 7, (s
->icr
[0] & 0xff),
704 (s
->icr
[0] >> 14) & 1, (s
->icr
[0] >> 15) & 1);
711 int n
= index
- 0x32;
713 if (n
== APIC_LVT_TIMER
)
714 apic_timer_update(s
, qemu_get_clock(vm_clock
));
718 s
->initial_count
= val
;
719 s
->initial_count_load_time
= qemu_get_clock(vm_clock
);
720 apic_timer_update(s
, s
->initial_count_load_time
);
727 s
->divide_conf
= val
& 0xb;
728 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
729 s
->count_shift
= (v
+ 1) & 7;
733 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
738 static void apic_save(QEMUFile
*f
, void *opaque
)
740 APICState
*s
= opaque
;
743 qemu_put_be32s(f
, &s
->apicbase
);
744 qemu_put_8s(f
, &s
->id
);
745 qemu_put_8s(f
, &s
->arb_id
);
746 qemu_put_8s(f
, &s
->tpr
);
747 qemu_put_be32s(f
, &s
->spurious_vec
);
748 qemu_put_8s(f
, &s
->log_dest
);
749 qemu_put_8s(f
, &s
->dest_mode
);
750 for (i
= 0; i
< 8; i
++) {
751 qemu_put_be32s(f
, &s
->isr
[i
]);
752 qemu_put_be32s(f
, &s
->tmr
[i
]);
753 qemu_put_be32s(f
, &s
->irr
[i
]);
755 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
756 qemu_put_be32s(f
, &s
->lvt
[i
]);
758 qemu_put_be32s(f
, &s
->esr
);
759 qemu_put_be32s(f
, &s
->icr
[0]);
760 qemu_put_be32s(f
, &s
->icr
[1]);
761 qemu_put_be32s(f
, &s
->divide_conf
);
762 qemu_put_be32s(f
, &s
->count_shift
);
763 qemu_put_be32s(f
, &s
->initial_count
);
764 qemu_put_be64s(f
, &s
->initial_count_load_time
);
765 qemu_put_be64s(f
, &s
->next_time
);
767 qemu_put_timer(f
, s
->timer
);
770 static int apic_load(QEMUFile
*f
, void *opaque
, int version_id
)
772 APICState
*s
= opaque
;
778 /* XXX: what if the base changes? (registered memory regions) */
779 qemu_get_be32s(f
, &s
->apicbase
);
780 qemu_get_8s(f
, &s
->id
);
781 qemu_get_8s(f
, &s
->arb_id
);
782 qemu_get_8s(f
, &s
->tpr
);
783 qemu_get_be32s(f
, &s
->spurious_vec
);
784 qemu_get_8s(f
, &s
->log_dest
);
785 qemu_get_8s(f
, &s
->dest_mode
);
786 for (i
= 0; i
< 8; i
++) {
787 qemu_get_be32s(f
, &s
->isr
[i
]);
788 qemu_get_be32s(f
, &s
->tmr
[i
]);
789 qemu_get_be32s(f
, &s
->irr
[i
]);
791 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
792 qemu_get_be32s(f
, &s
->lvt
[i
]);
794 qemu_get_be32s(f
, &s
->esr
);
795 qemu_get_be32s(f
, &s
->icr
[0]);
796 qemu_get_be32s(f
, &s
->icr
[1]);
797 qemu_get_be32s(f
, &s
->divide_conf
);
798 qemu_get_be32s(f
, &s
->count_shift
);
799 qemu_get_be32s(f
, &s
->initial_count
);
800 qemu_get_be64s(f
, &s
->initial_count_load_time
);
801 qemu_get_be64s(f
, &s
->next_time
);
804 qemu_get_timer(f
, s
->timer
);
808 static void apic_reset(void *opaque
)
810 APICState
*s
= opaque
;
814 * LINT0 delivery mode is set to ExtInt at initialization time
815 * typically by BIOS, so PIC interrupt can be delivered to the
816 * processor when local APIC is enabled.
818 s
->lvt
[APIC_LVT_LINT0
] = 0x700;
821 static CPUReadMemoryFunc
*apic_mem_read
[3] = {
827 static CPUWriteMemoryFunc
*apic_mem_write
[3] = {
833 int apic_init(CPUState
*env
)
837 if (last_apic_id
>= MAX_APICS
)
839 s
= qemu_mallocz(sizeof(APICState
));
844 s
->id
= last_apic_id
++;
845 env
->cpuid_apic_id
= s
->id
;
847 s
->apicbase
= 0xfee00000 |
848 (s
->id
? 0 : MSR_IA32_APICBASE_BSP
) | MSR_IA32_APICBASE_ENABLE
;
851 * LINT0 delivery mode is set to ExtInt at initialization time
852 * typically by BIOS, so PIC interrupt can be delivered to the
853 * processor when local APIC is enabled.
855 s
->lvt
[APIC_LVT_LINT0
] = 0x700;
857 /* XXX: mapping more APICs at the same memory location */
858 if (apic_io_memory
== 0) {
859 /* NOTE: the APIC is directly connected to the CPU - it is not
860 on the global memory bus. */
861 apic_io_memory
= cpu_register_io_memory(0, apic_mem_read
,
862 apic_mem_write
, NULL
);
863 cpu_register_physical_memory(s
->apicbase
& ~0xfff, 0x1000,
866 s
->timer
= qemu_new_timer(vm_clock
, apic_timer
, s
);
868 register_savevm("apic", s
->id
, 2, apic_save
, apic_load
, s
);
869 qemu_register_reset(apic_reset
, s
);
871 local_apics
[s
->id
] = s
;
875 static void ioapic_service(IOAPICState
*s
)
880 uint8_t delivery_mode
;
886 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
888 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
891 entry
= s
->ioredtbl
[i
];
892 if (!(entry
& APIC_LVT_MASKED
)) {
893 trig_mode
= ((entry
>> 15) & 1);
895 dest_mode
= (entry
>> 11) & 1;
896 delivery_mode
= (entry
>> 8) & 7;
897 polarity
= (entry
>> 13) & 1;
898 if (trig_mode
== APIC_TRIGGER_EDGE
)
900 if (delivery_mode
== APIC_DM_EXTINT
)
901 vector
= pic_read_irq(isa_pic
);
903 vector
= entry
& 0xff;
905 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
906 apic_bus_deliver(deliver_bitmask
, delivery_mode
,
907 vector
, polarity
, trig_mode
);
913 void ioapic_set_irq(void *opaque
, int vector
, int level
)
915 IOAPICState
*s
= opaque
;
917 if (vector
>= 0 && vector
< IOAPIC_NUM_PINS
) {
918 uint32_t mask
= 1 << vector
;
919 uint64_t entry
= s
->ioredtbl
[vector
];
921 if ((entry
>> 15) & 1) {
922 /* level triggered */
939 static uint32_t ioapic_mem_readl(void *opaque
, target_phys_addr_t addr
)
941 IOAPICState
*s
= opaque
;
948 } else if (addr
== 0x10) {
949 switch (s
->ioregsel
) {
954 val
= 0x11 | ((IOAPIC_NUM_PINS
- 1) << 16); /* version 0x11 */
960 index
= (s
->ioregsel
- 0x10) >> 1;
961 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
963 val
= s
->ioredtbl
[index
] >> 32;
965 val
= s
->ioredtbl
[index
] & 0xffffffff;
969 printf("I/O APIC read: %08x = %08x\n", s
->ioregsel
, val
);
975 static void ioapic_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
977 IOAPICState
*s
= opaque
;
984 } else if (addr
== 0x10) {
986 printf("I/O APIC write: %08x = %08x\n", s
->ioregsel
, val
);
988 switch (s
->ioregsel
) {
990 s
->id
= (val
>> 24) & 0xff;
996 index
= (s
->ioregsel
- 0x10) >> 1;
997 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
998 if (s
->ioregsel
& 1) {
999 s
->ioredtbl
[index
] &= 0xffffffff;
1000 s
->ioredtbl
[index
] |= (uint64_t)val
<< 32;
1002 s
->ioredtbl
[index
] &= ~0xffffffffULL
;
1003 s
->ioredtbl
[index
] |= val
;
1011 static void ioapic_save(QEMUFile
*f
, void *opaque
)
1013 IOAPICState
*s
= opaque
;
1016 qemu_put_8s(f
, &s
->id
);
1017 qemu_put_8s(f
, &s
->ioregsel
);
1018 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1019 qemu_put_be64s(f
, &s
->ioredtbl
[i
]);
1023 static int ioapic_load(QEMUFile
*f
, void *opaque
, int version_id
)
1025 IOAPICState
*s
= opaque
;
1028 if (version_id
!= 1)
1031 qemu_get_8s(f
, &s
->id
);
1032 qemu_get_8s(f
, &s
->ioregsel
);
1033 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1034 qemu_get_be64s(f
, &s
->ioredtbl
[i
]);
1039 static void ioapic_reset(void *opaque
)
1041 IOAPICState
*s
= opaque
;
1044 memset(s
, 0, sizeof(*s
));
1045 for(i
= 0; i
< IOAPIC_NUM_PINS
; i
++)
1046 s
->ioredtbl
[i
] = 1 << 16; /* mask LVT */
1049 static CPUReadMemoryFunc
*ioapic_mem_read
[3] = {
1055 static CPUWriteMemoryFunc
*ioapic_mem_write
[3] = {
1061 IOAPICState
*ioapic_init(void)
1066 s
= qemu_mallocz(sizeof(IOAPICState
));
1070 s
->id
= last_apic_id
++;
1072 io_memory
= cpu_register_io_memory(0, ioapic_mem_read
,
1073 ioapic_mem_write
, s
);
1074 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory
);
1076 register_savevm("ioapic", 0, 1, ioapic_save
, ioapic_load
, s
);
1077 qemu_register_reset(ioapic_reset
, s
);