?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
CPU specific boot mode (Robert Reif)
[qemu/qemu_0_9_1_stable.git] / vl.h
blob92ffd3c84c75a0571ab88be4c971bb32ef7fffc6
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef likely
97 #if __GNUC__ < 3
98 #define __builtin_expect(x, n) (x)
99 #endif
100
101 #define likely(x) __builtin_expect(!!(x), 1)
102 #define unlikely(x) __builtin_expect(!!(x), 0)
103 #endif
104
105 #ifndef MIN
106 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
107 #endif
108 #ifndef MAX
109 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
110 #endif
111
112 #ifndef always_inline
113 #if (__GNUC__ < 3) || defined(__APPLE__)
114 #define always_inline inline
115 #else
116 #define always_inline __attribute__ (( always_inline )) inline
117 #endif
118 #endif
119
120 /* cutils.c */
121 void pstrcpy(char *buf, int buf_size, const char *str);
122 char *pstrcat(char *buf, int buf_size, const char *s);
123 int strstart(const char *str, const char *val, const char **ptr);
124 int stristart(const char *str, const char *val, const char **ptr);
125
126 /* vl.c */
127 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
128
129 void hw_error(const char *fmt, ...);
130
131 extern const char *bios_dir;
132 extern const char *bios_name;
133
134 extern int vm_running;
135 extern const char *qemu_name;
136
137 typedef struct vm_change_state_entry VMChangeStateEntry;
138 typedef void VMChangeStateHandler(void *opaque, int running);
139 typedef void VMStopHandler(void *opaque, int reason);
140
141 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
142 void *opaque);
143 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
144
145 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
146 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
147
148 void vm_start(void);
149 void vm_stop(int reason);
150
151 typedef void QEMUResetHandler(void *opaque);
152
153 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
154 void qemu_system_reset_request(void);
155 void qemu_system_shutdown_request(void);
156 void qemu_system_powerdown_request(void);
157 #if !defined(TARGET_SPARC)
158 // Please implement a power failure function to signal the OS
159 #define qemu_system_powerdown() do{}while(0)
160 #else
161 void qemu_system_powerdown(void);
162 #endif
163
164 void main_loop_wait(int timeout);
165
166 extern int ram_size;
167 extern int bios_size;
168 extern int rtc_utc;
169 extern int rtc_start_date;
170 extern int cirrus_vga_enabled;
171 extern int vmsvga_enabled;
172 extern int graphic_width;
173 extern int graphic_height;
174 extern int graphic_depth;
175 extern const char *keyboard_layout;
176 extern int kqemu_allowed;
177 extern int win2k_install_hack;
178 extern int alt_grab;
179 extern int usb_enabled;
180 extern int smp_cpus;
181 extern int cursor_hide;
182 extern int graphic_rotate;
183 extern int no_quit;
184 extern int semihosting_enabled;
185 extern int autostart;
186 extern int old_param;
187 extern const char *bootp_filename;
188
189 #define MAX_OPTION_ROMS 16
190 extern const char *option_rom[MAX_OPTION_ROMS];
191 extern int nb_option_roms;
192
193 #ifdef TARGET_SPARC
194 #define MAX_PROM_ENVS 128
195 extern const char *prom_envs[MAX_PROM_ENVS];
196 extern unsigned int nb_prom_envs;
197 #endif
198
199 /* XXX: make it dynamic */
200 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
201 #if defined (TARGET_PPC)
202 #define BIOS_SIZE (1024 * 1024)
203 #elif defined (TARGET_SPARC64)
204 #define BIOS_SIZE ((512 + 32) * 1024)
205 #elif defined(TARGET_MIPS)
206 #define BIOS_SIZE (4 * 1024 * 1024)
207 #endif
208
209 /* keyboard/mouse support */
210
211 #define MOUSE_EVENT_LBUTTON 0x01
212 #define MOUSE_EVENT_RBUTTON 0x02
213 #define MOUSE_EVENT_MBUTTON 0x04
214
215 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
216 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
217
218 typedef struct QEMUPutMouseEntry {
219 QEMUPutMouseEvent *qemu_put_mouse_event;
220 void *qemu_put_mouse_event_opaque;
221 int qemu_put_mouse_event_absolute;
222 char *qemu_put_mouse_event_name;
223
224 /* used internally by qemu for handling mice */
225 struct QEMUPutMouseEntry *next;
226 } QEMUPutMouseEntry;
227
228 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
229 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
230 void *opaque, int absolute,
231 const char *name);
232 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
233
234 void kbd_put_keycode(int keycode);
235 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
236 int kbd_mouse_is_absolute(void);
237
238 void do_info_mice(void);
239 void do_mouse_set(int index);
240
241 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
242 constants) */
243 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
244 #define QEMU_KEY_BACKSPACE 0x007f
245 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
246 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
247 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
248 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
249 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
250 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
251 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
252 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
253 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
254
255 #define QEMU_KEY_CTRL_UP 0xe400
256 #define QEMU_KEY_CTRL_DOWN 0xe401
257 #define QEMU_KEY_CTRL_LEFT 0xe402
258 #define QEMU_KEY_CTRL_RIGHT 0xe403
259 #define QEMU_KEY_CTRL_HOME 0xe404
260 #define QEMU_KEY_CTRL_END 0xe405
261 #define QEMU_KEY_CTRL_PAGEUP 0xe406
262 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
263
264 void kbd_put_keysym(int keysym);
265
266 /* async I/O support */
267
268 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
269 typedef int IOCanRWHandler(void *opaque);
270 typedef void IOHandler(void *opaque);
271
272 int qemu_set_fd_handler2(int fd,
273 IOCanRWHandler *fd_read_poll,
274 IOHandler *fd_read,
275 IOHandler *fd_write,
276 void *opaque);
277 int qemu_set_fd_handler(int fd,
278 IOHandler *fd_read,
279 IOHandler *fd_write,
280 void *opaque);
281
282 /* Polling handling */
283
284 /* return TRUE if no sleep should be done afterwards */
285 typedef int PollingFunc(void *opaque);
286
287 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
288 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
289
290 #ifdef _WIN32
291 /* Wait objects handling */
292 typedef void WaitObjectFunc(void *opaque);
293
294 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
295 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
296 #endif
297
298 typedef struct QEMUBH QEMUBH;
299
300 /* character device */
301
302 #define CHR_EVENT_BREAK 0 /* serial break char */
303 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
304 #define CHR_EVENT_RESET 2 /* new connection established */
305
306
307 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
308 typedef struct {
309 int speed;
310 int parity;
311 int data_bits;
312 int stop_bits;
313 } QEMUSerialSetParams;
314
315 #define CHR_IOCTL_SERIAL_SET_BREAK 2
316
317 #define CHR_IOCTL_PP_READ_DATA 3
318 #define CHR_IOCTL_PP_WRITE_DATA 4
319 #define CHR_IOCTL_PP_READ_CONTROL 5
320 #define CHR_IOCTL_PP_WRITE_CONTROL 6
321 #define CHR_IOCTL_PP_READ_STATUS 7
322 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
323 #define CHR_IOCTL_PP_EPP_READ 9
324 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
325 #define CHR_IOCTL_PP_EPP_WRITE 11
326
327 typedef void IOEventHandler(void *opaque, int event);
328
329 typedef struct CharDriverState {
330 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
331 void (*chr_update_read_handler)(struct CharDriverState *s);
332 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
333 IOEventHandler *chr_event;
334 IOCanRWHandler *chr_can_read;
335 IOReadHandler *chr_read;
336 void *handler_opaque;
337 void (*chr_send_event)(struct CharDriverState *chr, int event);
338 void (*chr_close)(struct CharDriverState *chr);
339 void *opaque;
340 int focus;
341 QEMUBH *bh;
342 } CharDriverState;
343
344 CharDriverState *qemu_chr_open(const char *filename);
345 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
346 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
347 void qemu_chr_send_event(CharDriverState *s, int event);
348 void qemu_chr_add_handlers(CharDriverState *s,
349 IOCanRWHandler *fd_can_read,
350 IOReadHandler *fd_read,
351 IOEventHandler *fd_event,
352 void *opaque);
353 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
354 void qemu_chr_reset(CharDriverState *s);
355 int qemu_chr_can_read(CharDriverState *s);
356 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
357
358 /* consoles */
359
360 typedef struct DisplayState DisplayState;
361 typedef struct TextConsole TextConsole;
362
363 typedef void (*vga_hw_update_ptr)(void *);
364 typedef void (*vga_hw_invalidate_ptr)(void *);
365 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
366
367 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
368 vga_hw_invalidate_ptr invalidate,
369 vga_hw_screen_dump_ptr screen_dump,
370 void *opaque);
371 void vga_hw_update(void);
372 void vga_hw_invalidate(void);
373 void vga_hw_screen_dump(const char *filename);
374
375 int is_graphic_console(void);
376 CharDriverState *text_console_init(DisplayState *ds, const char *p);
377 void console_select(unsigned int index);
378 void console_color_init(DisplayState *ds);
379
380 /* serial ports */
381
382 #define MAX_SERIAL_PORTS 4
383
384 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
385
386 /* parallel ports */
387
388 #define MAX_PARALLEL_PORTS 3
389
390 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
391
392 struct ParallelIOArg {
393 void *buffer;
394 int count;
395 };
396
397 /* VLANs support */
398
399 typedef struct VLANClientState VLANClientState;
400
401 struct VLANClientState {
402 IOReadHandler *fd_read;
403 /* Packets may still be sent if this returns zero. It's used to
404 rate-limit the slirp code. */
405 IOCanRWHandler *fd_can_read;
406 void *opaque;
407 struct VLANClientState *next;
408 struct VLANState *vlan;
409 char info_str[256];
410 };
411
412 typedef struct VLANState {
413 int id;
414 VLANClientState *first_client;
415 struct VLANState *next;
416 unsigned int nb_guest_devs, nb_host_devs;
417 } VLANState;
418
419 VLANState *qemu_find_vlan(int id);
420 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
421 IOReadHandler *fd_read,
422 IOCanRWHandler *fd_can_read,
423 void *opaque);
424 int qemu_can_send_packet(VLANClientState *vc);
425 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
426 void qemu_handler_true(void *opaque);
427
428 void do_info_network(void);
429
430 /* TAP win32 */
431 int tap_win32_init(VLANState *vlan, const char *ifname);
432
433 /* NIC info */
434
435 #define MAX_NICS 8
436
437 typedef struct NICInfo {
438 uint8_t macaddr[6];
439 const char *model;
440 VLANState *vlan;
441 } NICInfo;
442
443 extern int nb_nics;
444 extern NICInfo nd_table[MAX_NICS];
445
446 /* SLIRP */
447 void do_info_slirp(void);
448
449 /* timers */
450
451 typedef struct QEMUClock QEMUClock;
452 typedef struct QEMUTimer QEMUTimer;
453 typedef void QEMUTimerCB(void *opaque);
454
455 /* The real time clock should be used only for stuff which does not
456 change the virtual machine state, as it is run even if the virtual
457 machine is stopped. The real time clock has a frequency of 1000
458 Hz. */
459 extern QEMUClock *rt_clock;
460
461 /* The virtual clock is only run during the emulation. It is stopped
462 when the virtual machine is stopped. Virtual timers use a high
463 precision clock, usually cpu cycles (use ticks_per_sec). */
464 extern QEMUClock *vm_clock;
465
466 int64_t qemu_get_clock(QEMUClock *clock);
467
468 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
469 void qemu_free_timer(QEMUTimer *ts);
470 void qemu_del_timer(QEMUTimer *ts);
471 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
472 int qemu_timer_pending(QEMUTimer *ts);
473
474 extern int64_t ticks_per_sec;
475
476 int64_t cpu_get_ticks(void);
477 void cpu_enable_ticks(void);
478 void cpu_disable_ticks(void);
479
480 /* VM Load/Save */
481
482 typedef struct QEMUFile QEMUFile;
483
484 QEMUFile *qemu_fopen(const char *filename, const char *mode);
485 void qemu_fflush(QEMUFile *f);
486 void qemu_fclose(QEMUFile *f);
487 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
488 void qemu_put_byte(QEMUFile *f, int v);
489 void qemu_put_be16(QEMUFile *f, unsigned int v);
490 void qemu_put_be32(QEMUFile *f, unsigned int v);
491 void qemu_put_be64(QEMUFile *f, uint64_t v);
492 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
493 int qemu_get_byte(QEMUFile *f);
494 unsigned int qemu_get_be16(QEMUFile *f);
495 unsigned int qemu_get_be32(QEMUFile *f);
496 uint64_t qemu_get_be64(QEMUFile *f);
497
498 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
499 {
500 qemu_put_be64(f, *pv);
501 }
502
503 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
504 {
505 qemu_put_be32(f, *pv);
506 }
507
508 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
509 {
510 qemu_put_be16(f, *pv);
511 }
512
513 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
514 {
515 qemu_put_byte(f, *pv);
516 }
517
518 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
519 {
520 *pv = qemu_get_be64(f);
521 }
522
523 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
524 {
525 *pv = qemu_get_be32(f);
526 }
527
528 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
529 {
530 *pv = qemu_get_be16(f);
531 }
532
533 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
534 {
535 *pv = qemu_get_byte(f);
536 }
537
538 #if TARGET_LONG_BITS == 64
539 #define qemu_put_betl qemu_put_be64
540 #define qemu_get_betl qemu_get_be64
541 #define qemu_put_betls qemu_put_be64s
542 #define qemu_get_betls qemu_get_be64s
543 #else
544 #define qemu_put_betl qemu_put_be32
545 #define qemu_get_betl qemu_get_be32
546 #define qemu_put_betls qemu_put_be32s
547 #define qemu_get_betls qemu_get_be32s
548 #endif
549
550 int64_t qemu_ftell(QEMUFile *f);
551 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
552
553 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
554 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
555
556 int register_savevm(const char *idstr,
557 int instance_id,
558 int version_id,
559 SaveStateHandler *save_state,
560 LoadStateHandler *load_state,
561 void *opaque);
562 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
563 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
564
565 void cpu_save(QEMUFile *f, void *opaque);
566 int cpu_load(QEMUFile *f, void *opaque, int version_id);
567
568 void do_savevm(const char *name);
569 void do_loadvm(const char *name);
570 void do_delvm(const char *name);
571 void do_info_snapshots(void);
572
573 /* bottom halves */
574 typedef void QEMUBHFunc(void *opaque);
575
576 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
577 void qemu_bh_schedule(QEMUBH *bh);
578 void qemu_bh_cancel(QEMUBH *bh);
579 void qemu_bh_delete(QEMUBH *bh);
580 int qemu_bh_poll(void);
581
582 /* block.c */
583 typedef struct BlockDriverState BlockDriverState;
584 typedef struct BlockDriver BlockDriver;
585
586 extern BlockDriver bdrv_raw;
587 extern BlockDriver bdrv_host_device;
588 extern BlockDriver bdrv_cow;
589 extern BlockDriver bdrv_qcow;
590 extern BlockDriver bdrv_vmdk;
591 extern BlockDriver bdrv_cloop;
592 extern BlockDriver bdrv_dmg;
593 extern BlockDriver bdrv_bochs;
594 extern BlockDriver bdrv_vpc;
595 extern BlockDriver bdrv_vvfat;
596 extern BlockDriver bdrv_qcow2;
597 extern BlockDriver bdrv_parallels;
598
599 typedef struct BlockDriverInfo {
600 /* in bytes, 0 if irrelevant */
601 int cluster_size;
602 /* offset at which the VM state can be saved (0 if not possible) */
603 int64_t vm_state_offset;
604 } BlockDriverInfo;
605
606 typedef struct QEMUSnapshotInfo {
607 char id_str[128]; /* unique snapshot id */
608 /* the following fields are informative. They are not needed for
609 the consistency of the snapshot */
610 char name[256]; /* user choosen name */
611 uint32_t vm_state_size; /* VM state info size */
612 uint32_t date_sec; /* UTC date of the snapshot */
613 uint32_t date_nsec;
614 uint64_t vm_clock_nsec; /* VM clock relative to boot */
615 } QEMUSnapshotInfo;
616
617 #define BDRV_O_RDONLY 0x0000
618 #define BDRV_O_RDWR 0x0002
619 #define BDRV_O_ACCESS 0x0003
620 #define BDRV_O_CREAT 0x0004 /* create an empty file */
621 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
622 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
623 use a disk image format on top of
624 it (default for
625 bdrv_file_open()) */
626
627 void bdrv_init(void);
628 BlockDriver *bdrv_find_format(const char *format_name);
629 int bdrv_create(BlockDriver *drv,
630 const char *filename, int64_t size_in_sectors,
631 const char *backing_file, int flags);
632 BlockDriverState *bdrv_new(const char *device_name);
633 void bdrv_delete(BlockDriverState *bs);
634 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
635 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
636 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
637 BlockDriver *drv);
638 void bdrv_close(BlockDriverState *bs);
639 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
640 uint8_t *buf, int nb_sectors);
641 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
642 const uint8_t *buf, int nb_sectors);
643 int bdrv_pread(BlockDriverState *bs, int64_t offset,
644 void *buf, int count);
645 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
646 const void *buf, int count);
647 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
648 int64_t bdrv_getlength(BlockDriverState *bs);
649 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
650 int bdrv_commit(BlockDriverState *bs);
651 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
652 /* async block I/O */
653 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
654 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
655
656 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
657 uint8_t *buf, int nb_sectors,
658 BlockDriverCompletionFunc *cb, void *opaque);
659 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
660 const uint8_t *buf, int nb_sectors,
661 BlockDriverCompletionFunc *cb, void *opaque);
662 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
663
664 void qemu_aio_init(void);
665 void qemu_aio_poll(void);
666 void qemu_aio_flush(void);
667 void qemu_aio_wait_start(void);
668 void qemu_aio_wait(void);
669 void qemu_aio_wait_end(void);
670
671 int qemu_key_check(BlockDriverState *bs, const char *name);
672
673 /* Ensure contents are flushed to disk. */
674 void bdrv_flush(BlockDriverState *bs);
675
676 #define BDRV_TYPE_HD 0
677 #define BDRV_TYPE_CDROM 1
678 #define BDRV_TYPE_FLOPPY 2
679 #define BIOS_ATA_TRANSLATION_AUTO 0
680 #define BIOS_ATA_TRANSLATION_NONE 1
681 #define BIOS_ATA_TRANSLATION_LBA 2
682 #define BIOS_ATA_TRANSLATION_LARGE 3
683 #define BIOS_ATA_TRANSLATION_RECHS 4
684
685 void bdrv_set_geometry_hint(BlockDriverState *bs,
686 int cyls, int heads, int secs);
687 void bdrv_set_type_hint(BlockDriverState *bs, int type);
688 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
689 void bdrv_get_geometry_hint(BlockDriverState *bs,
690 int *pcyls, int *pheads, int *psecs);
691 int bdrv_get_type_hint(BlockDriverState *bs);
692 int bdrv_get_translation_hint(BlockDriverState *bs);
693 int bdrv_is_removable(BlockDriverState *bs);
694 int bdrv_is_read_only(BlockDriverState *bs);
695 int bdrv_is_inserted(BlockDriverState *bs);
696 int bdrv_media_changed(BlockDriverState *bs);
697 int bdrv_is_locked(BlockDriverState *bs);
698 void bdrv_set_locked(BlockDriverState *bs, int locked);
699 void bdrv_eject(BlockDriverState *bs, int eject_flag);
700 void bdrv_set_change_cb(BlockDriverState *bs,
701 void (*change_cb)(void *opaque), void *opaque);
702 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
703 void bdrv_info(void);
704 BlockDriverState *bdrv_find(const char *name);
705 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
706 int bdrv_is_encrypted(BlockDriverState *bs);
707 int bdrv_set_key(BlockDriverState *bs, const char *key);
708 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
709 void *opaque);
710 const char *bdrv_get_device_name(BlockDriverState *bs);
711 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
712 const uint8_t *buf, int nb_sectors);
713 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
714
715 void bdrv_get_backing_filename(BlockDriverState *bs,
716 char *filename, int filename_size);
717 int bdrv_snapshot_create(BlockDriverState *bs,
718 QEMUSnapshotInfo *sn_info);
719 int bdrv_snapshot_goto(BlockDriverState *bs,
720 const char *snapshot_id);
721 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
722 int bdrv_snapshot_list(BlockDriverState *bs,
723 QEMUSnapshotInfo **psn_info);
724 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
725
726 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
727 int path_is_absolute(const char *path);
728 void path_combine(char *dest, int dest_size,
729 const char *base_path,
730 const char *filename);
731
732 #ifndef QEMU_TOOL
733
734 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
735 const char *boot_device,
736 DisplayState *ds, const char **fd_filename, int snapshot,
737 const char *kernel_filename, const char *kernel_cmdline,
738 const char *initrd_filename, const char *cpu_model);
739
740 typedef struct QEMUMachine {
741 const char *name;
742 const char *desc;
743 QEMUMachineInitFunc *init;
744 struct QEMUMachine *next;
745 } QEMUMachine;
746
747 int qemu_register_machine(QEMUMachine *m);
748
749 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
750
751 #include "hw/irq.h"
752
753 /* ISA bus */
754
755 extern target_phys_addr_t isa_mem_base;
756
757 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
758 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
759
760 int register_ioport_read(int start, int length, int size,
761 IOPortReadFunc *func, void *opaque);
762 int register_ioport_write(int start, int length, int size,
763 IOPortWriteFunc *func, void *opaque);
764 void isa_unassign_ioport(int start, int length);
765
766 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
767
768 /* PCI bus */
769
770 extern target_phys_addr_t pci_mem_base;
771
772 typedef struct PCIBus PCIBus;
773 typedef struct PCIDevice PCIDevice;
774
775 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
776 uint32_t address, uint32_t data, int len);
777 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
778 uint32_t address, int len);
779 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
780 uint32_t addr, uint32_t size, int type);
781
782 #define PCI_ADDRESS_SPACE_MEM 0x00
783 #define PCI_ADDRESS_SPACE_IO 0x01
784 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
785
786 typedef struct PCIIORegion {
787 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
788 uint32_t size;
789 uint8_t type;
790 PCIMapIORegionFunc *map_func;
791 } PCIIORegion;
792
793 #define PCI_ROM_SLOT 6
794 #define PCI_NUM_REGIONS 7
795
796 #define PCI_DEVICES_MAX 64
797
798 #define PCI_VENDOR_ID 0x00 /* 16 bits */
799 #define PCI_DEVICE_ID 0x02 /* 16 bits */
800 #define PCI_COMMAND 0x04 /* 16 bits */
801 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
802 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
803 #define PCI_CLASS_DEVICE 0x0a /* Device class */
804 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
805 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
806 #define PCI_MIN_GNT 0x3e /* 8 bits */
807 #define PCI_MAX_LAT 0x3f /* 8 bits */
808
809 struct PCIDevice {
810 /* PCI config space */
811 uint8_t config[256];
812
813 /* the following fields are read only */
814 PCIBus *bus;
815 int devfn;
816 char name[64];
817 PCIIORegion io_regions[PCI_NUM_REGIONS];
818
819 /* do not access the following fields */
820 PCIConfigReadFunc *config_read;
821 PCIConfigWriteFunc *config_write;
822 /* ??? This is a PC-specific hack, and should be removed. */
823 int irq_index;
824
825 /* IRQ objects for the INTA-INTD pins. */
826 qemu_irq *irq;
827
828 /* Current IRQ levels. Used internally by the generic PCI code. */
829 int irq_state[4];
830 };
831
832 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
833 int instance_size, int devfn,
834 PCIConfigReadFunc *config_read,
835 PCIConfigWriteFunc *config_write);
836
837 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
838 uint32_t size, int type,
839 PCIMapIORegionFunc *map_func);
840
841 uint32_t pci_default_read_config(PCIDevice *d,
842 uint32_t address, int len);
843 void pci_default_write_config(PCIDevice *d,
844 uint32_t address, uint32_t val, int len);
845 void pci_device_save(PCIDevice *s, QEMUFile *f);
846 int pci_device_load(PCIDevice *s, QEMUFile *f);
847
848 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
849 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
850 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
851 qemu_irq *pic, int devfn_min, int nirq);
852
853 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
854 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
855 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
856 int pci_bus_num(PCIBus *s);
857 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
858
859 void pci_info(void);
860 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
861 pci_map_irq_fn map_irq, const char *name);
862
863 /* prep_pci.c */
864 PCIBus *pci_prep_init(qemu_irq *pic);
865
866 /* apb_pci.c */
867 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
868 qemu_irq *pic);
869
870 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
871
872 /* piix_pci.c */
873 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
874 void i440fx_set_smm(PCIDevice *d, int val);
875 int piix3_init(PCIBus *bus, int devfn);
876 void i440fx_init_memory_mappings(PCIDevice *d);
877
878 int piix4_init(PCIBus *bus, int devfn);
879
880 /* openpic.c */
881 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
882 enum {
883 OPENPIC_OUTPUT_INT = 0, /* IRQ */
884 OPENPIC_OUTPUT_CINT, /* critical IRQ */
885 OPENPIC_OUTPUT_MCK, /* Machine check event */
886 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
887 OPENPIC_OUTPUT_RESET, /* Core reset event */
888 OPENPIC_OUTPUT_NB,
889 };
890 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
891 qemu_irq **irqs, qemu_irq irq_out);
892
893 /* gt64xxx.c */
894 PCIBus *pci_gt64120_init(qemu_irq *pic);
895
896 #ifdef HAS_AUDIO
897 struct soundhw {
898 const char *name;
899 const char *descr;
900 int enabled;
901 int isa;
902 union {
903 int (*init_isa) (AudioState *s, qemu_irq *pic);
904 int (*init_pci) (PCIBus *bus, AudioState *s);
905 } init;
906 };
907
908 extern struct soundhw soundhw[];
909 #endif
910
911 /* vga.c */
912
913 #ifndef TARGET_SPARC
914 #define VGA_RAM_SIZE (8192 * 1024)
915 #else
916 #define VGA_RAM_SIZE (9 * 1024 * 1024)
917 #endif
918
919 struct DisplayState {
920 uint8_t *data;
921 int linesize;
922 int depth;
923 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
924 int width;
925 int height;
926 void *opaque;
927 QEMUTimer *gui_timer;
928
929 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
930 void (*dpy_resize)(struct DisplayState *s, int w, int h);
931 void (*dpy_refresh)(struct DisplayState *s);
932 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
933 int dst_x, int dst_y, int w, int h);
934 void (*dpy_fill)(struct DisplayState *s, int x, int y,
935 int w, int h, uint32_t c);
936 void (*mouse_set)(int x, int y, int on);
937 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
938 uint8_t *image, uint8_t *mask);
939 };
940
941 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
942 {
943 s->dpy_update(s, x, y, w, h);
944 }
945
946 static inline void dpy_resize(DisplayState *s, int w, int h)
947 {
948 s->dpy_resize(s, w, h);
949 }
950
951 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
952 unsigned long vga_ram_offset, int vga_ram_size);
953 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
954 unsigned long vga_ram_offset, int vga_ram_size,
955 unsigned long vga_bios_offset, int vga_bios_size);
956 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
957 unsigned long vga_ram_offset, int vga_ram_size,
958 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
959 int it_shift);
960
961 /* cirrus_vga.c */
962 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
963 unsigned long vga_ram_offset, int vga_ram_size);
964 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
965 unsigned long vga_ram_offset, int vga_ram_size);
966
967 /* vmware_vga.c */
968 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
969 unsigned long vga_ram_offset, int vga_ram_size);
970
971 /* sdl.c */
972 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
973
974 /* cocoa.m */
975 void cocoa_display_init(DisplayState *ds, int full_screen);
976
977 /* vnc.c */
978 void vnc_display_init(DisplayState *ds);
979 void vnc_display_close(DisplayState *ds);
980 int vnc_display_open(DisplayState *ds, const char *display);
981 int vnc_display_password(DisplayState *ds, const char *password);
982 void do_info_vnc(void);
983
984 /* x_keymap.c */
985 extern uint8_t _translate_keycode(const int key);
986
987 /* ide.c */
988 #define MAX_DISKS 4
989
990 extern BlockDriverState *bs_table[MAX_DISKS + 1];
991 extern BlockDriverState *sd_bdrv;
992 extern BlockDriverState *mtd_bdrv;
993
994 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
995 BlockDriverState *hd0, BlockDriverState *hd1);
996 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
997 int secondary_ide_enabled);
998 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
999 qemu_irq *pic);
1000 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1001 qemu_irq *pic);
1002
1003 /* cdrom.c */
1004 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1005 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1006
1007 /* ds1225y.c */
1008 typedef struct ds1225y_t ds1225y_t;
1009 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1010
1011 /* es1370.c */
1012 int es1370_init (PCIBus *bus, AudioState *s);
1013
1014 /* sb16.c */
1015 int SB16_init (AudioState *s, qemu_irq *pic);
1016
1017 /* adlib.c */
1018 int Adlib_init (AudioState *s, qemu_irq *pic);
1019
1020 /* gus.c */
1021 int GUS_init (AudioState *s, qemu_irq *pic);
1022
1023 /* dma.c */
1024 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1025 int DMA_get_channel_mode (int nchan);
1026 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1027 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1028 void DMA_hold_DREQ (int nchan);
1029 void DMA_release_DREQ (int nchan);
1030 void DMA_schedule(int nchan);
1031 void DMA_run (void);
1032 void DMA_init (int high_page_enable);
1033 void DMA_register_channel (int nchan,
1034 DMA_transfer_handler transfer_handler,
1035 void *opaque);
1036 /* fdc.c */
1037 #define MAX_FD 2
1038 extern BlockDriverState *fd_table[MAX_FD];
1039
1040 typedef struct fdctrl_t fdctrl_t;
1041
1042 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1043 target_phys_addr_t io_base,
1044 BlockDriverState **fds);
1045 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1046 BlockDriverState **fds);
1047 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1048
1049 /* eepro100.c */
1050
1051 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1052 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1053 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1054
1055 /* ne2000.c */
1056
1057 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1058 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1059
1060 /* rtl8139.c */
1061
1062 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1063
1064 /* pcnet.c */
1065
1066 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1067 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1068 qemu_irq irq, qemu_irq *reset);
1069
1070 /* mipsnet.c */
1071 void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
1072
1073 /* vmmouse.c */
1074 void *vmmouse_init(void *m);
1075
1076 /* vmport.c */
1077 #ifdef TARGET_I386
1078 void vmport_init(CPUState *env);
1079 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1080 #endif
1081
1082 /* pckbd.c */
1083
1084 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1085 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1086 target_phys_addr_t base, int it_shift);
1087
1088 /* mc146818rtc.c */
1089
1090 typedef struct RTCState RTCState;
1091
1092 RTCState *rtc_init(int base, qemu_irq irq);
1093 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1094 void rtc_set_memory(RTCState *s, int addr, int val);
1095 void rtc_set_date(RTCState *s, const struct tm *tm);
1096
1097 /* serial.c */
1098
1099 typedef struct SerialState SerialState;
1100 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1101 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1102 qemu_irq irq, CharDriverState *chr,
1103 int ioregister);
1104 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1105 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1106 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1107 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1108 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1109 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1110
1111 /* parallel.c */
1112
1113 typedef struct ParallelState ParallelState;
1114 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1115 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1116
1117 /* i8259.c */
1118
1119 typedef struct PicState2 PicState2;
1120 extern PicState2 *isa_pic;
1121 void pic_set_irq(int irq, int level);
1122 void pic_set_irq_new(void *opaque, int irq, int level);
1123 qemu_irq *i8259_init(qemu_irq parent_irq);
1124 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1125 void *alt_irq_opaque);
1126 int pic_read_irq(PicState2 *s);
1127 void pic_update_irq(PicState2 *s);
1128 uint32_t pic_intack_read(PicState2 *s);
1129 void pic_info(void);
1130 void irq_info(void);
1131
1132 /* APIC */
1133 typedef struct IOAPICState IOAPICState;
1134
1135 int apic_init(CPUState *env);
1136 int apic_accept_pic_intr(CPUState *env);
1137 int apic_get_interrupt(CPUState *env);
1138 IOAPICState *ioapic_init(void);
1139 void ioapic_set_irq(void *opaque, int vector, int level);
1140
1141 /* i8254.c */
1142
1143 #define PIT_FREQ 1193182
1144
1145 typedef struct PITState PITState;
1146
1147 PITState *pit_init(int base, qemu_irq irq);
1148 void pit_set_gate(PITState *pit, int channel, int val);
1149 int pit_get_gate(PITState *pit, int channel);
1150 int pit_get_initial_count(PITState *pit, int channel);
1151 int pit_get_mode(PITState *pit, int channel);
1152 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1153
1154 /* jazz_led.c */
1155 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1156
1157 /* pcspk.c */
1158 void pcspk_init(PITState *);
1159 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1160
1161 #include "hw/i2c.h"
1162
1163 #include "hw/smbus.h"
1164
1165 /* acpi.c */
1166 extern int acpi_enabled;
1167 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1168 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1169 void acpi_bios_init(void);
1170
1171 /* Axis ETRAX. */
1172 extern QEMUMachine bareetraxfs_machine;
1173
1174 /* pc.c */
1175 extern QEMUMachine pc_machine;
1176 extern QEMUMachine isapc_machine;
1177 extern int fd_bootchk;
1178
1179 void ioport_set_a20(int enable);
1180 int ioport_get_a20(void);
1181
1182 /* ppc.c */
1183 extern QEMUMachine prep_machine;
1184 extern QEMUMachine core99_machine;
1185 extern QEMUMachine heathrow_machine;
1186 extern QEMUMachine ref405ep_machine;
1187 extern QEMUMachine taihu_machine;
1188
1189 /* mips_r4k.c */
1190 extern QEMUMachine mips_machine;
1191
1192 /* mips_malta.c */
1193 extern QEMUMachine mips_malta_machine;
1194
1195 /* mips_pica61.c */
1196 extern QEMUMachine mips_pica61_machine;
1197
1198 /* mips_mipssim.c */
1199 extern QEMUMachine mips_mipssim_machine;
1200
1201 /* mips_int.c */
1202 extern void cpu_mips_irq_init_cpu(CPUState *env);
1203
1204 /* mips_timer.c */
1205 extern void cpu_mips_clock_init(CPUState *);
1206 extern void cpu_mips_irqctrl_init (void);
1207
1208 /* shix.c */
1209 extern QEMUMachine shix_machine;
1210
1211 /* r2d.c */
1212 extern QEMUMachine r2d_machine;
1213
1214 #ifdef TARGET_PPC
1215 /* PowerPC hardware exceptions management helpers */
1216 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1217 typedef struct clk_setup_t clk_setup_t;
1218 struct clk_setup_t {
1219 clk_setup_cb cb;
1220 void *opaque;
1221 };
1222 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1223 {
1224 if (clk->cb != NULL)
1225 (*clk->cb)(clk->opaque, freq);
1226 }
1227
1228 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1229 /* Embedded PowerPC DCR management */
1230 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1231 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1232 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1233 int (*dcr_write_error)(int dcrn));
1234 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1235 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1236 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1237 /* Embedded PowerPC reset */
1238 void ppc40x_core_reset (CPUState *env);
1239 void ppc40x_chip_reset (CPUState *env);
1240 void ppc40x_system_reset (CPUState *env);
1241 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1242
1243 extern CPUWriteMemoryFunc *PPC_io_write[];
1244 extern CPUReadMemoryFunc *PPC_io_read[];
1245 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1246 #endif
1247
1248 /* sun4m.c */
1249 extern QEMUMachine ss5_machine, ss10_machine;
1250
1251 /* iommu.c */
1252 void *iommu_init(target_phys_addr_t addr);
1253 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1254 uint8_t *buf, int len, int is_write);
1255 static inline void sparc_iommu_memory_read(void *opaque,
1256 target_phys_addr_t addr,
1257 uint8_t *buf, int len)
1258 {
1259 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1260 }
1261
1262 static inline void sparc_iommu_memory_write(void *opaque,
1263 target_phys_addr_t addr,
1264 uint8_t *buf, int len)
1265 {
1266 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1267 }
1268
1269 /* tcx.c */
1270 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1271 unsigned long vram_offset, int vram_size, int width, int height,
1272 int depth);
1273
1274 /* slavio_intctl.c */
1275 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1276 const uint32_t *intbit_to_level,
1277 qemu_irq **irq, qemu_irq **cpu_irq,
1278 qemu_irq **parent_irq, unsigned int cputimer);
1279 void slavio_pic_info(void *opaque);
1280 void slavio_irq_info(void *opaque);
1281
1282 /* loader.c */
1283 int get_image_size(const char *filename);
1284 int load_image(const char *filename, uint8_t *addr);
1285 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1286 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1287 int load_aout(const char *filename, uint8_t *addr);
1288 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1289
1290 /* slavio_timer.c */
1291 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1292 qemu_irq *cpu_irqs);
1293
1294 /* slavio_serial.c */
1295 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1296 CharDriverState *chr1, CharDriverState *chr2);
1297 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1298
1299 /* slavio_misc.c */
1300 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1301 qemu_irq irq);
1302 void slavio_set_power_fail(void *opaque, int power_failing);
1303
1304 /* esp.c */
1305 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1306 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1307 void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1308
1309 /* sparc32_dma.c */
1310 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1311 void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1312 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1313 uint8_t *buf, int len, int do_bswap);
1314 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1315 uint8_t *buf, int len, int do_bswap);
1316 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1317 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1318
1319 /* cs4231.c */
1320 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1321
1322 /* sun4u.c */
1323 extern QEMUMachine sun4u_machine;
1324
1325 /* NVRAM helpers */
1326 typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
1327 typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
1328 typedef struct nvram_t {
1329 void *opaque;
1330 nvram_read_t read_fn;
1331 nvram_write_t write_fn;
1332 } nvram_t;
1333
1334 #include "hw/m48t59.h"
1335
1336 void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
1337 uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
1338 void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
1339 uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
1340 void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
1341 uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
1342 void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
1343 const unsigned char *str, uint32_t max);
1344 int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
1345 void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
1346 uint32_t start, uint32_t count);
1347 int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1348 const unsigned char *arch,
1349 uint32_t RAM_size, int boot_device,
1350 uint32_t kernel_image, uint32_t kernel_size,
1351 const char *cmdline,
1352 uint32_t initrd_image, uint32_t initrd_size,
1353 uint32_t NVRAM_image,
1354 int width, int height, int depth);
1355
1356 /* adb.c */
1357
1358 #define MAX_ADB_DEVICES 16
1359
1360 #define ADB_MAX_OUT_LEN 16
1361
1362 typedef struct ADBDevice ADBDevice;
1363
1364 /* buf = NULL means polling */
1365 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1366 const uint8_t *buf, int len);
1367 typedef int ADBDeviceReset(ADBDevice *d);
1368
1369 struct ADBDevice {
1370 struct ADBBusState *bus;
1371 int devaddr;
1372 int handler;
1373 ADBDeviceRequest *devreq;
1374 ADBDeviceReset *devreset;
1375 void *opaque;
1376 };
1377
1378 typedef struct ADBBusState {
1379 ADBDevice devices[MAX_ADB_DEVICES];
1380 int nb_devices;
1381 int poll_index;
1382 } ADBBusState;
1383
1384 int adb_request(ADBBusState *s, uint8_t *buf_out,
1385 const uint8_t *buf, int len);
1386 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1387
1388 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1389 ADBDeviceRequest *devreq,
1390 ADBDeviceReset *devreset,
1391 void *opaque);
1392 void adb_kbd_init(ADBBusState *bus);
1393 void adb_mouse_init(ADBBusState *bus);
1394
1395 extern ADBBusState adb_bus;
1396
1397 #include "hw/usb.h"
1398
1399 /* usb ports of the VM */
1400
1401 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1402 usb_attachfn attach);
1403
1404 #define VM_USB_HUB_SIZE 8
1405
1406 void do_usb_add(const char *devname);
1407 void do_usb_del(const char *devname);
1408 void usb_info(void);
1409
1410 /* scsi-disk.c */
1411 enum scsi_reason {
1412 SCSI_REASON_DONE, /* Command complete. */
1413 SCSI_REASON_DATA /* Transfer complete, more data required. */
1414 };
1415
1416 typedef struct SCSIDevice SCSIDevice;
1417 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1418 uint32_t arg);
1419
1420 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1421 int tcq,
1422 scsi_completionfn completion,
1423 void *opaque);
1424 void scsi_disk_destroy(SCSIDevice *s);
1425
1426 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1427 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1428 layer the completion routine may be called directly by
1429 scsi_{read,write}_data. */
1430 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1431 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1432 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1433 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1434
1435 /* lsi53c895a.c */
1436 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1437 void *lsi_scsi_init(PCIBus *bus, int devfn);
1438
1439 /* integratorcp.c */
1440 extern QEMUMachine integratorcp_machine;
1441
1442 /* versatilepb.c */
1443 extern QEMUMachine versatilepb_machine;
1444 extern QEMUMachine versatileab_machine;
1445
1446 /* realview.c */
1447 extern QEMUMachine realview_machine;
1448
1449 /* spitz.c */
1450 extern QEMUMachine akitapda_machine;
1451 extern QEMUMachine spitzpda_machine;
1452 extern QEMUMachine borzoipda_machine;
1453 extern QEMUMachine terrierpda_machine;
1454
1455 /* palm.c */
1456 extern QEMUMachine palmte_machine;
1457
1458 /* ps2.c */
1459 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1460 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1461 void ps2_write_mouse(void *, int val);
1462 void ps2_write_keyboard(void *, int val);
1463 uint32_t ps2_read_data(void *);
1464 void ps2_queue(void *, int b);
1465 void ps2_keyboard_set_translation(void *opaque, int mode);
1466 void ps2_mouse_fake_event(void *opaque);
1467
1468 /* smc91c111.c */
1469 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1470
1471 /* pl031.c */
1472 void pl031_init(uint32_t base, qemu_irq irq);
1473
1474 /* pl110.c */
1475 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1476
1477 /* pl011.c */
1478 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1479
1480 /* pl050.c */
1481 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1482
1483 /* pl080.c */
1484 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1485
1486 /* pl181.c */
1487 void pl181_init(uint32_t base, BlockDriverState *bd,
1488 qemu_irq irq0, qemu_irq irq1);
1489
1490 /* pl190.c */
1491 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1492
1493 /* arm-timer.c */
1494 void sp804_init(uint32_t base, qemu_irq irq);
1495 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1496
1497 /* arm_sysctl.c */
1498 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1499
1500 /* arm_gic.c */
1501 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1502
1503 /* arm_boot.c */
1504
1505 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1506 const char *kernel_cmdline, const char *initrd_filename,
1507 int board_id, target_phys_addr_t loader_start);
1508
1509 /* sh7750.c */
1510 struct SH7750State;
1511
1512 struct SH7750State *sh7750_init(CPUState * cpu);
1513
1514 typedef struct {
1515 /* The callback will be triggered if any of the designated lines change */
1516 uint16_t portamask_trigger;
1517 uint16_t portbmask_trigger;
1518 /* Return 0 if no action was taken */
1519 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1520 uint16_t * periph_pdtra,
1521 uint16_t * periph_portdira,
1522 uint16_t * periph_pdtrb,
1523 uint16_t * periph_portdirb);
1524 } sh7750_io_device;
1525
1526 int sh7750_register_io_device(struct SH7750State *s,
1527 sh7750_io_device * device);
1528 /* sh_timer.c */
1529 #define TMU012_FEAT_TOCR (1 << 0)
1530 #define TMU012_FEAT_3CHAN (1 << 1)
1531 #define TMU012_FEAT_EXTCLK (1 << 2)
1532 void tmu012_init(uint32_t base, int feat, uint32_t freq);
1533
1534 /* sh_serial.c */
1535 #define SH_SERIAL_FEAT_SCIF (1 << 0)
1536 void sh_serial_init (target_phys_addr_t base, int feat,
1537 uint32_t freq, CharDriverState *chr);
1538
1539 /* tc58128.c */
1540 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1541
1542 /* NOR flash devices */
1543 #define MAX_PFLASH 4
1544 extern BlockDriverState *pflash_table[MAX_PFLASH];
1545 typedef struct pflash_t pflash_t;
1546
1547 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1548 BlockDriverState *bs,
1549 uint32_t sector_len, int nb_blocs, int width,
1550 uint16_t id0, uint16_t id1,
1551 uint16_t id2, uint16_t id3);
1552
1553 /* nand.c */
1554 struct nand_flash_s;
1555 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1556 void nand_done(struct nand_flash_s *s);
1557 void nand_setpins(struct nand_flash_s *s,
1558 int cle, int ale, int ce, int wp, int gnd);
1559 void nand_getpins(struct nand_flash_s *s, int *rb);
1560 void nand_setio(struct nand_flash_s *s, uint8_t value);
1561 uint8_t nand_getio(struct nand_flash_s *s);
1562
1563 #define NAND_MFR_TOSHIBA 0x98
1564 #define NAND_MFR_SAMSUNG 0xec
1565 #define NAND_MFR_FUJITSU 0x04
1566 #define NAND_MFR_NATIONAL 0x8f
1567 #define NAND_MFR_RENESAS 0x07
1568 #define NAND_MFR_STMICRO 0x20
1569 #define NAND_MFR_HYNIX 0xad
1570 #define NAND_MFR_MICRON 0x2c
1571
1572 /* ecc.c */
1573 struct ecc_state_s {
1574 uint8_t cp; /* Column parity */
1575 uint16_t lp[2]; /* Line parity */
1576 uint16_t count;
1577 };
1578
1579 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1580 void ecc_reset(struct ecc_state_s *s);
1581 void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1582 void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1583
1584 /* GPIO */
1585 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1586
1587 /* ads7846.c */
1588 struct ads7846_state_s;
1589 uint32_t ads7846_read(void *opaque);
1590 void ads7846_write(void *opaque, uint32_t value);
1591 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1592
1593 /* max111x.c */
1594 struct max111x_s;
1595 uint32_t max111x_read(void *opaque);
1596 void max111x_write(void *opaque, uint32_t value);
1597 struct max111x_s *max1110_init(qemu_irq cb);
1598 struct max111x_s *max1111_init(qemu_irq cb);
1599 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1600
1601 /* PCMCIA/Cardbus */
1602
1603 struct pcmcia_socket_s {
1604 qemu_irq irq;
1605 int attached;
1606 const char *slot_string;
1607 const char *card_string;
1608 };
1609
1610 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1611 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1612 void pcmcia_info(void);
1613
1614 struct pcmcia_card_s {
1615 void *state;
1616 struct pcmcia_socket_s *slot;
1617 int (*attach)(void *state);
1618 int (*detach)(void *state);
1619 const uint8_t *cis;
1620 int cis_len;
1621
1622 /* Only valid if attached */
1623 uint8_t (*attr_read)(void *state, uint32_t address);
1624 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1625 uint16_t (*common_read)(void *state, uint32_t address);
1626 void (*common_write)(void *state, uint32_t address, uint16_t value);
1627 uint16_t (*io_read)(void *state, uint32_t address);
1628 void (*io_write)(void *state, uint32_t address, uint16_t value);
1629 };
1630
1631 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1632 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1633 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1634 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1635 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1636 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1637 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1638 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1639 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1640 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1641 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1642 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1643 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1644 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1645 #define CISTPL_END 0xff /* Tuple End */
1646 #define CISTPL_ENDMARK 0xff
1647
1648 /* dscm1xxxx.c */
1649 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1650
1651 /* ptimer.c */
1652 typedef struct ptimer_state ptimer_state;
1653 typedef void (*ptimer_cb)(void *opaque);
1654
1655 ptimer_state *ptimer_init(QEMUBH *bh);
1656 void ptimer_set_period(ptimer_state *s, int64_t period);
1657 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1658 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1659 uint64_t ptimer_get_count(ptimer_state *s);
1660 void ptimer_set_count(ptimer_state *s, uint64_t count);
1661 void ptimer_run(ptimer_state *s, int oneshot);
1662 void ptimer_stop(ptimer_state *s);
1663 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1664 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1665
1666 #include "hw/pxa.h"
1667
1668 #include "hw/omap.h"
1669
1670 /* tsc210x.c */
1671 struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
1672 struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
1673
1674 /* mcf_uart.c */
1675 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1676 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1677 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1678 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1679 CharDriverState *chr);
1680
1681 /* mcf_intc.c */
1682 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1683
1684 /* mcf_fec.c */
1685 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1686
1687 /* mcf5206.c */
1688 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1689
1690 /* an5206.c */
1691 extern QEMUMachine an5206_machine;
1692
1693 /* mcf5208.c */
1694 extern QEMUMachine mcf5208evb_machine;
1695
1696 #include "gdbstub.h"
1697
1698 #endif /* defined(QEMU_TOOL) */
1699
1700 /* monitor.c */
1701 void monitor_init(CharDriverState *hd, int show_banner);
1702 void term_puts(const char *str);
1703 void term_vprintf(const char *fmt, va_list ap);
1704 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1705 void term_print_filename(const char *filename);
1706 void term_flush(void);
1707 void term_print_help(void);
1708 void monitor_readline(const char *prompt, int is_password,
1709 char *buf, int buf_size);
1710
1711 /* readline.c */
1712 typedef void ReadLineFunc(void *opaque, const char *str);
1713
1714 extern int completion_index;
1715 void add_completion(const char *str);
1716 void readline_handle_byte(int ch);
1717 void readline_find_completion(const char *cmdline);
1718 const char *readline_get_history(unsigned int index);
1719 void readline_start(const char *prompt, int is_password,
1720 ReadLineFunc *readline_func, void *opaque);
1721
1722 void kqemu_record_dump(void);
1723
1724 #endif /* VL_H */
Stable branch of Qemu 0.9.1