?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sysret fix - better cpuid support - lcall support for x86_64 - efer access in i386...
[qemu/qemu_0_9_1_stable.git] / target-i386 / helper.c
blobee3f670b5137cc14771f47f9563914b8e4309748
1 /*
2 * i386 helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21
22 //#define DEBUG_PCALL
23
24 #if 0
25 #define raise_exception_err(a, b)\
26 do {\
27 fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
28 (raise_exception_err)(a, b);\
29 } while (0)
30 #endif
31
32 const uint8_t parity_table[256] = {
33 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
34 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
35 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
36 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
37 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
38 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
39 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
40 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
41 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
42 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
43 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
44 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
45 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
46 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
47 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
49 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
50 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
51 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
53 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
54 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
55 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
56 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
57 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
58 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
59 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
61 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
62 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
63 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
65 };
66
67 /* modulo 17 table */
68 const uint8_t rclw_table[32] = {
69 0, 1, 2, 3, 4, 5, 6, 7,
70 8, 9,10,11,12,13,14,15,
71 16, 0, 1, 2, 3, 4, 5, 6,
72 7, 8, 9,10,11,12,13,14,
73 };
74
75 /* modulo 9 table */
76 const uint8_t rclb_table[32] = {
77 0, 1, 2, 3, 4, 5, 6, 7,
78 8, 0, 1, 2, 3, 4, 5, 6,
79 7, 8, 0, 1, 2, 3, 4, 5,
80 6, 7, 8, 0, 1, 2, 3, 4,
81 };
82
83 const CPU86_LDouble f15rk[7] =
84 {
85 0.00000000000000000000L,
86 1.00000000000000000000L,
87 3.14159265358979323851L, /*pi*/
88 0.30102999566398119523L, /*lg2*/
89 0.69314718055994530943L, /*ln2*/
90 1.44269504088896340739L, /*l2e*/
91 3.32192809488736234781L, /*l2t*/
92 };
93
94 /* thread support */
95
96 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
97
98 void cpu_lock(void)
99 {
100 spin_lock(&global_cpu_lock);
101 }
102
103 void cpu_unlock(void)
104 {
105 spin_unlock(&global_cpu_lock);
106 }
107
108 void cpu_loop_exit(void)
109 {
110 /* NOTE: the register at this point must be saved by hand because
111 longjmp restore them */
112 regs_to_env();
113 longjmp(env->jmp_env, 1);
114 }
115
116 /* return non zero if error */
117 static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
118 int selector)
119 {
120 SegmentCache *dt;
121 int index;
122 target_ulong ptr;
123
124 if (selector & 0x4)
125 dt = &env->ldt;
126 else
127 dt = &env->gdt;
128 index = selector & ~7;
129 if ((index + 7) > dt->limit)
130 return -1;
131 ptr = dt->base + index;
132 *e1_ptr = ldl_kernel(ptr);
133 *e2_ptr = ldl_kernel(ptr + 4);
134 return 0;
135 }
136
137 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
138 {
139 unsigned int limit;
140 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
141 if (e2 & DESC_G_MASK)
142 limit = (limit << 12) | 0xfff;
143 return limit;
144 }
145
146 static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
147 {
148 return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
149 }
150
151 static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
152 {
153 sc->base = get_seg_base(e1, e2);
154 sc->limit = get_seg_limit(e1, e2);
155 sc->flags = e2;
156 }
157
158 /* init the segment cache in vm86 mode. */
159 static inline void load_seg_vm(int seg, int selector)
160 {
161 selector &= 0xffff;
162 cpu_x86_load_seg_cache(env, seg, selector,
163 (selector << 4), 0xffff, 0);
164 }
165
166 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
167 uint32_t *esp_ptr, int dpl)
168 {
169 int type, index, shift;
170
171 #if 0
172 {
173 int i;
174 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
175 for(i=0;i<env->tr.limit;i++) {
176 printf("%02x ", env->tr.base[i]);
177 if ((i & 7) == 7) printf("\n");
178 }
179 printf("\n");
180 }
181 #endif
182
183 if (!(env->tr.flags & DESC_P_MASK))
184 cpu_abort(env, "invalid tss");
185 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
186 if ((type & 7) != 1)
187 cpu_abort(env, "invalid tss type");
188 shift = type >> 3;
189 index = (dpl * 4 + 2) << shift;
190 if (index + (4 << shift) - 1 > env->tr.limit)
191 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
192 if (shift == 0) {
193 *esp_ptr = lduw_kernel(env->tr.base + index);
194 *ss_ptr = lduw_kernel(env->tr.base + index + 2);
195 } else {
196 *esp_ptr = ldl_kernel(env->tr.base + index);
197 *ss_ptr = lduw_kernel(env->tr.base + index + 4);
198 }
199 }
200
201 /* XXX: merge with load_seg() */
202 static void tss_load_seg(int seg_reg, int selector)
203 {
204 uint32_t e1, e2;
205 int rpl, dpl, cpl;
206
207 if ((selector & 0xfffc) != 0) {
208 if (load_segment(&e1, &e2, selector) != 0)
209 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
210 if (!(e2 & DESC_S_MASK))
211 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
212 rpl = selector & 3;
213 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
214 cpl = env->hflags & HF_CPL_MASK;
215 if (seg_reg == R_CS) {
216 if (!(e2 & DESC_CS_MASK))
217 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
218 if (dpl != rpl)
219 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
220 if ((e2 & DESC_C_MASK) && dpl > rpl)
221 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
222
223 } else if (seg_reg == R_SS) {
224 /* SS must be writable data */
225 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
226 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
227 if (dpl != cpl || dpl != rpl)
228 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
229 } else {
230 /* not readable code */
231 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
232 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
233 /* if data or non conforming code, checks the rights */
234 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
235 if (dpl < cpl || dpl < rpl)
236 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
237 }
238 }
239 if (!(e2 & DESC_P_MASK))
240 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
241 cpu_x86_load_seg_cache(env, seg_reg, selector,
242 get_seg_base(e1, e2),
243 get_seg_limit(e1, e2),
244 e2);
245 } else {
246 if (seg_reg == R_SS || seg_reg == R_CS)
247 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
248 }
249 }
250
251 #define SWITCH_TSS_JMP 0
252 #define SWITCH_TSS_IRET 1
253 #define SWITCH_TSS_CALL 2
254
255 /* XXX: restore CPU state in registers (PowerPC case) */
256 static void switch_tss(int tss_selector,
257 uint32_t e1, uint32_t e2, int source,
258 uint32_t next_eip)
259 {
260 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
261 target_ulong tss_base;
262 uint32_t new_regs[8], new_segs[6];
263 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
264 uint32_t old_eflags, eflags_mask;
265 SegmentCache *dt;
266 int index;
267 target_ulong ptr;
268
269 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
270 #ifdef DEBUG_PCALL
271 if (loglevel & CPU_LOG_PCALL)
272 fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
273 #endif
274
275 /* if task gate, we read the TSS segment and we load it */
276 if (type == 5) {
277 if (!(e2 & DESC_P_MASK))
278 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
279 tss_selector = e1 >> 16;
280 if (tss_selector & 4)
281 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
282 if (load_segment(&e1, &e2, tss_selector) != 0)
283 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
284 if (e2 & DESC_S_MASK)
285 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
286 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
287 if ((type & 7) != 1)
288 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
289 }
290
291 if (!(e2 & DESC_P_MASK))
292 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
293
294 if (type & 8)
295 tss_limit_max = 103;
296 else
297 tss_limit_max = 43;
298 tss_limit = get_seg_limit(e1, e2);
299 tss_base = get_seg_base(e1, e2);
300 if ((tss_selector & 4) != 0 ||
301 tss_limit < tss_limit_max)
302 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
303 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
304 if (old_type & 8)
305 old_tss_limit_max = 103;
306 else
307 old_tss_limit_max = 43;
308
309 /* read all the registers from the new TSS */
310 if (type & 8) {
311 /* 32 bit */
312 new_cr3 = ldl_kernel(tss_base + 0x1c);
313 new_eip = ldl_kernel(tss_base + 0x20);
314 new_eflags = ldl_kernel(tss_base + 0x24);
315 for(i = 0; i < 8; i++)
316 new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
317 for(i = 0; i < 6; i++)
318 new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
319 new_ldt = lduw_kernel(tss_base + 0x60);
320 new_trap = ldl_kernel(tss_base + 0x64);
321 } else {
322 /* 16 bit */
323 new_cr3 = 0;
324 new_eip = lduw_kernel(tss_base + 0x0e);
325 new_eflags = lduw_kernel(tss_base + 0x10);
326 for(i = 0; i < 8; i++)
327 new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000;
328 for(i = 0; i < 4; i++)
329 new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
330 new_ldt = lduw_kernel(tss_base + 0x2a);
331 new_segs[R_FS] = 0;
332 new_segs[R_GS] = 0;
333 new_trap = 0;
334 }
335
336 /* NOTE: we must avoid memory exceptions during the task switch,
337 so we make dummy accesses before */
338 /* XXX: it can still fail in some cases, so a bigger hack is
339 necessary to valid the TLB after having done the accesses */
340
341 v1 = ldub_kernel(env->tr.base);
342 v2 = ldub(env->tr.base + old_tss_limit_max);
343 stb_kernel(env->tr.base, v1);
344 stb_kernel(env->tr.base + old_tss_limit_max, v2);
345
346 /* clear busy bit (it is restartable) */
347 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
348 target_ulong ptr;
349 uint32_t e2;
350 ptr = env->gdt.base + (env->tr.selector & ~7);
351 e2 = ldl_kernel(ptr + 4);
352 e2 &= ~DESC_TSS_BUSY_MASK;
353 stl_kernel(ptr + 4, e2);
354 }
355 old_eflags = compute_eflags();
356 if (source == SWITCH_TSS_IRET)
357 old_eflags &= ~NT_MASK;
358
359 /* save the current state in the old TSS */
360 if (type & 8) {
361 /* 32 bit */
362 stl_kernel(env->tr.base + 0x20, next_eip);
363 stl_kernel(env->tr.base + 0x24, old_eflags);
364 stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
365 stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
366 stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
367 stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
368 stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
369 stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
370 stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
371 stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
372 for(i = 0; i < 6; i++)
373 stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
374 } else {
375 /* 16 bit */
376 stw_kernel(env->tr.base + 0x0e, next_eip);
377 stw_kernel(env->tr.base + 0x10, old_eflags);
378 stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
379 stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
380 stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
381 stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
382 stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
383 stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
384 stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
385 stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
386 for(i = 0; i < 4; i++)
387 stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
388 }
389
390 /* now if an exception occurs, it will occurs in the next task
391 context */
392
393 if (source == SWITCH_TSS_CALL) {
394 stw_kernel(tss_base, env->tr.selector);
395 new_eflags |= NT_MASK;
396 }
397
398 /* set busy bit */
399 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
400 target_ulong ptr;
401 uint32_t e2;
402 ptr = env->gdt.base + (tss_selector & ~7);
403 e2 = ldl_kernel(ptr + 4);
404 e2 |= DESC_TSS_BUSY_MASK;
405 stl_kernel(ptr + 4, e2);
406 }
407
408 /* set the new CPU state */
409 /* from this point, any exception which occurs can give problems */
410 env->cr[0] |= CR0_TS_MASK;
411 env->hflags |= HF_TS_MASK;
412 env->tr.selector = tss_selector;
413 env->tr.base = tss_base;
414 env->tr.limit = tss_limit;
415 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
416
417 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
418 cpu_x86_update_cr3(env, new_cr3);
419 }
420
421 /* load all registers without an exception, then reload them with
422 possible exception */
423 env->eip = new_eip;
424 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
425 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
426 if (!(type & 8))
427 eflags_mask &= 0xffff;
428 load_eflags(new_eflags, eflags_mask);
429 /* XXX: what to do in 16 bit case ? */
430 EAX = new_regs[0];
431 ECX = new_regs[1];
432 EDX = new_regs[2];
433 EBX = new_regs[3];
434 ESP = new_regs[4];
435 EBP = new_regs[5];
436 ESI = new_regs[6];
437 EDI = new_regs[7];
438 if (new_eflags & VM_MASK) {
439 for(i = 0; i < 6; i++)
440 load_seg_vm(i, new_segs[i]);
441 /* in vm86, CPL is always 3 */
442 cpu_x86_set_cpl(env, 3);
443 } else {
444 /* CPL is set the RPL of CS */
445 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
446 /* first just selectors as the rest may trigger exceptions */
447 for(i = 0; i < 6; i++)
448 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
449 }
450
451 env->ldt.selector = new_ldt & ~4;
452 env->ldt.base = 0;
453 env->ldt.limit = 0;
454 env->ldt.flags = 0;
455
456 /* load the LDT */
457 if (new_ldt & 4)
458 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
459
460 if ((new_ldt & 0xfffc) != 0) {
461 dt = &env->gdt;
462 index = new_ldt & ~7;
463 if ((index + 7) > dt->limit)
464 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
465 ptr = dt->base + index;
466 e1 = ldl_kernel(ptr);
467 e2 = ldl_kernel(ptr + 4);
468 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
469 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
470 if (!(e2 & DESC_P_MASK))
471 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
472 load_seg_cache_raw_dt(&env->ldt, e1, e2);
473 }
474
475 /* load the segments */
476 if (!(new_eflags & VM_MASK)) {
477 tss_load_seg(R_CS, new_segs[R_CS]);
478 tss_load_seg(R_SS, new_segs[R_SS]);
479 tss_load_seg(R_ES, new_segs[R_ES]);
480 tss_load_seg(R_DS, new_segs[R_DS]);
481 tss_load_seg(R_FS, new_segs[R_FS]);
482 tss_load_seg(R_GS, new_segs[R_GS]);
483 }
484
485 /* check that EIP is in the CS segment limits */
486 if (new_eip > env->segs[R_CS].limit) {
487 /* XXX: different exception if CALL ? */
488 raise_exception_err(EXCP0D_GPF, 0);
489 }
490 }
491
492 /* check if Port I/O is allowed in TSS */
493 static inline void check_io(int addr, int size)
494 {
495 int io_offset, val, mask;
496
497 /* TSS must be a valid 32 bit one */
498 if (!(env->tr.flags & DESC_P_MASK) ||
499 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
500 env->tr.limit < 103)
501 goto fail;
502 io_offset = lduw_kernel(env->tr.base + 0x66);
503 io_offset += (addr >> 3);
504 /* Note: the check needs two bytes */
505 if ((io_offset + 1) > env->tr.limit)
506 goto fail;
507 val = lduw_kernel(env->tr.base + io_offset);
508 val >>= (addr & 7);
509 mask = (1 << size) - 1;
510 /* all bits must be zero to allow the I/O */
511 if ((val & mask) != 0) {
512 fail:
513 raise_exception_err(EXCP0D_GPF, 0);
514 }
515 }
516
517 void check_iob_T0(void)
518 {
519 check_io(T0, 1);
520 }
521
522 void check_iow_T0(void)
523 {
524 check_io(T0, 2);
525 }
526
527 void check_iol_T0(void)
528 {
529 check_io(T0, 4);
530 }
531
532 void check_iob_DX(void)
533 {
534 check_io(EDX & 0xffff, 1);
535 }
536
537 void check_iow_DX(void)
538 {
539 check_io(EDX & 0xffff, 2);
540 }
541
542 void check_iol_DX(void)
543 {
544 check_io(EDX & 0xffff, 4);
545 }
546
547 static inline unsigned int get_sp_mask(unsigned int e2)
548 {
549 if (e2 & DESC_B_MASK)
550 return 0xffffffff;
551 else
552 return 0xffff;
553 }
554
555 /* XXX: add a is_user flag to have proper security support */
556 #define PUSHW(ssp, sp, sp_mask, val)\
557 {\
558 sp -= 2;\
559 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
560 }
561
562 #define PUSHL(ssp, sp, sp_mask, val)\
563 {\
564 sp -= 4;\
565 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
566 }
567
568 #define POPW(ssp, sp, sp_mask, val)\
569 {\
570 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
571 sp += 2;\
572 }
573
574 #define POPL(ssp, sp, sp_mask, val)\
575 {\
576 val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
577 sp += 4;\
578 }
579
580 /* protected mode interrupt */
581 static void do_interrupt_protected(int intno, int is_int, int error_code,
582 unsigned int next_eip, int is_hw)
583 {
584 SegmentCache *dt;
585 target_ulong ptr, ssp;
586 int type, dpl, selector, ss_dpl, cpl, sp_mask;
587 int has_error_code, new_stack, shift;
588 uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
589 uint32_t old_eip;
590
591 has_error_code = 0;
592 if (!is_int && !is_hw) {
593 switch(intno) {
594 case 8:
595 case 10:
596 case 11:
597 case 12:
598 case 13:
599 case 14:
600 case 17:
601 has_error_code = 1;
602 break;
603 }
604 }
605 if (is_int)
606 old_eip = next_eip;
607 else
608 old_eip = env->eip;
609
610 dt = &env->idt;
611 if (intno * 8 + 7 > dt->limit)
612 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
613 ptr = dt->base + intno * 8;
614 e1 = ldl_kernel(ptr);
615 e2 = ldl_kernel(ptr + 4);
616 /* check gate type */
617 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
618 switch(type) {
619 case 5: /* task gate */
620 /* must do that check here to return the correct error code */
621 if (!(e2 & DESC_P_MASK))
622 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
623 switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
624 if (has_error_code) {
625 int mask;
626 /* push the error code */
627 shift = (env->segs[R_CS].flags >> DESC_B_SHIFT) & 1;
628 if (env->segs[R_SS].flags & DESC_B_MASK)
629 mask = 0xffffffff;
630 else
631 mask = 0xffff;
632 esp = (ESP - (2 << shift)) & mask;
633 ssp = env->segs[R_SS].base + esp;
634 if (shift)
635 stl_kernel(ssp, error_code);
636 else
637 stw_kernel(ssp, error_code);
638 ESP = (esp & mask) | (ESP & ~mask);
639 }
640 return;
641 case 6: /* 286 interrupt gate */
642 case 7: /* 286 trap gate */
643 case 14: /* 386 interrupt gate */
644 case 15: /* 386 trap gate */
645 break;
646 default:
647 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
648 break;
649 }
650 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
651 cpl = env->hflags & HF_CPL_MASK;
652 /* check privledge if software int */
653 if (is_int && dpl < cpl)
654 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
655 /* check valid bit */
656 if (!(e2 & DESC_P_MASK))
657 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
658 selector = e1 >> 16;
659 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
660 if ((selector & 0xfffc) == 0)
661 raise_exception_err(EXCP0D_GPF, 0);
662
663 if (load_segment(&e1, &e2, selector) != 0)
664 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
665 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
666 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
667 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
668 if (dpl > cpl)
669 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
670 if (!(e2 & DESC_P_MASK))
671 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
672 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
673 /* to inner priviledge */
674 get_ss_esp_from_tss(&ss, &esp, dpl);
675 if ((ss & 0xfffc) == 0)
676 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
677 if ((ss & 3) != dpl)
678 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
679 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
680 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
681 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
682 if (ss_dpl != dpl)
683 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
684 if (!(ss_e2 & DESC_S_MASK) ||
685 (ss_e2 & DESC_CS_MASK) ||
686 !(ss_e2 & DESC_W_MASK))
687 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
688 if (!(ss_e2 & DESC_P_MASK))
689 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
690 new_stack = 1;
691 sp_mask = get_sp_mask(ss_e2);
692 ssp = get_seg_base(ss_e1, ss_e2);
693 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
694 /* to same priviledge */
695 if (env->eflags & VM_MASK)
696 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
697 new_stack = 0;
698 sp_mask = get_sp_mask(env->segs[R_SS].flags);
699 ssp = env->segs[R_SS].base;
700 esp = ESP;
701 dpl = cpl;
702 } else {
703 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
704 new_stack = 0; /* avoid warning */
705 sp_mask = 0; /* avoid warning */
706 ssp = 0; /* avoid warning */
707 esp = 0; /* avoid warning */
708 }
709
710 shift = type >> 3;
711
712 #if 0
713 /* XXX: check that enough room is available */
714 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
715 if (env->eflags & VM_MASK)
716 push_size += 8;
717 push_size <<= shift;
718 #endif
719 if (shift == 1) {
720 if (new_stack) {
721 if (env->eflags & VM_MASK) {
722 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
723 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
724 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
725 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
726 }
727 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
728 PUSHL(ssp, esp, sp_mask, ESP);
729 }
730 PUSHL(ssp, esp, sp_mask, compute_eflags());
731 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
732 PUSHL(ssp, esp, sp_mask, old_eip);
733 if (has_error_code) {
734 PUSHL(ssp, esp, sp_mask, error_code);
735 }
736 } else {
737 if (new_stack) {
738 if (env->eflags & VM_MASK) {
739 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
740 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
741 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
742 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
743 }
744 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
745 PUSHW(ssp, esp, sp_mask, ESP);
746 }
747 PUSHW(ssp, esp, sp_mask, compute_eflags());
748 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
749 PUSHW(ssp, esp, sp_mask, old_eip);
750 if (has_error_code) {
751 PUSHW(ssp, esp, sp_mask, error_code);
752 }
753 }
754
755 if (new_stack) {
756 if (env->eflags & VM_MASK) {
757 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
758 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
759 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
760 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
761 }
762 ss = (ss & ~3) | dpl;
763 cpu_x86_load_seg_cache(env, R_SS, ss,
764 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
765 }
766 ESP = (ESP & ~sp_mask) | (esp & sp_mask);
767
768 selector = (selector & ~3) | dpl;
769 cpu_x86_load_seg_cache(env, R_CS, selector,
770 get_seg_base(e1, e2),
771 get_seg_limit(e1, e2),
772 e2);
773 cpu_x86_set_cpl(env, dpl);
774 env->eip = offset;
775
776 /* interrupt gate clear IF mask */
777 if ((type & 1) == 0) {
778 env->eflags &= ~IF_MASK;
779 }
780 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
781 }
782
783 #ifdef TARGET_X86_64
784
785 #define PUSHQ(sp, val)\
786 {\
787 sp -= 8;\
788 stq_kernel(sp, (val));\
789 }
790
791 #define POPQ(sp, val)\
792 {\
793 val = ldq_kernel(sp);\
794 sp += 8;\
795 }
796
797 static inline target_ulong get_rsp_from_tss(int level)
798 {
799 int index;
800
801 #if 0
802 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
803 env->tr.base, env->tr.limit);
804 #endif
805
806 if (!(env->tr.flags & DESC_P_MASK))
807 cpu_abort(env, "invalid tss");
808 index = 8 * level + 4;
809 if ((index + 7) > env->tr.limit)
810 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
811 return ldq_kernel(env->tr.base + index);
812 }
813
814 /* 64 bit interrupt */
815 static void do_interrupt64(int intno, int is_int, int error_code,
816 target_ulong next_eip, int is_hw)
817 {
818 SegmentCache *dt;
819 target_ulong ptr;
820 int type, dpl, selector, cpl, ist;
821 int has_error_code, new_stack;
822 uint32_t e1, e2, e3, ss;
823 target_ulong old_eip, esp, offset;
824
825 has_error_code = 0;
826 if (!is_int && !is_hw) {
827 switch(intno) {
828 case 8:
829 case 10:
830 case 11:
831 case 12:
832 case 13:
833 case 14:
834 case 17:
835 has_error_code = 1;
836 break;
837 }
838 }
839 if (is_int)
840 old_eip = next_eip;
841 else
842 old_eip = env->eip;
843
844 dt = &env->idt;
845 if (intno * 16 + 15 > dt->limit)
846 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
847 ptr = dt->base + intno * 16;
848 e1 = ldl_kernel(ptr);
849 e2 = ldl_kernel(ptr + 4);
850 e3 = ldl_kernel(ptr + 8);
851 /* check gate type */
852 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
853 switch(type) {
854 case 14: /* 386 interrupt gate */
855 case 15: /* 386 trap gate */
856 break;
857 default:
858 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
859 break;
860 }
861 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
862 cpl = env->hflags & HF_CPL_MASK;
863 /* check privledge if software int */
864 if (is_int && dpl < cpl)
865 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
866 /* check valid bit */
867 if (!(e2 & DESC_P_MASK))
868 raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
869 selector = e1 >> 16;
870 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
871 ist = e2 & 7;
872 if ((selector & 0xfffc) == 0)
873 raise_exception_err(EXCP0D_GPF, 0);
874
875 if (load_segment(&e1, &e2, selector) != 0)
876 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
877 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
878 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
879 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
880 if (dpl > cpl)
881 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
882 if (!(e2 & DESC_P_MASK))
883 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
884 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK))
885 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
886 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
887 /* to inner priviledge */
888 if (ist != 0)
889 esp = get_rsp_from_tss(ist + 3);
890 else
891 esp = get_rsp_from_tss(dpl);
892 ss = 0;
893 new_stack = 1;
894 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
895 /* to same priviledge */
896 if (env->eflags & VM_MASK)
897 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
898 new_stack = 0;
899 esp = ESP & ~0xf; /* align stack */
900 dpl = cpl;
901 } else {
902 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
903 new_stack = 0; /* avoid warning */
904 esp = 0; /* avoid warning */
905 }
906
907 PUSHQ(esp, env->segs[R_SS].selector);
908 PUSHQ(esp, ESP);
909 PUSHQ(esp, compute_eflags());
910 PUSHQ(esp, env->segs[R_CS].selector);
911 PUSHQ(esp, old_eip);
912 if (has_error_code) {
913 PUSHQ(esp, error_code);
914 }
915
916 if (new_stack) {
917 ss = 0 | dpl;
918 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
919 }
920 ESP = esp;
921
922 selector = (selector & ~3) | dpl;
923 cpu_x86_load_seg_cache(env, R_CS, selector,
924 get_seg_base(e1, e2),
925 get_seg_limit(e1, e2),
926 e2);
927 cpu_x86_set_cpl(env, dpl);
928 env->eip = offset;
929
930 /* interrupt gate clear IF mask */
931 if ((type & 1) == 0) {
932 env->eflags &= ~IF_MASK;
933 }
934 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
935 }
936 #endif
937
938 void helper_syscall(int next_eip_addend)
939 {
940 int selector;
941
942 if (!(env->efer & MSR_EFER_SCE)) {
943 raise_exception_err(EXCP06_ILLOP, 0);
944 }
945 selector = (env->star >> 32) & 0xffff;
946 #ifdef TARGET_X86_64
947 if (env->hflags & HF_LMA_MASK) {
948 ECX = env->eip + next_eip_addend;
949 env->regs[11] = compute_eflags();
950
951 cpu_x86_set_cpl(env, 0);
952 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
953 0, 0xffffffff,
954 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
955 DESC_S_MASK |
956 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
957 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
958 0, 0xffffffff,
959 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
960 DESC_S_MASK |
961 DESC_W_MASK | DESC_A_MASK);
962 env->eflags &= ~env->fmask;
963 if (env->hflags & HF_CS64_MASK)
964 env->eip = env->lstar;
965 else
966 env->eip = env->cstar;
967 } else
968 #endif
969 {
970 ECX = (uint32_t)(env->eip + next_eip_addend);
971
972 cpu_x86_set_cpl(env, 0);
973 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
974 0, 0xffffffff,
975 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
976 DESC_S_MASK |
977 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
978 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
979 0, 0xffffffff,
980 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
981 DESC_S_MASK |
982 DESC_W_MASK | DESC_A_MASK);
983 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
984 env->eip = (uint32_t)env->star;
985 }
986 }
987
988 void helper_sysret(int dflag)
989 {
990 int cpl, selector;
991
992 if (!(env->efer & MSR_EFER_SCE)) {
993 raise_exception_err(EXCP06_ILLOP, 0);
994 }
995 cpl = env->hflags & HF_CPL_MASK;
996 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
997 raise_exception_err(EXCP0D_GPF, 0);
998 }
999 selector = (env->star >> 48) & 0xffff;
1000 #ifdef TARGET_X86_64
1001 if (env->hflags & HF_LMA_MASK) {
1002 if (dflag == 2) {
1003 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1004 0, 0xffffffff,
1005 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1006 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1007 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1008 DESC_L_MASK);
1009 env->eip = ECX;
1010 } else {
1011 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1012 0, 0xffffffff,
1013 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1014 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1015 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1016 env->eip = (uint32_t)ECX;
1017 }
1018 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1019 0, 0xffffffff,
1020 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1021 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1022 DESC_W_MASK | DESC_A_MASK);
1023 load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK |
1024 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK);
1025 cpu_x86_set_cpl(env, 3);
1026 } else
1027 #endif
1028 {
1029 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1030 0, 0xffffffff,
1031 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1032 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1033 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1034 env->eip = (uint32_t)ECX;
1035 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1036 0, 0xffffffff,
1037 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1038 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1039 DESC_W_MASK | DESC_A_MASK);
1040 env->eflags |= IF_MASK;
1041 cpu_x86_set_cpl(env, 3);
1042 }
1043 #ifdef USE_KQEMU
1044 if (kqemu_is_ok(env)) {
1045 if (env->hflags & HF_LMA_MASK)
1046 CC_OP = CC_OP_EFLAGS;
1047 env->exception_index = -1;
1048 cpu_loop_exit();
1049 }
1050 #endif
1051 }
1052
1053 /* real mode interrupt */
1054 static void do_interrupt_real(int intno, int is_int, int error_code,
1055 unsigned int next_eip)
1056 {
1057 SegmentCache *dt;
1058 target_ulong ptr, ssp;
1059 int selector;
1060 uint32_t offset, esp;
1061 uint32_t old_cs, old_eip;
1062
1063 /* real mode (simpler !) */
1064 dt = &env->idt;
1065 if (intno * 4 + 3 > dt->limit)
1066 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1067 ptr = dt->base + intno * 4;
1068 offset = lduw_kernel(ptr);
1069 selector = lduw_kernel(ptr + 2);
1070 esp = ESP;
1071 ssp = env->segs[R_SS].base;
1072 if (is_int)
1073 old_eip = next_eip;
1074 else
1075 old_eip = env->eip;
1076 old_cs = env->segs[R_CS].selector;
1077 /* XXX: use SS segment size ? */
1078 PUSHW(ssp, esp, 0xffff, compute_eflags());
1079 PUSHW(ssp, esp, 0xffff, old_cs);
1080 PUSHW(ssp, esp, 0xffff, old_eip);
1081
1082 /* update processor state */
1083 ESP = (ESP & ~0xffff) | (esp & 0xffff);
1084 env->eip = offset;
1085 env->segs[R_CS].selector = selector;
1086 env->segs[R_CS].base = (selector << 4);
1087 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1088 }
1089
1090 /* fake user mode interrupt */
1091 void do_interrupt_user(int intno, int is_int, int error_code,
1092 target_ulong next_eip)
1093 {
1094 SegmentCache *dt;
1095 target_ulong ptr;
1096 int dpl, cpl;
1097 uint32_t e2;
1098
1099 dt = &env->idt;
1100 ptr = dt->base + (intno * 8);
1101 e2 = ldl_kernel(ptr + 4);
1102
1103 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1104 cpl = env->hflags & HF_CPL_MASK;
1105 /* check privledge if software int */
1106 if (is_int && dpl < cpl)
1107 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1108
1109 /* Since we emulate only user space, we cannot do more than
1110 exiting the emulation with the suitable exception and error
1111 code */
1112 if (is_int)
1113 EIP = next_eip;
1114 }
1115
1116 /*
1117 * Begin execution of an interruption. is_int is TRUE if coming from
1118 * the int instruction. next_eip is the EIP value AFTER the interrupt
1119 * instruction. It is only relevant if is_int is TRUE.
1120 */
1121 void do_interrupt(int intno, int is_int, int error_code,
1122 target_ulong next_eip, int is_hw)
1123 {
1124 #ifdef DEBUG_PCALL
1125 if (loglevel & (CPU_LOG_PCALL | CPU_LOG_INT)) {
1126 if ((env->cr[0] & CR0_PE_MASK)) {
1127 static int count;
1128 fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1129 count, intno, error_code, is_int,
1130 env->hflags & HF_CPL_MASK,
1131 env->segs[R_CS].selector, EIP,
1132 (int)env->segs[R_CS].base + EIP,
1133 env->segs[R_SS].selector, ESP);
1134 if (intno == 0x0e) {
1135 fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1136 } else {
1137 fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1138 }
1139 fprintf(logfile, "\n");
1140 #if 0
1141 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1142 {
1143 int i;
1144 uint8_t *ptr;
1145 fprintf(logfile, " code=");
1146 ptr = env->segs[R_CS].base + env->eip;
1147 for(i = 0; i < 16; i++) {
1148 fprintf(logfile, " %02x", ldub(ptr + i));
1149 }
1150 fprintf(logfile, "\n");
1151 }
1152 #endif
1153 count++;
1154 }
1155 }
1156 #endif
1157 if (env->cr[0] & CR0_PE_MASK) {
1158 #if TARGET_X86_64
1159 if (env->hflags & HF_LMA_MASK) {
1160 do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1161 } else
1162 #endif
1163 {
1164 do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1165 }
1166 } else {
1167 do_interrupt_real(intno, is_int, error_code, next_eip);
1168 }
1169 }
1170
1171 /*
1172 * Signal an interruption. It is executed in the main CPU loop.
1173 * is_int is TRUE if coming from the int instruction. next_eip is the
1174 * EIP value AFTER the interrupt instruction. It is only relevant if
1175 * is_int is TRUE.
1176 */
1177 void raise_interrupt(int intno, int is_int, int error_code,
1178 int next_eip_addend)
1179 {
1180 env->exception_index = intno;
1181 env->error_code = error_code;
1182 env->exception_is_int = is_int;
1183 env->exception_next_eip = env->eip + next_eip_addend;
1184 cpu_loop_exit();
1185 }
1186
1187 /* same as raise_exception_err, but do not restore global registers */
1188 static void raise_exception_err_norestore(int exception_index, int error_code)
1189 {
1190 env->exception_index = exception_index;
1191 env->error_code = error_code;
1192 env->exception_is_int = 0;
1193 env->exception_next_eip = 0;
1194 longjmp(env->jmp_env, 1);
1195 }
1196
1197 /* shortcuts to generate exceptions */
1198
1199 void (raise_exception_err)(int exception_index, int error_code)
1200 {
1201 raise_interrupt(exception_index, 0, error_code, 0);
1202 }
1203
1204 void raise_exception(int exception_index)
1205 {
1206 raise_interrupt(exception_index, 0, 0, 0);
1207 }
1208
1209 #ifdef BUGGY_GCC_DIV64
1210 /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1211 call it from another function */
1212 uint32_t div32(uint32_t *q_ptr, uint64_t num, uint32_t den)
1213 {
1214 *q_ptr = num / den;
1215 return num % den;
1216 }
1217
1218 int32_t idiv32(int32_t *q_ptr, int64_t num, int32_t den)
1219 {
1220 *q_ptr = num / den;
1221 return num % den;
1222 }
1223 #endif
1224
1225 void helper_divl_EAX_T0(void)
1226 {
1227 unsigned int den, q, r;
1228 uint64_t num;
1229
1230 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1231 den = T0;
1232 if (den == 0) {
1233 raise_exception(EXCP00_DIVZ);
1234 }
1235 #ifdef BUGGY_GCC_DIV64
1236 r = div32(&q, num, den);
1237 #else
1238 q = (num / den);
1239 r = (num % den);
1240 #endif
1241 EAX = (uint32_t)q;
1242 EDX = (uint32_t)r;
1243 }
1244
1245 void helper_idivl_EAX_T0(void)
1246 {
1247 int den, q, r;
1248 int64_t num;
1249
1250 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1251 den = T0;
1252 if (den == 0) {
1253 raise_exception(EXCP00_DIVZ);
1254 }
1255 #ifdef BUGGY_GCC_DIV64
1256 r = idiv32(&q, num, den);
1257 #else
1258 q = (num / den);
1259 r = (num % den);
1260 #endif
1261 EAX = (uint32_t)q;
1262 EDX = (uint32_t)r;
1263 }
1264
1265 void helper_cmpxchg8b(void)
1266 {
1267 uint64_t d;
1268 int eflags;
1269
1270 eflags = cc_table[CC_OP].compute_all();
1271 d = ldq(A0);
1272 if (d == (((uint64_t)EDX << 32) | EAX)) {
1273 stq(A0, ((uint64_t)ECX << 32) | EBX);
1274 eflags |= CC_Z;
1275 } else {
1276 EDX = d >> 32;
1277 EAX = d;
1278 eflags &= ~CC_Z;
1279 }
1280 CC_SRC = eflags;
1281 }
1282
1283 void helper_cpuid(void)
1284 {
1285 uint32_t index;
1286 index = (uint32_t)EAX;
1287
1288 /* test if maximum index reached */
1289 if (index & 0x80000000) {
1290 if (index > env->cpuid_xlevel)
1291 index = env->cpuid_level;
1292 } else {
1293 if (index > env->cpuid_level)
1294 index = env->cpuid_level;
1295 }
1296
1297 switch(index) {
1298 case 0:
1299 EAX = env->cpuid_level;
1300 EBX = env->cpuid_vendor1;
1301 EDX = env->cpuid_vendor2;
1302 ECX = env->cpuid_vendor3;
1303 break;
1304 case 1:
1305 EAX = env->cpuid_version;
1306 EBX = 0;
1307 ECX = env->cpuid_ext_features;
1308 EDX = env->cpuid_features;
1309 break;
1310 case 2:
1311 /* cache info: needed for Pentium Pro compatibility */
1312 EAX = 0x410601;
1313 EBX = 0;
1314 ECX = 0;
1315 EDX = 0;
1316 break;
1317 case 0x80000000:
1318 EAX = env->cpuid_xlevel;
1319 EBX = env->cpuid_vendor1;
1320 EDX = env->cpuid_vendor2;
1321 ECX = env->cpuid_vendor3;
1322 break;
1323 case 0x80000001:
1324 EAX = env->cpuid_features;
1325 EBX = 0;
1326 ECX = 0;
1327 EDX = env->cpuid_ext2_features;
1328 break;
1329 case 0x80000002:
1330 case 0x80000003:
1331 case 0x80000004:
1332 EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1333 EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1334 ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1335 EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1336 break;
1337 case 0x80000008:
1338 /* virtual & phys address size in low 2 bytes. */
1339 EAX = 0x00003028;
1340 EBX = 0;
1341 ECX = 0;
1342 EDX = 0;
1343 break;
1344 default:
1345 /* reserved values: zero */
1346 EAX = 0;
1347 EBX = 0;
1348 ECX = 0;
1349 EDX = 0;
1350 break;
1351 }
1352 }
1353
1354 void helper_enter_level(int level, int data32)
1355 {
1356 target_ulong ssp;
1357 uint32_t esp_mask, esp, ebp;
1358
1359 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1360 ssp = env->segs[R_SS].base;
1361 ebp = EBP;
1362 esp = ESP;
1363 if (data32) {
1364 /* 32 bit */
1365 esp -= 4;
1366 while (--level) {
1367 esp -= 4;
1368 ebp -= 4;
1369 stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1370 }
1371 esp -= 4;
1372 stl(ssp + (esp & esp_mask), T1);
1373 } else {
1374 /* 16 bit */
1375 esp -= 2;
1376 while (--level) {
1377 esp -= 2;
1378 ebp -= 2;
1379 stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1380 }
1381 esp -= 2;
1382 stw(ssp + (esp & esp_mask), T1);
1383 }
1384 }
1385
1386 void helper_lldt_T0(void)
1387 {
1388 int selector;
1389 SegmentCache *dt;
1390 uint32_t e1, e2;
1391 int index, entry_limit;
1392 target_ulong ptr;
1393
1394 selector = T0 & 0xffff;
1395 if ((selector & 0xfffc) == 0) {
1396 /* XXX: NULL selector case: invalid LDT */
1397 env->ldt.base = 0;
1398 env->ldt.limit = 0;
1399 } else {
1400 if (selector & 0x4)
1401 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1402 dt = &env->gdt;
1403 index = selector & ~7;
1404 #ifdef TARGET_X86_64
1405 if (env->hflags & HF_LMA_MASK)
1406 entry_limit = 15;
1407 else
1408 #endif
1409 entry_limit = 7;
1410 if ((index + entry_limit) > dt->limit)
1411 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1412 ptr = dt->base + index;
1413 e1 = ldl_kernel(ptr);
1414 e2 = ldl_kernel(ptr + 4);
1415 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1416 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1417 if (!(e2 & DESC_P_MASK))
1418 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1419 #ifdef TARGET_X86_64
1420 if (env->hflags & HF_LMA_MASK) {
1421 uint32_t e3;
1422 e3 = ldl_kernel(ptr + 8);
1423 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1424 env->ldt.base |= (target_ulong)e3 << 32;
1425 } else
1426 #endif
1427 {
1428 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1429 }
1430 }
1431 env->ldt.selector = selector;
1432 }
1433
1434 void helper_ltr_T0(void)
1435 {
1436 int selector;
1437 SegmentCache *dt;
1438 uint32_t e1, e2;
1439 int index, type, entry_limit;
1440 target_ulong ptr;
1441
1442 selector = T0 & 0xffff;
1443 if ((selector & 0xfffc) == 0) {
1444 /* NULL selector case: invalid TR */
1445 env->tr.base = 0;
1446 env->tr.limit = 0;
1447 env->tr.flags = 0;
1448 } else {
1449 if (selector & 0x4)
1450 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1451 dt = &env->gdt;
1452 index = selector & ~7;
1453 #ifdef TARGET_X86_64
1454 if (env->hflags & HF_LMA_MASK)
1455 entry_limit = 15;
1456 else
1457 #endif
1458 entry_limit = 7;
1459 if ((index + entry_limit) > dt->limit)
1460 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1461 ptr = dt->base + index;
1462 e1 = ldl_kernel(ptr);
1463 e2 = ldl_kernel(ptr + 4);
1464 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1465 if ((e2 & DESC_S_MASK) ||
1466 (type != 1 && type != 9))
1467 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1468 if (!(e2 & DESC_P_MASK))
1469 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1470 #ifdef TARGET_X86_64
1471 if (env->hflags & HF_LMA_MASK) {
1472 uint32_t e3;
1473 e3 = ldl_kernel(ptr + 8);
1474 load_seg_cache_raw_dt(&env->tr, e1, e2);
1475 env->tr.base |= (target_ulong)e3 << 32;
1476 } else
1477 #endif
1478 {
1479 load_seg_cache_raw_dt(&env->tr, e1, e2);
1480 }
1481 e2 |= DESC_TSS_BUSY_MASK;
1482 stl_kernel(ptr + 4, e2);
1483 }
1484 env->tr.selector = selector;
1485 }
1486
1487 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1488 void load_seg(int seg_reg, int selector)
1489 {
1490 uint32_t e1, e2;
1491 int cpl, dpl, rpl;
1492 SegmentCache *dt;
1493 int index;
1494 target_ulong ptr;
1495
1496 selector &= 0xffff;
1497 if ((selector & 0xfffc) == 0) {
1498 /* null selector case */
1499 if (seg_reg == R_SS
1500 #ifdef TARGET_X86_64
1501 && !(env->hflags & HF_CS64_MASK)
1502 #endif
1503 )
1504 raise_exception_err(EXCP0D_GPF, 0);
1505 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1506 } else {
1507
1508 if (selector & 0x4)
1509 dt = &env->ldt;
1510 else
1511 dt = &env->gdt;
1512 index = selector & ~7;
1513 if ((index + 7) > dt->limit)
1514 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1515 ptr = dt->base + index;
1516 e1 = ldl_kernel(ptr);
1517 e2 = ldl_kernel(ptr + 4);
1518
1519 if (!(e2 & DESC_S_MASK))
1520 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1521 rpl = selector & 3;
1522 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1523 cpl = env->hflags & HF_CPL_MASK;
1524 if (seg_reg == R_SS) {
1525 /* must be writable segment */
1526 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
1527 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1528 if (rpl != cpl || dpl != cpl)
1529 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1530 } else {
1531 /* must be readable segment */
1532 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK)
1533 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1534
1535 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1536 /* if not conforming code, test rights */
1537 if (dpl < cpl || dpl < rpl)
1538 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1539 }
1540 }
1541
1542 if (!(e2 & DESC_P_MASK)) {
1543 if (seg_reg == R_SS)
1544 raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
1545 else
1546 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1547 }
1548
1549 /* set the access bit if not already set */
1550 if (!(e2 & DESC_A_MASK)) {
1551 e2 |= DESC_A_MASK;
1552 stl_kernel(ptr + 4, e2);
1553 }
1554
1555 cpu_x86_load_seg_cache(env, seg_reg, selector,
1556 get_seg_base(e1, e2),
1557 get_seg_limit(e1, e2),
1558 e2);
1559 #if 0
1560 fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1561 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1562 #endif
1563 }
1564 }
1565
1566 /* protected mode jump */
1567 void helper_ljmp_protected_T0_T1(int next_eip_addend)
1568 {
1569 int new_cs, gate_cs, type;
1570 uint32_t e1, e2, cpl, dpl, rpl, limit;
1571 target_ulong new_eip, next_eip;
1572
1573 new_cs = T0;
1574 new_eip = T1;
1575 if ((new_cs & 0xfffc) == 0)
1576 raise_exception_err(EXCP0D_GPF, 0);
1577 if (load_segment(&e1, &e2, new_cs) != 0)
1578 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1579 cpl = env->hflags & HF_CPL_MASK;
1580 if (e2 & DESC_S_MASK) {
1581 if (!(e2 & DESC_CS_MASK))
1582 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1583 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1584 if (e2 & DESC_C_MASK) {
1585 /* conforming code segment */
1586 if (dpl > cpl)
1587 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1588 } else {
1589 /* non conforming code segment */
1590 rpl = new_cs & 3;
1591 if (rpl > cpl)
1592 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1593 if (dpl != cpl)
1594 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1595 }
1596 if (!(e2 & DESC_P_MASK))
1597 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1598 limit = get_seg_limit(e1, e2);
1599 if (new_eip > limit &&
1600 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
1601 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1602 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1603 get_seg_base(e1, e2), limit, e2);
1604 EIP = new_eip;
1605 } else {
1606 /* jump to call or task gate */
1607 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1608 rpl = new_cs & 3;
1609 cpl = env->hflags & HF_CPL_MASK;
1610 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1611 switch(type) {
1612 case 1: /* 286 TSS */
1613 case 9: /* 386 TSS */
1614 case 5: /* task gate */
1615 if (dpl < cpl || dpl < rpl)
1616 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1617 next_eip = env->eip + next_eip_addend;
1618 switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
1619 break;
1620 case 4: /* 286 call gate */
1621 case 12: /* 386 call gate */
1622 if ((dpl < cpl) || (dpl < rpl))
1623 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1624 if (!(e2 & DESC_P_MASK))
1625 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1626 gate_cs = e1 >> 16;
1627 new_eip = (e1 & 0xffff);
1628 if (type == 12)
1629 new_eip |= (e2 & 0xffff0000);
1630 if (load_segment(&e1, &e2, gate_cs) != 0)
1631 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1632 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1633 /* must be code segment */
1634 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1635 (DESC_S_MASK | DESC_CS_MASK)))
1636 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1637 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
1638 (!(e2 & DESC_C_MASK) && (dpl != cpl)))
1639 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1640 if (!(e2 & DESC_P_MASK))
1641 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1642 limit = get_seg_limit(e1, e2);
1643 if (new_eip > limit)
1644 raise_exception_err(EXCP0D_GPF, 0);
1645 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1646 get_seg_base(e1, e2), limit, e2);
1647 EIP = new_eip;
1648 break;
1649 default:
1650 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1651 break;
1652 }
1653 }
1654 }
1655
1656 /* real mode call */
1657 void helper_lcall_real_T0_T1(int shift, int next_eip)
1658 {
1659 int new_cs, new_eip;
1660 uint32_t esp, esp_mask;
1661 target_ulong ssp;
1662
1663 new_cs = T0;
1664 new_eip = T1;
1665 esp = ESP;
1666 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1667 ssp = env->segs[R_SS].base;
1668 if (shift) {
1669 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1670 PUSHL(ssp, esp, esp_mask, next_eip);
1671 } else {
1672 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1673 PUSHW(ssp, esp, esp_mask, next_eip);
1674 }
1675
1676 ESP = (ESP & ~esp_mask) | (esp & esp_mask);
1677 env->eip = new_eip;
1678 env->segs[R_CS].selector = new_cs;
1679 env->segs[R_CS].base = (new_cs << 4);
1680 }
1681
1682 /* protected mode call */
1683 void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
1684 {
1685 int new_cs, new_eip, new_stack, i;
1686 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1687 uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
1688 uint32_t val, limit, old_sp_mask;
1689 target_ulong ssp, old_ssp, next_eip;
1690
1691 new_cs = T0;
1692 new_eip = T1;
1693 next_eip = env->eip + next_eip_addend;
1694 #ifdef DEBUG_PCALL
1695 if (loglevel & CPU_LOG_PCALL) {
1696 fprintf(logfile, "lcall %04x:%08x s=%d\n",
1697 new_cs, new_eip, shift);
1698 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1699 }
1700 #endif
1701 if ((new_cs & 0xfffc) == 0)
1702 raise_exception_err(EXCP0D_GPF, 0);
1703 if (load_segment(&e1, &e2, new_cs) != 0)
1704 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1705 cpl = env->hflags & HF_CPL_MASK;
1706 #ifdef DEBUG_PCALL
1707 if (loglevel & CPU_LOG_PCALL) {
1708 fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
1709 }
1710 #endif
1711 if (e2 & DESC_S_MASK) {
1712 if (!(e2 & DESC_CS_MASK))
1713 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1714 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1715 if (e2 & DESC_C_MASK) {
1716 /* conforming code segment */
1717 if (dpl > cpl)
1718 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1719 } else {
1720 /* non conforming code segment */
1721 rpl = new_cs & 3;
1722 if (rpl > cpl)
1723 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1724 if (dpl != cpl)
1725 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1726 }
1727 if (!(e2 & DESC_P_MASK))
1728 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1729
1730 #ifdef TARGET_X86_64
1731 /* XXX: check 16/32 bit cases in long mode */
1732 if (shift == 2) {
1733 target_ulong rsp;
1734 /* 64 bit case */
1735 rsp = ESP;
1736 PUSHQ(rsp, env->segs[R_CS].selector);
1737 PUSHQ(rsp, next_eip);
1738 /* from this point, not restartable */
1739 ESP = rsp;
1740 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1741 get_seg_base(e1, e2),
1742 get_seg_limit(e1, e2), e2);
1743 EIP = new_eip;
1744 } else
1745 #endif
1746 {
1747 sp = ESP;
1748 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1749 ssp = env->segs[R_SS].base;
1750 if (shift) {
1751 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1752 PUSHL(ssp, sp, sp_mask, next_eip);
1753 } else {
1754 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1755 PUSHW(ssp, sp, sp_mask, next_eip);
1756 }
1757
1758 limit = get_seg_limit(e1, e2);
1759 if (new_eip > limit)
1760 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1761 /* from this point, not restartable */
1762 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1763 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1764 get_seg_base(e1, e2), limit, e2);
1765 EIP = new_eip;
1766 }
1767 } else {
1768 /* check gate type */
1769 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1770 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1771 rpl = new_cs & 3;
1772 switch(type) {
1773 case 1: /* available 286 TSS */
1774 case 9: /* available 386 TSS */
1775 case 5: /* task gate */
1776 if (dpl < cpl || dpl < rpl)
1777 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1778 switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
1779 return;
1780 case 4: /* 286 call gate */
1781 case 12: /* 386 call gate */
1782 break;
1783 default:
1784 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1785 break;
1786 }
1787 shift = type >> 3;
1788
1789 if (dpl < cpl || dpl < rpl)
1790 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1791 /* check valid bit */
1792 if (!(e2 & DESC_P_MASK))
1793 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1794 selector = e1 >> 16;
1795 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1796 param_count = e2 & 0x1f;
1797 if ((selector & 0xfffc) == 0)
1798 raise_exception_err(EXCP0D_GPF, 0);
1799
1800 if (load_segment(&e1, &e2, selector) != 0)
1801 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1802 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
1803 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1804 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1805 if (dpl > cpl)
1806 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1807 if (!(e2 & DESC_P_MASK))
1808 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1809
1810 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1811 /* to inner priviledge */
1812 get_ss_esp_from_tss(&ss, &sp, dpl);
1813 #ifdef DEBUG_PCALL
1814 if (loglevel & CPU_LOG_PCALL)
1815 fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
1816 ss, sp, param_count, ESP);
1817 #endif
1818 if ((ss & 0xfffc) == 0)
1819 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1820 if ((ss & 3) != dpl)
1821 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1822 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
1823 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1824 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
1825 if (ss_dpl != dpl)
1826 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1827 if (!(ss_e2 & DESC_S_MASK) ||
1828 (ss_e2 & DESC_CS_MASK) ||
1829 !(ss_e2 & DESC_W_MASK))
1830 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1831 if (!(ss_e2 & DESC_P_MASK))
1832 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1833
1834 // push_size = ((param_count * 2) + 8) << shift;
1835
1836 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1837 old_ssp = env->segs[R_SS].base;
1838
1839 sp_mask = get_sp_mask(ss_e2);
1840 ssp = get_seg_base(ss_e1, ss_e2);
1841 if (shift) {
1842 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
1843 PUSHL(ssp, sp, sp_mask, ESP);
1844 for(i = param_count - 1; i >= 0; i--) {
1845 val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
1846 PUSHL(ssp, sp, sp_mask, val);
1847 }
1848 } else {
1849 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
1850 PUSHW(ssp, sp, sp_mask, ESP);
1851 for(i = param_count - 1; i >= 0; i--) {
1852 val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
1853 PUSHW(ssp, sp, sp_mask, val);
1854 }
1855 }
1856 new_stack = 1;
1857 } else {
1858 /* to same priviledge */
1859 sp = ESP;
1860 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1861 ssp = env->segs[R_SS].base;
1862 // push_size = (4 << shift);
1863 new_stack = 0;
1864 }
1865
1866 if (shift) {
1867 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1868 PUSHL(ssp, sp, sp_mask, next_eip);
1869 } else {
1870 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1871 PUSHW(ssp, sp, sp_mask, next_eip);
1872 }
1873
1874 /* from this point, not restartable */
1875
1876 if (new_stack) {
1877 ss = (ss & ~3) | dpl;
1878 cpu_x86_load_seg_cache(env, R_SS, ss,
1879 ssp,
1880 get_seg_limit(ss_e1, ss_e2),
1881 ss_e2);
1882 }
1883
1884 selector = (selector & ~3) | dpl;
1885 cpu_x86_load_seg_cache(env, R_CS, selector,
1886 get_seg_base(e1, e2),
1887 get_seg_limit(e1, e2),
1888 e2);
1889 cpu_x86_set_cpl(env, dpl);
1890 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1891 EIP = offset;
1892 }
1893 #ifdef USE_KQEMU
1894 if (kqemu_is_ok(env)) {
1895 env->exception_index = -1;
1896 cpu_loop_exit();
1897 }
1898 #endif
1899 }
1900
1901 /* real and vm86 mode iret */
1902 void helper_iret_real(int shift)
1903 {
1904 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1905 target_ulong ssp;
1906 int eflags_mask;
1907
1908 sp_mask = 0xffff; /* XXXX: use SS segment size ? */
1909 sp = ESP;
1910 ssp = env->segs[R_SS].base;
1911 if (shift == 1) {
1912 /* 32 bits */
1913 POPL(ssp, sp, sp_mask, new_eip);
1914 POPL(ssp, sp, sp_mask, new_cs);
1915 new_cs &= 0xffff;
1916 POPL(ssp, sp, sp_mask, new_eflags);
1917 } else {
1918 /* 16 bits */
1919 POPW(ssp, sp, sp_mask, new_eip);
1920 POPW(ssp, sp, sp_mask, new_cs);
1921 POPW(ssp, sp, sp_mask, new_eflags);
1922 }
1923 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1924 load_seg_vm(R_CS, new_cs);
1925 env->eip = new_eip;
1926 if (env->eflags & VM_MASK)
1927 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | NT_MASK;
1928 else
1929 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | RF_MASK | NT_MASK;
1930 if (shift == 0)
1931 eflags_mask &= 0xffff;
1932 load_eflags(new_eflags, eflags_mask);
1933 }
1934
1935 static inline void validate_seg(int seg_reg, int cpl)
1936 {
1937 int dpl;
1938 uint32_t e2;
1939
1940 e2 = env->segs[seg_reg].flags;
1941 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1942 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1943 /* data or non conforming code segment */
1944 if (dpl < cpl) {
1945 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
1946 }
1947 }
1948 }
1949
1950 /* protected mode iret */
1951 static inline void helper_ret_protected(int shift, int is_iret, int addend)
1952 {
1953 uint32_t new_cs, new_eflags, new_ss;
1954 uint32_t new_es, new_ds, new_fs, new_gs;
1955 uint32_t e1, e2, ss_e1, ss_e2;
1956 int cpl, dpl, rpl, eflags_mask, iopl;
1957 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
1958
1959 #ifdef TARGET_X86_64
1960 if (shift == 2)
1961 sp_mask = -1;
1962 else
1963 #endif
1964 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1965 sp = ESP;
1966 ssp = env->segs[R_SS].base;
1967 new_eflags = 0; /* avoid warning */
1968 #ifdef TARGET_X86_64
1969 if (shift == 2) {
1970 POPQ(sp, new_eip);
1971 POPQ(sp, new_cs);
1972 new_cs &= 0xffff;
1973 if (is_iret) {
1974 POPQ(sp, new_eflags);
1975 }
1976 } else
1977 #endif
1978 if (shift == 1) {
1979 /* 32 bits */
1980 POPL(ssp, sp, sp_mask, new_eip);
1981 POPL(ssp, sp, sp_mask, new_cs);
1982 new_cs &= 0xffff;
1983 if (is_iret) {
1984 POPL(ssp, sp, sp_mask, new_eflags);
1985 if (new_eflags & VM_MASK)
1986 goto return_to_vm86;
1987 }
1988 } else {
1989 /* 16 bits */
1990 POPW(ssp, sp, sp_mask, new_eip);
1991 POPW(ssp, sp, sp_mask, new_cs);
1992 if (is_iret)
1993 POPW(ssp, sp, sp_mask, new_eflags);
1994 }
1995 #ifdef DEBUG_PCALL
1996 if (loglevel & CPU_LOG_PCALL) {
1997 fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
1998 new_cs, new_eip, shift, addend);
1999 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2000 }
2001 #endif
2002 if ((new_cs & 0xfffc) == 0)
2003 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2004 if (load_segment(&e1, &e2, new_cs) != 0)
2005 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2006 if (!(e2 & DESC_S_MASK) ||
2007 !(e2 & DESC_CS_MASK))
2008 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2009 cpl = env->hflags & HF_CPL_MASK;
2010 rpl = new_cs & 3;
2011 if (rpl < cpl)
2012 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2013 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2014 if (e2 & DESC_C_MASK) {
2015 if (dpl > rpl)
2016 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2017 } else {
2018 if (dpl != rpl)
2019 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2020 }
2021 if (!(e2 & DESC_P_MASK))
2022 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2023
2024 sp += addend;
2025 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2026 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2027 /* return to same priledge level */
2028 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2029 get_seg_base(e1, e2),
2030 get_seg_limit(e1, e2),
2031 e2);
2032 } else {
2033 /* return to different priviledge level */
2034 #ifdef TARGET_X86_64
2035 if (shift == 2) {
2036 POPQ(sp, new_esp);
2037 POPQ(sp, new_ss);
2038 new_ss &= 0xffff;
2039 } else
2040 #endif
2041 if (shift == 1) {
2042 /* 32 bits */
2043 POPL(ssp, sp, sp_mask, new_esp);
2044 POPL(ssp, sp, sp_mask, new_ss);
2045 new_ss &= 0xffff;
2046 } else {
2047 /* 16 bits */
2048 POPW(ssp, sp, sp_mask, new_esp);
2049 POPW(ssp, sp, sp_mask, new_ss);
2050 }
2051 #ifdef DEBUG_PCALL
2052 if (loglevel & CPU_LOG_PCALL) {
2053 fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2054 new_ss, new_esp);
2055 }
2056 #endif
2057 if ((env->hflags & HF_LMA_MASK) && (new_ss & 0xfffc) == 0) {
2058 /* NULL ss is allowed in long mode */
2059 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2060 0, 0xffffffff,
2061 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2062 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2063 DESC_W_MASK | DESC_A_MASK);
2064 } else {
2065 if ((new_ss & 3) != rpl)
2066 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2067 if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2068 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2069 if (!(ss_e2 & DESC_S_MASK) ||
2070 (ss_e2 & DESC_CS_MASK) ||
2071 !(ss_e2 & DESC_W_MASK))
2072 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2073 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2074 if (dpl != rpl)
2075 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2076 if (!(ss_e2 & DESC_P_MASK))
2077 raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2078 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2079 get_seg_base(ss_e1, ss_e2),
2080 get_seg_limit(ss_e1, ss_e2),
2081 ss_e2);
2082 }
2083
2084 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2085 get_seg_base(e1, e2),
2086 get_seg_limit(e1, e2),
2087 e2);
2088 cpu_x86_set_cpl(env, rpl);
2089 sp = new_esp;
2090 #ifdef TARGET_X86_64
2091 if (shift == 2)
2092 sp_mask = -1;
2093 else
2094 #endif
2095 sp_mask = get_sp_mask(ss_e2);
2096
2097 /* validate data segments */
2098 validate_seg(R_ES, cpl);
2099 validate_seg(R_DS, cpl);
2100 validate_seg(R_FS, cpl);
2101 validate_seg(R_GS, cpl);
2102
2103 sp += addend;
2104 }
2105 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2106 env->eip = new_eip;
2107 if (is_iret) {
2108 /* NOTE: 'cpl' is the _old_ CPL */
2109 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2110 if (cpl == 0)
2111 eflags_mask |= IOPL_MASK;
2112 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2113 if (cpl <= iopl)
2114 eflags_mask |= IF_MASK;
2115 if (shift == 0)
2116 eflags_mask &= 0xffff;
2117 load_eflags(new_eflags, eflags_mask);
2118 }
2119 return;
2120
2121 return_to_vm86:
2122 POPL(ssp, sp, sp_mask, new_esp);
2123 POPL(ssp, sp, sp_mask, new_ss);
2124 POPL(ssp, sp, sp_mask, new_es);
2125 POPL(ssp, sp, sp_mask, new_ds);
2126 POPL(ssp, sp, sp_mask, new_fs);
2127 POPL(ssp, sp, sp_mask, new_gs);
2128
2129 /* modify processor state */
2130 load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK |
2131 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK);
2132 load_seg_vm(R_CS, new_cs & 0xffff);
2133 cpu_x86_set_cpl(env, 3);
2134 load_seg_vm(R_SS, new_ss & 0xffff);
2135 load_seg_vm(R_ES, new_es & 0xffff);
2136 load_seg_vm(R_DS, new_ds & 0xffff);
2137 load_seg_vm(R_FS, new_fs & 0xffff);
2138 load_seg_vm(R_GS, new_gs & 0xffff);
2139
2140 env->eip = new_eip & 0xffff;
2141 ESP = new_esp;
2142 }
2143
2144 void helper_iret_protected(int shift, int next_eip)
2145 {
2146 int tss_selector, type;
2147 uint32_t e1, e2;
2148
2149 /* specific case for TSS */
2150 if (env->eflags & NT_MASK) {
2151 #ifdef TARGET_X86_64
2152 if (env->hflags & HF_LMA_MASK)
2153 raise_exception_err(EXCP0D_GPF, 0);
2154 #endif
2155 tss_selector = lduw_kernel(env->tr.base + 0);
2156 if (tss_selector & 4)
2157 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2158 if (load_segment(&e1, &e2, tss_selector) != 0)
2159 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2160 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2161 /* NOTE: we check both segment and busy TSS */
2162 if (type != 3)
2163 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2164 switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2165 } else {
2166 helper_ret_protected(shift, 1, 0);
2167 }
2168 #ifdef USE_KQEMU
2169 if (kqemu_is_ok(env)) {
2170 CC_OP = CC_OP_EFLAGS;
2171 env->exception_index = -1;
2172 cpu_loop_exit();
2173 }
2174 #endif
2175 }
2176
2177 void helper_lret_protected(int shift, int addend)
2178 {
2179 helper_ret_protected(shift, 0, addend);
2180 #ifdef USE_KQEMU
2181 if (kqemu_is_ok(env)) {
2182 env->exception_index = -1;
2183 cpu_loop_exit();
2184 }
2185 #endif
2186 }
2187
2188 void helper_sysenter(void)
2189 {
2190 if (env->sysenter_cs == 0) {
2191 raise_exception_err(EXCP0D_GPF, 0);
2192 }
2193 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2194 cpu_x86_set_cpl(env, 0);
2195 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2196 0, 0xffffffff,
2197 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2198 DESC_S_MASK |
2199 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2200 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2201 0, 0xffffffff,
2202 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2203 DESC_S_MASK |
2204 DESC_W_MASK | DESC_A_MASK);
2205 ESP = env->sysenter_esp;
2206 EIP = env->sysenter_eip;
2207 }
2208
2209 void helper_sysexit(void)
2210 {
2211 int cpl;
2212
2213 cpl = env->hflags & HF_CPL_MASK;
2214 if (env->sysenter_cs == 0 || cpl != 0) {
2215 raise_exception_err(EXCP0D_GPF, 0);
2216 }
2217 cpu_x86_set_cpl(env, 3);
2218 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
2219 0, 0xffffffff,
2220 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2221 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2222 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2223 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3,
2224 0, 0xffffffff,
2225 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2226 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2227 DESC_W_MASK | DESC_A_MASK);
2228 ESP = ECX;
2229 EIP = EDX;
2230 #ifdef USE_KQEMU
2231 if (kqemu_is_ok(env)) {
2232 env->exception_index = -1;
2233 cpu_loop_exit();
2234 }
2235 #endif
2236 }
2237
2238 void helper_movl_crN_T0(int reg)
2239 {
2240 #if !defined(CONFIG_USER_ONLY)
2241 switch(reg) {
2242 case 0:
2243 cpu_x86_update_cr0(env, T0);
2244 break;
2245 case 3:
2246 cpu_x86_update_cr3(env, T0);
2247 break;
2248 case 4:
2249 cpu_x86_update_cr4(env, T0);
2250 break;
2251 case 8:
2252 cpu_set_apic_tpr(env, T0);
2253 break;
2254 default:
2255 env->cr[reg] = T0;
2256 break;
2257 }
2258 #endif
2259 }
2260
2261 /* XXX: do more */
2262 void helper_movl_drN_T0(int reg)
2263 {
2264 env->dr[reg] = T0;
2265 }
2266
2267 void helper_invlpg(unsigned int addr)
2268 {
2269 cpu_x86_flush_tlb(env, addr);
2270 }
2271
2272 void helper_rdtsc(void)
2273 {
2274 uint64_t val;
2275
2276 val = cpu_get_tsc(env);
2277 EAX = (uint32_t)(val);
2278 EDX = (uint32_t)(val >> 32);
2279 }
2280
2281 #if defined(CONFIG_USER_ONLY)
2282 void helper_wrmsr(void)
2283 {
2284 }
2285
2286 void helper_rdmsr(void)
2287 {
2288 }
2289 #else
2290 void helper_wrmsr(void)
2291 {
2292 uint64_t val;
2293
2294 val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
2295
2296 switch((uint32_t)ECX) {
2297 case MSR_IA32_SYSENTER_CS:
2298 env->sysenter_cs = val & 0xffff;
2299 break;
2300 case MSR_IA32_SYSENTER_ESP:
2301 env->sysenter_esp = val;
2302 break;
2303 case MSR_IA32_SYSENTER_EIP:
2304 env->sysenter_eip = val;
2305 break;
2306 case MSR_IA32_APICBASE:
2307 cpu_set_apic_base(env, val);
2308 break;
2309 case MSR_EFER:
2310 {
2311 uint64_t update_mask;
2312 update_mask = 0;
2313 if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
2314 update_mask |= MSR_EFER_SCE;
2315 if (env->cpuid_ext2_features & CPUID_EXT2_LM)
2316 update_mask |= MSR_EFER_LME;
2317 if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
2318 update_mask |= MSR_EFER_FFXSR;
2319 if (env->cpuid_ext2_features & CPUID_EXT2_NX)
2320 update_mask |= MSR_EFER_NXE;
2321 env->efer = (env->efer & ~update_mask) |
2322 (val & update_mask);
2323 }
2324 break;
2325 case MSR_STAR:
2326 env->star = val;
2327 break;
2328 #ifdef TARGET_X86_64
2329 case MSR_LSTAR:
2330 env->lstar = val;
2331 break;
2332 case MSR_CSTAR:
2333 env->cstar = val;
2334 break;
2335 case MSR_FMASK:
2336 env->fmask = val;
2337 break;
2338 case MSR_FSBASE:
2339 env->segs[R_FS].base = val;
2340 break;
2341 case MSR_GSBASE:
2342 env->segs[R_GS].base = val;
2343 break;
2344 case MSR_KERNELGSBASE:
2345 env->kernelgsbase = val;
2346 break;
2347 #endif
2348 default:
2349 /* XXX: exception ? */
2350 break;
2351 }
2352 }
2353
2354 void helper_rdmsr(void)
2355 {
2356 uint64_t val;
2357 switch((uint32_t)ECX) {
2358 case MSR_IA32_SYSENTER_CS:
2359 val = env->sysenter_cs;
2360 break;
2361 case MSR_IA32_SYSENTER_ESP:
2362 val = env->sysenter_esp;
2363 break;
2364 case MSR_IA32_SYSENTER_EIP:
2365 val = env->sysenter_eip;
2366 break;
2367 case MSR_IA32_APICBASE:
2368 val = cpu_get_apic_base(env);
2369 break;
2370 case MSR_EFER:
2371 val = env->efer;
2372 break;
2373 case MSR_STAR:
2374 val = env->star;
2375 break;
2376 #ifdef TARGET_X86_64
2377 case MSR_LSTAR:
2378 val = env->lstar;
2379 break;
2380 case MSR_CSTAR:
2381 val = env->cstar;
2382 break;
2383 case MSR_FMASK:
2384 val = env->fmask;
2385 break;
2386 case MSR_FSBASE:
2387 val = env->segs[R_FS].base;
2388 break;
2389 case MSR_GSBASE:
2390 val = env->segs[R_GS].base;
2391 break;
2392 case MSR_KERNELGSBASE:
2393 val = env->kernelgsbase;
2394 break;
2395 #endif
2396 default:
2397 /* XXX: exception ? */
2398 val = 0;
2399 break;
2400 }
2401 EAX = (uint32_t)(val);
2402 EDX = (uint32_t)(val >> 32);
2403 }
2404 #endif
2405
2406 void helper_lsl(void)
2407 {
2408 unsigned int selector, limit;
2409 uint32_t e1, e2, eflags;
2410 int rpl, dpl, cpl, type;
2411
2412 eflags = cc_table[CC_OP].compute_all();
2413 selector = T0 & 0xffff;
2414 if (load_segment(&e1, &e2, selector) != 0)
2415 goto fail;
2416 rpl = selector & 3;
2417 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2418 cpl = env->hflags & HF_CPL_MASK;
2419 if (e2 & DESC_S_MASK) {
2420 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2421 /* conforming */
2422 } else {
2423 if (dpl < cpl || dpl < rpl)
2424 goto fail;
2425 }
2426 } else {
2427 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2428 switch(type) {
2429 case 1:
2430 case 2:
2431 case 3:
2432 case 9:
2433 case 11:
2434 break;
2435 default:
2436 goto fail;
2437 }
2438 if (dpl < cpl || dpl < rpl) {
2439 fail:
2440 CC_SRC = eflags & ~CC_Z;
2441 return;
2442 }
2443 }
2444 limit = get_seg_limit(e1, e2);
2445 T1 = limit;
2446 CC_SRC = eflags | CC_Z;
2447 }
2448
2449 void helper_lar(void)
2450 {
2451 unsigned int selector;
2452 uint32_t e1, e2, eflags;
2453 int rpl, dpl, cpl, type;
2454
2455 eflags = cc_table[CC_OP].compute_all();
2456 selector = T0 & 0xffff;
2457 if ((selector & 0xfffc) == 0)
2458 goto fail;
2459 if (load_segment(&e1, &e2, selector) != 0)
2460 goto fail;
2461 rpl = selector & 3;
2462 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2463 cpl = env->hflags & HF_CPL_MASK;
2464 if (e2 & DESC_S_MASK) {
2465 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2466 /* conforming */
2467 } else {
2468 if (dpl < cpl || dpl < rpl)
2469 goto fail;
2470 }
2471 } else {
2472 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2473 switch(type) {
2474 case 1:
2475 case 2:
2476 case 3:
2477 case 4:
2478 case 5:
2479 case 9:
2480 case 11:
2481 case 12:
2482 break;
2483 default:
2484 goto fail;
2485 }
2486 if (dpl < cpl || dpl < rpl) {
2487 fail:
2488 CC_SRC = eflags & ~CC_Z;
2489 return;
2490 }
2491 }
2492 T1 = e2 & 0x00f0ff00;
2493 CC_SRC = eflags | CC_Z;
2494 }
2495
2496 void helper_verr(void)
2497 {
2498 unsigned int selector;
2499 uint32_t e1, e2, eflags;
2500 int rpl, dpl, cpl;
2501
2502 eflags = cc_table[CC_OP].compute_all();
2503 selector = T0 & 0xffff;
2504 if ((selector & 0xfffc) == 0)
2505 goto fail;
2506 if (load_segment(&e1, &e2, selector) != 0)
2507 goto fail;
2508 if (!(e2 & DESC_S_MASK))
2509 goto fail;
2510 rpl = selector & 3;
2511 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2512 cpl = env->hflags & HF_CPL_MASK;
2513 if (e2 & DESC_CS_MASK) {
2514 if (!(e2 & DESC_R_MASK))
2515 goto fail;
2516 if (!(e2 & DESC_C_MASK)) {
2517 if (dpl < cpl || dpl < rpl)
2518 goto fail;
2519 }
2520 } else {
2521 if (dpl < cpl || dpl < rpl) {
2522 fail:
2523 CC_SRC = eflags & ~CC_Z;
2524 return;
2525 }
2526 }
2527 CC_SRC = eflags | CC_Z;
2528 }
2529
2530 void helper_verw(void)
2531 {
2532 unsigned int selector;
2533 uint32_t e1, e2, eflags;
2534 int rpl, dpl, cpl;
2535
2536 eflags = cc_table[CC_OP].compute_all();
2537 selector = T0 & 0xffff;
2538 if ((selector & 0xfffc) == 0)
2539 goto fail;
2540 if (load_segment(&e1, &e2, selector) != 0)
2541 goto fail;
2542 if (!(e2 & DESC_S_MASK))
2543 goto fail;
2544 rpl = selector & 3;
2545 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2546 cpl = env->hflags & HF_CPL_MASK;
2547 if (e2 & DESC_CS_MASK) {
2548 goto fail;
2549 } else {
2550 if (dpl < cpl || dpl < rpl)
2551 goto fail;
2552 if (!(e2 & DESC_W_MASK)) {
2553 fail:
2554 CC_SRC = eflags & ~CC_Z;
2555 return;
2556 }
2557 }
2558 CC_SRC = eflags | CC_Z;
2559 }
2560
2561 /* FPU helpers */
2562
2563 void helper_fldt_ST0_A0(void)
2564 {
2565 int new_fpstt;
2566 new_fpstt = (env->fpstt - 1) & 7;
2567 env->fpregs[new_fpstt].d = helper_fldt(A0);
2568 env->fpstt = new_fpstt;
2569 env->fptags[new_fpstt] = 0; /* validate stack entry */
2570 }
2571
2572 void helper_fstt_ST0_A0(void)
2573 {
2574 helper_fstt(ST0, A0);
2575 }
2576
2577 void fpu_set_exception(int mask)
2578 {
2579 env->fpus |= mask;
2580 if (env->fpus & (~env->fpuc & FPUC_EM))
2581 env->fpus |= FPUS_SE | FPUS_B;
2582 }
2583
2584 CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
2585 {
2586 if (b == 0.0)
2587 fpu_set_exception(FPUS_ZE);
2588 return a / b;
2589 }
2590
2591 void fpu_raise_exception(void)
2592 {
2593 if (env->cr[0] & CR0_NE_MASK) {
2594 raise_exception(EXCP10_COPR);
2595 }
2596 #if !defined(CONFIG_USER_ONLY)
2597 else {
2598 cpu_set_ferr(env);
2599 }
2600 #endif
2601 }
2602
2603 /* BCD ops */
2604
2605 void helper_fbld_ST0_A0(void)
2606 {
2607 CPU86_LDouble tmp;
2608 uint64_t val;
2609 unsigned int v;
2610 int i;
2611
2612 val = 0;
2613 for(i = 8; i >= 0; i--) {
2614 v = ldub(A0 + i);
2615 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
2616 }
2617 tmp = val;
2618 if (ldub(A0 + 9) & 0x80)
2619 tmp = -tmp;
2620 fpush();
2621 ST0 = tmp;
2622 }
2623
2624 void helper_fbst_ST0_A0(void)
2625 {
2626 int v;
2627 target_ulong mem_ref, mem_end;
2628 int64_t val;
2629
2630 val = floatx_to_int64(ST0, &env->fp_status);
2631 mem_ref = A0;
2632 mem_end = mem_ref + 9;
2633 if (val < 0) {
2634 stb(mem_end, 0x80);
2635 val = -val;
2636 } else {
2637 stb(mem_end, 0x00);
2638 }
2639 while (mem_ref < mem_end) {
2640 if (val == 0)
2641 break;
2642 v = val % 100;
2643 val = val / 100;
2644 v = ((v / 10) << 4) | (v % 10);
2645 stb(mem_ref++, v);
2646 }
2647 while (mem_ref < mem_end) {
2648 stb(mem_ref++, 0);
2649 }
2650 }
2651
2652 void helper_f2xm1(void)
2653 {
2654 ST0 = pow(2.0,ST0) - 1.0;
2655 }
2656
2657 void helper_fyl2x(void)
2658 {
2659 CPU86_LDouble fptemp;
2660
2661 fptemp = ST0;
2662 if (fptemp>0.0){
2663 fptemp = log(fptemp)/log(2.0); /* log2(ST) */
2664 ST1 *= fptemp;
2665 fpop();
2666 } else {
2667 env->fpus &= (~0x4700);
2668 env->fpus |= 0x400;
2669 }
2670 }
2671
2672 void helper_fptan(void)
2673 {
2674 CPU86_LDouble fptemp;
2675
2676 fptemp = ST0;
2677 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2678 env->fpus |= 0x400;
2679 } else {
2680 ST0 = tan(fptemp);
2681 fpush();
2682 ST0 = 1.0;
2683 env->fpus &= (~0x400); /* C2 <-- 0 */
2684 /* the above code is for |arg| < 2**52 only */
2685 }
2686 }
2687
2688 void helper_fpatan(void)
2689 {
2690 CPU86_LDouble fptemp, fpsrcop;
2691
2692 fpsrcop = ST1;
2693 fptemp = ST0;
2694 ST1 = atan2(fpsrcop,fptemp);
2695 fpop();
2696 }
2697
2698 void helper_fxtract(void)
2699 {
2700 CPU86_LDoubleU temp;
2701 unsigned int expdif;
2702
2703 temp.d = ST0;
2704 expdif = EXPD(temp) - EXPBIAS;
2705 /*DP exponent bias*/
2706 ST0 = expdif;
2707 fpush();
2708 BIASEXPONENT(temp);
2709 ST0 = temp.d;
2710 }
2711
2712 void helper_fprem1(void)
2713 {
2714 CPU86_LDouble dblq, fpsrcop, fptemp;
2715 CPU86_LDoubleU fpsrcop1, fptemp1;
2716 int expdif;
2717 int q;
2718
2719 fpsrcop = ST0;
2720 fptemp = ST1;
2721 fpsrcop1.d = fpsrcop;
2722 fptemp1.d = fptemp;
2723 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2724 if (expdif < 53) {
2725 dblq = fpsrcop / fptemp;
2726 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2727 ST0 = fpsrcop - fptemp*dblq;
2728 q = (int)dblq; /* cutting off top bits is assumed here */
2729 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2730 /* (C0,C1,C3) <-- (q2,q1,q0) */
2731 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2732 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2733 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2734 } else {
2735 env->fpus |= 0x400; /* C2 <-- 1 */
2736 fptemp = pow(2.0, expdif-50);
2737 fpsrcop = (ST0 / ST1) / fptemp;
2738 /* fpsrcop = integer obtained by rounding to the nearest */
2739 fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
2740 floor(fpsrcop): ceil(fpsrcop);
2741 ST0 -= (ST1 * fpsrcop * fptemp);
2742 }
2743 }
2744
2745 void helper_fprem(void)
2746 {
2747 CPU86_LDouble dblq, fpsrcop, fptemp;
2748 CPU86_LDoubleU fpsrcop1, fptemp1;
2749 int expdif;
2750 int q;
2751
2752 fpsrcop = ST0;
2753 fptemp = ST1;
2754 fpsrcop1.d = fpsrcop;
2755 fptemp1.d = fptemp;
2756 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2757 if ( expdif < 53 ) {
2758 dblq = fpsrcop / fptemp;
2759 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2760 ST0 = fpsrcop - fptemp*dblq;
2761 q = (int)dblq; /* cutting off top bits is assumed here */
2762 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2763 /* (C0,C1,C3) <-- (q2,q1,q0) */
2764 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2765 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2766 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2767 } else {
2768 env->fpus |= 0x400; /* C2 <-- 1 */
2769 fptemp = pow(2.0, expdif-50);
2770 fpsrcop = (ST0 / ST1) / fptemp;
2771 /* fpsrcop = integer obtained by chopping */
2772 fpsrcop = (fpsrcop < 0.0)?
2773 -(floor(fabs(fpsrcop))): floor(fpsrcop);
2774 ST0 -= (ST1 * fpsrcop * fptemp);
2775 }
2776 }
2777
2778 void helper_fyl2xp1(void)
2779 {
2780 CPU86_LDouble fptemp;
2781
2782 fptemp = ST0;
2783 if ((fptemp+1.0)>0.0) {
2784 fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
2785 ST1 *= fptemp;
2786 fpop();
2787 } else {
2788 env->fpus &= (~0x4700);
2789 env->fpus |= 0x400;
2790 }
2791 }
2792
2793 void helper_fsqrt(void)
2794 {
2795 CPU86_LDouble fptemp;
2796
2797 fptemp = ST0;
2798 if (fptemp<0.0) {
2799 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2800 env->fpus |= 0x400;
2801 }
2802 ST0 = sqrt(fptemp);
2803 }
2804
2805 void helper_fsincos(void)
2806 {
2807 CPU86_LDouble fptemp;
2808
2809 fptemp = ST0;
2810 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2811 env->fpus |= 0x400;
2812 } else {
2813 ST0 = sin(fptemp);
2814 fpush();
2815 ST0 = cos(fptemp);
2816 env->fpus &= (~0x400); /* C2 <-- 0 */
2817 /* the above code is for |arg| < 2**63 only */
2818 }
2819 }
2820
2821 void helper_frndint(void)
2822 {
2823 ST0 = floatx_round_to_int(ST0, &env->fp_status);
2824 }
2825
2826 void helper_fscale(void)
2827 {
2828 CPU86_LDouble fpsrcop, fptemp;
2829
2830 fpsrcop = 2.0;
2831 fptemp = pow(fpsrcop,ST1);
2832 ST0 *= fptemp;
2833 }
2834
2835 void helper_fsin(void)
2836 {
2837 CPU86_LDouble fptemp;
2838
2839 fptemp = ST0;
2840 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2841 env->fpus |= 0x400;
2842 } else {
2843 ST0 = sin(fptemp);
2844 env->fpus &= (~0x400); /* C2 <-- 0 */
2845 /* the above code is for |arg| < 2**53 only */
2846 }
2847 }
2848
2849 void helper_fcos(void)
2850 {
2851 CPU86_LDouble fptemp;
2852
2853 fptemp = ST0;
2854 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2855 env->fpus |= 0x400;
2856 } else {
2857 ST0 = cos(fptemp);
2858 env->fpus &= (~0x400); /* C2 <-- 0 */
2859 /* the above code is for |arg5 < 2**63 only */
2860 }
2861 }
2862
2863 void helper_fxam_ST0(void)
2864 {
2865 CPU86_LDoubleU temp;
2866 int expdif;
2867
2868 temp.d = ST0;
2869
2870 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2871 if (SIGND(temp))
2872 env->fpus |= 0x200; /* C1 <-- 1 */
2873
2874 expdif = EXPD(temp);
2875 if (expdif == MAXEXPD) {
2876 if (MANTD(temp) == 0)
2877 env->fpus |= 0x500 /*Infinity*/;
2878 else
2879 env->fpus |= 0x100 /*NaN*/;
2880 } else if (expdif == 0) {
2881 if (MANTD(temp) == 0)
2882 env->fpus |= 0x4000 /*Zero*/;
2883 else
2884 env->fpus |= 0x4400 /*Denormal*/;
2885 } else {
2886 env->fpus |= 0x400;
2887 }
2888 }
2889
2890 void helper_fstenv(target_ulong ptr, int data32)
2891 {
2892 int fpus, fptag, exp, i;
2893 uint64_t mant;
2894 CPU86_LDoubleU tmp;
2895
2896 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
2897 fptag = 0;
2898 for (i=7; i>=0; i--) {
2899 fptag <<= 2;
2900 if (env->fptags[i]) {
2901 fptag |= 3;
2902 } else {
2903 tmp.d = env->fpregs[i].d;
2904 exp = EXPD(tmp);
2905 mant = MANTD(tmp);
2906 if (exp == 0 && mant == 0) {
2907 /* zero */
2908 fptag |= 1;
2909 } else if (exp == 0 || exp == MAXEXPD
2910 #ifdef USE_X86LDOUBLE
2911 || (mant & (1LL << 63)) == 0
2912 #endif
2913 ) {
2914 /* NaNs, infinity, denormal */
2915 fptag |= 2;
2916 }
2917 }
2918 }
2919 if (data32) {
2920 /* 32 bit */
2921 stl(ptr, env->fpuc);
2922 stl(ptr + 4, fpus);
2923 stl(ptr + 8, fptag);
2924 stl(ptr + 12, 0); /* fpip */
2925 stl(ptr + 16, 0); /* fpcs */
2926 stl(ptr + 20, 0); /* fpoo */
2927 stl(ptr + 24, 0); /* fpos */
2928 } else {
2929 /* 16 bit */
2930 stw(ptr, env->fpuc);
2931 stw(ptr + 2, fpus);
2932 stw(ptr + 4, fptag);
2933 stw(ptr + 6, 0);
2934 stw(ptr + 8, 0);
2935 stw(ptr + 10, 0);
2936 stw(ptr + 12, 0);
2937 }
2938 }
2939
2940 void helper_fldenv(target_ulong ptr, int data32)
2941 {
2942 int i, fpus, fptag;
2943
2944 if (data32) {
2945 env->fpuc = lduw(ptr);
2946 fpus = lduw(ptr + 4);
2947 fptag = lduw(ptr + 8);
2948 }
2949 else {
2950 env->fpuc = lduw(ptr);
2951 fpus = lduw(ptr + 2);
2952 fptag = lduw(ptr + 4);
2953 }
2954 env->fpstt = (fpus >> 11) & 7;
2955 env->fpus = fpus & ~0x3800;
2956 for(i = 0;i < 8; i++) {
2957 env->fptags[i] = ((fptag & 3) == 3);
2958 fptag >>= 2;
2959 }
2960 }
2961
2962 void helper_fsave(target_ulong ptr, int data32)
2963 {
2964 CPU86_LDouble tmp;
2965 int i;
2966
2967 helper_fstenv(ptr, data32);
2968
2969 ptr += (14 << data32);
2970 for(i = 0;i < 8; i++) {
2971 tmp = ST(i);
2972 helper_fstt(tmp, ptr);
2973 ptr += 10;
2974 }
2975
2976 /* fninit */
2977 env->fpus = 0;
2978 env->fpstt = 0;
2979 env->fpuc = 0x37f;
2980 env->fptags[0] = 1;
2981 env->fptags[1] = 1;
2982 env->fptags[2] = 1;
2983 env->fptags[3] = 1;
2984 env->fptags[4] = 1;
2985 env->fptags[5] = 1;
2986 env->fptags[6] = 1;
2987 env->fptags[7] = 1;
2988 }
2989
2990 void helper_frstor(target_ulong ptr, int data32)
2991 {
2992 CPU86_LDouble tmp;
2993 int i;
2994
2995 helper_fldenv(ptr, data32);
2996 ptr += (14 << data32);
2997
2998 for(i = 0;i < 8; i++) {
2999 tmp = helper_fldt(ptr);
3000 ST(i) = tmp;
3001 ptr += 10;
3002 }
3003 }
3004
3005 void helper_fxsave(target_ulong ptr, int data64)
3006 {
3007 int fpus, fptag, i, nb_xmm_regs;
3008 CPU86_LDouble tmp;
3009 target_ulong addr;
3010
3011 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3012 fptag = 0;
3013 for(i = 0; i < 8; i++) {
3014 fptag |= (env->fptags[i] << i);
3015 }
3016 stw(ptr, env->fpuc);
3017 stw(ptr + 2, fpus);
3018 stw(ptr + 4, fptag ^ 0xff);
3019
3020 addr = ptr + 0x20;
3021 for(i = 0;i < 8; i++) {
3022 tmp = ST(i);
3023 helper_fstt(tmp, addr);
3024 addr += 16;
3025 }
3026
3027 if (env->cr[4] & CR4_OSFXSR_MASK) {
3028 /* XXX: finish it */
3029 stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3030 stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3031 nb_xmm_regs = 8 << data64;
3032 addr = ptr + 0xa0;
3033 for(i = 0; i < nb_xmm_regs; i++) {
3034 stq(addr, env->xmm_regs[i].XMM_Q(0));
3035 stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3036 addr += 16;
3037 }
3038 }
3039 }
3040
3041 void helper_fxrstor(target_ulong ptr, int data64)
3042 {
3043 int i, fpus, fptag, nb_xmm_regs;
3044 CPU86_LDouble tmp;
3045 target_ulong addr;
3046
3047 env->fpuc = lduw(ptr);
3048 fpus = lduw(ptr + 2);
3049 fptag = lduw(ptr + 4);
3050 env->fpstt = (fpus >> 11) & 7;
3051 env->fpus = fpus & ~0x3800;
3052 fptag ^= 0xff;
3053 for(i = 0;i < 8; i++) {
3054 env->fptags[i] = ((fptag >> i) & 1);
3055 }
3056
3057 addr = ptr + 0x20;
3058 for(i = 0;i < 8; i++) {
3059 tmp = helper_fldt(addr);
3060 ST(i) = tmp;
3061 addr += 16;
3062 }
3063
3064 if (env->cr[4] & CR4_OSFXSR_MASK) {
3065 /* XXX: finish it */
3066 env->mxcsr = ldl(ptr + 0x18);
3067 //ldl(ptr + 0x1c);
3068 nb_xmm_regs = 8 << data64;
3069 addr = ptr + 0xa0;
3070 for(i = 0; i < nb_xmm_regs; i++) {
3071 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3072 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3073 addr += 16;
3074 }
3075 }
3076 }
3077
3078 #ifndef USE_X86LDOUBLE
3079
3080 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3081 {
3082 CPU86_LDoubleU temp;
3083 int e;
3084
3085 temp.d = f;
3086 /* mantissa */
3087 *pmant = (MANTD(temp) << 11) | (1LL << 63);
3088 /* exponent + sign */
3089 e = EXPD(temp) - EXPBIAS + 16383;
3090 e |= SIGND(temp) >> 16;
3091 *pexp = e;
3092 }
3093
3094 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3095 {
3096 CPU86_LDoubleU temp;
3097 int e;
3098 uint64_t ll;
3099
3100 /* XXX: handle overflow ? */
3101 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3102 e |= (upper >> 4) & 0x800; /* sign */
3103 ll = (mant >> 11) & ((1LL << 52) - 1);
3104 #ifdef __arm__
3105 temp.l.upper = (e << 20) | (ll >> 32);
3106 temp.l.lower = ll;
3107 #else
3108 temp.ll = ll | ((uint64_t)e << 52);
3109 #endif
3110 return temp.d;
3111 }
3112
3113 #else
3114
3115 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3116 {
3117 CPU86_LDoubleU temp;
3118
3119 temp.d = f;
3120 *pmant = temp.l.lower;
3121 *pexp = temp.l.upper;
3122 }
3123
3124 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3125 {
3126 CPU86_LDoubleU temp;
3127
3128 temp.l.upper = upper;
3129 temp.l.lower = mant;
3130 return temp.d;
3131 }
3132 #endif
3133
3134 #ifdef TARGET_X86_64
3135
3136 //#define DEBUG_MULDIV
3137
3138 static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3139 {
3140 *plow += a;
3141 /* carry test */
3142 if (*plow < a)
3143 (*phigh)++;
3144 *phigh += b;
3145 }
3146
3147 static void neg128(uint64_t *plow, uint64_t *phigh)
3148 {
3149 *plow = ~ *plow;
3150 *phigh = ~ *phigh;
3151 add128(plow, phigh, 1, 0);
3152 }
3153
3154 static void mul64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3155 {
3156 uint32_t a0, a1, b0, b1;
3157 uint64_t v;
3158
3159 a0 = a;
3160 a1 = a >> 32;
3161
3162 b0 = b;
3163 b1 = b >> 32;
3164
3165 v = (uint64_t)a0 * (uint64_t)b0;
3166 *plow = v;
3167 *phigh = 0;
3168
3169 v = (uint64_t)a0 * (uint64_t)b1;
3170 add128(plow, phigh, v << 32, v >> 32);
3171
3172 v = (uint64_t)a1 * (uint64_t)b0;
3173 add128(plow, phigh, v << 32, v >> 32);
3174
3175 v = (uint64_t)a1 * (uint64_t)b1;
3176 *phigh += v;
3177 #ifdef DEBUG_MULDIV
3178 printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
3179 a, b, *phigh, *plow);
3180 #endif
3181 }
3182
3183 static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
3184 {
3185 int sa, sb;
3186 sa = (a < 0);
3187 if (sa)
3188 a = -a;
3189 sb = (b < 0);
3190 if (sb)
3191 b = -b;
3192 mul64(plow, phigh, a, b);
3193 if (sa ^ sb) {
3194 neg128(plow, phigh);
3195 }
3196 }
3197
3198 /* XXX: overflow support */
3199 static void div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
3200 {
3201 uint64_t q, r, a1, a0;
3202 int i, qb;
3203
3204 a0 = *plow;
3205 a1 = *phigh;
3206 if (a1 == 0) {
3207 q = a0 / b;
3208 r = a0 % b;
3209 *plow = q;
3210 *phigh = r;
3211 } else {
3212 /* XXX: use a better algorithm */
3213 for(i = 0; i < 64; i++) {
3214 a1 = (a1 << 1) | (a0 >> 63);
3215 if (a1 >= b) {
3216 a1 -= b;
3217 qb = 1;
3218 } else {
3219 qb = 0;
3220 }
3221 a0 = (a0 << 1) | qb;
3222 }
3223 #if defined(DEBUG_MULDIV)
3224 printf("div: 0x%016llx%016llx / 0x%016llx: q=0x%016llx r=0x%016llx\n",
3225 *phigh, *plow, b, a0, a1);
3226 #endif
3227 *plow = a0;
3228 *phigh = a1;
3229 }
3230 }
3231
3232 static void idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
3233 {
3234 int sa, sb;
3235 sa = ((int64_t)*phigh < 0);
3236 if (sa)
3237 neg128(plow, phigh);
3238 sb = (b < 0);
3239 if (sb)
3240 b = -b;
3241 div64(plow, phigh, b);
3242 if (sa ^ sb)
3243 *plow = - *plow;
3244 if (sa)
3245 *phigh = - *phigh;
3246 }
3247
3248 void helper_mulq_EAX_T0(void)
3249 {
3250 uint64_t r0, r1;
3251
3252 mul64(&r0, &r1, EAX, T0);
3253 EAX = r0;
3254 EDX = r1;
3255 CC_DST = r0;
3256 CC_SRC = r1;
3257 }
3258
3259 void helper_imulq_EAX_T0(void)
3260 {
3261 uint64_t r0, r1;
3262
3263 imul64(&r0, &r1, EAX, T0);
3264 EAX = r0;
3265 EDX = r1;
3266 CC_DST = r0;
3267 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3268 }
3269
3270 void helper_imulq_T0_T1(void)
3271 {
3272 uint64_t r0, r1;
3273
3274 imul64(&r0, &r1, T0, T1);
3275 T0 = r0;
3276 CC_DST = r0;
3277 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3278 }
3279
3280 void helper_divq_EAX_T0(void)
3281 {
3282 uint64_t r0, r1;
3283 if (T0 == 0) {
3284 raise_exception(EXCP00_DIVZ);
3285 }
3286 r0 = EAX;
3287 r1 = EDX;
3288 div64(&r0, &r1, T0);
3289 EAX = r0;
3290 EDX = r1;
3291 }
3292
3293 void helper_idivq_EAX_T0(void)
3294 {
3295 uint64_t r0, r1;
3296 if (T0 == 0) {
3297 raise_exception(EXCP00_DIVZ);
3298 }
3299 r0 = EAX;
3300 r1 = EDX;
3301 idiv64(&r0, &r1, T0);
3302 EAX = r0;
3303 EDX = r1;
3304 }
3305
3306 #endif
3307
3308 float approx_rsqrt(float a)
3309 {
3310 return 1.0 / sqrt(a);
3311 }
3312
3313 float approx_rcp(float a)
3314 {
3315 return 1.0 / a;
3316 }
3317
3318 void update_fp_status(void)
3319 {
3320 int rnd_type;
3321
3322 /* set rounding mode */
3323 switch(env->fpuc & RC_MASK) {
3324 default:
3325 case RC_NEAR:
3326 rnd_type = float_round_nearest_even;
3327 break;
3328 case RC_DOWN:
3329 rnd_type = float_round_down;
3330 break;
3331 case RC_UP:
3332 rnd_type = float_round_up;
3333 break;
3334 case RC_CHOP:
3335 rnd_type = float_round_to_zero;
3336 break;
3337 }
3338 set_float_rounding_mode(rnd_type, &env->fp_status);
3339 #ifdef FLOATX80
3340 switch((env->fpuc >> 8) & 3) {
3341 case 0:
3342 rnd_type = 32;
3343 break;
3344 case 2:
3345 rnd_type = 64;
3346 break;
3347 case 3:
3348 default:
3349 rnd_type = 80;
3350 break;
3351 }
3352 set_floatx80_rounding_precision(rnd_type, &env->fp_status);
3353 #endif
3354 }
3355
3356 #if !defined(CONFIG_USER_ONLY)
3357
3358 #define MMUSUFFIX _mmu
3359 #define GETPC() (__builtin_return_address(0))
3360
3361 #define SHIFT 0
3362 #include "softmmu_template.h"
3363
3364 #define SHIFT 1
3365 #include "softmmu_template.h"
3366
3367 #define SHIFT 2
3368 #include "softmmu_template.h"
3369
3370 #define SHIFT 3
3371 #include "softmmu_template.h"
3372
3373 #endif
3374
3375 /* try to fill the TLB and return an exception if error. If retaddr is
3376 NULL, it means that the function was called in C code (i.e. not
3377 from generated code or from helper.c) */
3378 /* XXX: fix it to restore all registers */
3379 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
3380 {
3381 TranslationBlock *tb;
3382 int ret;
3383 unsigned long pc;
3384 CPUX86State *saved_env;
3385
3386 /* XXX: hack to restore env in all cases, even if not called from
3387 generated code */
3388 saved_env = env;
3389 env = cpu_single_env;
3390
3391 ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
3392 if (ret) {
3393 if (retaddr) {
3394 /* now we have a real cpu fault */
3395 pc = (unsigned long)retaddr;
3396 tb = tb_find_pc(pc);
3397 if (tb) {
3398 /* the PC is inside the translated code. It means that we have
3399 a virtual CPU fault */
3400 cpu_restore_state(tb, env, pc, NULL);
3401 }
3402 }
3403 if (retaddr)
3404 raise_exception_err(EXCP0E_PAGE, env->error_code);
3405 else
3406 raise_exception_err_norestore(EXCP0E_PAGE, env->error_code);
3407 }
3408 env = saved_env;
3409 }
Stable branch of Qemu 0.9.1