2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define DO_SINGLE_STEP
31 #define ALPHA_DEBUG_DISAS
34 typedef struct DisasContext DisasContext
;
38 #if !defined (CONFIG_USER_ONLY)
44 #ifdef USE_DIRECT_JUMP
47 #define TBPARAM(x) (long)(x)
51 #define DEF(s, n, copy_size) INDEX_op_ ## s,
57 static uint16_t *gen_opc_ptr
;
58 static uint32_t *gen_opparam_ptr
;
62 static inline void gen_op_nop (void)
64 #if defined(GENERATE_NOP)
69 #define GEN32(func, NAME) \
70 static GenOpFunc *NAME ## _table [32] = { \
71 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
72 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
73 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
74 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
75 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
76 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
77 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
78 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
80 static inline void func(int n) \
82 NAME ## _table[n](); \
86 /* Special hacks for ir31 */
87 #define gen_op_load_T0_ir31 gen_op_reset_T0
88 #define gen_op_load_T1_ir31 gen_op_reset_T1
89 #define gen_op_load_T2_ir31 gen_op_reset_T2
90 #define gen_op_store_T0_ir31 gen_op_nop
91 #define gen_op_store_T1_ir31 gen_op_nop
92 #define gen_op_store_T2_ir31 gen_op_nop
93 #define gen_op_cmov_ir31 gen_op_nop
94 GEN32(gen_op_load_T0_ir
, gen_op_load_T0_ir
);
95 GEN32(gen_op_load_T1_ir
, gen_op_load_T1_ir
);
96 GEN32(gen_op_load_T2_ir
, gen_op_load_T2_ir
);
97 GEN32(gen_op_store_T0_ir
, gen_op_store_T0_ir
);
98 GEN32(gen_op_store_T1_ir
, gen_op_store_T1_ir
);
99 GEN32(gen_op_store_T2_ir
, gen_op_store_T2_ir
);
100 GEN32(gen_op_cmov_ir
, gen_op_cmov_ir
);
102 static inline void gen_load_ir (DisasContext
*ctx
, int irn
, int Tn
)
106 gen_op_load_T0_ir(irn
);
109 gen_op_load_T1_ir(irn
);
112 gen_op_load_T2_ir(irn
);
117 static inline void gen_store_ir (DisasContext
*ctx
, int irn
, int Tn
)
121 gen_op_store_T0_ir(irn
);
124 gen_op_store_T1_ir(irn
);
127 gen_op_store_T2_ir(irn
);
133 /* Special hacks for fir31 */
134 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
135 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
136 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
137 #define gen_op_store_FT0_fir31 gen_op_nop
138 #define gen_op_store_FT1_fir31 gen_op_nop
139 #define gen_op_store_FT2_fir31 gen_op_nop
140 #define gen_op_cmov_fir31 gen_op_nop
141 GEN32(gen_op_load_FT0_fir
, gen_op_load_FT0_fir
);
142 GEN32(gen_op_load_FT1_fir
, gen_op_load_FT1_fir
);
143 GEN32(gen_op_load_FT2_fir
, gen_op_load_FT2_fir
);
144 GEN32(gen_op_store_FT0_fir
, gen_op_store_FT0_fir
);
145 GEN32(gen_op_store_FT1_fir
, gen_op_store_FT1_fir
);
146 GEN32(gen_op_store_FT2_fir
, gen_op_store_FT2_fir
);
147 GEN32(gen_op_cmov_fir
, gen_op_cmov_fir
);
149 static inline void gen_load_fir (DisasContext
*ctx
, int firn
, int Tn
)
153 gen_op_load_FT0_fir(firn
);
156 gen_op_load_FT1_fir(firn
);
159 gen_op_load_FT2_fir(firn
);
164 static inline void gen_store_fir (DisasContext
*ctx
, int firn
, int Tn
)
168 gen_op_store_FT0_fir(firn
);
171 gen_op_store_FT1_fir(firn
);
174 gen_op_store_FT2_fir(firn
);
180 #if defined(CONFIG_USER_ONLY)
181 #define OP_LD_TABLE(width) \
182 static GenOpFunc *gen_op_ld##width[] = { \
183 &gen_op_ld##width##_raw, \
185 #define OP_ST_TABLE(width) \
186 static GenOpFunc *gen_op_st##width[] = { \
187 &gen_op_st##width##_raw, \
190 #define OP_LD_TABLE(width) \
191 static GenOpFunc *gen_op_ld##width[] = { \
192 &gen_op_ld##width##_kernel, \
193 &gen_op_ld##width##_user, /* executive */ \
194 &gen_op_ld##width##_data, /* supervisor */ \
195 &gen_op_ld##width##_data, /* user */ \
197 #define OP_ST_TABLE(width) \
198 static GenOpFunc *gen_op_st##width[] = { \
199 &gen_op_st##width##_kernel, \
200 &gen_op_st##width##_user, /* executive */ \
201 &gen_op_st##width##_data, /* supervisor */ \
202 &gen_op_st##width##_data, /* user */ \
206 #define GEN_LD(width) \
207 OP_LD_TABLE(width); \
208 static void gen_ld##width (DisasContext *ctx) \
210 (*gen_op_ld##width[ctx->mem_idx])(); \
213 #define GEN_ST(width) \
214 OP_ST_TABLE(width); \
215 static void gen_st##width (DisasContext *ctx) \
217 (*gen_op_st##width[ctx->mem_idx])(); \
235 #if 0 /* currently unused */
246 #if defined(__i386__) || defined(__x86_64__)
247 static inline void gen_op_set_s16_T0 (int16_t imm
)
249 gen_op_set_s32_T0((int32_t)imm
);
252 static inline void gen_op_set_s16_T1 (int16_t imm
)
254 gen_op_set_s32_T1((int32_t)imm
);
257 static inline void gen_op_set_u16_T0 (uint16_t imm
)
259 gen_op_set_s32_T0((uint32_t)imm
);
262 static inline void gen_op_set_u16_T1 (uint16_t imm
)
264 gen_op_set_s32_T1((uint32_t)imm
);
268 static inline void gen_set_sT0 (DisasContext
*ctx
, int64_t imm
)
280 gen_op_set_s16_T0(imm16
);
283 gen_op_set_s32_T0(imm32
);
286 #if 0 // Qemu does not know how to do this...
287 gen_op_set_64_T0(imm
);
289 gen_op_set_64_T0(imm
>> 32, imm
);
294 static inline void gen_set_sT1 (DisasContext
*ctx
, int64_t imm
)
306 gen_op_set_s16_T1(imm16
);
309 gen_op_set_s32_T1(imm32
);
312 #if 0 // Qemu does not know how to do this...
313 gen_op_set_64_T1(imm
);
315 gen_op_set_64_T1(imm
>> 32, imm
);
320 static inline void gen_set_uT0 (DisasContext
*ctx
, uint64_t imm
)
327 gen_op_set_u16_T0(imm
);
329 gen_op_set_u32_T0(imm
);
332 #if 0 // Qemu does not know how to do this...
333 gen_op_set_64_T0(imm
);
335 gen_op_set_64_T0(imm
>> 32, imm
);
340 static inline void gen_set_uT1 (DisasContext
*ctx
, uint64_t imm
)
347 gen_op_set_u16_T1(imm
);
349 gen_op_set_u32_T1(imm
);
352 #if 0 // Qemu does not know how to do this...
353 gen_op_set_64_T1(imm
);
355 gen_op_set_64_T1(imm
>> 32, imm
);
360 static inline void gen_update_pc (DisasContext
*ctx
)
362 if (!(ctx
->pc
>> 32)) {
363 gen_op_update_pc32(ctx
->pc
);
365 #if 0 // Qemu does not know how to do this...
366 gen_op_update_pc(ctx
->pc
);
368 gen_op_update_pc(ctx
->pc
>> 32, ctx
->pc
);
373 static inline void _gen_op_bcond (DisasContext
*ctx
)
375 #if 0 // Qemu does not know how to do this...
376 gen_op_bcond(ctx
->pc
);
378 gen_op_bcond(ctx
->pc
>> 32, ctx
->pc
);
382 static inline void gen_excp (DisasContext
*ctx
, int exception
, int error_code
)
385 gen_op_excp(exception
, error_code
);
388 static inline void gen_invalid (DisasContext
*ctx
)
390 gen_excp(ctx
, EXCP_OPCDEC
, 0);
393 static void gen_load_mem (DisasContext
*ctx
,
394 void (*gen_load_op
)(DisasContext
*ctx
),
395 int ra
, int rb
, int32_t disp16
, int clear
)
397 if (ra
== 31 && disp16
== 0) {
401 gen_load_ir(ctx
, rb
, 0);
403 gen_set_sT1(ctx
, disp16
);
409 gen_store_ir(ctx
, ra
, 1);
413 static void gen_store_mem (DisasContext
*ctx
,
414 void (*gen_store_op
)(DisasContext
*ctx
),
415 int ra
, int rb
, int32_t disp16
, int clear
)
417 gen_load_ir(ctx
, rb
, 0);
419 gen_set_sT1(ctx
, disp16
);
424 gen_load_ir(ctx
, ra
, 1);
425 (*gen_store_op
)(ctx
);
428 static void gen_load_fmem (DisasContext
*ctx
,
429 void (*gen_load_fop
)(DisasContext
*ctx
),
430 int ra
, int rb
, int32_t disp16
)
432 gen_load_ir(ctx
, rb
, 0);
434 gen_set_sT1(ctx
, disp16
);
437 (*gen_load_fop
)(ctx
);
438 gen_store_fir(ctx
, ra
, 1);
441 static void gen_store_fmem (DisasContext
*ctx
,
442 void (*gen_store_fop
)(DisasContext
*ctx
),
443 int ra
, int rb
, int32_t disp16
)
445 gen_load_ir(ctx
, rb
, 0);
447 gen_set_sT1(ctx
, disp16
);
450 gen_load_fir(ctx
, ra
, 1);
451 (*gen_store_fop
)(ctx
);
454 static void gen_bcond (DisasContext
*ctx
, void (*gen_test_op
)(void),
455 int ra
, int32_t disp16
)
458 gen_set_uT0(ctx
, ctx
->pc
);
459 gen_set_sT1(ctx
, disp16
<< 2);
462 gen_set_uT1(ctx
, ctx
->pc
);
464 gen_load_ir(ctx
, ra
, 0);
469 static void gen_fbcond (DisasContext
*ctx
, void (*gen_test_op
)(void),
470 int ra
, int32_t disp16
)
473 gen_set_uT0(ctx
, ctx
->pc
);
474 gen_set_sT1(ctx
, disp16
<< 2);
477 gen_set_uT1(ctx
, ctx
->pc
);
479 gen_load_fir(ctx
, ra
, 0);
484 static void gen_arith2 (DisasContext
*ctx
, void (*gen_arith_op
)(void),
485 int rb
, int rc
, int islit
, int8_t lit
)
488 gen_set_sT0(ctx
, lit
);
490 gen_load_ir(ctx
, rb
, 0);
492 gen_store_ir(ctx
, rc
, 0);
495 static void gen_arith3 (DisasContext
*ctx
, void (*gen_arith_op
)(void),
496 int ra
, int rb
, int rc
, int islit
, int8_t lit
)
498 gen_load_ir(ctx
, ra
, 0);
500 gen_set_sT1(ctx
, lit
);
502 gen_load_ir(ctx
, rb
, 1);
504 gen_store_ir(ctx
, rc
, 0);
507 static void gen_cmov (DisasContext
*ctx
, void (*gen_test_op
)(void),
508 int ra
, int rb
, int rc
, int islit
, int8_t lit
)
510 gen_load_ir(ctx
, ra
, 1);
512 gen_set_sT0(ctx
, lit
);
514 gen_load_ir(ctx
, rb
, 0);
519 static void gen_farith2 (DisasContext
*ctx
, void (*gen_arith_fop
)(void),
522 gen_load_fir(ctx
, rb
, 0);
524 gen_store_fir(ctx
, rc
, 0);
527 static void gen_farith3 (DisasContext
*ctx
, void (*gen_arith_fop
)(void),
528 int ra
, int rb
, int rc
)
530 gen_load_fir(ctx
, ra
, 0);
531 gen_load_fir(ctx
, rb
, 1);
533 gen_store_fir(ctx
, rc
, 0);
536 static void gen_fcmov (DisasContext
*ctx
, void (*gen_test_fop
)(void),
537 int ra
, int rb
, int rc
)
539 gen_load_fir(ctx
, ra
, 0);
540 gen_load_fir(ctx
, rb
, 1);
545 static void gen_fti (DisasContext
*ctx
, void (*gen_move_fop
)(void),
548 gen_load_fir(ctx
, rc
, 0);
550 gen_store_ir(ctx
, ra
, 0);
553 static void gen_itf (DisasContext
*ctx
, void (*gen_move_fop
)(void),
556 gen_load_ir(ctx
, ra
, 0);
558 gen_store_fir(ctx
, rc
, 0);
561 static void gen_s4addl (void)
567 static void gen_s4subl (void)
573 static void gen_s8addl (void)
579 static void gen_s8subl (void)
585 static void gen_s4addq (void)
591 static void gen_s4subq (void)
597 static void gen_s8addq (void)
603 static void gen_s8subq (void)
609 static void gen_amask (void)
615 static int translate_one (DisasContext
*ctx
, uint32_t insn
)
618 int32_t disp21
, disp16
, disp12
;
620 uint8_t opc
, ra
, rb
, rc
, sbz
, fpfn
, fn7
, fn2
, islit
;
624 /* Decode all instruction fields */
626 ra
= (insn
>> 21) & 0x1F;
627 rb
= (insn
>> 16) & 0x1F;
629 sbz
= (insn
>> 13) & 0x07;
630 islit
= (insn
>> 12) & 1;
631 lit
= (insn
>> 13) & 0xFF;
632 palcode
= insn
& 0x03FFFFFF;
633 disp21
= ((int32_t)((insn
& 0x001FFFFF) << 11)) >> 11;
634 disp16
= (int16_t)(insn
& 0x0000FFFF);
635 disp12
= (int32_t)((insn
& 0x00000FFF) << 20) >> 20;
636 fn16
= insn
& 0x0000FFFF;
637 fn11
= (insn
>> 5) & 0x000007FF;
639 fn7
= (insn
>> 5) & 0x0000007F;
640 fn2
= (insn
>> 5) & 0x00000003;
642 #if defined ALPHA_DEBUG_DISAS
643 if (logfile
!= NULL
) {
644 fprintf(logfile
, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
645 opc
, ra
, rb
, rc
, disp16
);
651 if (palcode
>= 0x80 && palcode
< 0xC0) {
652 /* Unprivileged PAL call */
653 gen_excp(ctx
, EXCP_CALL_PAL
+ ((palcode
& 0x1F) << 6), 0);
654 #if !defined (CONFIG_USER_ONLY)
655 } else if (palcode
< 0x40) {
656 /* Privileged PAL code */
657 if (ctx
->mem_idx
& 1)
660 gen_excp(ctx
, EXCP_CALL_PALP
+ ((palcode
& 0x1F) << 6), 0);
663 /* Invalid PAL call */
691 gen_load_ir(ctx
, rb
, 0);
692 gen_set_sT1(ctx
, disp16
);
694 gen_store_ir(ctx
, ra
, 0);
698 gen_load_ir(ctx
, rb
, 0);
699 gen_set_sT1(ctx
, disp16
<< 16);
701 gen_store_ir(ctx
, ra
, 0);
705 if (!(ctx
->amask
& AMASK_BWX
))
707 gen_load_mem(ctx
, &gen_ldbu
, ra
, rb
, disp16
, 0);
711 gen_load_mem(ctx
, &gen_ldq_u
, ra
, rb
, disp16
, 1);
715 if (!(ctx
->amask
& AMASK_BWX
))
717 gen_load_mem(ctx
, &gen_ldwu
, ra
, rb
, disp16
, 0);
721 if (!(ctx
->amask
& AMASK_BWX
))
723 gen_store_mem(ctx
, &gen_stw
, ra
, rb
, disp16
, 0);
727 if (!(ctx
->amask
& AMASK_BWX
))
729 gen_store_mem(ctx
, &gen_stb
, ra
, rb
, disp16
, 0);
733 gen_store_mem(ctx
, &gen_stq_u
, ra
, rb
, disp16
, 1);
739 gen_arith3(ctx
, &gen_op_addl
, ra
, rb
, rc
, islit
, lit
);
743 gen_arith3(ctx
, &gen_s4addl
, ra
, rb
, rc
, islit
, lit
);
747 gen_arith3(ctx
, &gen_op_subl
, ra
, rb
, rc
, islit
, lit
);
751 gen_arith3(ctx
, &gen_s4subl
, ra
, rb
, rc
, islit
, lit
);
755 gen_arith3(ctx
, &gen_op_cmpbge
, ra
, rb
, rc
, islit
, lit
);
759 gen_arith3(ctx
, &gen_s8addl
, ra
, rb
, rc
, islit
, lit
);
763 gen_arith3(ctx
, &gen_s8subl
, ra
, rb
, rc
, islit
, lit
);
767 gen_arith3(ctx
, &gen_op_cmpult
, ra
, rb
, rc
, islit
, lit
);
771 gen_arith3(ctx
, &gen_op_addq
, ra
, rb
, rc
, islit
, lit
);
775 gen_arith3(ctx
, &gen_s4addq
, ra
, rb
, rc
, islit
, lit
);
779 gen_arith3(ctx
, &gen_op_subq
, ra
, rb
, rc
, islit
, lit
);
783 gen_arith3(ctx
, &gen_s4subq
, ra
, rb
, rc
, islit
, lit
);
787 gen_arith3(ctx
, &gen_op_cmpeq
, ra
, rb
, rc
, islit
, lit
);
791 gen_arith3(ctx
, &gen_s8addq
, ra
, rb
, rc
, islit
, lit
);
795 gen_arith3(ctx
, &gen_s8subq
, ra
, rb
, rc
, islit
, lit
);
799 gen_arith3(ctx
, &gen_op_cmpule
, ra
, rb
, rc
, islit
, lit
);
803 gen_arith3(ctx
, &gen_op_addlv
, ra
, rb
, rc
, islit
, lit
);
807 gen_arith3(ctx
, &gen_op_sublv
, ra
, rb
, rc
, islit
, lit
);
811 gen_arith3(ctx
, &gen_op_cmplt
, ra
, rb
, rc
, islit
, lit
);
815 gen_arith3(ctx
, &gen_op_addqv
, ra
, rb
, rc
, islit
, lit
);
819 gen_arith3(ctx
, &gen_op_subqv
, ra
, rb
, rc
, islit
, lit
);
823 gen_arith3(ctx
, &gen_op_cmple
, ra
, rb
, rc
, islit
, lit
);
833 gen_arith3(ctx
, &gen_op_and
, ra
, rb
, rc
, islit
, lit
);
837 gen_arith3(ctx
, &gen_op_bic
, ra
, rb
, rc
, islit
, lit
);
841 gen_cmov(ctx
, &gen_op_cmplbs
, ra
, rb
, rc
, islit
, lit
);
845 gen_cmov(ctx
, &gen_op_cmplbc
, ra
, rb
, rc
, islit
, lit
);
849 if (ra
== rb
|| ra
== 31 || rb
== 31) {
850 if (ra
== 31 && rc
== 31) {
855 gen_load_ir(ctx
, rb
, 0);
856 gen_store_ir(ctx
, rc
, 0);
859 gen_arith3(ctx
, &gen_op_bis
, ra
, rb
, rc
, islit
, lit
);
864 gen_cmov(ctx
, &gen_op_cmpeqz
, ra
, rb
, rc
, islit
, lit
);
868 gen_cmov(ctx
, &gen_op_cmpnez
, ra
, rb
, rc
, islit
, lit
);
872 gen_arith3(ctx
, &gen_op_ornot
, ra
, rb
, rc
, islit
, lit
);
876 gen_arith3(ctx
, &gen_op_xor
, ra
, rb
, rc
, islit
, lit
);
880 gen_cmov(ctx
, &gen_op_cmpltz
, ra
, rb
, rc
, islit
, lit
);
884 gen_cmov(ctx
, &gen_op_cmpgez
, ra
, rb
, rc
, islit
, lit
);
888 gen_arith3(ctx
, &gen_op_eqv
, ra
, rb
, rc
, islit
, lit
);
892 gen_arith2(ctx
, &gen_amask
, rb
, rc
, islit
, lit
);
896 gen_cmov(ctx
, &gen_op_cmplez
, ra
, rb
, rc
, islit
, lit
);
900 gen_cmov(ctx
, &gen_op_cmpgtz
, ra
, rb
, rc
, islit
, lit
);
904 gen_op_load_implver();
905 gen_store_ir(ctx
, rc
, 0);
915 gen_arith3(ctx
, &gen_op_mskbl
, ra
, rb
, rc
, islit
, lit
);
919 gen_arith3(ctx
, &gen_op_extbl
, ra
, rb
, rc
, islit
, lit
);
923 gen_arith3(ctx
, &gen_op_insbl
, ra
, rb
, rc
, islit
, lit
);
927 gen_arith3(ctx
, &gen_op_mskwl
, ra
, rb
, rc
, islit
, lit
);
931 gen_arith3(ctx
, &gen_op_extwl
, ra
, rb
, rc
, islit
, lit
);
935 gen_arith3(ctx
, &gen_op_inswl
, ra
, rb
, rc
, islit
, lit
);
939 gen_arith3(ctx
, &gen_op_mskll
, ra
, rb
, rc
, islit
, lit
);
943 gen_arith3(ctx
, &gen_op_extll
, ra
, rb
, rc
, islit
, lit
);
947 gen_arith3(ctx
, &gen_op_insll
, ra
, rb
, rc
, islit
, lit
);
951 gen_arith3(ctx
, &gen_op_zap
, ra
, rb
, rc
, islit
, lit
);
955 gen_arith3(ctx
, &gen_op_zapnot
, ra
, rb
, rc
, islit
, lit
);
959 gen_arith3(ctx
, &gen_op_mskql
, ra
, rb
, rc
, islit
, lit
);
963 gen_arith3(ctx
, &gen_op_srl
, ra
, rb
, rc
, islit
, lit
);
967 gen_arith3(ctx
, &gen_op_extql
, ra
, rb
, rc
, islit
, lit
);
971 gen_arith3(ctx
, &gen_op_sll
, ra
, rb
, rc
, islit
, lit
);
975 gen_arith3(ctx
, &gen_op_insql
, ra
, rb
, rc
, islit
, lit
);
979 gen_arith3(ctx
, &gen_op_sra
, ra
, rb
, rc
, islit
, lit
);
983 gen_arith3(ctx
, &gen_op_mskwh
, ra
, rb
, rc
, islit
, lit
);
987 gen_arith3(ctx
, &gen_op_inswh
, ra
, rb
, rc
, islit
, lit
);
991 gen_arith3(ctx
, &gen_op_extwh
, ra
, rb
, rc
, islit
, lit
);
995 gen_arith3(ctx
, &gen_op_msklh
, ra
, rb
, rc
, islit
, lit
);
999 gen_arith3(ctx
, &gen_op_inslh
, ra
, rb
, rc
, islit
, lit
);
1003 gen_arith3(ctx
, &gen_op_extlh
, ra
, rb
, rc
, islit
, lit
);
1007 gen_arith3(ctx
, &gen_op_mskqh
, ra
, rb
, rc
, islit
, lit
);
1011 gen_arith3(ctx
, &gen_op_insqh
, ra
, rb
, rc
, islit
, lit
);
1015 gen_arith3(ctx
, &gen_op_extqh
, ra
, rb
, rc
, islit
, lit
);
1025 gen_arith3(ctx
, &gen_op_mull
, ra
, rb
, rc
, islit
, lit
);
1029 gen_arith3(ctx
, &gen_op_mulq
, ra
, rb
, rc
, islit
, lit
);
1033 gen_arith3(ctx
, &gen_op_umulh
, ra
, rb
, rc
, islit
, lit
);
1037 gen_arith3(ctx
, &gen_op_mullv
, ra
, rb
, rc
, islit
, lit
);
1041 gen_arith3(ctx
, &gen_op_mulqv
, ra
, rb
, rc
, islit
, lit
);
1048 switch (fpfn
) { /* f11 & 0x3F */
1051 if (!(ctx
->amask
& AMASK_FIX
))
1053 gen_itf(ctx
, &gen_op_itofs
, ra
, rc
);
1057 if (!(ctx
->amask
& AMASK_FIX
))
1059 gen_farith2(ctx
, &gen_op_sqrtf
, rb
, rc
);
1063 if (!(ctx
->amask
& AMASK_FIX
))
1065 gen_farith2(ctx
, &gen_op_sqrts
, rb
, rc
);
1069 if (!(ctx
->amask
& AMASK_FIX
))
1072 gen_itf(ctx
, &gen_op_itoff
, ra
, rc
);
1079 if (!(ctx
->amask
& AMASK_FIX
))
1081 gen_itf(ctx
, &gen_op_itoft
, ra
, rc
);
1085 if (!(ctx
->amask
& AMASK_FIX
))
1087 gen_farith2(ctx
, &gen_op_sqrtg
, rb
, rc
);
1091 if (!(ctx
->amask
& AMASK_FIX
))
1093 gen_farith2(ctx
, &gen_op_sqrtt
, rb
, rc
);
1100 /* VAX floating point */
1101 /* XXX: rounding mode and trap are ignored (!) */
1102 switch (fpfn
) { /* f11 & 0x3F */
1105 gen_farith3(ctx
, &gen_op_addf
, ra
, rb
, rc
);
1109 gen_farith3(ctx
, &gen_op_subf
, ra
, rb
, rc
);
1113 gen_farith3(ctx
, &gen_op_mulf
, ra
, rb
, rc
);
1117 gen_farith3(ctx
, &gen_op_divf
, ra
, rb
, rc
);
1122 gen_farith2(ctx
, &gen_op_cvtdg
, rb
, rc
);
1129 gen_farith3(ctx
, &gen_op_addg
, ra
, rb
, rc
);
1133 gen_farith3(ctx
, &gen_op_subg
, ra
, rb
, rc
);
1137 gen_farith3(ctx
, &gen_op_mulg
, ra
, rb
, rc
);
1141 gen_farith3(ctx
, &gen_op_divg
, ra
, rb
, rc
);
1145 gen_farith3(ctx
, &gen_op_cmpgeq
, ra
, rb
, rc
);
1149 gen_farith3(ctx
, &gen_op_cmpglt
, ra
, rb
, rc
);
1153 gen_farith3(ctx
, &gen_op_cmpgle
, ra
, rb
, rc
);
1157 gen_farith2(ctx
, &gen_op_cvtgf
, rb
, rc
);
1162 gen_farith2(ctx
, &gen_op_cvtgd
, rb
, rc
);
1169 gen_farith2(ctx
, &gen_op_cvtgq
, rb
, rc
);
1173 gen_farith2(ctx
, &gen_op_cvtqf
, rb
, rc
);
1177 gen_farith2(ctx
, &gen_op_cvtqg
, rb
, rc
);
1184 /* IEEE floating-point */
1185 /* XXX: rounding mode and traps are ignored (!) */
1186 switch (fpfn
) { /* f11 & 0x3F */
1189 gen_farith3(ctx
, &gen_op_adds
, ra
, rb
, rc
);
1193 gen_farith3(ctx
, &gen_op_subs
, ra
, rb
, rc
);
1197 gen_farith3(ctx
, &gen_op_muls
, ra
, rb
, rc
);
1201 gen_farith3(ctx
, &gen_op_divs
, ra
, rb
, rc
);
1205 gen_farith3(ctx
, &gen_op_addt
, ra
, rb
, rc
);
1209 gen_farith3(ctx
, &gen_op_subt
, ra
, rb
, rc
);
1213 gen_farith3(ctx
, &gen_op_mult
, ra
, rb
, rc
);
1217 gen_farith3(ctx
, &gen_op_divt
, ra
, rb
, rc
);
1221 gen_farith3(ctx
, &gen_op_cmptun
, ra
, rb
, rc
);
1225 gen_farith3(ctx
, &gen_op_cmpteq
, ra
, rb
, rc
);
1229 gen_farith3(ctx
, &gen_op_cmptlt
, ra
, rb
, rc
);
1233 gen_farith3(ctx
, &gen_op_cmptle
, ra
, rb
, rc
);
1236 /* XXX: incorrect */
1237 if (fn11
== 0x2AC) {
1239 gen_farith2(ctx
, &gen_op_cvtst
, rb
, rc
);
1242 gen_farith2(ctx
, &gen_op_cvtts
, rb
, rc
);
1247 gen_farith2(ctx
, &gen_op_cvttq
, rb
, rc
);
1251 gen_farith2(ctx
, &gen_op_cvtqs
, rb
, rc
);
1255 gen_farith2(ctx
, &gen_op_cvtqt
, rb
, rc
);
1265 gen_farith2(ctx
, &gen_op_cvtlq
, rb
, rc
);
1270 if (ra
== 31 && rc
== 31) {
1275 gen_load_fir(ctx
, rb
, 0);
1276 gen_store_fir(ctx
, rc
, 0);
1279 gen_farith3(ctx
, &gen_op_cpys
, ra
, rb
, rc
);
1284 gen_farith2(ctx
, &gen_op_cpysn
, rb
, rc
);
1288 gen_farith2(ctx
, &gen_op_cpyse
, rb
, rc
);
1292 gen_load_fir(ctx
, ra
, 0);
1293 gen_op_store_fpcr();
1298 gen_store_fir(ctx
, ra
, 0);
1302 gen_fcmov(ctx
, &gen_op_cmpfeq
, ra
, rb
, rc
);
1306 gen_fcmov(ctx
, &gen_op_cmpfne
, ra
, rb
, rc
);
1310 gen_fcmov(ctx
, &gen_op_cmpflt
, ra
, rb
, rc
);
1314 gen_fcmov(ctx
, &gen_op_cmpfge
, ra
, rb
, rc
);
1318 gen_fcmov(ctx
, &gen_op_cmpfle
, ra
, rb
, rc
);
1322 gen_fcmov(ctx
, &gen_op_cmpfgt
, ra
, rb
, rc
);
1326 gen_farith2(ctx
, &gen_op_cvtql
, rb
, rc
);
1330 gen_farith2(ctx
, &gen_op_cvtqlv
, rb
, rc
);
1334 gen_farith2(ctx
, &gen_op_cvtqlsv
, rb
, rc
);
1341 switch ((uint16_t)disp16
) {
1344 /* No-op. Just exit from the current tb */
1349 /* No-op. Just exit from the current tb */
1371 gen_store_ir(ctx
, ra
, 0);
1376 gen_store_ir(ctx
, ra
, 0);
1381 /* XXX: TODO: evict tb cache at address rb */
1391 gen_store_ir(ctx
, ra
, 0);
1403 /* HW_MFPR (PALcode) */
1404 #if defined (CONFIG_USER_ONLY)
1409 gen_op_mfpr(insn
& 0xFF);
1410 gen_store_ir(ctx
, ra
, 0);
1414 gen_load_ir(ctx
, rb
, 0);
1416 gen_set_uT1(ctx
, ctx
->pc
);
1417 gen_store_ir(ctx
, ra
, 1);
1420 /* Those four jumps only differ by the branch prediction hint */
1438 /* HW_LD (PALcode) */
1439 #if defined (CONFIG_USER_ONLY)
1444 gen_load_ir(ctx
, rb
, 0);
1445 gen_set_sT1(ctx
, disp12
);
1447 switch ((insn
>> 12) & 0xF) {
1449 /* Longword physical access */
1453 /* Quadword physical access */
1457 /* Longword physical access with lock */
1461 /* Quadword physical access with lock */
1465 /* Longword virtual PTE fetch */
1466 gen_op_ldl_kernel();
1469 /* Quadword virtual PTE fetch */
1470 gen_op_ldq_kernel();
1479 /* Longword virtual access */
1480 gen_op_ld_phys_to_virt();
1484 /* Quadword virtual access */
1485 gen_op_ld_phys_to_virt();
1489 /* Longword virtual access with protection check */
1493 /* Quadword virtual access with protection check */
1497 /* Longword virtual access with altenate access mode */
1498 gen_op_set_alt_mode();
1499 gen_op_ld_phys_to_virt();
1501 gen_op_restore_mode();
1504 /* Quadword virtual access with altenate access mode */
1505 gen_op_set_alt_mode();
1506 gen_op_ld_phys_to_virt();
1508 gen_op_restore_mode();
1511 /* Longword virtual access with alternate access mode and
1514 gen_op_set_alt_mode();
1516 gen_op_restore_mode();
1519 /* Quadword virtual access with alternate access mode and
1522 gen_op_set_alt_mode();
1524 gen_op_restore_mode();
1527 gen_store_ir(ctx
, ra
, 1);
1534 if (!(ctx
->amask
& AMASK_BWX
))
1536 gen_arith2(ctx
, &gen_op_sextb
, rb
, rc
, islit
, lit
);
1540 if (!(ctx
->amask
& AMASK_BWX
))
1542 gen_arith2(ctx
, &gen_op_sextw
, rb
, rc
, islit
, lit
);
1546 if (!(ctx
->amask
& AMASK_CIX
))
1548 gen_arith2(ctx
, &gen_op_ctpop
, rb
, rc
, 0, 0);
1552 if (!(ctx
->amask
& AMASK_MVI
))
1559 if (!(ctx
->amask
& AMASK_CIX
))
1561 gen_arith2(ctx
, &gen_op_ctlz
, rb
, rc
, 0, 0);
1565 if (!(ctx
->amask
& AMASK_CIX
))
1567 gen_arith2(ctx
, &gen_op_cttz
, rb
, rc
, 0, 0);
1571 if (!(ctx
->amask
& AMASK_MVI
))
1578 if (!(ctx
->amask
& AMASK_MVI
))
1585 if (!(ctx
->amask
& AMASK_MVI
))
1592 if (!(ctx
->amask
& AMASK_MVI
))
1599 if (!(ctx
->amask
& AMASK_MVI
))
1606 if (!(ctx
->amask
& AMASK_MVI
))
1613 if (!(ctx
->amask
& AMASK_MVI
))
1620 if (!(ctx
->amask
& AMASK_MVI
))
1627 if (!(ctx
->amask
& AMASK_MVI
))
1634 if (!(ctx
->amask
& AMASK_MVI
))
1641 if (!(ctx
->amask
& AMASK_MVI
))
1648 if (!(ctx
->amask
& AMASK_MVI
))
1655 if (!(ctx
->amask
& AMASK_FIX
))
1657 gen_fti(ctx
, &gen_op_ftoit
, ra
, rb
);
1661 if (!(ctx
->amask
& AMASK_FIX
))
1663 gen_fti(ctx
, &gen_op_ftois
, ra
, rb
);
1670 /* HW_MTPR (PALcode) */
1671 #if defined (CONFIG_USER_ONLY)
1676 gen_load_ir(ctx
, ra
, 0);
1677 gen_op_mtpr(insn
& 0xFF);
1682 /* HW_REI (PALcode) */
1683 #if defined (CONFIG_USER_ONLY)
1692 gen_load_ir(ctx
, rb
, 0);
1693 gen_set_uT1(ctx
, (((int64_t)insn
<< 51) >> 51));
1701 /* HW_ST (PALcode) */
1702 #if defined (CONFIG_USER_ONLY)
1707 gen_load_ir(ctx
, rb
, 0);
1708 gen_set_sT1(ctx
, disp12
);
1710 gen_load_ir(ctx
, ra
, 1);
1711 switch ((insn
>> 12) & 0xF) {
1713 /* Longword physical access */
1717 /* Quadword physical access */
1721 /* Longword physical access with lock */
1725 /* Quadword physical access with lock */
1729 /* Longword virtual access */
1730 gen_op_st_phys_to_virt();
1734 /* Quadword virtual access */
1735 gen_op_st_phys_to_virt();
1757 /* Longword virtual access with alternate access mode */
1758 gen_op_set_alt_mode();
1759 gen_op_st_phys_to_virt();
1761 gen_op_restore_mode();
1764 /* Quadword virtual access with alternate access mode */
1765 gen_op_set_alt_mode();
1766 gen_op_st_phys_to_virt();
1768 gen_op_restore_mode();
1783 gen_load_fmem(ctx
, &gen_ldf
, ra
, rb
, disp16
);
1791 gen_load_fmem(ctx
, &gen_ldg
, ra
, rb
, disp16
);
1798 gen_load_fmem(ctx
, &gen_lds
, ra
, rb
, disp16
);
1802 gen_load_fmem(ctx
, &gen_ldt
, ra
, rb
, disp16
);
1807 gen_store_fmem(ctx
, &gen_stf
, ra
, rb
, disp16
);
1815 gen_store_fmem(ctx
, &gen_stg
, ra
, rb
, disp16
);
1822 gen_store_fmem(ctx
, &gen_sts
, ra
, rb
, disp16
);
1826 gen_store_fmem(ctx
, &gen_stt
, ra
, rb
, disp16
);
1830 gen_load_mem(ctx
, &gen_ldl
, ra
, rb
, disp16
, 0);
1834 gen_load_mem(ctx
, &gen_ldq
, ra
, rb
, disp16
, 0);
1838 gen_load_mem(ctx
, &gen_ldl_l
, ra
, rb
, disp16
, 0);
1842 gen_load_mem(ctx
, &gen_ldq_l
, ra
, rb
, disp16
, 0);
1846 gen_store_mem(ctx
, &gen_stl
, ra
, rb
, disp16
, 0);
1850 gen_store_mem(ctx
, &gen_stq
, ra
, rb
, disp16
, 0);
1854 gen_store_mem(ctx
, &gen_stl_c
, ra
, rb
, disp16
, 0);
1858 gen_store_mem(ctx
, &gen_stq_c
, ra
, rb
, disp16
, 0);
1862 gen_set_uT0(ctx
, ctx
->pc
);
1863 gen_store_ir(ctx
, ra
, 0);
1865 gen_set_sT1(ctx
, disp21
<< 2);
1873 gen_fbcond(ctx
, &gen_op_cmpfeq
, ra
, disp16
);
1878 gen_fbcond(ctx
, &gen_op_cmpflt
, ra
, disp16
);
1883 gen_fbcond(ctx
, &gen_op_cmpfle
, ra
, disp16
);
1888 gen_set_uT0(ctx
, ctx
->pc
);
1889 gen_store_ir(ctx
, ra
, 0);
1891 gen_set_sT1(ctx
, disp21
<< 2);
1899 gen_fbcond(ctx
, &gen_op_cmpfne
, ra
, disp16
);
1904 gen_fbcond(ctx
, &gen_op_cmpfge
, ra
, disp16
);
1909 gen_fbcond(ctx
, &gen_op_cmpfgt
, ra
, disp16
);
1914 gen_bcond(ctx
, &gen_op_cmplbc
, ra
, disp16
);
1919 gen_bcond(ctx
, &gen_op_cmpeqz
, ra
, disp16
);
1924 gen_bcond(ctx
, &gen_op_cmpltz
, ra
, disp16
);
1929 gen_bcond(ctx
, &gen_op_cmplez
, ra
, disp16
);
1934 gen_bcond(ctx
, &gen_op_cmplbs
, ra
, disp16
);
1939 gen_bcond(ctx
, &gen_op_cmpnez
, ra
, disp16
);
1944 gen_bcond(ctx
, &gen_op_cmpgez
, ra
, disp16
);
1949 gen_bcond(ctx
, &gen_op_cmpgtz
, ra
, disp16
);
1961 int gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
1964 #if defined ALPHA_DEBUG_DISAS
1965 static int insn_count
;
1967 DisasContext ctx
, *ctxp
= &ctx
;
1968 target_ulong pc_start
;
1970 uint16_t *gen_opc_end
;
1975 gen_opc_ptr
= gen_opc_buf
;
1976 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1977 gen_opparam_ptr
= gen_opparam_buf
;
1980 ctx
.amask
= env
->amask
;
1981 #if defined (CONFIG_USER_ONLY)
1984 ctx
.mem_idx
= ((env
->ps
>> 3) & 3);
1985 ctx
.pal_mode
= env
->ipr
[IPR_EXC_ADDR
] & 1;
1987 for (ret
= 0; ret
== 0;) {
1988 if (env
->nb_breakpoints
> 0) {
1989 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
1990 if (env
->breakpoints
[j
] == ctx
.pc
) {
1991 gen_excp(&ctx
, EXCP_DEBUG
, 0);
1997 j
= gen_opc_ptr
- gen_opc_buf
;
2001 gen_opc_instr_start
[lj
++] = 0;
2002 gen_opc_pc
[lj
] = ctx
.pc
;
2003 gen_opc_instr_start
[lj
] = 1;
2006 #if defined ALPHA_DEBUG_DISAS
2008 if (logfile
!= NULL
) {
2009 fprintf(logfile
, "pc " TARGET_FMT_lx
" mem_idx %d\n",
2010 ctx
.pc
, ctx
.mem_idx
);
2013 insn
= ldl_code(ctx
.pc
);
2014 #if defined ALPHA_DEBUG_DISAS
2016 if (logfile
!= NULL
) {
2017 fprintf(logfile
, "opcode %08x %d\n", insn
, insn_count
);
2021 ret
= translate_one(ctxp
, insn
);
2024 /* if we reach a page boundary or are single stepping, stop
2027 if (((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
2028 (env
->singlestep_enabled
)) {
2031 #if defined (DO_SINGLE_STEP)
2035 if (ret
!= 1 && ret
!= 3) {
2036 gen_update_pc(&ctx
);
2039 #if defined (DO_TB_FLUSH)
2042 /* Generate the return instruction */
2044 *gen_opc_ptr
= INDEX_op_end
;
2046 j
= gen_opc_ptr
- gen_opc_buf
;
2049 gen_opc_instr_start
[lj
++] = 0;
2052 tb
->size
= ctx
.pc
- pc_start
;
2054 #if defined ALPHA_DEBUG_DISAS
2055 if (loglevel
& CPU_LOG_TB_CPU
) {
2056 cpu_dump_state(env
, logfile
, fprintf
, 0);
2058 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2059 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2060 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 1);
2061 fprintf(logfile
, "\n");
2063 if (loglevel
& CPU_LOG_TB_OP
) {
2064 fprintf(logfile
, "OP:\n");
2065 dump_ops(gen_opc_buf
, gen_opparam_buf
);
2066 fprintf(logfile
, "\n");
2073 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2075 return gen_intermediate_code_internal(env
, tb
, 0);
2078 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2080 return gen_intermediate_code_internal(env
, tb
, 1);
2083 CPUAlphaState
* cpu_alpha_init (void)
2088 env
= qemu_mallocz(sizeof(CPUAlphaState
));
2093 /* XXX: should not be hardcoded */
2094 env
->implver
= IMPLVER_2106x
;
2096 #if defined (CONFIG_USER_ONLY)
2100 /* Initialize IPR */
2101 hwpcb
= env
->ipr
[IPR_PCBB
];
2102 env
->ipr
[IPR_ASN
] = 0;
2103 env
->ipr
[IPR_ASTEN
] = 0;
2104 env
->ipr
[IPR_ASTSR
] = 0;
2105 env
->ipr
[IPR_DATFX
] = 0;
2107 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2108 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2109 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2110 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2111 env
->ipr
[IPR_FEN
] = 0;
2112 env
->ipr
[IPR_IPL
] = 31;
2113 env
->ipr
[IPR_MCES
] = 0;
2114 env
->ipr
[IPR_PERFMON
] = 0; /* Implementation specific */
2115 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2116 env
->ipr
[IPR_SISR
] = 0;
2117 env
->ipr
[IPR_VIRBND
] = -1ULL;