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Add -m64 to OS_LDFLAGS for Solaris/x86_64. Use OS_CFLAGS when looking for
[qemu/qemu_0_9_1_stable.git] / hw / omap.c
blob1e79831d8fa4634a0419f5362c43ccca01175644
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21 #include "hw.h"
22 #include "arm-misc.h"
23 #include "omap.h"
24 #include "sysemu.h"
25 #include "qemu-timer.h"
26 /* We use pc-style serial ports. */
27 #include "pc.h"
28
29 /* Should signal the TCMI */
30 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
31 {
32 uint8_t ret;
33
34 OMAP_8B_REG(addr);
35 cpu_physical_memory_read(addr, (void *) &ret, 1);
36 return ret;
37 }
38
39 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
40 uint32_t value)
41 {
42 uint8_t val8 = value;
43
44 OMAP_8B_REG(addr);
45 cpu_physical_memory_write(addr, (void *) &val8, 1);
46 }
47
48 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
49 {
50 uint16_t ret;
51
52 OMAP_16B_REG(addr);
53 cpu_physical_memory_read(addr, (void *) &ret, 2);
54 return ret;
55 }
56
57 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
58 uint32_t value)
59 {
60 uint16_t val16 = value;
61
62 OMAP_16B_REG(addr);
63 cpu_physical_memory_write(addr, (void *) &val16, 2);
64 }
65
66 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
67 {
68 uint32_t ret;
69
70 OMAP_32B_REG(addr);
71 cpu_physical_memory_read(addr, (void *) &ret, 4);
72 return ret;
73 }
74
75 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
76 uint32_t value)
77 {
78 OMAP_32B_REG(addr);
79 cpu_physical_memory_write(addr, (void *) &value, 4);
80 }
81
82 /* Interrupt Handlers */
83 struct omap_intr_handler_s {
84 qemu_irq *pins;
85 qemu_irq *parent_pic;
86 target_phys_addr_t base;
87
88 /* state */
89 uint32_t irqs;
90 uint32_t mask;
91 uint32_t sens_edge;
92 uint32_t fiq;
93 int priority[32];
94 uint32_t new_irq_agr;
95 uint32_t new_fiq_agr;
96 int sir_irq;
97 int sir_fiq;
98 int stats[32];
99 };
100
101 static void omap_inth_update(struct omap_intr_handler_s *s)
102 {
103 uint32_t irq = s->irqs & ~s->mask & ~s->fiq;
104 uint32_t fiq = s->irqs & ~s->mask & s->fiq;
105
106 if (s->new_irq_agr || !irq) {
107 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ], irq);
108 if (irq)
109 s->new_irq_agr = 0;
110 }
111
112 if (s->new_fiq_agr || !irq) {
113 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ], fiq);
114 if (fiq)
115 s->new_fiq_agr = 0;
116 }
117 }
118
119 static void omap_inth_sir_update(struct omap_intr_handler_s *s)
120 {
121 int i, intr_irq, intr_fiq, p_irq, p_fiq, p, f;
122 uint32_t level = s->irqs & ~s->mask;
123
124 intr_irq = 0;
125 intr_fiq = 0;
126 p_irq = -1;
127 p_fiq = -1;
128 /* Find the interrupt line with the highest dynamic priority */
129 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, level >>= f) {
130 p = s->priority[i];
131 if (s->fiq & (1 << i)) {
132 if (p > p_fiq) {
133 p_fiq = p;
134 intr_fiq = i;
135 }
136 } else {
137 if (p > p_irq) {
138 p_irq = p;
139 intr_irq = i;
140 }
141 }
142
143 f = ffs(level >> 1);
144 }
145
146 s->sir_irq = intr_irq;
147 s->sir_fiq = intr_fiq;
148 }
149
150 #define INT_FALLING_EDGE 0
151 #define INT_LOW_LEVEL 1
152
153 static void omap_set_intr(void *opaque, int irq, int req)
154 {
155 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
156 uint32_t rise;
157
158 if (req) {
159 rise = ~ih->irqs & (1 << irq);
160 ih->irqs |= rise;
161 ih->stats[irq] += !!rise;
162 } else {
163 rise = ih->sens_edge & ih->irqs & (1 << irq);
164 ih->irqs &= ~rise;
165 }
166
167 if (rise & ~ih->mask) {
168 omap_inth_sir_update(ih);
169
170 omap_inth_update(ih);
171 }
172 }
173
174 static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
175 {
176 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
177 int i, offset = addr - s->base;
178
179 switch (offset) {
180 case 0x00: /* ITR */
181 return s->irqs;
182
183 case 0x04: /* MIR */
184 return s->mask;
185
186 case 0x10: /* SIR_IRQ_CODE */
187 i = s->sir_irq;
188 if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) {
189 s->irqs &= ~(1 << i);
190 omap_inth_sir_update(s);
191 omap_inth_update(s);
192 }
193 return i;
194
195 case 0x14: /* SIR_FIQ_CODE */
196 i = s->sir_fiq;
197 if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) {
198 s->irqs &= ~(1 << i);
199 omap_inth_sir_update(s);
200 omap_inth_update(s);
201 }
202 return i;
203
204 case 0x18: /* CONTROL_REG */
205 return 0;
206
207 case 0x1c: /* ILR0 */
208 case 0x20: /* ILR1 */
209 case 0x24: /* ILR2 */
210 case 0x28: /* ILR3 */
211 case 0x2c: /* ILR4 */
212 case 0x30: /* ILR5 */
213 case 0x34: /* ILR6 */
214 case 0x38: /* ILR7 */
215 case 0x3c: /* ILR8 */
216 case 0x40: /* ILR9 */
217 case 0x44: /* ILR10 */
218 case 0x48: /* ILR11 */
219 case 0x4c: /* ILR12 */
220 case 0x50: /* ILR13 */
221 case 0x54: /* ILR14 */
222 case 0x58: /* ILR15 */
223 case 0x5c: /* ILR16 */
224 case 0x60: /* ILR17 */
225 case 0x64: /* ILR18 */
226 case 0x68: /* ILR19 */
227 case 0x6c: /* ILR20 */
228 case 0x70: /* ILR21 */
229 case 0x74: /* ILR22 */
230 case 0x78: /* ILR23 */
231 case 0x7c: /* ILR24 */
232 case 0x80: /* ILR25 */
233 case 0x84: /* ILR26 */
234 case 0x88: /* ILR27 */
235 case 0x8c: /* ILR28 */
236 case 0x90: /* ILR29 */
237 case 0x94: /* ILR30 */
238 case 0x98: /* ILR31 */
239 i = (offset - 0x1c) >> 2;
240 return (s->priority[i] << 2) |
241 (((s->sens_edge >> i) & 1) << 1) |
242 ((s->fiq >> i) & 1);
243
244 case 0x9c: /* ISR */
245 return 0x00000000;
246
247 default:
248 OMAP_BAD_REG(addr);
249 break;
250 }
251 return 0;
252 }
253
254 static void omap_inth_write(void *opaque, target_phys_addr_t addr,
255 uint32_t value)
256 {
257 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
258 int i, offset = addr - s->base;
259
260 switch (offset) {
261 case 0x00: /* ITR */
262 s->irqs &= value | 1;
263 omap_inth_sir_update(s);
264 omap_inth_update(s);
265 return;
266
267 case 0x04: /* MIR */
268 s->mask = value;
269 omap_inth_sir_update(s);
270 omap_inth_update(s);
271 return;
272
273 case 0x10: /* SIR_IRQ_CODE */
274 case 0x14: /* SIR_FIQ_CODE */
275 OMAP_RO_REG(addr);
276 break;
277
278 case 0x18: /* CONTROL_REG */
279 if (value & 2)
280 s->new_fiq_agr = ~0;
281 if (value & 1)
282 s->new_irq_agr = ~0;
283 omap_inth_update(s);
284 return;
285
286 case 0x1c: /* ILR0 */
287 case 0x20: /* ILR1 */
288 case 0x24: /* ILR2 */
289 case 0x28: /* ILR3 */
290 case 0x2c: /* ILR4 */
291 case 0x30: /* ILR5 */
292 case 0x34: /* ILR6 */
293 case 0x38: /* ILR7 */
294 case 0x3c: /* ILR8 */
295 case 0x40: /* ILR9 */
296 case 0x44: /* ILR10 */
297 case 0x48: /* ILR11 */
298 case 0x4c: /* ILR12 */
299 case 0x50: /* ILR13 */
300 case 0x54: /* ILR14 */
301 case 0x58: /* ILR15 */
302 case 0x5c: /* ILR16 */
303 case 0x60: /* ILR17 */
304 case 0x64: /* ILR18 */
305 case 0x68: /* ILR19 */
306 case 0x6c: /* ILR20 */
307 case 0x70: /* ILR21 */
308 case 0x74: /* ILR22 */
309 case 0x78: /* ILR23 */
310 case 0x7c: /* ILR24 */
311 case 0x80: /* ILR25 */
312 case 0x84: /* ILR26 */
313 case 0x88: /* ILR27 */
314 case 0x8c: /* ILR28 */
315 case 0x90: /* ILR29 */
316 case 0x94: /* ILR30 */
317 case 0x98: /* ILR31 */
318 i = (offset - 0x1c) >> 2;
319 s->priority[i] = (value >> 2) & 0x1f;
320 s->sens_edge &= ~(1 << i);
321 s->sens_edge |= ((value >> 1) & 1) << i;
322 s->fiq &= ~(1 << i);
323 s->fiq |= (value & 1) << i;
324 return;
325
326 case 0x9c: /* ISR */
327 for (i = 0; i < 32; i ++)
328 if (value & (1 << i)) {
329 omap_set_intr(s, i, 1);
330 return;
331 }
332 return;
333
334 default:
335 OMAP_BAD_REG(addr);
336 }
337 }
338
339 static CPUReadMemoryFunc *omap_inth_readfn[] = {
340 omap_badwidth_read32,
341 omap_badwidth_read32,
342 omap_inth_read,
343 };
344
345 static CPUWriteMemoryFunc *omap_inth_writefn[] = {
346 omap_inth_write,
347 omap_inth_write,
348 omap_inth_write,
349 };
350
351 static void omap_inth_reset(struct omap_intr_handler_s *s)
352 {
353 s->irqs = 0x00000000;
354 s->mask = 0xffffffff;
355 s->sens_edge = 0x00000000;
356 s->fiq = 0x00000000;
357 memset(s->priority, 0, sizeof(s->priority));
358 s->new_irq_agr = ~0;
359 s->new_fiq_agr = ~0;
360 s->sir_irq = 0;
361 s->sir_fiq = 0;
362
363 omap_inth_update(s);
364 }
365
366 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
367 unsigned long size, qemu_irq parent[2], omap_clk clk)
368 {
369 int iomemtype;
370 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
371 qemu_mallocz(sizeof(struct omap_intr_handler_s));
372
373 s->parent_pic = parent;
374 s->base = base;
375 s->pins = qemu_allocate_irqs(omap_set_intr, s, 32);
376 omap_inth_reset(s);
377
378 iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
379 omap_inth_writefn, s);
380 cpu_register_physical_memory(s->base, size, iomemtype);
381
382 return s;
383 }
384
385 /* OMAP1 DMA module */
386 typedef enum {
387 constant = 0,
388 post_incremented,
389 single_index,
390 double_index,
391 } omap_dma_addressing_t;
392
393 struct omap_dma_channel_s {
394 int burst[2];
395 int pack[2];
396 enum omap_dma_port port[2];
397 target_phys_addr_t addr[2];
398 omap_dma_addressing_t mode[2];
399 int data_type;
400 int end_prog;
401 int repeat;
402 int auto_init;
403 int priority;
404 int fs;
405 int sync;
406 int running;
407 int interrupts;
408 int status;
409 int signalled;
410 int post_sync;
411 int transfer;
412 uint16_t elements;
413 uint16_t frames;
414 uint16_t frame_index;
415 uint16_t element_index;
416 uint16_t cpc;
417
418 struct omap_dma_reg_set_s {
419 target_phys_addr_t src, dest;
420 int frame;
421 int element;
422 int frame_delta[2];
423 int elem_delta[2];
424 int frames;
425 int elements;
426 } active_set;
427 };
428
429 struct omap_dma_s {
430 qemu_irq *ih;
431 QEMUTimer *tm;
432 struct omap_mpu_state_s *mpu;
433 target_phys_addr_t base;
434 omap_clk clk;
435 int64_t delay;
436 uint32_t drq;
437
438 uint16_t gcr;
439 int run_count;
440
441 int chans;
442 struct omap_dma_channel_s ch[16];
443 struct omap_dma_lcd_channel_s lcd_ch;
444 };
445
446 static void omap_dma_interrupts_update(struct omap_dma_s *s)
447 {
448 /* First three interrupts are shared between two channels each. */
449 qemu_set_irq(s->ih[OMAP_INT_DMA_CH0_6],
450 (s->ch[0].status | s->ch[6].status) & 0x3f);
451 qemu_set_irq(s->ih[OMAP_INT_DMA_CH1_7],
452 (s->ch[1].status | s->ch[7].status) & 0x3f);
453 qemu_set_irq(s->ih[OMAP_INT_DMA_CH2_8],
454 (s->ch[2].status | s->ch[8].status) & 0x3f);
455 qemu_set_irq(s->ih[OMAP_INT_DMA_CH3],
456 (s->ch[3].status) & 0x3f);
457 qemu_set_irq(s->ih[OMAP_INT_DMA_CH4],
458 (s->ch[4].status) & 0x3f);
459 qemu_set_irq(s->ih[OMAP_INT_DMA_CH5],
460 (s->ch[5].status) & 0x3f);
461 }
462
463 static void omap_dma_channel_load(struct omap_dma_s *s, int ch)
464 {
465 struct omap_dma_reg_set_s *a = &s->ch[ch].active_set;
466 int i;
467
468 /*
469 * TODO: verify address ranges and alignment
470 * TODO: port endianness
471 */
472
473 a->src = s->ch[ch].addr[0];
474 a->dest = s->ch[ch].addr[1];
475 a->frames = s->ch[ch].frames;
476 a->elements = s->ch[ch].elements;
477 a->frame = 0;
478 a->element = 0;
479
480 if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) {
481 printf("%s: bad DMA request\n", __FUNCTION__);
482 return;
483 }
484
485 for (i = 0; i < 2; i ++)
486 switch (s->ch[ch].mode[i]) {
487 case constant:
488 a->elem_delta[i] = 0;
489 a->frame_delta[i] = 0;
490 break;
491 case post_incremented:
492 a->elem_delta[i] = s->ch[ch].data_type;
493 a->frame_delta[i] = 0;
494 break;
495 case single_index:
496 a->elem_delta[i] = s->ch[ch].data_type +
497 s->ch[ch].element_index - 1;
498 if (s->ch[ch].element_index > 0x7fff)
499 a->elem_delta[i] -= 0x10000;
500 a->frame_delta[i] = 0;
501 break;
502 case double_index:
503 a->elem_delta[i] = s->ch[ch].data_type +
504 s->ch[ch].element_index - 1;
505 if (s->ch[ch].element_index > 0x7fff)
506 a->elem_delta[i] -= 0x10000;
507 a->frame_delta[i] = s->ch[ch].frame_index -
508 s->ch[ch].element_index;
509 if (s->ch[ch].frame_index > 0x7fff)
510 a->frame_delta[i] -= 0x10000;
511 break;
512 default:
513 break;
514 }
515 }
516
517 static inline void omap_dma_request_run(struct omap_dma_s *s,
518 int channel, int request)
519 {
520 next_channel:
521 if (request > 0)
522 for (; channel < 9; channel ++)
523 if (s->ch[channel].sync == request && s->ch[channel].running)
524 break;
525 if (channel >= 9)
526 return;
527
528 if (s->ch[channel].transfer) {
529 if (request > 0) {
530 s->ch[channel ++].post_sync = request;
531 goto next_channel;
532 }
533 s->ch[channel].status |= 0x02; /* Synchronisation drop */
534 omap_dma_interrupts_update(s);
535 return;
536 }
537
538 if (!s->ch[channel].signalled)
539 s->run_count ++;
540 s->ch[channel].signalled = 1;
541
542 if (request > 0)
543 s->ch[channel].status |= 0x40; /* External request */
544
545 if (s->delay && !qemu_timer_pending(s->tm))
546 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
547
548 if (request > 0) {
549 channel ++;
550 goto next_channel;
551 }
552 }
553
554 static inline void omap_dma_request_stop(struct omap_dma_s *s, int channel)
555 {
556 if (s->ch[channel].signalled)
557 s->run_count --;
558 s->ch[channel].signalled = 0;
559
560 if (!s->run_count)
561 qemu_del_timer(s->tm);
562 }
563
564 static void omap_dma_channel_run(struct omap_dma_s *s)
565 {
566 int ch;
567 uint16_t status;
568 uint8_t value[4];
569 struct omap_dma_port_if_s *src_p, *dest_p;
570 struct omap_dma_reg_set_s *a;
571
572 for (ch = 0; ch < 9; ch ++) {
573 a = &s->ch[ch].active_set;
574
575 src_p = &s->mpu->port[s->ch[ch].port[0]];
576 dest_p = &s->mpu->port[s->ch[ch].port[1]];
577 if (s->ch[ch].signalled && (!src_p->addr_valid(s->mpu, a->src) ||
578 !dest_p->addr_valid(s->mpu, a->dest))) {
579 #if 0
580 /* Bus time-out */
581 if (s->ch[ch].interrupts & 0x01)
582 s->ch[ch].status |= 0x01;
583 omap_dma_request_stop(s, ch);
584 continue;
585 #endif
586 printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch);
587 }
588
589 status = s->ch[ch].status;
590 while (status == s->ch[ch].status && s->ch[ch].signalled) {
591 /* Transfer a single element */
592 s->ch[ch].transfer = 1;
593 cpu_physical_memory_read(a->src, value, s->ch[ch].data_type);
594 cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type);
595 s->ch[ch].transfer = 0;
596
597 a->src += a->elem_delta[0];
598 a->dest += a->elem_delta[1];
599 a->element ++;
600
601 /* Check interrupt conditions */
602 if (a->element == a->elements) {
603 a->element = 0;
604 a->src += a->frame_delta[0];
605 a->dest += a->frame_delta[1];
606 a->frame ++;
607
608 if (a->frame == a->frames) {
609 if (!s->ch[ch].repeat || !s->ch[ch].auto_init)
610 s->ch[ch].running = 0;
611
612 if (s->ch[ch].auto_init &&
613 (s->ch[ch].repeat ||
614 s->ch[ch].end_prog))
615 omap_dma_channel_load(s, ch);
616
617 if (s->ch[ch].interrupts & 0x20)
618 s->ch[ch].status |= 0x20;
619
620 if (!s->ch[ch].sync)
621 omap_dma_request_stop(s, ch);
622 }
623
624 if (s->ch[ch].interrupts & 0x08)
625 s->ch[ch].status |= 0x08;
626
627 if (s->ch[ch].sync && s->ch[ch].fs &&
628 !(s->drq & (1 << s->ch[ch].sync))) {
629 s->ch[ch].status &= ~0x40;
630 omap_dma_request_stop(s, ch);
631 }
632 }
633
634 if (a->element == 1 && a->frame == a->frames - 1)
635 if (s->ch[ch].interrupts & 0x10)
636 s->ch[ch].status |= 0x10;
637
638 if (a->element == (a->elements >> 1))
639 if (s->ch[ch].interrupts & 0x04)
640 s->ch[ch].status |= 0x04;
641
642 if (s->ch[ch].sync && !s->ch[ch].fs &&
643 !(s->drq & (1 << s->ch[ch].sync))) {
644 s->ch[ch].status &= ~0x40;
645 omap_dma_request_stop(s, ch);
646 }
647
648 /*
649 * Process requests made while the element was
650 * being transferred.
651 */
652 if (s->ch[ch].post_sync) {
653 omap_dma_request_run(s, 0, s->ch[ch].post_sync);
654 s->ch[ch].post_sync = 0;
655 }
656
657 #if 0
658 break;
659 #endif
660 }
661
662 s->ch[ch].cpc = a->dest & 0x0000ffff;
663 }
664
665 omap_dma_interrupts_update(s);
666 if (s->run_count && s->delay)
667 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
668 }
669
670 static int omap_dma_ch_reg_read(struct omap_dma_s *s,
671 int ch, int reg, uint16_t *value) {
672 switch (reg) {
673 case 0x00: /* SYS_DMA_CSDP_CH0 */
674 *value = (s->ch[ch].burst[1] << 14) |
675 (s->ch[ch].pack[1] << 13) |
676 (s->ch[ch].port[1] << 9) |
677 (s->ch[ch].burst[0] << 7) |
678 (s->ch[ch].pack[0] << 6) |
679 (s->ch[ch].port[0] << 2) |
680 (s->ch[ch].data_type >> 1);
681 break;
682
683 case 0x02: /* SYS_DMA_CCR_CH0 */
684 *value = (s->ch[ch].mode[1] << 14) |
685 (s->ch[ch].mode[0] << 12) |
686 (s->ch[ch].end_prog << 11) |
687 (s->ch[ch].repeat << 9) |
688 (s->ch[ch].auto_init << 8) |
689 (s->ch[ch].running << 7) |
690 (s->ch[ch].priority << 6) |
691 (s->ch[ch].fs << 5) | s->ch[ch].sync;
692 break;
693
694 case 0x04: /* SYS_DMA_CICR_CH0 */
695 *value = s->ch[ch].interrupts;
696 break;
697
698 case 0x06: /* SYS_DMA_CSR_CH0 */
699 /* FIXME: shared CSR for channels sharing the interrupts */
700 *value = s->ch[ch].status;
701 s->ch[ch].status &= 0x40;
702 omap_dma_interrupts_update(s);
703 break;
704
705 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
706 *value = s->ch[ch].addr[0] & 0x0000ffff;
707 break;
708
709 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
710 *value = s->ch[ch].addr[0] >> 16;
711 break;
712
713 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
714 *value = s->ch[ch].addr[1] & 0x0000ffff;
715 break;
716
717 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
718 *value = s->ch[ch].addr[1] >> 16;
719 break;
720
721 case 0x10: /* SYS_DMA_CEN_CH0 */
722 *value = s->ch[ch].elements;
723 break;
724
725 case 0x12: /* SYS_DMA_CFN_CH0 */
726 *value = s->ch[ch].frames;
727 break;
728
729 case 0x14: /* SYS_DMA_CFI_CH0 */
730 *value = s->ch[ch].frame_index;
731 break;
732
733 case 0x16: /* SYS_DMA_CEI_CH0 */
734 *value = s->ch[ch].element_index;
735 break;
736
737 case 0x18: /* SYS_DMA_CPC_CH0 */
738 *value = s->ch[ch].cpc;
739 break;
740
741 default:
742 return 1;
743 }
744 return 0;
745 }
746
747 static int omap_dma_ch_reg_write(struct omap_dma_s *s,
748 int ch, int reg, uint16_t value) {
749 switch (reg) {
750 case 0x00: /* SYS_DMA_CSDP_CH0 */
751 s->ch[ch].burst[1] = (value & 0xc000) >> 14;
752 s->ch[ch].pack[1] = (value & 0x2000) >> 13;
753 s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
754 s->ch[ch].burst[0] = (value & 0x0180) >> 7;
755 s->ch[ch].pack[0] = (value & 0x0040) >> 6;
756 s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
757 s->ch[ch].data_type = (1 << (value & 3));
758 if (s->ch[ch].port[0] >= omap_dma_port_last)
759 printf("%s: invalid DMA port %i\n", __FUNCTION__,
760 s->ch[ch].port[0]);
761 if (s->ch[ch].port[1] >= omap_dma_port_last)
762 printf("%s: invalid DMA port %i\n", __FUNCTION__,
763 s->ch[ch].port[1]);
764 if ((value & 3) == 3)
765 printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch);
766 break;
767
768 case 0x02: /* SYS_DMA_CCR_CH0 */
769 s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
770 s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
771 s->ch[ch].end_prog = (value & 0x0800) >> 11;
772 s->ch[ch].repeat = (value & 0x0200) >> 9;
773 s->ch[ch].auto_init = (value & 0x0100) >> 8;
774 s->ch[ch].priority = (value & 0x0040) >> 6;
775 s->ch[ch].fs = (value & 0x0020) >> 5;
776 s->ch[ch].sync = value & 0x001f;
777 if (value & 0x0080) {
778 if (s->ch[ch].running) {
779 if (!s->ch[ch].signalled &&
780 s->ch[ch].auto_init && s->ch[ch].end_prog)
781 omap_dma_channel_load(s, ch);
782 } else {
783 s->ch[ch].running = 1;
784 omap_dma_channel_load(s, ch);
785 }
786 if (!s->ch[ch].sync || (s->drq & (1 << s->ch[ch].sync)))
787 omap_dma_request_run(s, ch, 0);
788 } else {
789 s->ch[ch].running = 0;
790 omap_dma_request_stop(s, ch);
791 }
792 break;
793
794 case 0x04: /* SYS_DMA_CICR_CH0 */
795 s->ch[ch].interrupts = value & 0x003f;
796 break;
797
798 case 0x06: /* SYS_DMA_CSR_CH0 */
799 return 1;
800
801 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
802 s->ch[ch].addr[0] &= 0xffff0000;
803 s->ch[ch].addr[0] |= value;
804 break;
805
806 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
807 s->ch[ch].addr[0] &= 0x0000ffff;
808 s->ch[ch].addr[0] |= (uint32_t) value << 16;
809 break;
810
811 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
812 s->ch[ch].addr[1] &= 0xffff0000;
813 s->ch[ch].addr[1] |= value;
814 break;
815
816 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
817 s->ch[ch].addr[1] &= 0x0000ffff;
818 s->ch[ch].addr[1] |= (uint32_t) value << 16;
819 break;
820
821 case 0x10: /* SYS_DMA_CEN_CH0 */
822 s->ch[ch].elements = value & 0xffff;
823 break;
824
825 case 0x12: /* SYS_DMA_CFN_CH0 */
826 s->ch[ch].frames = value & 0xffff;
827 break;
828
829 case 0x14: /* SYS_DMA_CFI_CH0 */
830 s->ch[ch].frame_index = value & 0xffff;
831 break;
832
833 case 0x16: /* SYS_DMA_CEI_CH0 */
834 s->ch[ch].element_index = value & 0xffff;
835 break;
836
837 case 0x18: /* SYS_DMA_CPC_CH0 */
838 return 1;
839
840 default:
841 OMAP_BAD_REG((target_phys_addr_t) reg);
842 }
843 return 0;
844 }
845
846 static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
847 {
848 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
849 int i, reg, ch, offset = addr - s->base;
850 uint16_t ret;
851
852 switch (offset) {
853 case 0x000 ... 0x2fe:
854 reg = offset & 0x3f;
855 ch = (offset >> 6) & 0x0f;
856 if (omap_dma_ch_reg_read(s, ch, reg, &ret))
857 break;
858 return ret;
859
860 case 0x300: /* SYS_DMA_LCD_CTRL */
861 i = s->lcd_ch.condition;
862 s->lcd_ch.condition = 0;
863 qemu_irq_lower(s->lcd_ch.irq);
864 return ((s->lcd_ch.src == imif) << 6) | (i << 3) |
865 (s->lcd_ch.interrupts << 1) | s->lcd_ch.dual;
866
867 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
868 return s->lcd_ch.src_f1_top & 0xffff;
869
870 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
871 return s->lcd_ch.src_f1_top >> 16;
872
873 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
874 return s->lcd_ch.src_f1_bottom & 0xffff;
875
876 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
877 return s->lcd_ch.src_f1_bottom >> 16;
878
879 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
880 return s->lcd_ch.src_f2_top & 0xffff;
881
882 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
883 return s->lcd_ch.src_f2_top >> 16;
884
885 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
886 return s->lcd_ch.src_f2_bottom & 0xffff;
887
888 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
889 return s->lcd_ch.src_f2_bottom >> 16;
890
891 case 0x400: /* SYS_DMA_GCR */
892 return s->gcr;
893 }
894
895 OMAP_BAD_REG(addr);
896 return 0;
897 }
898
899 static void omap_dma_write(void *opaque, target_phys_addr_t addr,
900 uint32_t value)
901 {
902 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
903 int reg, ch, offset = addr - s->base;
904
905 switch (offset) {
906 case 0x000 ... 0x2fe:
907 reg = offset & 0x3f;
908 ch = (offset >> 6) & 0x0f;
909 if (omap_dma_ch_reg_write(s, ch, reg, value))
910 OMAP_RO_REG(addr);
911 break;
912
913 case 0x300: /* SYS_DMA_LCD_CTRL */
914 s->lcd_ch.src = (value & 0x40) ? imif : emiff;
915 s->lcd_ch.condition = 0;
916 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
917 s->lcd_ch.interrupts = (value >> 1) & 1;
918 s->lcd_ch.dual = value & 1;
919 break;
920
921 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
922 s->lcd_ch.src_f1_top &= 0xffff0000;
923 s->lcd_ch.src_f1_top |= 0x0000ffff & value;
924 break;
925
926 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
927 s->lcd_ch.src_f1_top &= 0x0000ffff;
928 s->lcd_ch.src_f1_top |= value << 16;
929 break;
930
931 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
932 s->lcd_ch.src_f1_bottom &= 0xffff0000;
933 s->lcd_ch.src_f1_bottom |= 0x0000ffff & value;
934 break;
935
936 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
937 s->lcd_ch.src_f1_bottom &= 0x0000ffff;
938 s->lcd_ch.src_f1_bottom |= value << 16;
939 break;
940
941 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
942 s->lcd_ch.src_f2_top &= 0xffff0000;
943 s->lcd_ch.src_f2_top |= 0x0000ffff & value;
944 break;
945
946 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
947 s->lcd_ch.src_f2_top &= 0x0000ffff;
948 s->lcd_ch.src_f2_top |= value << 16;
949 break;
950
951 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
952 s->lcd_ch.src_f2_bottom &= 0xffff0000;
953 s->lcd_ch.src_f2_bottom |= 0x0000ffff & value;
954 break;
955
956 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
957 s->lcd_ch.src_f2_bottom &= 0x0000ffff;
958 s->lcd_ch.src_f2_bottom |= value << 16;
959 break;
960
961 case 0x400: /* SYS_DMA_GCR */
962 s->gcr = value & 0x000c;
963 break;
964
965 default:
966 OMAP_BAD_REG(addr);
967 }
968 }
969
970 static CPUReadMemoryFunc *omap_dma_readfn[] = {
971 omap_badwidth_read16,
972 omap_dma_read,
973 omap_badwidth_read16,
974 };
975
976 static CPUWriteMemoryFunc *omap_dma_writefn[] = {
977 omap_badwidth_write16,
978 omap_dma_write,
979 omap_badwidth_write16,
980 };
981
982 static void omap_dma_request(void *opaque, int drq, int req)
983 {
984 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
985 /* The request pins are level triggered. */
986 if (req) {
987 if (~s->drq & (1 << drq)) {
988 s->drq |= 1 << drq;
989 omap_dma_request_run(s, 0, drq);
990 }
991 } else
992 s->drq &= ~(1 << drq);
993 }
994
995 static void omap_dma_clk_update(void *opaque, int line, int on)
996 {
997 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
998
999 if (on) {
1000 s->delay = ticks_per_sec >> 7;
1001 if (s->run_count)
1002 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
1003 } else {
1004 s->delay = 0;
1005 qemu_del_timer(s->tm);
1006 }
1007 }
1008
1009 static void omap_dma_reset(struct omap_dma_s *s)
1010 {
1011 int i;
1012
1013 qemu_del_timer(s->tm);
1014 s->gcr = 0x0004;
1015 s->drq = 0x00000000;
1016 s->run_count = 0;
1017 s->lcd_ch.src = emiff;
1018 s->lcd_ch.condition = 0;
1019 s->lcd_ch.interrupts = 0;
1020 s->lcd_ch.dual = 0;
1021 memset(s->ch, 0, sizeof(s->ch));
1022 for (i = 0; i < s->chans; i ++)
1023 s->ch[i].interrupts = 0x0003;
1024 }
1025
1026 struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
1027 qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk)
1028 {
1029 int iomemtype;
1030 struct omap_dma_s *s = (struct omap_dma_s *)
1031 qemu_mallocz(sizeof(struct omap_dma_s));
1032
1033 s->ih = pic;
1034 s->base = base;
1035 s->chans = 9;
1036 s->mpu = mpu;
1037 s->clk = clk;
1038 s->lcd_ch.irq = pic[OMAP_INT_DMA_LCD];
1039 s->lcd_ch.mpu = mpu;
1040 s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s);
1041 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
1042 mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1043 omap_dma_reset(s);
1044 omap_dma_clk_update(s, 0, 1);
1045
1046 iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
1047 omap_dma_writefn, s);
1048 cpu_register_physical_memory(s->base, 0x800, iomemtype);
1049
1050 return s;
1051 }
1052
1053 /* DMA ports */
1054 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
1055 target_phys_addr_t addr)
1056 {
1057 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
1058 }
1059
1060 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
1061 target_phys_addr_t addr)
1062 {
1063 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
1064 }
1065
1066 static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
1067 target_phys_addr_t addr)
1068 {
1069 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
1070 }
1071
1072 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
1073 target_phys_addr_t addr)
1074 {
1075 return addr >= 0xfffb0000 && addr < 0xffff0000;
1076 }
1077
1078 static int omap_validate_local_addr(struct omap_mpu_state_s *s,
1079 target_phys_addr_t addr)
1080 {
1081 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
1082 }
1083
1084 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
1085 target_phys_addr_t addr)
1086 {
1087 return addr >= 0xe1010000 && addr < 0xe1020004;
1088 }
1089
1090 /* MPU OS timers */
1091 struct omap_mpu_timer_s {
1092 qemu_irq irq;
1093 omap_clk clk;
1094 target_phys_addr_t base;
1095 uint32_t val;
1096 int64_t time;
1097 QEMUTimer *timer;
1098 int64_t rate;
1099 int it_ena;
1100
1101 int enable;
1102 int ptv;
1103 int ar;
1104 int st;
1105 uint32_t reset_val;
1106 };
1107
1108 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
1109 {
1110 uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
1111
1112 if (timer->st && timer->enable && timer->rate)
1113 return timer->val - muldiv64(distance >> (timer->ptv + 1),
1114 timer->rate, ticks_per_sec);
1115 else
1116 return timer->val;
1117 }
1118
1119 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
1120 {
1121 timer->val = omap_timer_read(timer);
1122 timer->time = qemu_get_clock(vm_clock);
1123 }
1124
1125 static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
1126 {
1127 int64_t expires;
1128
1129 if (timer->enable && timer->st && timer->rate) {
1130 timer->val = timer->reset_val; /* Should skip this on clk enable */
1131 expires = muldiv64(timer->val << (timer->ptv + 1),
1132 ticks_per_sec, timer->rate);
1133
1134 /* If timer expiry would be sooner than in about 1 ms and
1135 * auto-reload isn't set, then fire immediately. This is a hack
1136 * to make systems like PalmOS run in acceptable time. PalmOS
1137 * sets the interval to a very low value and polls the status bit
1138 * in a busy loop when it wants to sleep just a couple of CPU
1139 * ticks. */
1140 if (expires > (ticks_per_sec >> 10) || timer->ar)
1141 qemu_mod_timer(timer->timer, timer->time + expires);
1142 else {
1143 timer->val = 0;
1144 timer->st = 0;
1145 if (timer->it_ena)
1146 qemu_irq_raise(timer->irq);
1147 }
1148 } else
1149 qemu_del_timer(timer->timer);
1150 }
1151
1152 static void omap_timer_tick(void *opaque)
1153 {
1154 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
1155 omap_timer_sync(timer);
1156
1157 if (!timer->ar) {
1158 timer->val = 0;
1159 timer->st = 0;
1160 }
1161
1162 if (timer->it_ena)
1163 qemu_irq_raise(timer->irq);
1164 omap_timer_update(timer);
1165 }
1166
1167 static void omap_timer_clk_update(void *opaque, int line, int on)
1168 {
1169 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
1170
1171 omap_timer_sync(timer);
1172 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
1173 omap_timer_update(timer);
1174 }
1175
1176 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
1177 {
1178 omap_clk_adduser(timer->clk,
1179 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
1180 timer->rate = omap_clk_getrate(timer->clk);
1181 }
1182
1183 static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
1184 {
1185 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
1186 int offset = addr - s->base;
1187
1188 switch (offset) {
1189 case 0x00: /* CNTL_TIMER */
1190 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
1191
1192 case 0x04: /* LOAD_TIM */
1193 break;
1194
1195 case 0x08: /* READ_TIM */
1196 return omap_timer_read(s);
1197 }
1198
1199 OMAP_BAD_REG(addr);
1200 return 0;
1201 }
1202
1203 static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
1204 uint32_t value)
1205 {
1206 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
1207 int offset = addr - s->base;
1208
1209 switch (offset) {
1210 case 0x00: /* CNTL_TIMER */
1211 omap_timer_sync(s);
1212 s->enable = (value >> 5) & 1;
1213 s->ptv = (value >> 2) & 7;
1214 s->ar = (value >> 1) & 1;
1215 s->st = value & 1;
1216 omap_timer_update(s);
1217 return;
1218
1219 case 0x04: /* LOAD_TIM */
1220 s->reset_val = value;
1221 return;
1222
1223 case 0x08: /* READ_TIM */
1224 OMAP_RO_REG(addr);
1225 break;
1226
1227 default:
1228 OMAP_BAD_REG(addr);
1229 }
1230 }
1231
1232 static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
1233 omap_badwidth_read32,
1234 omap_badwidth_read32,
1235 omap_mpu_timer_read,
1236 };
1237
1238 static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
1239 omap_badwidth_write32,
1240 omap_badwidth_write32,
1241 omap_mpu_timer_write,
1242 };
1243
1244 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
1245 {
1246 qemu_del_timer(s->timer);
1247 s->enable = 0;
1248 s->reset_val = 31337;
1249 s->val = 0;
1250 s->ptv = 0;
1251 s->ar = 0;
1252 s->st = 0;
1253 s->it_ena = 1;
1254 }
1255
1256 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
1257 qemu_irq irq, omap_clk clk)
1258 {
1259 int iomemtype;
1260 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
1261 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
1262
1263 s->irq = irq;
1264 s->clk = clk;
1265 s->base = base;
1266 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
1267 omap_mpu_timer_reset(s);
1268 omap_timer_clk_setup(s);
1269
1270 iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
1271 omap_mpu_timer_writefn, s);
1272 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1273
1274 return s;
1275 }
1276
1277 /* Watchdog timer */
1278 struct omap_watchdog_timer_s {
1279 struct omap_mpu_timer_s timer;
1280 uint8_t last_wr;
1281 int mode;
1282 int free;
1283 int reset;
1284 };
1285
1286 static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
1287 {
1288 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
1289 int offset = addr - s->timer.base;
1290
1291 switch (offset) {
1292 case 0x00: /* CNTL_TIMER */
1293 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
1294 (s->timer.st << 7) | (s->free << 1);
1295
1296 case 0x04: /* READ_TIMER */
1297 return omap_timer_read(&s->timer);
1298
1299 case 0x08: /* TIMER_MODE */
1300 return s->mode << 15;
1301 }
1302
1303 OMAP_BAD_REG(addr);
1304 return 0;
1305 }
1306
1307 static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
1308 uint32_t value)
1309 {
1310 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
1311 int offset = addr - s->timer.base;
1312
1313 switch (offset) {
1314 case 0x00: /* CNTL_TIMER */
1315 omap_timer_sync(&s->timer);
1316 s->timer.ptv = (value >> 9) & 7;
1317 s->timer.ar = (value >> 8) & 1;
1318 s->timer.st = (value >> 7) & 1;
1319 s->free = (value >> 1) & 1;
1320 omap_timer_update(&s->timer);
1321 break;
1322
1323 case 0x04: /* LOAD_TIMER */
1324 s->timer.reset_val = value & 0xffff;
1325 break;
1326
1327 case 0x08: /* TIMER_MODE */
1328 if (!s->mode && ((value >> 15) & 1))
1329 omap_clk_get(s->timer.clk);
1330 s->mode |= (value >> 15) & 1;
1331 if (s->last_wr == 0xf5) {
1332 if ((value & 0xff) == 0xa0) {
1333 if (s->mode) {
1334 s->mode = 0;
1335 omap_clk_put(s->timer.clk);
1336 }
1337 } else {
1338 /* XXX: on T|E hardware somehow this has no effect,
1339 * on Zire 71 it works as specified. */
1340 s->reset = 1;
1341 qemu_system_reset_request();
1342 }
1343 }
1344 s->last_wr = value & 0xff;
1345 break;
1346
1347 default:
1348 OMAP_BAD_REG(addr);
1349 }
1350 }
1351
1352 static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
1353 omap_badwidth_read16,
1354 omap_wd_timer_read,
1355 omap_badwidth_read16,
1356 };
1357
1358 static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
1359 omap_badwidth_write16,
1360 omap_wd_timer_write,
1361 omap_badwidth_write16,
1362 };
1363
1364 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
1365 {
1366 qemu_del_timer(s->timer.timer);
1367 if (!s->mode)
1368 omap_clk_get(s->timer.clk);
1369 s->mode = 1;
1370 s->free = 1;
1371 s->reset = 0;
1372 s->timer.enable = 1;
1373 s->timer.it_ena = 1;
1374 s->timer.reset_val = 0xffff;
1375 s->timer.val = 0;
1376 s->timer.st = 0;
1377 s->timer.ptv = 0;
1378 s->timer.ar = 0;
1379 omap_timer_update(&s->timer);
1380 }
1381
1382 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
1383 qemu_irq irq, omap_clk clk)
1384 {
1385 int iomemtype;
1386 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
1387 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
1388
1389 s->timer.irq = irq;
1390 s->timer.clk = clk;
1391 s->timer.base = base;
1392 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1393 omap_wd_timer_reset(s);
1394 omap_timer_clk_setup(&s->timer);
1395
1396 iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
1397 omap_wd_timer_writefn, s);
1398 cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
1399
1400 return s;
1401 }
1402
1403 /* 32-kHz timer */
1404 struct omap_32khz_timer_s {
1405 struct omap_mpu_timer_s timer;
1406 };
1407
1408 static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
1409 {
1410 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
1411 int offset = addr & OMAP_MPUI_REG_MASK;
1412
1413 switch (offset) {
1414 case 0x00: /* TVR */
1415 return s->timer.reset_val;
1416
1417 case 0x04: /* TCR */
1418 return omap_timer_read(&s->timer);
1419
1420 case 0x08: /* CR */
1421 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
1422
1423 default:
1424 break;
1425 }
1426 OMAP_BAD_REG(addr);
1427 return 0;
1428 }
1429
1430 static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
1431 uint32_t value)
1432 {
1433 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
1434 int offset = addr & OMAP_MPUI_REG_MASK;
1435
1436 switch (offset) {
1437 case 0x00: /* TVR */
1438 s->timer.reset_val = value & 0x00ffffff;
1439 break;
1440
1441 case 0x04: /* TCR */
1442 OMAP_RO_REG(addr);
1443 break;
1444
1445 case 0x08: /* CR */
1446 s->timer.ar = (value >> 3) & 1;
1447 s->timer.it_ena = (value >> 2) & 1;
1448 if (s->timer.st != (value & 1) || (value & 2)) {
1449 omap_timer_sync(&s->timer);
1450 s->timer.enable = value & 1;
1451 s->timer.st = value & 1;
1452 omap_timer_update(&s->timer);
1453 }
1454 break;
1455
1456 default:
1457 OMAP_BAD_REG(addr);
1458 }
1459 }
1460
1461 static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
1462 omap_badwidth_read32,
1463 omap_badwidth_read32,
1464 omap_os_timer_read,
1465 };
1466
1467 static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
1468 omap_badwidth_write32,
1469 omap_badwidth_write32,
1470 omap_os_timer_write,
1471 };
1472
1473 static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
1474 {
1475 qemu_del_timer(s->timer.timer);
1476 s->timer.enable = 0;
1477 s->timer.it_ena = 0;
1478 s->timer.reset_val = 0x00ffffff;
1479 s->timer.val = 0;
1480 s->timer.st = 0;
1481 s->timer.ptv = 0;
1482 s->timer.ar = 1;
1483 }
1484
1485 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
1486 qemu_irq irq, omap_clk clk)
1487 {
1488 int iomemtype;
1489 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
1490 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
1491
1492 s->timer.irq = irq;
1493 s->timer.clk = clk;
1494 s->timer.base = base;
1495 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1496 omap_os_timer_reset(s);
1497 omap_timer_clk_setup(&s->timer);
1498
1499 iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
1500 omap_os_timer_writefn, s);
1501 cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
1502
1503 return s;
1504 }
1505
1506 /* Ultra Low-Power Device Module */
1507 static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
1508 {
1509 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1510 int offset = addr - s->ulpd_pm_base;
1511 uint16_t ret;
1512
1513 switch (offset) {
1514 case 0x14: /* IT_STATUS */
1515 ret = s->ulpd_pm_regs[offset >> 2];
1516 s->ulpd_pm_regs[offset >> 2] = 0;
1517 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
1518 return ret;
1519
1520 case 0x18: /* Reserved */
1521 case 0x1c: /* Reserved */
1522 case 0x20: /* Reserved */
1523 case 0x28: /* Reserved */
1524 case 0x2c: /* Reserved */
1525 OMAP_BAD_REG(addr);
1526 case 0x00: /* COUNTER_32_LSB */
1527 case 0x04: /* COUNTER_32_MSB */
1528 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1529 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1530 case 0x10: /* GAUGING_CTRL */
1531 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1532 case 0x30: /* CLOCK_CTRL */
1533 case 0x34: /* SOFT_REQ */
1534 case 0x38: /* COUNTER_32_FIQ */
1535 case 0x3c: /* DPLL_CTRL */
1536 case 0x40: /* STATUS_REQ */
1537 /* XXX: check clk::usecount state for every clock */
1538 case 0x48: /* LOCL_TIME */
1539 case 0x4c: /* APLL_CTRL */
1540 case 0x50: /* POWER_CTRL */
1541 return s->ulpd_pm_regs[offset >> 2];
1542 }
1543
1544 OMAP_BAD_REG(addr);
1545 return 0;
1546 }
1547
1548 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
1549 uint16_t diff, uint16_t value)
1550 {
1551 if (diff & (1 << 4)) /* USB_MCLK_EN */
1552 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
1553 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
1554 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
1555 }
1556
1557 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
1558 uint16_t diff, uint16_t value)
1559 {
1560 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
1561 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
1562 if (diff & (1 << 1)) /* SOFT_COM_REQ */
1563 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
1564 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
1565 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
1566 if (diff & (1 << 3)) /* SOFT_USB_REQ */
1567 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
1568 }
1569
1570 static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
1571 uint32_t value)
1572 {
1573 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1574 int offset = addr - s->ulpd_pm_base;
1575 int64_t now, ticks;
1576 int div, mult;
1577 static const int bypass_div[4] = { 1, 2, 4, 4 };
1578 uint16_t diff;
1579
1580 switch (offset) {
1581 case 0x00: /* COUNTER_32_LSB */
1582 case 0x04: /* COUNTER_32_MSB */
1583 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1584 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1585 case 0x14: /* IT_STATUS */
1586 case 0x40: /* STATUS_REQ */
1587 OMAP_RO_REG(addr);
1588 break;
1589
1590 case 0x10: /* GAUGING_CTRL */
1591 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
1592 if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
1593 now = qemu_get_clock(vm_clock);
1594
1595 if (value & 1)
1596 s->ulpd_gauge_start = now;
1597 else {
1598 now -= s->ulpd_gauge_start;
1599
1600 /* 32-kHz ticks */
1601 ticks = muldiv64(now, 32768, ticks_per_sec);
1602 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
1603 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
1604 if (ticks >> 32) /* OVERFLOW_32K */
1605 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
1606
1607 /* High frequency ticks */
1608 ticks = muldiv64(now, 12000000, ticks_per_sec);
1609 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
1610 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
1611 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
1612 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
1613
1614 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1615 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
1616 }
1617 }
1618 s->ulpd_pm_regs[offset >> 2] = value;
1619 break;
1620
1621 case 0x18: /* Reserved */
1622 case 0x1c: /* Reserved */
1623 case 0x20: /* Reserved */
1624 case 0x28: /* Reserved */
1625 case 0x2c: /* Reserved */
1626 OMAP_BAD_REG(addr);
1627 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1628 case 0x38: /* COUNTER_32_FIQ */
1629 case 0x48: /* LOCL_TIME */
1630 case 0x50: /* POWER_CTRL */
1631 s->ulpd_pm_regs[offset >> 2] = value;
1632 break;
1633
1634 case 0x30: /* CLOCK_CTRL */
1635 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1636 s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
1637 omap_ulpd_clk_update(s, diff, value);
1638 break;
1639
1640 case 0x34: /* SOFT_REQ */
1641 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1642 s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
1643 omap_ulpd_req_update(s, diff, value);
1644 break;
1645
1646 case 0x3c: /* DPLL_CTRL */
1647 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1648 * omitted altogether, probably a typo. */
1649 /* This register has identical semantics with DPLL(1:3) control
1650 * registers, see omap_dpll_write() */
1651 diff = s->ulpd_pm_regs[offset >> 2] & value;
1652 s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
1653 if (diff & (0x3ff << 2)) {
1654 if (value & (1 << 4)) { /* PLL_ENABLE */
1655 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1656 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1657 } else {
1658 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1659 mult = 1;
1660 }
1661 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
1662 }
1663
1664 /* Enter the desired mode. */
1665 s->ulpd_pm_regs[offset >> 2] =
1666 (s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
1667 ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
1668
1669 /* Act as if the lock is restored. */
1670 s->ulpd_pm_regs[offset >> 2] |= 2;
1671 break;
1672
1673 case 0x4c: /* APLL_CTRL */
1674 diff = s->ulpd_pm_regs[offset >> 2] & value;
1675 s->ulpd_pm_regs[offset >> 2] = value & 0xf;
1676 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
1677 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
1678 (value & (1 << 0)) ? "apll" : "dpll4"));
1679 break;
1680
1681 default:
1682 OMAP_BAD_REG(addr);
1683 }
1684 }
1685
1686 static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
1687 omap_badwidth_read16,
1688 omap_ulpd_pm_read,
1689 omap_badwidth_read16,
1690 };
1691
1692 static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
1693 omap_badwidth_write16,
1694 omap_ulpd_pm_write,
1695 omap_badwidth_write16,
1696 };
1697
1698 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
1699 {
1700 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
1701 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
1702 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
1703 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
1704 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
1705 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
1706 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
1707 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
1708 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
1709 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
1710 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
1711 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
1712 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
1713 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
1714 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
1715 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
1716 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
1717 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1718 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
1719 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
1720 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
1721 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
1722 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
1723 }
1724
1725 static void omap_ulpd_pm_init(target_phys_addr_t base,
1726 struct omap_mpu_state_s *mpu)
1727 {
1728 int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
1729 omap_ulpd_pm_writefn, mpu);
1730
1731 mpu->ulpd_pm_base = base;
1732 cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
1733 omap_ulpd_pm_reset(mpu);
1734 }
1735
1736 /* OMAP Pin Configuration */
1737 static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
1738 {
1739 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1740 int offset = addr - s->pin_cfg_base;
1741
1742 switch (offset) {
1743 case 0x00: /* FUNC_MUX_CTRL_0 */
1744 case 0x04: /* FUNC_MUX_CTRL_1 */
1745 case 0x08: /* FUNC_MUX_CTRL_2 */
1746 return s->func_mux_ctrl[offset >> 2];
1747
1748 case 0x0c: /* COMP_MODE_CTRL_0 */
1749 return s->comp_mode_ctrl[0];
1750
1751 case 0x10: /* FUNC_MUX_CTRL_3 */
1752 case 0x14: /* FUNC_MUX_CTRL_4 */
1753 case 0x18: /* FUNC_MUX_CTRL_5 */
1754 case 0x1c: /* FUNC_MUX_CTRL_6 */
1755 case 0x20: /* FUNC_MUX_CTRL_7 */
1756 case 0x24: /* FUNC_MUX_CTRL_8 */
1757 case 0x28: /* FUNC_MUX_CTRL_9 */
1758 case 0x2c: /* FUNC_MUX_CTRL_A */
1759 case 0x30: /* FUNC_MUX_CTRL_B */
1760 case 0x34: /* FUNC_MUX_CTRL_C */
1761 case 0x38: /* FUNC_MUX_CTRL_D */
1762 return s->func_mux_ctrl[(offset >> 2) - 1];
1763
1764 case 0x40: /* PULL_DWN_CTRL_0 */
1765 case 0x44: /* PULL_DWN_CTRL_1 */
1766 case 0x48: /* PULL_DWN_CTRL_2 */
1767 case 0x4c: /* PULL_DWN_CTRL_3 */
1768 return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
1769
1770 case 0x50: /* GATE_INH_CTRL_0 */
1771 return s->gate_inh_ctrl[0];
1772
1773 case 0x60: /* VOLTAGE_CTRL_0 */
1774 return s->voltage_ctrl[0];
1775
1776 case 0x70: /* TEST_DBG_CTRL_0 */
1777 return s->test_dbg_ctrl[0];
1778
1779 case 0x80: /* MOD_CONF_CTRL_0 */
1780 return s->mod_conf_ctrl[0];
1781 }
1782
1783 OMAP_BAD_REG(addr);
1784 return 0;
1785 }
1786
1787 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
1788 uint32_t diff, uint32_t value)
1789 {
1790 if (s->compat1509) {
1791 if (diff & (1 << 9)) /* BLUETOOTH */
1792 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
1793 (~value >> 9) & 1);
1794 if (diff & (1 << 7)) /* USB.CLKO */
1795 omap_clk_onoff(omap_findclk(s, "usb.clko"),
1796 (value >> 7) & 1);
1797 }
1798 }
1799
1800 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
1801 uint32_t diff, uint32_t value)
1802 {
1803 if (s->compat1509) {
1804 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1805 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
1806 (value >> 31) & 1);
1807 if (diff & (1 << 1)) /* CLK32K */
1808 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
1809 (~value >> 1) & 1);
1810 }
1811 }
1812
1813 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
1814 uint32_t diff, uint32_t value)
1815 {
1816 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1817 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
1818 omap_findclk(s, ((value >> 31) & 1) ?
1819 "ck_48m" : "armper_ck"));
1820 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1821 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
1822 omap_findclk(s, ((value >> 30) & 1) ?
1823 "ck_48m" : "armper_ck"));
1824 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1825 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
1826 omap_findclk(s, ((value >> 29) & 1) ?
1827 "ck_48m" : "armper_ck"));
1828 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1829 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
1830 omap_findclk(s, ((value >> 23) & 1) ?
1831 "ck_48m" : "armper_ck"));
1832 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1833 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
1834 omap_findclk(s, ((value >> 12) & 1) ?
1835 "ck_48m" : "armper_ck"));
1836 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1837 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
1838 }
1839
1840 static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
1841 uint32_t value)
1842 {
1843 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1844 int offset = addr - s->pin_cfg_base;
1845 uint32_t diff;
1846
1847 switch (offset) {
1848 case 0x00: /* FUNC_MUX_CTRL_0 */
1849 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1850 s->func_mux_ctrl[offset >> 2] = value;
1851 omap_pin_funcmux0_update(s, diff, value);
1852 return;
1853
1854 case 0x04: /* FUNC_MUX_CTRL_1 */
1855 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1856 s->func_mux_ctrl[offset >> 2] = value;
1857 omap_pin_funcmux1_update(s, diff, value);
1858 return;
1859
1860 case 0x08: /* FUNC_MUX_CTRL_2 */
1861 s->func_mux_ctrl[offset >> 2] = value;
1862 return;
1863
1864 case 0x0c: /* COMP_MODE_CTRL_0 */
1865 s->comp_mode_ctrl[0] = value;
1866 s->compat1509 = (value != 0x0000eaef);
1867 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
1868 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
1869 return;
1870
1871 case 0x10: /* FUNC_MUX_CTRL_3 */
1872 case 0x14: /* FUNC_MUX_CTRL_4 */
1873 case 0x18: /* FUNC_MUX_CTRL_5 */
1874 case 0x1c: /* FUNC_MUX_CTRL_6 */
1875 case 0x20: /* FUNC_MUX_CTRL_7 */
1876 case 0x24: /* FUNC_MUX_CTRL_8 */
1877 case 0x28: /* FUNC_MUX_CTRL_9 */
1878 case 0x2c: /* FUNC_MUX_CTRL_A */
1879 case 0x30: /* FUNC_MUX_CTRL_B */
1880 case 0x34: /* FUNC_MUX_CTRL_C */
1881 case 0x38: /* FUNC_MUX_CTRL_D */
1882 s->func_mux_ctrl[(offset >> 2) - 1] = value;
1883 return;
1884
1885 case 0x40: /* PULL_DWN_CTRL_0 */
1886 case 0x44: /* PULL_DWN_CTRL_1 */
1887 case 0x48: /* PULL_DWN_CTRL_2 */
1888 case 0x4c: /* PULL_DWN_CTRL_3 */
1889 s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
1890 return;
1891
1892 case 0x50: /* GATE_INH_CTRL_0 */
1893 s->gate_inh_ctrl[0] = value;
1894 return;
1895
1896 case 0x60: /* VOLTAGE_CTRL_0 */
1897 s->voltage_ctrl[0] = value;
1898 return;
1899
1900 case 0x70: /* TEST_DBG_CTRL_0 */
1901 s->test_dbg_ctrl[0] = value;
1902 return;
1903
1904 case 0x80: /* MOD_CONF_CTRL_0 */
1905 diff = s->mod_conf_ctrl[0] ^ value;
1906 s->mod_conf_ctrl[0] = value;
1907 omap_pin_modconf1_update(s, diff, value);
1908 return;
1909
1910 default:
1911 OMAP_BAD_REG(addr);
1912 }
1913 }
1914
1915 static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
1916 omap_badwidth_read32,
1917 omap_badwidth_read32,
1918 omap_pin_cfg_read,
1919 };
1920
1921 static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
1922 omap_badwidth_write32,
1923 omap_badwidth_write32,
1924 omap_pin_cfg_write,
1925 };
1926
1927 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
1928 {
1929 /* Start in Compatibility Mode. */
1930 mpu->compat1509 = 1;
1931 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
1932 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
1933 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
1934 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
1935 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
1936 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
1937 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
1938 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
1939 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
1940 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
1941 }
1942
1943 static void omap_pin_cfg_init(target_phys_addr_t base,
1944 struct omap_mpu_state_s *mpu)
1945 {
1946 int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
1947 omap_pin_cfg_writefn, mpu);
1948
1949 mpu->pin_cfg_base = base;
1950 cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
1951 omap_pin_cfg_reset(mpu);
1952 }
1953
1954 /* Device Identification, Die Identification */
1955 static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
1956 {
1957 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1958
1959 switch (addr) {
1960 case 0xfffe1800: /* DIE_ID_LSB */
1961 return 0xc9581f0e;
1962 case 0xfffe1804: /* DIE_ID_MSB */
1963 return 0xa8858bfa;
1964
1965 case 0xfffe2000: /* PRODUCT_ID_LSB */
1966 return 0x00aaaafc;
1967 case 0xfffe2004: /* PRODUCT_ID_MSB */
1968 return 0xcafeb574;
1969
1970 case 0xfffed400: /* JTAG_ID_LSB */
1971 switch (s->mpu_model) {
1972 case omap310:
1973 return 0x03310315;
1974 case omap1510:
1975 return 0x03310115;
1976 }
1977 break;
1978
1979 case 0xfffed404: /* JTAG_ID_MSB */
1980 switch (s->mpu_model) {
1981 case omap310:
1982 return 0xfb57402f;
1983 case omap1510:
1984 return 0xfb47002f;
1985 }
1986 break;
1987 }
1988
1989 OMAP_BAD_REG(addr);
1990 return 0;
1991 }
1992
1993 static void omap_id_write(void *opaque, target_phys_addr_t addr,
1994 uint32_t value)
1995 {
1996 OMAP_BAD_REG(addr);
1997 }
1998
1999 static CPUReadMemoryFunc *omap_id_readfn[] = {
2000 omap_badwidth_read32,
2001 omap_badwidth_read32,
2002 omap_id_read,
2003 };
2004
2005 static CPUWriteMemoryFunc *omap_id_writefn[] = {
2006 omap_badwidth_write32,
2007 omap_badwidth_write32,
2008 omap_id_write,
2009 };
2010
2011 static void omap_id_init(struct omap_mpu_state_s *mpu)
2012 {
2013 int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
2014 omap_id_writefn, mpu);
2015 cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
2016 cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
2017 if (!cpu_is_omap15xx(mpu))
2018 cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
2019 }
2020
2021 /* MPUI Control (Dummy) */
2022 static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
2023 {
2024 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2025 int offset = addr - s->mpui_base;
2026
2027 switch (offset) {
2028 case 0x00: /* CTRL */
2029 return s->mpui_ctrl;
2030 case 0x04: /* DEBUG_ADDR */
2031 return 0x01ffffff;
2032 case 0x08: /* DEBUG_DATA */
2033 return 0xffffffff;
2034 case 0x0c: /* DEBUG_FLAG */
2035 return 0x00000800;
2036 case 0x10: /* STATUS */
2037 return 0x00000000;
2038
2039 /* Not in OMAP310 */
2040 case 0x14: /* DSP_STATUS */
2041 case 0x18: /* DSP_BOOT_CONFIG */
2042 return 0x00000000;
2043 case 0x1c: /* DSP_MPUI_CONFIG */
2044 return 0x0000ffff;
2045 }
2046
2047 OMAP_BAD_REG(addr);
2048 return 0;
2049 }
2050
2051 static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
2052 uint32_t value)
2053 {
2054 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2055 int offset = addr - s->mpui_base;
2056
2057 switch (offset) {
2058 case 0x00: /* CTRL */
2059 s->mpui_ctrl = value & 0x007fffff;
2060 break;
2061
2062 case 0x04: /* DEBUG_ADDR */
2063 case 0x08: /* DEBUG_DATA */
2064 case 0x0c: /* DEBUG_FLAG */
2065 case 0x10: /* STATUS */
2066 /* Not in OMAP310 */
2067 case 0x14: /* DSP_STATUS */
2068 OMAP_RO_REG(addr);
2069 case 0x18: /* DSP_BOOT_CONFIG */
2070 case 0x1c: /* DSP_MPUI_CONFIG */
2071 break;
2072
2073 default:
2074 OMAP_BAD_REG(addr);
2075 }
2076 }
2077
2078 static CPUReadMemoryFunc *omap_mpui_readfn[] = {
2079 omap_badwidth_read32,
2080 omap_badwidth_read32,
2081 omap_mpui_read,
2082 };
2083
2084 static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
2085 omap_badwidth_write32,
2086 omap_badwidth_write32,
2087 omap_mpui_write,
2088 };
2089
2090 static void omap_mpui_reset(struct omap_mpu_state_s *s)
2091 {
2092 s->mpui_ctrl = 0x0003ff1b;
2093 }
2094
2095 static void omap_mpui_init(target_phys_addr_t base,
2096 struct omap_mpu_state_s *mpu)
2097 {
2098 int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
2099 omap_mpui_writefn, mpu);
2100
2101 mpu->mpui_base = base;
2102 cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
2103
2104 omap_mpui_reset(mpu);
2105 }
2106
2107 /* TIPB Bridges */
2108 struct omap_tipb_bridge_s {
2109 target_phys_addr_t base;
2110 qemu_irq abort;
2111
2112 int width_intr;
2113 uint16_t control;
2114 uint16_t alloc;
2115 uint16_t buffer;
2116 uint16_t enh_control;
2117 };
2118
2119 static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
2120 {
2121 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
2122 int offset = addr - s->base;
2123
2124 switch (offset) {
2125 case 0x00: /* TIPB_CNTL */
2126 return s->control;
2127 case 0x04: /* TIPB_BUS_ALLOC */
2128 return s->alloc;
2129 case 0x08: /* MPU_TIPB_CNTL */
2130 return s->buffer;
2131 case 0x0c: /* ENHANCED_TIPB_CNTL */
2132 return s->enh_control;
2133 case 0x10: /* ADDRESS_DBG */
2134 case 0x14: /* DATA_DEBUG_LOW */
2135 case 0x18: /* DATA_DEBUG_HIGH */
2136 return 0xffff;
2137 case 0x1c: /* DEBUG_CNTR_SIG */
2138 return 0x00f8;
2139 }
2140
2141 OMAP_BAD_REG(addr);
2142 return 0;
2143 }
2144
2145 static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
2146 uint32_t value)
2147 {
2148 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
2149 int offset = addr - s->base;
2150
2151 switch (offset) {
2152 case 0x00: /* TIPB_CNTL */
2153 s->control = value & 0xffff;
2154 break;
2155
2156 case 0x04: /* TIPB_BUS_ALLOC */
2157 s->alloc = value & 0x003f;
2158 break;
2159
2160 case 0x08: /* MPU_TIPB_CNTL */
2161 s->buffer = value & 0x0003;
2162 break;
2163
2164 case 0x0c: /* ENHANCED_TIPB_CNTL */
2165 s->width_intr = !(value & 2);
2166 s->enh_control = value & 0x000f;
2167 break;
2168
2169 case 0x10: /* ADDRESS_DBG */
2170 case 0x14: /* DATA_DEBUG_LOW */
2171 case 0x18: /* DATA_DEBUG_HIGH */
2172 case 0x1c: /* DEBUG_CNTR_SIG */
2173 OMAP_RO_REG(addr);
2174 break;
2175
2176 default:
2177 OMAP_BAD_REG(addr);
2178 }
2179 }
2180
2181 static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
2182 omap_badwidth_read16,
2183 omap_tipb_bridge_read,
2184 omap_tipb_bridge_read,
2185 };
2186
2187 static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
2188 omap_badwidth_write16,
2189 omap_tipb_bridge_write,
2190 omap_tipb_bridge_write,
2191 };
2192
2193 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
2194 {
2195 s->control = 0xffff;
2196 s->alloc = 0x0009;
2197 s->buffer = 0x0000;
2198 s->enh_control = 0x000f;
2199 }
2200
2201 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
2202 qemu_irq abort_irq, omap_clk clk)
2203 {
2204 int iomemtype;
2205 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
2206 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
2207
2208 s->abort = abort_irq;
2209 s->base = base;
2210 omap_tipb_bridge_reset(s);
2211
2212 iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
2213 omap_tipb_bridge_writefn, s);
2214 cpu_register_physical_memory(s->base, 0x100, iomemtype);
2215
2216 return s;
2217 }
2218
2219 /* Dummy Traffic Controller's Memory Interface */
2220 static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
2221 {
2222 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2223 int offset = addr - s->tcmi_base;
2224 uint32_t ret;
2225
2226 switch (offset) {
2227 case 0x00: /* IMIF_PRIO */
2228 case 0x04: /* EMIFS_PRIO */
2229 case 0x08: /* EMIFF_PRIO */
2230 case 0x0c: /* EMIFS_CONFIG */
2231 case 0x10: /* EMIFS_CS0_CONFIG */
2232 case 0x14: /* EMIFS_CS1_CONFIG */
2233 case 0x18: /* EMIFS_CS2_CONFIG */
2234 case 0x1c: /* EMIFS_CS3_CONFIG */
2235 case 0x24: /* EMIFF_MRS */
2236 case 0x28: /* TIMEOUT1 */
2237 case 0x2c: /* TIMEOUT2 */
2238 case 0x30: /* TIMEOUT3 */
2239 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
2240 case 0x40: /* EMIFS_CFG_DYN_WAIT */
2241 return s->tcmi_regs[offset >> 2];
2242
2243 case 0x20: /* EMIFF_SDRAM_CONFIG */
2244 ret = s->tcmi_regs[offset >> 2];
2245 s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
2246 /* XXX: We can try using the VGA_DIRTY flag for this */
2247 return ret;
2248 }
2249
2250 OMAP_BAD_REG(addr);
2251 return 0;
2252 }
2253
2254 static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
2255 uint32_t value)
2256 {
2257 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2258 int offset = addr - s->tcmi_base;
2259
2260 switch (offset) {
2261 case 0x00: /* IMIF_PRIO */
2262 case 0x04: /* EMIFS_PRIO */
2263 case 0x08: /* EMIFF_PRIO */
2264 case 0x10: /* EMIFS_CS0_CONFIG */
2265 case 0x14: /* EMIFS_CS1_CONFIG */
2266 case 0x18: /* EMIFS_CS2_CONFIG */
2267 case 0x1c: /* EMIFS_CS3_CONFIG */
2268 case 0x20: /* EMIFF_SDRAM_CONFIG */
2269 case 0x24: /* EMIFF_MRS */
2270 case 0x28: /* TIMEOUT1 */
2271 case 0x2c: /* TIMEOUT2 */
2272 case 0x30: /* TIMEOUT3 */
2273 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
2274 case 0x40: /* EMIFS_CFG_DYN_WAIT */
2275 s->tcmi_regs[offset >> 2] = value;
2276 break;
2277 case 0x0c: /* EMIFS_CONFIG */
2278 s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
2279 break;
2280
2281 default:
2282 OMAP_BAD_REG(addr);
2283 }
2284 }
2285
2286 static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
2287 omap_badwidth_read32,
2288 omap_badwidth_read32,
2289 omap_tcmi_read,
2290 };
2291
2292 static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
2293 omap_badwidth_write32,
2294 omap_badwidth_write32,
2295 omap_tcmi_write,
2296 };
2297
2298 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
2299 {
2300 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
2301 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
2302 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
2303 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
2304 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
2305 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
2306 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
2307 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
2308 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
2309 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
2310 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
2311 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
2312 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
2313 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
2314 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
2315 }
2316
2317 static void omap_tcmi_init(target_phys_addr_t base,
2318 struct omap_mpu_state_s *mpu)
2319 {
2320 int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
2321 omap_tcmi_writefn, mpu);
2322
2323 mpu->tcmi_base = base;
2324 cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
2325 omap_tcmi_reset(mpu);
2326 }
2327
2328 /* Digital phase-locked loops control */
2329 static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
2330 {
2331 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
2332 int offset = addr - s->base;
2333
2334 if (offset == 0x00) /* CTL_REG */
2335 return s->mode;
2336
2337 OMAP_BAD_REG(addr);
2338 return 0;
2339 }
2340
2341 static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
2342 uint32_t value)
2343 {
2344 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
2345 uint16_t diff;
2346 int offset = addr - s->base;
2347 static const int bypass_div[4] = { 1, 2, 4, 4 };
2348 int div, mult;
2349
2350 if (offset == 0x00) { /* CTL_REG */
2351 /* See omap_ulpd_pm_write() too */
2352 diff = s->mode & value;
2353 s->mode = value & 0x2fff;
2354 if (diff & (0x3ff << 2)) {
2355 if (value & (1 << 4)) { /* PLL_ENABLE */
2356 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
2357 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
2358 } else {
2359 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
2360 mult = 1;
2361 }
2362 omap_clk_setrate(s->dpll, div, mult);
2363 }
2364
2365 /* Enter the desired mode. */
2366 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
2367
2368 /* Act as if the lock is restored. */
2369 s->mode |= 2;
2370 } else {
2371 OMAP_BAD_REG(addr);
2372 }
2373 }
2374
2375 static CPUReadMemoryFunc *omap_dpll_readfn[] = {
2376 omap_badwidth_read16,
2377 omap_dpll_read,
2378 omap_badwidth_read16,
2379 };
2380
2381 static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
2382 omap_badwidth_write16,
2383 omap_dpll_write,
2384 omap_badwidth_write16,
2385 };
2386
2387 static void omap_dpll_reset(struct dpll_ctl_s *s)
2388 {
2389 s->mode = 0x2002;
2390 omap_clk_setrate(s->dpll, 1, 1);
2391 }
2392
2393 static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
2394 omap_clk clk)
2395 {
2396 int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
2397 omap_dpll_writefn, s);
2398
2399 s->base = base;
2400 s->dpll = clk;
2401 omap_dpll_reset(s);
2402
2403 cpu_register_physical_memory(s->base, 0x100, iomemtype);
2404 }
2405
2406 /* UARTs */
2407 struct omap_uart_s {
2408 SerialState *serial; /* TODO */
2409 };
2410
2411 static void omap_uart_reset(struct omap_uart_s *s)
2412 {
2413 }
2414
2415 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
2416 qemu_irq irq, omap_clk clk, CharDriverState *chr)
2417 {
2418 struct omap_uart_s *s = (struct omap_uart_s *)
2419 qemu_mallocz(sizeof(struct omap_uart_s));
2420 if (chr)
2421 s->serial = serial_mm_init(base, 2, irq, chr, 1);
2422 return s;
2423 }
2424
2425 /* MPU Clock/Reset/Power Mode Control */
2426 static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
2427 {
2428 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2429 int offset = addr - s->clkm.mpu_base;
2430
2431 switch (offset) {
2432 case 0x00: /* ARM_CKCTL */
2433 return s->clkm.arm_ckctl;
2434
2435 case 0x04: /* ARM_IDLECT1 */
2436 return s->clkm.arm_idlect1;
2437
2438 case 0x08: /* ARM_IDLECT2 */
2439 return s->clkm.arm_idlect2;
2440
2441 case 0x0c: /* ARM_EWUPCT */
2442 return s->clkm.arm_ewupct;
2443
2444 case 0x10: /* ARM_RSTCT1 */
2445 return s->clkm.arm_rstct1;
2446
2447 case 0x14: /* ARM_RSTCT2 */
2448 return s->clkm.arm_rstct2;
2449
2450 case 0x18: /* ARM_SYSST */
2451 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
2452
2453 case 0x1c: /* ARM_CKOUT1 */
2454 return s->clkm.arm_ckout1;
2455
2456 case 0x20: /* ARM_CKOUT2 */
2457 break;
2458 }
2459
2460 OMAP_BAD_REG(addr);
2461 return 0;
2462 }
2463
2464 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
2465 uint16_t diff, uint16_t value)
2466 {
2467 omap_clk clk;
2468
2469 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
2470 if (value & (1 << 14))
2471 /* Reserved */;
2472 else {
2473 clk = omap_findclk(s, "arminth_ck");
2474 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2475 }
2476 }
2477 if (diff & (1 << 12)) { /* ARM_TIMXO */
2478 clk = omap_findclk(s, "armtim_ck");
2479 if (value & (1 << 12))
2480 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
2481 else
2482 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2483 }
2484 /* XXX: en_dspck */
2485 if (diff & (3 << 10)) { /* DSPMMUDIV */
2486 clk = omap_findclk(s, "dspmmu_ck");
2487 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
2488 }
2489 if (diff & (3 << 8)) { /* TCDIV */
2490 clk = omap_findclk(s, "tc_ck");
2491 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
2492 }
2493 if (diff & (3 << 6)) { /* DSPDIV */
2494 clk = omap_findclk(s, "dsp_ck");
2495 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
2496 }
2497 if (diff & (3 << 4)) { /* ARMDIV */
2498 clk = omap_findclk(s, "arm_ck");
2499 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
2500 }
2501 if (diff & (3 << 2)) { /* LCDDIV */
2502 clk = omap_findclk(s, "lcd_ck");
2503 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
2504 }
2505 if (diff & (3 << 0)) { /* PERDIV */
2506 clk = omap_findclk(s, "armper_ck");
2507 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
2508 }
2509 }
2510
2511 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
2512 uint16_t diff, uint16_t value)
2513 {
2514 omap_clk clk;
2515
2516 if (value & (1 << 11)) /* SETARM_IDLE */
2517 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
2518 if (!(value & (1 << 10))) /* WKUP_MODE */
2519 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2520
2521 #define SET_CANIDLE(clock, bit) \
2522 if (diff & (1 << bit)) { \
2523 clk = omap_findclk(s, clock); \
2524 omap_clk_canidle(clk, (value >> bit) & 1); \
2525 }
2526 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2527 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2528 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2529 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2530 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2531 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2532 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2533 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2534 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2535 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2536 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2537 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2538 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2539 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2540 }
2541
2542 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
2543 uint16_t diff, uint16_t value)
2544 {
2545 omap_clk clk;
2546
2547 #define SET_ONOFF(clock, bit) \
2548 if (diff & (1 << bit)) { \
2549 clk = omap_findclk(s, clock); \
2550 omap_clk_onoff(clk, (value >> bit) & 1); \
2551 }
2552 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2553 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2554 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2555 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2556 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2557 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2558 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2559 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2560 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2561 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2562 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2563 }
2564
2565 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
2566 uint16_t diff, uint16_t value)
2567 {
2568 omap_clk clk;
2569
2570 if (diff & (3 << 4)) { /* TCLKOUT */
2571 clk = omap_findclk(s, "tclk_out");
2572 switch ((value >> 4) & 3) {
2573 case 1:
2574 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
2575 omap_clk_onoff(clk, 1);
2576 break;
2577 case 2:
2578 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2579 omap_clk_onoff(clk, 1);
2580 break;
2581 default:
2582 omap_clk_onoff(clk, 0);
2583 }
2584 }
2585 if (diff & (3 << 2)) { /* DCLKOUT */
2586 clk = omap_findclk(s, "dclk_out");
2587 switch ((value >> 2) & 3) {
2588 case 0:
2589 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
2590 break;
2591 case 1:
2592 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
2593 break;
2594 case 2:
2595 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
2596 break;
2597 case 3:
2598 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2599 break;
2600 }
2601 }
2602 if (diff & (3 << 0)) { /* ACLKOUT */
2603 clk = omap_findclk(s, "aclk_out");
2604 switch ((value >> 0) & 3) {
2605 case 1:
2606 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2607 omap_clk_onoff(clk, 1);
2608 break;
2609 case 2:
2610 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
2611 omap_clk_onoff(clk, 1);
2612 break;
2613 case 3:
2614 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2615 omap_clk_onoff(clk, 1);
2616 break;
2617 default:
2618 omap_clk_onoff(clk, 0);
2619 }
2620 }
2621 }
2622
2623 static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
2624 uint32_t value)
2625 {
2626 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2627 int offset = addr - s->clkm.mpu_base;
2628 uint16_t diff;
2629 omap_clk clk;
2630 static const char *clkschemename[8] = {
2631 "fully synchronous", "fully asynchronous", "synchronous scalable",
2632 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2633 };
2634
2635 switch (offset) {
2636 case 0x00: /* ARM_CKCTL */
2637 diff = s->clkm.arm_ckctl ^ value;
2638 s->clkm.arm_ckctl = value & 0x7fff;
2639 omap_clkm_ckctl_update(s, diff, value);
2640 return;
2641
2642 case 0x04: /* ARM_IDLECT1 */
2643 diff = s->clkm.arm_idlect1 ^ value;
2644 s->clkm.arm_idlect1 = value & 0x0fff;
2645 omap_clkm_idlect1_update(s, diff, value);
2646 return;
2647
2648 case 0x08: /* ARM_IDLECT2 */
2649 diff = s->clkm.arm_idlect2 ^ value;
2650 s->clkm.arm_idlect2 = value & 0x07ff;
2651 omap_clkm_idlect2_update(s, diff, value);
2652 return;
2653
2654 case 0x0c: /* ARM_EWUPCT */
2655 diff = s->clkm.arm_ewupct ^ value;
2656 s->clkm.arm_ewupct = value & 0x003f;
2657 return;
2658
2659 case 0x10: /* ARM_RSTCT1 */
2660 diff = s->clkm.arm_rstct1 ^ value;
2661 s->clkm.arm_rstct1 = value & 0x0007;
2662 if (value & 9) {
2663 qemu_system_reset_request();
2664 s->clkm.cold_start = 0xa;
2665 }
2666 if (diff & ~value & 4) { /* DSP_RST */
2667 omap_mpui_reset(s);
2668 omap_tipb_bridge_reset(s->private_tipb);
2669 omap_tipb_bridge_reset(s->public_tipb);
2670 }
2671 if (diff & 2) { /* DSP_EN */
2672 clk = omap_findclk(s, "dsp_ck");
2673 omap_clk_canidle(clk, (~value >> 1) & 1);
2674 }
2675 return;
2676
2677 case 0x14: /* ARM_RSTCT2 */
2678 s->clkm.arm_rstct2 = value & 0x0001;
2679 return;
2680
2681 case 0x18: /* ARM_SYSST */
2682 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
2683 s->clkm.clocking_scheme = (value >> 11) & 7;
2684 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
2685 clkschemename[s->clkm.clocking_scheme]);
2686 }
2687 s->clkm.cold_start &= value & 0x3f;
2688 return;
2689
2690 case 0x1c: /* ARM_CKOUT1 */
2691 diff = s->clkm.arm_ckout1 ^ value;
2692 s->clkm.arm_ckout1 = value & 0x003f;
2693 omap_clkm_ckout1_update(s, diff, value);
2694 return;
2695
2696 case 0x20: /* ARM_CKOUT2 */
2697 default:
2698 OMAP_BAD_REG(addr);
2699 }
2700 }
2701
2702 static CPUReadMemoryFunc *omap_clkm_readfn[] = {
2703 omap_badwidth_read16,
2704 omap_clkm_read,
2705 omap_badwidth_read16,
2706 };
2707
2708 static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
2709 omap_badwidth_write16,
2710 omap_clkm_write,
2711 omap_badwidth_write16,
2712 };
2713
2714 static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
2715 {
2716 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2717 int offset = addr - s->clkm.dsp_base;
2718
2719 switch (offset) {
2720 case 0x04: /* DSP_IDLECT1 */
2721 return s->clkm.dsp_idlect1;
2722
2723 case 0x08: /* DSP_IDLECT2 */
2724 return s->clkm.dsp_idlect2;
2725
2726 case 0x14: /* DSP_RSTCT2 */
2727 return s->clkm.dsp_rstct2;
2728
2729 case 0x18: /* DSP_SYSST */
2730 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
2731 (s->env->halted << 6); /* Quite useless... */
2732 }
2733
2734 OMAP_BAD_REG(addr);
2735 return 0;
2736 }
2737
2738 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
2739 uint16_t diff, uint16_t value)
2740 {
2741 omap_clk clk;
2742
2743 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2744 }
2745
2746 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
2747 uint16_t diff, uint16_t value)
2748 {
2749 omap_clk clk;
2750
2751 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2752 }
2753
2754 static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
2755 uint32_t value)
2756 {
2757 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2758 int offset = addr - s->clkm.dsp_base;
2759 uint16_t diff;
2760
2761 switch (offset) {
2762 case 0x04: /* DSP_IDLECT1 */
2763 diff = s->clkm.dsp_idlect1 ^ value;
2764 s->clkm.dsp_idlect1 = value & 0x01f7;
2765 omap_clkdsp_idlect1_update(s, diff, value);
2766 break;
2767
2768 case 0x08: /* DSP_IDLECT2 */
2769 s->clkm.dsp_idlect2 = value & 0x0037;
2770 diff = s->clkm.dsp_idlect1 ^ value;
2771 omap_clkdsp_idlect2_update(s, diff, value);
2772 break;
2773
2774 case 0x14: /* DSP_RSTCT2 */
2775 s->clkm.dsp_rstct2 = value & 0x0001;
2776 break;
2777
2778 case 0x18: /* DSP_SYSST */
2779 s->clkm.cold_start &= value & 0x3f;
2780 break;
2781
2782 default:
2783 OMAP_BAD_REG(addr);
2784 }
2785 }
2786
2787 static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
2788 omap_badwidth_read16,
2789 omap_clkdsp_read,
2790 omap_badwidth_read16,
2791 };
2792
2793 static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
2794 omap_badwidth_write16,
2795 omap_clkdsp_write,
2796 omap_badwidth_write16,
2797 };
2798
2799 static void omap_clkm_reset(struct omap_mpu_state_s *s)
2800 {
2801 if (s->wdt && s->wdt->reset)
2802 s->clkm.cold_start = 0x6;
2803 s->clkm.clocking_scheme = 0;
2804 omap_clkm_ckctl_update(s, ~0, 0x3000);
2805 s->clkm.arm_ckctl = 0x3000;
2806 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
2807 s->clkm.arm_idlect1 = 0x0400;
2808 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
2809 s->clkm.arm_idlect2 = 0x0100;
2810 s->clkm.arm_ewupct = 0x003f;
2811 s->clkm.arm_rstct1 = 0x0000;
2812 s->clkm.arm_rstct2 = 0x0000;
2813 s->clkm.arm_ckout1 = 0x0015;
2814 s->clkm.dpll1_mode = 0x2002;
2815 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
2816 s->clkm.dsp_idlect1 = 0x0040;
2817 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
2818 s->clkm.dsp_idlect2 = 0x0000;
2819 s->clkm.dsp_rstct2 = 0x0000;
2820 }
2821
2822 static void omap_clkm_init(target_phys_addr_t mpu_base,
2823 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
2824 {
2825 int iomemtype[2] = {
2826 cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
2827 cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
2828 };
2829
2830 s->clkm.mpu_base = mpu_base;
2831 s->clkm.dsp_base = dsp_base;
2832 s->clkm.arm_idlect1 = 0x03ff;
2833 s->clkm.arm_idlect2 = 0x0100;
2834 s->clkm.dsp_idlect1 = 0x0002;
2835 omap_clkm_reset(s);
2836 s->clkm.cold_start = 0x3a;
2837
2838 cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
2839 cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
2840 }
2841
2842 /* MPU I/O */
2843 struct omap_mpuio_s {
2844 target_phys_addr_t base;
2845 qemu_irq irq;
2846 qemu_irq kbd_irq;
2847 qemu_irq *in;
2848 qemu_irq handler[16];
2849 qemu_irq wakeup;
2850
2851 uint16_t inputs;
2852 uint16_t outputs;
2853 uint16_t dir;
2854 uint16_t edge;
2855 uint16_t mask;
2856 uint16_t ints;
2857
2858 uint16_t debounce;
2859 uint16_t latch;
2860 uint8_t event;
2861
2862 uint8_t buttons[5];
2863 uint8_t row_latch;
2864 uint8_t cols;
2865 int kbd_mask;
2866 int clk;
2867 };
2868
2869 static void omap_mpuio_set(void *opaque, int line, int level)
2870 {
2871 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2872 uint16_t prev = s->inputs;
2873
2874 if (level)
2875 s->inputs |= 1 << line;
2876 else
2877 s->inputs &= ~(1 << line);
2878
2879 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
2880 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
2881 s->ints |= 1 << line;
2882 qemu_irq_raise(s->irq);
2883 /* TODO: wakeup */
2884 }
2885 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
2886 (s->event >> 1) == line) /* PIN_SELECT */
2887 s->latch = s->inputs;
2888 }
2889 }
2890
2891 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
2892 {
2893 int i;
2894 uint8_t *row, rows = 0, cols = ~s->cols;
2895
2896 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
2897 if (*row & cols)
2898 rows |= i;
2899
2900 qemu_set_irq(s->kbd_irq, rows && ~s->kbd_mask && s->clk);
2901 s->row_latch = rows ^ 0x1f;
2902 }
2903
2904 static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
2905 {
2906 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2907 int offset = addr & OMAP_MPUI_REG_MASK;
2908 uint16_t ret;
2909
2910 switch (offset) {
2911 case 0x00: /* INPUT_LATCH */
2912 return s->inputs;
2913
2914 case 0x04: /* OUTPUT_REG */
2915 return s->outputs;
2916
2917 case 0x08: /* IO_CNTL */
2918 return s->dir;
2919
2920 case 0x10: /* KBR_LATCH */
2921 return s->row_latch;
2922
2923 case 0x14: /* KBC_REG */
2924 return s->cols;
2925
2926 case 0x18: /* GPIO_EVENT_MODE_REG */
2927 return s->event;
2928
2929 case 0x1c: /* GPIO_INT_EDGE_REG */
2930 return s->edge;
2931
2932 case 0x20: /* KBD_INT */
2933 return (s->row_latch != 0x1f) && !s->kbd_mask;
2934
2935 case 0x24: /* GPIO_INT */
2936 ret = s->ints;
2937 s->ints &= s->mask;
2938 if (ret)
2939 qemu_irq_lower(s->irq);
2940 return ret;
2941
2942 case 0x28: /* KBD_MASKIT */
2943 return s->kbd_mask;
2944
2945 case 0x2c: /* GPIO_MASKIT */
2946 return s->mask;
2947
2948 case 0x30: /* GPIO_DEBOUNCING_REG */
2949 return s->debounce;
2950
2951 case 0x34: /* GPIO_LATCH_REG */
2952 return s->latch;
2953 }
2954
2955 OMAP_BAD_REG(addr);
2956 return 0;
2957 }
2958
2959 static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
2960 uint32_t value)
2961 {
2962 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2963 int offset = addr & OMAP_MPUI_REG_MASK;
2964 uint16_t diff;
2965 int ln;
2966
2967 switch (offset) {
2968 case 0x04: /* OUTPUT_REG */
2969 diff = (s->outputs ^ value) & ~s->dir;
2970 s->outputs = value;
2971 while ((ln = ffs(diff))) {
2972 ln --;
2973 if (s->handler[ln])
2974 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2975 diff &= ~(1 << ln);
2976 }
2977 break;
2978
2979 case 0x08: /* IO_CNTL */
2980 diff = s->outputs & (s->dir ^ value);
2981 s->dir = value;
2982
2983 value = s->outputs & ~s->dir;
2984 while ((ln = ffs(diff))) {
2985 ln --;
2986 if (s->handler[ln])
2987 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2988 diff &= ~(1 << ln);
2989 }
2990 break;
2991
2992 case 0x14: /* KBC_REG */
2993 s->cols = value;
2994 omap_mpuio_kbd_update(s);
2995 break;
2996
2997 case 0x18: /* GPIO_EVENT_MODE_REG */
2998 s->event = value & 0x1f;
2999 break;
3000
3001 case 0x1c: /* GPIO_INT_EDGE_REG */
3002 s->edge = value;
3003 break;
3004
3005 case 0x28: /* KBD_MASKIT */
3006 s->kbd_mask = value & 1;
3007 omap_mpuio_kbd_update(s);
3008 break;
3009
3010 case 0x2c: /* GPIO_MASKIT */
3011 s->mask = value;
3012 break;
3013
3014 case 0x30: /* GPIO_DEBOUNCING_REG */
3015 s->debounce = value & 0x1ff;
3016 break;
3017
3018 case 0x00: /* INPUT_LATCH */
3019 case 0x10: /* KBR_LATCH */
3020 case 0x20: /* KBD_INT */
3021 case 0x24: /* GPIO_INT */
3022 case 0x34: /* GPIO_LATCH_REG */
3023 OMAP_RO_REG(addr);
3024 return;
3025
3026 default:
3027 OMAP_BAD_REG(addr);
3028 return;
3029 }
3030 }
3031
3032 static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
3033 omap_badwidth_read16,
3034 omap_mpuio_read,
3035 omap_badwidth_read16,
3036 };
3037
3038 static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
3039 omap_badwidth_write16,
3040 omap_mpuio_write,
3041 omap_badwidth_write16,
3042 };
3043
3044 static void omap_mpuio_reset(struct omap_mpuio_s *s)
3045 {
3046 s->inputs = 0;
3047 s->outputs = 0;
3048 s->dir = ~0;
3049 s->event = 0;
3050 s->edge = 0;
3051 s->kbd_mask = 0;
3052 s->mask = 0;
3053 s->debounce = 0;
3054 s->latch = 0;
3055 s->ints = 0;
3056 s->row_latch = 0x1f;
3057 s->clk = 1;
3058 }
3059
3060 static void omap_mpuio_onoff(void *opaque, int line, int on)
3061 {
3062 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
3063
3064 s->clk = on;
3065 if (on)
3066 omap_mpuio_kbd_update(s);
3067 }
3068
3069 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
3070 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
3071 omap_clk clk)
3072 {
3073 int iomemtype;
3074 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
3075 qemu_mallocz(sizeof(struct omap_mpuio_s));
3076
3077 s->base = base;
3078 s->irq = gpio_int;
3079 s->kbd_irq = kbd_int;
3080 s->wakeup = wakeup;
3081 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
3082 omap_mpuio_reset(s);
3083
3084 iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
3085 omap_mpuio_writefn, s);
3086 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3087
3088 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
3089
3090 return s;
3091 }
3092
3093 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
3094 {
3095 return s->in;
3096 }
3097
3098 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
3099 {
3100 if (line >= 16 || line < 0)
3101 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
3102 s->handler[line] = handler;
3103 }
3104
3105 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
3106 {
3107 if (row >= 5 || row < 0)
3108 cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
3109 __FUNCTION__, col, row);
3110
3111 if (down)
3112 s->buttons[row] |= 1 << col;
3113 else
3114 s->buttons[row] &= ~(1 << col);
3115
3116 omap_mpuio_kbd_update(s);
3117 }
3118
3119 /* General-Purpose I/O */
3120 struct omap_gpio_s {
3121 target_phys_addr_t base;
3122 qemu_irq irq;
3123 qemu_irq *in;
3124 qemu_irq handler[16];
3125
3126 uint16_t inputs;
3127 uint16_t outputs;
3128 uint16_t dir;
3129 uint16_t edge;
3130 uint16_t mask;
3131 uint16_t ints;
3132 uint16_t pins;
3133 };
3134
3135 static void omap_gpio_set(void *opaque, int line, int level)
3136 {
3137 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
3138 uint16_t prev = s->inputs;
3139
3140 if (level)
3141 s->inputs |= 1 << line;
3142 else
3143 s->inputs &= ~(1 << line);
3144
3145 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
3146 (1 << line) & s->dir & ~s->mask) {
3147 s->ints |= 1 << line;
3148 qemu_irq_raise(s->irq);
3149 }
3150 }
3151
3152 static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
3153 {
3154 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
3155 int offset = addr & OMAP_MPUI_REG_MASK;
3156
3157 switch (offset) {
3158 case 0x00: /* DATA_INPUT */
3159 return s->inputs & s->pins;
3160
3161 case 0x04: /* DATA_OUTPUT */
3162 return s->outputs;
3163
3164 case 0x08: /* DIRECTION_CONTROL */
3165 return s->dir;
3166
3167 case 0x0c: /* INTERRUPT_CONTROL */
3168 return s->edge;
3169
3170 case 0x10: /* INTERRUPT_MASK */
3171 return s->mask;
3172
3173 case 0x14: /* INTERRUPT_STATUS */
3174 return s->ints;
3175
3176 case 0x18: /* PIN_CONTROL (not in OMAP310) */
3177 OMAP_BAD_REG(addr);
3178 return s->pins;
3179 }
3180
3181 OMAP_BAD_REG(addr);
3182 return 0;
3183 }
3184
3185 static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
3186 uint32_t value)
3187 {
3188 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
3189 int offset = addr & OMAP_MPUI_REG_MASK;
3190 uint16_t diff;
3191 int ln;
3192
3193 switch (offset) {
3194 case 0x00: /* DATA_INPUT */
3195 OMAP_RO_REG(addr);
3196 return;
3197
3198 case 0x04: /* DATA_OUTPUT */
3199 diff = (s->outputs ^ value) & ~s->dir;
3200 s->outputs = value;
3201 while ((ln = ffs(diff))) {
3202 ln --;
3203 if (s->handler[ln])
3204 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
3205 diff &= ~(1 << ln);
3206 }
3207 break;
3208
3209 case 0x08: /* DIRECTION_CONTROL */
3210 diff = s->outputs & (s->dir ^ value);
3211 s->dir = value;
3212
3213 value = s->outputs & ~s->dir;
3214 while ((ln = ffs(diff))) {
3215 ln --;
3216 if (s->handler[ln])
3217 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
3218 diff &= ~(1 << ln);
3219 }
3220 break;
3221
3222 case 0x0c: /* INTERRUPT_CONTROL */
3223 s->edge = value;
3224 break;
3225
3226 case 0x10: /* INTERRUPT_MASK */
3227 s->mask = value;
3228 break;
3229
3230 case 0x14: /* INTERRUPT_STATUS */
3231 s->ints &= ~value;
3232 if (!s->ints)
3233 qemu_irq_lower(s->irq);
3234 break;
3235
3236 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
3237 OMAP_BAD_REG(addr);
3238 s->pins = value;
3239 break;
3240
3241 default:
3242 OMAP_BAD_REG(addr);
3243 return;
3244 }
3245 }
3246
3247 /* *Some* sources say the memory region is 32-bit. */
3248 static CPUReadMemoryFunc *omap_gpio_readfn[] = {
3249 omap_badwidth_read16,
3250 omap_gpio_read,
3251 omap_badwidth_read16,
3252 };
3253
3254 static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
3255 omap_badwidth_write16,
3256 omap_gpio_write,
3257 omap_badwidth_write16,
3258 };
3259
3260 static void omap_gpio_reset(struct omap_gpio_s *s)
3261 {
3262 s->inputs = 0;
3263 s->outputs = ~0;
3264 s->dir = ~0;
3265 s->edge = ~0;
3266 s->mask = ~0;
3267 s->ints = 0;
3268 s->pins = ~0;
3269 }
3270
3271 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
3272 qemu_irq irq, omap_clk clk)
3273 {
3274 int iomemtype;
3275 struct omap_gpio_s *s = (struct omap_gpio_s *)
3276 qemu_mallocz(sizeof(struct omap_gpio_s));
3277
3278 s->base = base;
3279 s->irq = irq;
3280 s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
3281 omap_gpio_reset(s);
3282
3283 iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
3284 omap_gpio_writefn, s);
3285 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
3286
3287 return s;
3288 }
3289
3290 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
3291 {
3292 return s->in;
3293 }
3294
3295 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
3296 {
3297 if (line >= 16 || line < 0)
3298 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
3299 s->handler[line] = handler;
3300 }
3301
3302 /* MicroWire Interface */
3303 struct omap_uwire_s {
3304 target_phys_addr_t base;
3305 qemu_irq txirq;
3306 qemu_irq rxirq;
3307 qemu_irq txdrq;
3308
3309 uint16_t txbuf;
3310 uint16_t rxbuf;
3311 uint16_t control;
3312 uint16_t setup[5];
3313
3314 struct uwire_slave_s *chip[4];
3315 };
3316
3317 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
3318 {
3319 int chipselect = (s->control >> 10) & 3; /* INDEX */
3320 struct uwire_slave_s *slave = s->chip[chipselect];
3321
3322 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
3323 if (s->control & (1 << 12)) /* CS_CMD */
3324 if (slave && slave->send)
3325 slave->send(slave->opaque,
3326 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
3327 s->control &= ~(1 << 14); /* CSRB */
3328 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3329 * a DRQ. When is the level IRQ supposed to be reset? */
3330 }
3331
3332 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
3333 if (s->control & (1 << 12)) /* CS_CMD */
3334 if (slave && slave->receive)
3335 s->rxbuf = slave->receive(slave->opaque);
3336 s->control |= 1 << 15; /* RDRB */
3337 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3338 * a DRQ. When is the level IRQ supposed to be reset? */
3339 }
3340 }
3341
3342 static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
3343 {
3344 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3345 int offset = addr & OMAP_MPUI_REG_MASK;
3346
3347 switch (offset) {
3348 case 0x00: /* RDR */
3349 s->control &= ~(1 << 15); /* RDRB */
3350 return s->rxbuf;
3351
3352 case 0x04: /* CSR */
3353 return s->control;
3354
3355 case 0x08: /* SR1 */
3356 return s->setup[0];
3357 case 0x0c: /* SR2 */
3358 return s->setup[1];
3359 case 0x10: /* SR3 */
3360 return s->setup[2];
3361 case 0x14: /* SR4 */
3362 return s->setup[3];
3363 case 0x18: /* SR5 */
3364 return s->setup[4];
3365 }
3366
3367 OMAP_BAD_REG(addr);
3368 return 0;
3369 }
3370
3371 static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
3372 uint32_t value)
3373 {
3374 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3375 int offset = addr & OMAP_MPUI_REG_MASK;
3376
3377 switch (offset) {
3378 case 0x00: /* TDR */
3379 s->txbuf = value; /* TD */
3380 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
3381 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
3382 (s->control & (1 << 12)))) { /* CS_CMD */
3383 s->control |= 1 << 14; /* CSRB */
3384 omap_uwire_transfer_start(s);
3385 }
3386 break;
3387
3388 case 0x04: /* CSR */
3389 s->control = value & 0x1fff;
3390 if (value & (1 << 13)) /* START */
3391 omap_uwire_transfer_start(s);
3392 break;
3393
3394 case 0x08: /* SR1 */
3395 s->setup[0] = value & 0x003f;
3396 break;
3397
3398 case 0x0c: /* SR2 */
3399 s->setup[1] = value & 0x0fc0;
3400 break;
3401
3402 case 0x10: /* SR3 */
3403 s->setup[2] = value & 0x0003;
3404 break;
3405
3406 case 0x14: /* SR4 */
3407 s->setup[3] = value & 0x0001;
3408 break;
3409
3410 case 0x18: /* SR5 */
3411 s->setup[4] = value & 0x000f;
3412 break;
3413
3414 default:
3415 OMAP_BAD_REG(addr);
3416 return;
3417 }
3418 }
3419
3420 static CPUReadMemoryFunc *omap_uwire_readfn[] = {
3421 omap_badwidth_read16,
3422 omap_uwire_read,
3423 omap_badwidth_read16,
3424 };
3425
3426 static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
3427 omap_badwidth_write16,
3428 omap_uwire_write,
3429 omap_badwidth_write16,
3430 };
3431
3432 static void omap_uwire_reset(struct omap_uwire_s *s)
3433 {
3434 s->control = 0;
3435 s->setup[0] = 0;
3436 s->setup[1] = 0;
3437 s->setup[2] = 0;
3438 s->setup[3] = 0;
3439 s->setup[4] = 0;
3440 }
3441
3442 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
3443 qemu_irq *irq, qemu_irq dma, omap_clk clk)
3444 {
3445 int iomemtype;
3446 struct omap_uwire_s *s = (struct omap_uwire_s *)
3447 qemu_mallocz(sizeof(struct omap_uwire_s));
3448
3449 s->base = base;
3450 s->txirq = irq[0];
3451 s->rxirq = irq[1];
3452 s->txdrq = dma;
3453 omap_uwire_reset(s);
3454
3455 iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
3456 omap_uwire_writefn, s);
3457 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3458
3459 return s;
3460 }
3461
3462 void omap_uwire_attach(struct omap_uwire_s *s,
3463 struct uwire_slave_s *slave, int chipselect)
3464 {
3465 if (chipselect < 0 || chipselect > 3)
3466 cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n", __FUNCTION__,
3467 chipselect);
3468
3469 s->chip[chipselect] = slave;
3470 }
3471
3472 /* Pseudonoise Pulse-Width Light Modulator */
3473 static void omap_pwl_update(struct omap_mpu_state_s *s)
3474 {
3475 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
3476
3477 if (output != s->pwl.output) {
3478 s->pwl.output = output;
3479 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
3480 }
3481 }
3482
3483 static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
3484 {
3485 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3486 int offset = addr & OMAP_MPUI_REG_MASK;
3487
3488 switch (offset) {
3489 case 0x00: /* PWL_LEVEL */
3490 return s->pwl.level;
3491 case 0x04: /* PWL_CTRL */
3492 return s->pwl.enable;
3493 }
3494 OMAP_BAD_REG(addr);
3495 return 0;
3496 }
3497
3498 static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
3499 uint32_t value)
3500 {
3501 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3502 int offset = addr & OMAP_MPUI_REG_MASK;
3503
3504 switch (offset) {
3505 case 0x00: /* PWL_LEVEL */
3506 s->pwl.level = value;
3507 omap_pwl_update(s);
3508 break;
3509 case 0x04: /* PWL_CTRL */
3510 s->pwl.enable = value & 1;
3511 omap_pwl_update(s);
3512 break;
3513 default:
3514 OMAP_BAD_REG(addr);
3515 return;
3516 }
3517 }
3518
3519 static CPUReadMemoryFunc *omap_pwl_readfn[] = {
3520 omap_pwl_read,
3521 omap_badwidth_read8,
3522 omap_badwidth_read8,
3523 };
3524
3525 static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
3526 omap_pwl_write,
3527 omap_badwidth_write8,
3528 omap_badwidth_write8,
3529 };
3530
3531 static void omap_pwl_reset(struct omap_mpu_state_s *s)
3532 {
3533 s->pwl.output = 0;
3534 s->pwl.level = 0;
3535 s->pwl.enable = 0;
3536 s->pwl.clk = 1;
3537 omap_pwl_update(s);
3538 }
3539
3540 static void omap_pwl_clk_update(void *opaque, int line, int on)
3541 {
3542 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3543
3544 s->pwl.clk = on;
3545 omap_pwl_update(s);
3546 }
3547
3548 static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3549 omap_clk clk)
3550 {
3551 int iomemtype;
3552
3553 omap_pwl_reset(s);
3554
3555 iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
3556 omap_pwl_writefn, s);
3557 cpu_register_physical_memory(base, 0x800, iomemtype);
3558
3559 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
3560 }
3561
3562 /* Pulse-Width Tone module */
3563 static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
3564 {
3565 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3566 int offset = addr & OMAP_MPUI_REG_MASK;
3567
3568 switch (offset) {
3569 case 0x00: /* FRC */
3570 return s->pwt.frc;
3571 case 0x04: /* VCR */
3572 return s->pwt.vrc;
3573 case 0x08: /* GCR */
3574 return s->pwt.gcr;
3575 }
3576 OMAP_BAD_REG(addr);
3577 return 0;
3578 }
3579
3580 static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
3581 uint32_t value)
3582 {
3583 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3584 int offset = addr & OMAP_MPUI_REG_MASK;
3585
3586 switch (offset) {
3587 case 0x00: /* FRC */
3588 s->pwt.frc = value & 0x3f;
3589 break;
3590 case 0x04: /* VRC */
3591 if ((value ^ s->pwt.vrc) & 1) {
3592 if (value & 1)
3593 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
3594 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
3595 ((omap_clk_getrate(s->pwt.clk) >> 3) /
3596 /* Pre-multiplexer divider */
3597 ((s->pwt.gcr & 2) ? 1 : 154) /
3598 /* Octave multiplexer */
3599 (2 << (value & 3)) *
3600 /* 101/107 divider */
3601 ((value & (1 << 2)) ? 101 : 107) *
3602 /* 49/55 divider */
3603 ((value & (1 << 3)) ? 49 : 55) *
3604 /* 50/63 divider */
3605 ((value & (1 << 4)) ? 50 : 63) *
3606 /* 80/127 divider */
3607 ((value & (1 << 5)) ? 80 : 127) /
3608 (107 * 55 * 63 * 127)));
3609 else
3610 printf("%s: silence!\n", __FUNCTION__);
3611 }
3612 s->pwt.vrc = value & 0x7f;
3613 break;
3614 case 0x08: /* GCR */
3615 s->pwt.gcr = value & 3;
3616 break;
3617 default:
3618 OMAP_BAD_REG(addr);
3619 return;
3620 }
3621 }
3622
3623 static CPUReadMemoryFunc *omap_pwt_readfn[] = {
3624 omap_pwt_read,
3625 omap_badwidth_read8,
3626 omap_badwidth_read8,
3627 };
3628
3629 static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
3630 omap_pwt_write,
3631 omap_badwidth_write8,
3632 omap_badwidth_write8,
3633 };
3634
3635 static void omap_pwt_reset(struct omap_mpu_state_s *s)
3636 {
3637 s->pwt.frc = 0;
3638 s->pwt.vrc = 0;
3639 s->pwt.gcr = 0;
3640 }
3641
3642 static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3643 omap_clk clk)
3644 {
3645 int iomemtype;
3646
3647 s->pwt.clk = clk;
3648 omap_pwt_reset(s);
3649
3650 iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
3651 omap_pwt_writefn, s);
3652 cpu_register_physical_memory(base, 0x800, iomemtype);
3653 }
3654
3655 /* Real-time Clock module */
3656 struct omap_rtc_s {
3657 target_phys_addr_t base;
3658 qemu_irq irq;
3659 qemu_irq alarm;
3660 QEMUTimer *clk;
3661
3662 uint8_t interrupts;
3663 uint8_t status;
3664 int16_t comp_reg;
3665 int running;
3666 int pm_am;
3667 int auto_comp;
3668 int round;
3669 struct tm *(*convert)(const time_t *timep, struct tm *result);
3670 struct tm alarm_tm;
3671 time_t alarm_ti;
3672
3673 struct tm current_tm;
3674 time_t ti;
3675 uint64_t tick;
3676 };
3677
3678 static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
3679 {
3680 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
3681 }
3682
3683 static void omap_rtc_alarm_update(struct omap_rtc_s *s)
3684 {
3685 s->alarm_ti = mktime(&s->alarm_tm);
3686 if (s->alarm_ti == -1)
3687 printf("%s: conversion failed\n", __FUNCTION__);
3688 }
3689
3690 static inline uint8_t omap_rtc_bcd(int num)
3691 {
3692 return ((num / 10) << 4) | (num % 10);
3693 }
3694
3695 static inline int omap_rtc_bin(uint8_t num)
3696 {
3697 return (num & 15) + 10 * (num >> 4);
3698 }
3699
3700 static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
3701 {
3702 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3703 int offset = addr & OMAP_MPUI_REG_MASK;
3704 uint8_t i;
3705
3706 switch (offset) {
3707 case 0x00: /* SECONDS_REG */
3708 return omap_rtc_bcd(s->current_tm.tm_sec);
3709
3710 case 0x04: /* MINUTES_REG */
3711 return omap_rtc_bcd(s->current_tm.tm_min);
3712
3713 case 0x08: /* HOURS_REG */
3714 if (s->pm_am)
3715 return ((s->current_tm.tm_hour > 11) << 7) |
3716 omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
3717 else
3718 return omap_rtc_bcd(s->current_tm.tm_hour);
3719
3720 case 0x0c: /* DAYS_REG */
3721 return omap_rtc_bcd(s->current_tm.tm_mday);
3722
3723 case 0x10: /* MONTHS_REG */
3724 return omap_rtc_bcd(s->current_tm.tm_mon + 1);
3725
3726 case 0x14: /* YEARS_REG */
3727 return omap_rtc_bcd(s->current_tm.tm_year % 100);
3728
3729 case 0x18: /* WEEK_REG */
3730 return s->current_tm.tm_wday;
3731
3732 case 0x20: /* ALARM_SECONDS_REG */
3733 return omap_rtc_bcd(s->alarm_tm.tm_sec);
3734
3735 case 0x24: /* ALARM_MINUTES_REG */
3736 return omap_rtc_bcd(s->alarm_tm.tm_min);
3737
3738 case 0x28: /* ALARM_HOURS_REG */
3739 if (s->pm_am)
3740 return ((s->alarm_tm.tm_hour > 11) << 7) |
3741 omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
3742 else
3743 return omap_rtc_bcd(s->alarm_tm.tm_hour);
3744
3745 case 0x2c: /* ALARM_DAYS_REG */
3746 return omap_rtc_bcd(s->alarm_tm.tm_mday);
3747
3748 case 0x30: /* ALARM_MONTHS_REG */
3749 return omap_rtc_bcd(s->alarm_tm.tm_mon + 1);
3750
3751 case 0x34: /* ALARM_YEARS_REG */
3752 return omap_rtc_bcd(s->alarm_tm.tm_year % 100);
3753
3754 case 0x40: /* RTC_CTRL_REG */
3755 return (s->pm_am << 3) | (s->auto_comp << 2) |
3756 (s->round << 1) | s->running;
3757
3758 case 0x44: /* RTC_STATUS_REG */
3759 i = s->status;
3760 s->status &= ~0x3d;
3761 return i;
3762
3763 case 0x48: /* RTC_INTERRUPTS_REG */
3764 return s->interrupts;
3765
3766 case 0x4c: /* RTC_COMP_LSB_REG */
3767 return ((uint16_t) s->comp_reg) & 0xff;
3768
3769 case 0x50: /* RTC_COMP_MSB_REG */
3770 return ((uint16_t) s->comp_reg) >> 8;
3771 }
3772
3773 OMAP_BAD_REG(addr);
3774 return 0;
3775 }
3776
3777 static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
3778 uint32_t value)
3779 {
3780 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3781 int offset = addr & OMAP_MPUI_REG_MASK;
3782 struct tm new_tm;
3783 time_t ti[2];
3784
3785 switch (offset) {
3786 case 0x00: /* SECONDS_REG */
3787 #if ALMDEBUG
3788 printf("RTC SEC_REG <-- %02x\n", value);
3789 #endif
3790 s->ti -= s->current_tm.tm_sec;
3791 s->ti += omap_rtc_bin(value);
3792 return;
3793
3794 case 0x04: /* MINUTES_REG */
3795 #if ALMDEBUG
3796 printf("RTC MIN_REG <-- %02x\n", value);
3797 #endif
3798 s->ti -= s->current_tm.tm_min * 60;
3799 s->ti += omap_rtc_bin(value) * 60;
3800 return;
3801
3802 case 0x08: /* HOURS_REG */
3803 #if ALMDEBUG
3804 printf("RTC HRS_REG <-- %02x\n", value);
3805 #endif
3806 s->ti -= s->current_tm.tm_hour * 3600;
3807 if (s->pm_am) {
3808 s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600;
3809 s->ti += ((value >> 7) & 1) * 43200;
3810 } else
3811 s->ti += omap_rtc_bin(value & 0x3f) * 3600;
3812 return;
3813
3814 case 0x0c: /* DAYS_REG */
3815 #if ALMDEBUG
3816 printf("RTC DAY_REG <-- %02x\n", value);
3817 #endif
3818 s->ti -= s->current_tm.tm_mday * 86400;
3819 s->ti += omap_rtc_bin(value) * 86400;
3820 return;
3821
3822 case 0x10: /* MONTHS_REG */
3823 #if ALMDEBUG
3824 printf("RTC MTH_REG <-- %02x\n", value);
3825 #endif
3826 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3827 new_tm.tm_mon = omap_rtc_bin(value);
3828 ti[0] = mktime(&s->current_tm);
3829 ti[1] = mktime(&new_tm);
3830
3831 if (ti[0] != -1 && ti[1] != -1) {
3832 s->ti -= ti[0];
3833 s->ti += ti[1];
3834 } else {
3835 /* A less accurate version */
3836 s->ti -= s->current_tm.tm_mon * 2592000;
3837 s->ti += omap_rtc_bin(value) * 2592000;
3838 }
3839 return;
3840
3841 case 0x14: /* YEARS_REG */
3842 #if ALMDEBUG
3843 printf("RTC YRS_REG <-- %02x\n", value);
3844 #endif
3845 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3846 new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
3847 ti[0] = mktime(&s->current_tm);
3848 ti[1] = mktime(&new_tm);
3849
3850 if (ti[0] != -1 && ti[1] != -1) {
3851 s->ti -= ti[0];
3852 s->ti += ti[1];
3853 } else {
3854 /* A less accurate version */
3855 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
3856 s->ti += omap_rtc_bin(value) * 31536000;
3857 }
3858 return;
3859
3860 case 0x18: /* WEEK_REG */
3861 return; /* Ignored */
3862
3863 case 0x20: /* ALARM_SECONDS_REG */
3864 #if ALMDEBUG
3865 printf("ALM SEC_REG <-- %02x\n", value);
3866 #endif
3867 s->alarm_tm.tm_sec = omap_rtc_bin(value);
3868 omap_rtc_alarm_update(s);
3869 return;
3870
3871 case 0x24: /* ALARM_MINUTES_REG */
3872 #if ALMDEBUG
3873 printf("ALM MIN_REG <-- %02x\n", value);
3874 #endif
3875 s->alarm_tm.tm_min = omap_rtc_bin(value);
3876 omap_rtc_alarm_update(s);
3877 return;
3878
3879 case 0x28: /* ALARM_HOURS_REG */
3880 #if ALMDEBUG
3881 printf("ALM HRS_REG <-- %02x\n", value);
3882 #endif
3883 if (s->pm_am)
3884 s->alarm_tm.tm_hour =
3885 ((omap_rtc_bin(value & 0x3f)) % 12) +
3886 ((value >> 7) & 1) * 12;
3887 else
3888 s->alarm_tm.tm_hour = omap_rtc_bin(value);
3889 omap_rtc_alarm_update(s);
3890 return;
3891
3892 case 0x2c: /* ALARM_DAYS_REG */
3893 #if ALMDEBUG
3894 printf("ALM DAY_REG <-- %02x\n", value);
3895 #endif
3896 s->alarm_tm.tm_mday = omap_rtc_bin(value);
3897 omap_rtc_alarm_update(s);
3898 return;
3899
3900 case 0x30: /* ALARM_MONTHS_REG */
3901 #if ALMDEBUG
3902 printf("ALM MON_REG <-- %02x\n", value);
3903 #endif
3904 s->alarm_tm.tm_mon = omap_rtc_bin(value);
3905 omap_rtc_alarm_update(s);
3906 return;
3907
3908 case 0x34: /* ALARM_YEARS_REG */
3909 #if ALMDEBUG
3910 printf("ALM YRS_REG <-- %02x\n", value);
3911 #endif
3912 s->alarm_tm.tm_year = omap_rtc_bin(value);
3913 omap_rtc_alarm_update(s);
3914 return;
3915
3916 case 0x40: /* RTC_CTRL_REG */
3917 #if ALMDEBUG
3918 printf("RTC CONTROL <-- %02x\n", value);
3919 #endif
3920 s->pm_am = (value >> 3) & 1;
3921 s->auto_comp = (value >> 2) & 1;
3922 s->round = (value >> 1) & 1;
3923 s->running = value & 1;
3924 s->status &= 0xfd;
3925 s->status |= s->running << 1;
3926 return;
3927
3928 case 0x44: /* RTC_STATUS_REG */
3929 #if ALMDEBUG
3930 printf("RTC STATUSL <-- %02x\n", value);
3931 #endif
3932 s->status &= ~((value & 0xc0) ^ 0x80);
3933 omap_rtc_interrupts_update(s);
3934 return;
3935
3936 case 0x48: /* RTC_INTERRUPTS_REG */
3937 #if ALMDEBUG
3938 printf("RTC INTRS <-- %02x\n", value);
3939 #endif
3940 s->interrupts = value;
3941 return;
3942
3943 case 0x4c: /* RTC_COMP_LSB_REG */
3944 #if ALMDEBUG
3945 printf("RTC COMPLSB <-- %02x\n", value);
3946 #endif
3947 s->comp_reg &= 0xff00;
3948 s->comp_reg |= 0x00ff & value;
3949 return;
3950
3951 case 0x50: /* RTC_COMP_MSB_REG */
3952 #if ALMDEBUG
3953 printf("RTC COMPMSB <-- %02x\n", value);
3954 #endif
3955 s->comp_reg &= 0x00ff;
3956 s->comp_reg |= 0xff00 & (value << 8);
3957 return;
3958
3959 default:
3960 OMAP_BAD_REG(addr);
3961 return;
3962 }
3963 }
3964
3965 static CPUReadMemoryFunc *omap_rtc_readfn[] = {
3966 omap_rtc_read,
3967 omap_badwidth_read8,
3968 omap_badwidth_read8,
3969 };
3970
3971 static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
3972 omap_rtc_write,
3973 omap_badwidth_write8,
3974 omap_badwidth_write8,
3975 };
3976
3977 static void omap_rtc_tick(void *opaque)
3978 {
3979 struct omap_rtc_s *s = opaque;
3980
3981 if (s->round) {
3982 /* Round to nearest full minute. */
3983 if (s->current_tm.tm_sec < 30)
3984 s->ti -= s->current_tm.tm_sec;
3985 else
3986 s->ti += 60 - s->current_tm.tm_sec;
3987
3988 s->round = 0;
3989 }
3990
3991 localtime_r(&s->ti, &s->current_tm);
3992
3993 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
3994 s->status |= 0x40;
3995 omap_rtc_interrupts_update(s);
3996 }
3997
3998 if (s->interrupts & 0x04)
3999 switch (s->interrupts & 3) {
4000 case 0:
4001 s->status |= 0x04;
4002 qemu_irq_raise(s->irq);
4003 break;
4004 case 1:
4005 if (s->current_tm.tm_sec)
4006 break;
4007 s->status |= 0x08;
4008 qemu_irq_raise(s->irq);
4009 break;
4010 case 2:
4011 if (s->current_tm.tm_sec || s->current_tm.tm_min)
4012 break;
4013 s->status |= 0x10;
4014 qemu_irq_raise(s->irq);
4015 break;
4016 case 3:
4017 if (s->current_tm.tm_sec ||
4018 s->current_tm.tm_min || s->current_tm.tm_hour)
4019 break;
4020 s->status |= 0x20;
4021 qemu_irq_raise(s->irq);
4022 break;
4023 }
4024
4025 /* Move on */
4026 if (s->running)
4027 s->ti ++;
4028 s->tick += 1000;
4029
4030 /*
4031 * Every full hour add a rough approximation of the compensation
4032 * register to the 32kHz Timer (which drives the RTC) value.
4033 */
4034 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
4035 s->tick += s->comp_reg * 1000 / 32768;
4036
4037 qemu_mod_timer(s->clk, s->tick);
4038 }
4039
4040 static void omap_rtc_reset(struct omap_rtc_s *s)
4041 {
4042 s->interrupts = 0;
4043 s->comp_reg = 0;
4044 s->running = 0;
4045 s->pm_am = 0;
4046 s->auto_comp = 0;
4047 s->round = 0;
4048 s->tick = qemu_get_clock(rt_clock);
4049 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
4050 s->alarm_tm.tm_mday = 0x01;
4051 s->status = 1 << 7;
4052 time(&s->ti);
4053 s->ti = mktime(s->convert(&s->ti, &s->current_tm));
4054
4055 omap_rtc_alarm_update(s);
4056 omap_rtc_tick(s);
4057 }
4058
4059 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
4060 qemu_irq *irq, omap_clk clk)
4061 {
4062 int iomemtype;
4063 struct omap_rtc_s *s = (struct omap_rtc_s *)
4064 qemu_mallocz(sizeof(struct omap_rtc_s));
4065
4066 s->base = base;
4067 s->irq = irq[0];
4068 s->alarm = irq[1];
4069 s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);
4070 s->convert = rtc_utc ? gmtime_r : localtime_r;
4071
4072 omap_rtc_reset(s);
4073
4074 iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
4075 omap_rtc_writefn, s);
4076 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4077
4078 return s;
4079 }
4080
4081 /* Multi-channel Buffered Serial Port interfaces */
4082 struct omap_mcbsp_s {
4083 target_phys_addr_t base;
4084 qemu_irq txirq;
4085 qemu_irq rxirq;
4086 qemu_irq txdrq;
4087 qemu_irq rxdrq;
4088
4089 uint16_t spcr[2];
4090 uint16_t rcr[2];
4091 uint16_t xcr[2];
4092 uint16_t srgr[2];
4093 uint16_t mcr[2];
4094 uint16_t pcr;
4095 uint16_t rcer[8];
4096 uint16_t xcer[8];
4097 int tx_rate;
4098 int rx_rate;
4099 int tx_req;
4100
4101 struct i2s_codec_s *codec;
4102 };
4103
4104 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
4105 {
4106 int irq;
4107
4108 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
4109 case 0:
4110 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
4111 break;
4112 case 3:
4113 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
4114 break;
4115 default:
4116 irq = 0;
4117 break;
4118 }
4119
4120 qemu_set_irq(s->rxirq, irq);
4121
4122 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
4123 case 0:
4124 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
4125 break;
4126 case 3:
4127 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
4128 break;
4129 default:
4130 irq = 0;
4131 break;
4132 }
4133
4134 qemu_set_irq(s->txirq, irq);
4135 }
4136
4137 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
4138 {
4139 int prev = s->tx_req;
4140
4141 s->tx_req = (s->tx_rate ||
4142 (s->spcr[0] & (1 << 12))) && /* CLKSTP */
4143 (s->spcr[1] & (1 << 6)) && /* GRST */
4144 (s->spcr[1] & (1 << 0)); /* XRST */
4145
4146 if (!s->tx_req && prev) {
4147 s->spcr[1] &= ~(1 << 1); /* XRDY */
4148 qemu_irq_lower(s->txdrq);
4149 omap_mcbsp_intr_update(s);
4150
4151 if (s->codec)
4152 s->codec->tx_swallow(s->codec->opaque);
4153 } else if (s->codec && s->tx_req && !prev) {
4154 s->spcr[1] |= 1 << 1; /* XRDY */
4155 qemu_irq_raise(s->txdrq);
4156 omap_mcbsp_intr_update(s);
4157 }
4158 }
4159
4160 static void omap_mcbsp_rate_update(struct omap_mcbsp_s *s)
4161 {
4162 int rx_clk = 0, tx_clk = 0;
4163 int cpu_rate = 1500000; /* XXX */
4164 if (!s->codec)
4165 return;
4166
4167 if (s->spcr[1] & (1 << 6)) { /* GRST */
4168 if (s->spcr[0] & (1 << 0)) /* RRST */
4169 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
4170 (s->pcr & (1 << 8))) /* CLKRM */
4171 if (~s->pcr & (1 << 7)) /* SCLKME */
4172 rx_clk = cpu_rate /
4173 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
4174 if (s->spcr[1] & (1 << 0)) /* XRST */
4175 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
4176 (s->pcr & (1 << 9))) /* CLKXM */
4177 if (~s->pcr & (1 << 7)) /* SCLKME */
4178 tx_clk = cpu_rate /
4179 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
4180 }
4181
4182 s->codec->set_rate(s->codec->opaque, rx_clk, tx_clk);
4183 }
4184
4185 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
4186 {
4187 if (!(s->spcr[0] & 1)) { /* RRST */
4188 if (s->codec)
4189 s->codec->in.len = 0;
4190 return;
4191 }
4192
4193 if ((s->spcr[0] >> 1) & 1) /* RRDY */
4194 s->spcr[0] |= 1 << 2; /* RFULL */
4195 s->spcr[0] |= 1 << 1; /* RRDY */
4196 qemu_irq_raise(s->rxdrq);
4197 omap_mcbsp_intr_update(s);
4198 }
4199
4200 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
4201 {
4202 s->spcr[0] &= ~(1 << 1); /* RRDY */
4203 qemu_irq_lower(s->rxdrq);
4204 omap_mcbsp_intr_update(s);
4205 }
4206
4207 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
4208 {
4209 if (s->tx_rate)
4210 return;
4211 s->tx_rate = 1;
4212 omap_mcbsp_req_update(s);
4213 }
4214
4215 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
4216 {
4217 s->tx_rate = 0;
4218 omap_mcbsp_req_update(s);
4219 }
4220
4221 static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
4222 {
4223 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4224 int offset = addr & OMAP_MPUI_REG_MASK;
4225 uint16_t ret;
4226
4227 switch (offset) {
4228 case 0x00: /* DRR2 */
4229 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
4230 return 0x0000;
4231 /* Fall through. */
4232 case 0x02: /* DRR1 */
4233 if (!s->codec)
4234 return 0x0000;
4235 if (s->codec->in.len < 2) {
4236 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
4237 omap_mcbsp_rx_stop(s);
4238 } else {
4239 s->codec->in.len -= 2;
4240 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
4241 ret |= s->codec->in.fifo[s->codec->in.start ++];
4242 if (!s->codec->in.len)
4243 omap_mcbsp_rx_stop(s);
4244 return ret;
4245 }
4246 return 0x0000;
4247
4248 case 0x04: /* DXR2 */
4249 case 0x06: /* DXR1 */
4250 return 0x0000;
4251
4252 case 0x08: /* SPCR2 */
4253 return s->spcr[1];
4254 case 0x0a: /* SPCR1 */
4255 return s->spcr[0];
4256 case 0x0c: /* RCR2 */
4257 return s->rcr[1];
4258 case 0x0e: /* RCR1 */
4259 return s->rcr[0];
4260 case 0x10: /* XCR2 */
4261 return s->xcr[1];
4262 case 0x12: /* XCR1 */
4263 return s->xcr[0];
4264 case 0x14: /* SRGR2 */
4265 return s->srgr[1];
4266 case 0x16: /* SRGR1 */
4267 return s->srgr[0];
4268 case 0x18: /* MCR2 */
4269 return s->mcr[1];
4270 case 0x1a: /* MCR1 */
4271 return s->mcr[0];
4272 case 0x1c: /* RCERA */
4273 return s->rcer[0];
4274 case 0x1e: /* RCERB */
4275 return s->rcer[1];
4276 case 0x20: /* XCERA */
4277 return s->xcer[0];
4278 case 0x22: /* XCERB */
4279 return s->xcer[1];
4280 case 0x24: /* PCR0 */
4281 return s->pcr;
4282 case 0x26: /* RCERC */
4283 return s->rcer[2];
4284 case 0x28: /* RCERD */
4285 return s->rcer[3];
4286 case 0x2a: /* XCERC */
4287 return s->xcer[2];
4288 case 0x2c: /* XCERD */
4289 return s->xcer[3];
4290 case 0x2e: /* RCERE */
4291 return s->rcer[4];
4292 case 0x30: /* RCERF */
4293 return s->rcer[5];
4294 case 0x32: /* XCERE */
4295 return s->xcer[4];
4296 case 0x34: /* XCERF */
4297 return s->xcer[5];
4298 case 0x36: /* RCERG */
4299 return s->rcer[6];
4300 case 0x38: /* RCERH */
4301 return s->rcer[7];
4302 case 0x3a: /* XCERG */
4303 return s->xcer[6];
4304 case 0x3c: /* XCERH */
4305 return s->xcer[7];
4306 }
4307
4308 OMAP_BAD_REG(addr);
4309 return 0;
4310 }
4311
4312 static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
4313 uint32_t value)
4314 {
4315 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4316 int offset = addr & OMAP_MPUI_REG_MASK;
4317
4318 switch (offset) {
4319 case 0x00: /* DRR2 */
4320 case 0x02: /* DRR1 */
4321 OMAP_RO_REG(addr);
4322 return;
4323
4324 case 0x04: /* DXR2 */
4325 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4326 return;
4327 /* Fall through. */
4328 case 0x06: /* DXR1 */
4329 if (!s->codec)
4330 return;
4331 if (s->tx_req) {
4332 if (s->codec->out.len > s->codec->out.size - 2) {
4333 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4334 omap_mcbsp_tx_stop(s);
4335 } else {
4336 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
4337 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
4338 if (s->codec->out.len >= s->codec->out.size)
4339 omap_mcbsp_tx_stop(s);
4340 }
4341 } else
4342 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4343 return;
4344
4345 case 0x08: /* SPCR2 */
4346 s->spcr[1] &= 0x0002;
4347 s->spcr[1] |= 0x03f9 & value;
4348 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
4349 if (~value & 1) { /* XRST */
4350 s->spcr[1] &= ~6;
4351 qemu_irq_lower(s->rxdrq);
4352 if (s->codec)
4353 s->codec->out.len = 0;
4354 }
4355 if (s->codec)
4356 omap_mcbsp_rate_update(s);
4357 omap_mcbsp_req_update(s);
4358 return;
4359 case 0x0a: /* SPCR1 */
4360 s->spcr[0] &= 0x0006;
4361 s->spcr[0] |= 0xf8f9 & value;
4362 if (value & (1 << 15)) /* DLB */
4363 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
4364 if (~value & 1) { /* RRST */
4365 s->spcr[0] &= ~6;
4366 qemu_irq_lower(s->txdrq);
4367 if (s->codec)
4368 s->codec->in.len = 0;
4369 }
4370 if (s->codec)
4371 omap_mcbsp_rate_update(s);
4372 omap_mcbsp_req_update(s);
4373 return;
4374
4375 case 0x0c: /* RCR2 */
4376 s->rcr[1] = value & 0xffff;
4377 return;
4378 case 0x0e: /* RCR1 */
4379 s->rcr[0] = value & 0x7fe0;
4380 return;
4381 case 0x10: /* XCR2 */
4382 s->xcr[1] = value & 0xffff;
4383 return;
4384 case 0x12: /* XCR1 */
4385 s->xcr[0] = value & 0x7fe0;
4386 return;
4387 case 0x14: /* SRGR2 */
4388 s->srgr[1] = value & 0xffff;
4389 omap_mcbsp_rate_update(s);
4390 return;
4391 case 0x16: /* SRGR1 */
4392 s->srgr[0] = value & 0xffff;
4393 omap_mcbsp_rate_update(s);
4394 return;
4395 case 0x18: /* MCR2 */
4396 s->mcr[1] = value & 0x03e3;
4397 if (value & 3) /* XMCM */
4398 printf("%s: Tx channel selection mode enable attempt\n",
4399 __FUNCTION__);
4400 return;
4401 case 0x1a: /* MCR1 */
4402 s->mcr[0] = value & 0x03e1;
4403 if (value & 1) /* RMCM */
4404 printf("%s: Rx channel selection mode enable attempt\n",
4405 __FUNCTION__);
4406 return;
4407 case 0x1c: /* RCERA */
4408 s->rcer[0] = value & 0xffff;
4409 return;
4410 case 0x1e: /* RCERB */
4411 s->rcer[1] = value & 0xffff;
4412 return;
4413 case 0x20: /* XCERA */
4414 s->xcer[0] = value & 0xffff;
4415 return;
4416 case 0x22: /* XCERB */
4417 s->xcer[1] = value & 0xffff;
4418 return;
4419 case 0x24: /* PCR0 */
4420 s->pcr = value & 0x7faf;
4421 return;
4422 case 0x26: /* RCERC */
4423 s->rcer[2] = value & 0xffff;
4424 return;
4425 case 0x28: /* RCERD */
4426 s->rcer[3] = value & 0xffff;
4427 return;
4428 case 0x2a: /* XCERC */
4429 s->xcer[2] = value & 0xffff;
4430 return;
4431 case 0x2c: /* XCERD */
4432 s->xcer[3] = value & 0xffff;
4433 return;
4434 case 0x2e: /* RCERE */
4435 s->rcer[4] = value & 0xffff;
4436 return;
4437 case 0x30: /* RCERF */
4438 s->rcer[5] = value & 0xffff;
4439 return;
4440 case 0x32: /* XCERE */
4441 s->xcer[4] = value & 0xffff;
4442 return;
4443 case 0x34: /* XCERF */
4444 s->xcer[5] = value & 0xffff;
4445 return;
4446 case 0x36: /* RCERG */
4447 s->rcer[6] = value & 0xffff;
4448 return;
4449 case 0x38: /* RCERH */
4450 s->rcer[7] = value & 0xffff;
4451 return;
4452 case 0x3a: /* XCERG */
4453 s->xcer[6] = value & 0xffff;
4454 return;
4455 case 0x3c: /* XCERH */
4456 s->xcer[7] = value & 0xffff;
4457 return;
4458 }
4459
4460 OMAP_BAD_REG(addr);
4461 }
4462
4463 static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
4464 omap_badwidth_read16,
4465 omap_mcbsp_read,
4466 omap_badwidth_read16,
4467 };
4468
4469 static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
4470 omap_badwidth_write16,
4471 omap_mcbsp_write,
4472 omap_badwidth_write16,
4473 };
4474
4475 static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
4476 {
4477 memset(&s->spcr, 0, sizeof(s->spcr));
4478 memset(&s->rcr, 0, sizeof(s->rcr));
4479 memset(&s->xcr, 0, sizeof(s->xcr));
4480 s->srgr[0] = 0x0001;
4481 s->srgr[1] = 0x2000;
4482 memset(&s->mcr, 0, sizeof(s->mcr));
4483 memset(&s->pcr, 0, sizeof(s->pcr));
4484 memset(&s->rcer, 0, sizeof(s->rcer));
4485 memset(&s->xcer, 0, sizeof(s->xcer));
4486 s->tx_req = 0;
4487 s->tx_rate = 0;
4488 s->rx_rate = 0;
4489 }
4490
4491 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
4492 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
4493 {
4494 int iomemtype;
4495 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
4496 qemu_mallocz(sizeof(struct omap_mcbsp_s));
4497
4498 s->base = base;
4499 s->txirq = irq[0];
4500 s->rxirq = irq[1];
4501 s->txdrq = dma[0];
4502 s->rxdrq = dma[1];
4503 omap_mcbsp_reset(s);
4504
4505 iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
4506 omap_mcbsp_writefn, s);
4507 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4508
4509 return s;
4510 }
4511
4512 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
4513 {
4514 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4515
4516 omap_mcbsp_rx_start(s);
4517 }
4518
4519 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
4520 {
4521 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4522
4523 omap_mcbsp_tx_start(s);
4524 }
4525
4526 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave)
4527 {
4528 s->codec = slave;
4529 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
4530 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
4531 }
4532
4533 /* General chip reset */
4534 static void omap_mpu_reset(void *opaque)
4535 {
4536 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4537
4538 omap_clkm_reset(mpu);
4539 omap_inth_reset(mpu->ih[0]);
4540 omap_inth_reset(mpu->ih[1]);
4541 omap_dma_reset(mpu->dma);
4542 omap_mpu_timer_reset(mpu->timer[0]);
4543 omap_mpu_timer_reset(mpu->timer[1]);
4544 omap_mpu_timer_reset(mpu->timer[2]);
4545 omap_wd_timer_reset(mpu->wdt);
4546 omap_os_timer_reset(mpu->os_timer);
4547 omap_lcdc_reset(mpu->lcd);
4548 omap_ulpd_pm_reset(mpu);
4549 omap_pin_cfg_reset(mpu);
4550 omap_mpui_reset(mpu);
4551 omap_tipb_bridge_reset(mpu->private_tipb);
4552 omap_tipb_bridge_reset(mpu->public_tipb);
4553 omap_dpll_reset(&mpu->dpll[0]);
4554 omap_dpll_reset(&mpu->dpll[1]);
4555 omap_dpll_reset(&mpu->dpll[2]);
4556 omap_uart_reset(mpu->uart[0]);
4557 omap_uart_reset(mpu->uart[1]);
4558 omap_uart_reset(mpu->uart[2]);
4559 omap_mmc_reset(mpu->mmc);
4560 omap_mpuio_reset(mpu->mpuio);
4561 omap_gpio_reset(mpu->gpio);
4562 omap_uwire_reset(mpu->microwire);
4563 omap_pwl_reset(mpu);
4564 omap_pwt_reset(mpu);
4565 omap_i2c_reset(mpu->i2c);
4566 omap_rtc_reset(mpu->rtc);
4567 omap_mcbsp_reset(mpu->mcbsp1);
4568 omap_mcbsp_reset(mpu->mcbsp2);
4569 omap_mcbsp_reset(mpu->mcbsp3);
4570 cpu_reset(mpu->env);
4571 }
4572
4573 static const struct omap_map_s {
4574 target_phys_addr_t phys_dsp;
4575 target_phys_addr_t phys_mpu;
4576 uint32_t size;
4577 const char *name;
4578 } omap15xx_dsp_mm[] = {
4579 /* Strobe 0 */
4580 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
4581 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
4582 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
4583 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
4584 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
4585 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
4586 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
4587 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
4588 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
4589 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
4590 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
4591 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
4592 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
4593 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
4594 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
4595 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
4596 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
4597 /* Strobe 1 */
4598 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
4599
4600 { 0 }
4601 };
4602
4603 static void omap_setup_dsp_mapping(const struct omap_map_s *map)
4604 {
4605 int io;
4606
4607 for (; map->phys_dsp; map ++) {
4608 io = cpu_get_physical_page_desc(map->phys_mpu);
4609
4610 cpu_register_physical_memory(map->phys_dsp, map->size, io);
4611 }
4612 }
4613
4614 static void omap_mpu_wakeup(void *opaque, int irq, int req)
4615 {
4616 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4617
4618 if (mpu->env->halted)
4619 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
4620 }
4621
4622 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
4623 DisplayState *ds, const char *core)
4624 {
4625 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4626 qemu_mallocz(sizeof(struct omap_mpu_state_s));
4627 ram_addr_t imif_base, emiff_base;
4628
4629 if (!core)
4630 core = "ti925t";
4631
4632 /* Core */
4633 s->mpu_model = omap310;
4634 s->env = cpu_init(core);
4635 if (!s->env) {
4636 fprintf(stderr, "Unable to find CPU definition\n");
4637 exit(1);
4638 }
4639 s->sdram_size = sdram_size;
4640 s->sram_size = OMAP15XX_SRAM_SIZE;
4641
4642 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4643
4644 /* Clocks */
4645 omap_clk_init(s);
4646
4647 /* Memory-mapped stuff */
4648 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
4649 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4650 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
4651 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4652
4653 omap_clkm_init(0xfffece00, 0xe1008000, s);
4654
4655 s->ih[0] = omap_inth_init(0xfffecb00, 0x100,
4656 arm_pic_init_cpu(s->env),
4657 omap_findclk(s, "arminth_ck"));
4658 s->ih[1] = omap_inth_init(0xfffe0000, 0x800,
4659 &s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ],
4660 omap_findclk(s, "arminth_ck"));
4661 s->irq[0] = s->ih[0]->pins;
4662 s->irq[1] = s->ih[1]->pins;
4663
4664 s->dma = omap_dma_init(0xfffed800, s->irq[0], s,
4665 omap_findclk(s, "dma_ck"));
4666 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
4667 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
4668 s->port[imif ].addr_valid = omap_validate_imif_addr;
4669 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
4670 s->port[local ].addr_valid = omap_validate_local_addr;
4671 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
4672
4673 s->timer[0] = omap_mpu_timer_init(0xfffec500,
4674 s->irq[0][OMAP_INT_TIMER1],
4675 omap_findclk(s, "mputim_ck"));
4676 s->timer[1] = omap_mpu_timer_init(0xfffec600,
4677 s->irq[0][OMAP_INT_TIMER2],
4678 omap_findclk(s, "mputim_ck"));
4679 s->timer[2] = omap_mpu_timer_init(0xfffec700,
4680 s->irq[0][OMAP_INT_TIMER3],
4681 omap_findclk(s, "mputim_ck"));
4682
4683 s->wdt = omap_wd_timer_init(0xfffec800,
4684 s->irq[0][OMAP_INT_WD_TIMER],
4685 omap_findclk(s, "armwdt_ck"));
4686
4687 s->os_timer = omap_os_timer_init(0xfffb9000,
4688 s->irq[1][OMAP_INT_OS_TIMER],
4689 omap_findclk(s, "clk32-kHz"));
4690
4691 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
4692 &s->dma->lcd_ch, ds, imif_base, emiff_base,
4693 omap_findclk(s, "lcd_ck"));
4694
4695 omap_ulpd_pm_init(0xfffe0800, s);
4696 omap_pin_cfg_init(0xfffe1000, s);
4697 omap_id_init(s);
4698
4699 omap_mpui_init(0xfffec900, s);
4700
4701 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
4702 s->irq[0][OMAP_INT_BRIDGE_PRIV],
4703 omap_findclk(s, "tipb_ck"));
4704 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
4705 s->irq[0][OMAP_INT_BRIDGE_PUB],
4706 omap_findclk(s, "tipb_ck"));
4707
4708 omap_tcmi_init(0xfffecc00, s);
4709
4710 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
4711 omap_findclk(s, "uart1_ck"),
4712 serial_hds[0]);
4713 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
4714 omap_findclk(s, "uart2_ck"),
4715 serial_hds[0] ? serial_hds[1] : 0);
4716 s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3],
4717 omap_findclk(s, "uart3_ck"),
4718 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
4719
4720 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
4721 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
4722 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
4723
4724 s->mmc = omap_mmc_init(0xfffb7800, sd_bdrv, s->irq[1][OMAP_INT_OQN],
4725 &s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck"));
4726
4727 s->mpuio = omap_mpuio_init(0xfffb5000,
4728 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
4729 s->wakeup, omap_findclk(s, "clk32-kHz"));
4730
4731 s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1],
4732 omap_findclk(s, "arm_gpio_ck"));
4733
4734 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
4735 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4736
4737 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
4738 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
4739
4740 s->i2c = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
4741 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
4742
4743 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
4744 omap_findclk(s, "clk32-kHz"));
4745
4746 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
4747 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
4748 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
4749 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
4750 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
4751 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4752
4753 /* Register mappings not currenlty implemented:
4754 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4755 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4756 * USB W2FC fffb4000 - fffb47ff
4757 * Camera Interface fffb6800 - fffb6fff
4758 * USB Host fffba000 - fffba7ff
4759 * FAC fffba800 - fffbafff
4760 * HDQ/1-Wire fffbc000 - fffbc7ff
4761 * TIPB switches fffbc800 - fffbcfff
4762 * LED1 fffbd000 - fffbd7ff
4763 * LED2 fffbd800 - fffbdfff
4764 * Mailbox fffcf000 - fffcf7ff
4765 * Local bus IF fffec100 - fffec1ff
4766 * Local bus MMU fffec200 - fffec2ff
4767 * DSP MMU fffed200 - fffed2ff
4768 */
4769
4770 omap_setup_dsp_mapping(omap15xx_dsp_mm);
4771
4772 qemu_register_reset(omap_mpu_reset, s);
4773
4774 return s;
4775 }
Stable branch of Qemu 0.9.1