softmmu_header.h

   1 /*
   2  *  Software MMU support
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if DATA_SIZE == 8
  21 #define SUFFIX q
  22 #define USUFFIX q
  23 #define DATA_TYPE uint64_t
  24 #elif DATA_SIZE == 4
  25 #define SUFFIX l
  26 #define USUFFIX l
  27 #define DATA_TYPE uint32_t
  28 #elif DATA_SIZE == 2
  29 #define SUFFIX w
  30 #define USUFFIX uw
  31 #define DATA_TYPE uint16_t
  32 #define DATA_STYPE int16_t
  33 #elif DATA_SIZE == 1
  34 #define SUFFIX b
  35 #define USUFFIX ub
  36 #define DATA_TYPE uint8_t
  37 #define DATA_STYPE int8_t
  38 #else
  39 #error unsupported data size
  40 #endif
  41
  42 #if ACCESS_TYPE < (NB_MMU_MODES)
  43
  44 #define CPU_MMU_INDEX ACCESS_TYPE
  45 #define MMUSUFFIX _mmu
  46
  47 #elif ACCESS_TYPE == (NB_MMU_MODES)
  48
  49 #define CPU_MMU_INDEX (cpu_mmu_index(env))
  50 #define MMUSUFFIX _mmu
  51
  52 #elif ACCESS_TYPE == (NB_MMU_MODES + 1)
  53
  54 #define CPU_MMU_INDEX (cpu_mmu_index(env))
  55 #define MMUSUFFIX _cmmu
  56
  57 #else
  58 #error invalid ACCESS_TYPE
  59 #endif
  60
  61 #if DATA_SIZE == 8
  62 #define RES_TYPE uint64_t
  63 #else
  64 #define RES_TYPE int
  65 #endif
  66
  67 #if ACCESS_TYPE == (NB_MMU_MODES + 1)
  68 #define ADDR_READ addr_code
  69 #else
  70 #define ADDR_READ addr_read
  71 #endif
  72
  73 DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
  74                                                          int mmu_idx);
  75 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
  76
  77 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
  78     (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
  79
  80 #define CPU_TLB_ENTRY_BITS 4
  81
  82 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
  83 {
  84     int res;
  85
  86     asm volatile ("movl %1, %%edx\n"
  87                   "movl %1, %%eax\n"
  88                   "shrl %3, %%edx\n"
  89                   "andl %4, %%eax\n"
  90                   "andl %2, %%edx\n"
  91                   "leal %5(%%edx, %%ebp), %%edx\n"
  92                   "cmpl (%%edx), %%eax\n"
  93                   "movl %1, %%eax\n"
  94                   "je 1f\n"
  95                   "pushl %6\n"
  96                   "call %7\n"
  97                   "popl %%edx\n"
  98                   "movl %%eax, %0\n"
  99                   "jmp 2f\n"
 100                   "1:\n"
 101                   "addl 12(%%edx), %%eax\n"
 102 #if DATA_SIZE == 1
 103                   "movzbl (%%eax), %0\n"
 104 #elif DATA_SIZE == 2
 105                   "movzwl (%%eax), %0\n"
 106 #elif DATA_SIZE == 4
 107                   "movl (%%eax), %0\n"
 108 #else
 109 #error unsupported size
 110 #endif
 111                   "2:\n"
 112                   : "=r" (res)
 113                   : "r" (ptr),
 114                   "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
 115                   "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
 116                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
 117                   "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
 118                   "i" (CPU_MMU_INDEX),
 119                   "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
 120                   : "%eax", "%ecx", "%edx", "memory", "cc");
 121     return res;
 122 }
 123
 124 #if DATA_SIZE <= 2
 125 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
 126 {
 127     int res;
 128
 129     asm volatile ("movl %1, %%edx\n"
 130                   "movl %1, %%eax\n"
 131                   "shrl %3, %%edx\n"
 132                   "andl %4, %%eax\n"
 133                   "andl %2, %%edx\n"
 134                   "leal %5(%%edx, %%ebp), %%edx\n"
 135                   "cmpl (%%edx), %%eax\n"
 136                   "movl %1, %%eax\n"
 137                   "je 1f\n"
 138                   "pushl %6\n"
 139                   "call %7\n"
 140                   "popl %%edx\n"
 141 #if DATA_SIZE == 1
 142                   "movsbl %%al, %0\n"
 143 #elif DATA_SIZE == 2
 144                   "movswl %%ax, %0\n"
 145 #else
 146 #error unsupported size
 147 #endif
 148                   "jmp 2f\n"
 149                   "1:\n"
 150                   "addl 12(%%edx), %%eax\n"
 151 #if DATA_SIZE == 1
 152                   "movsbl (%%eax), %0\n"
 153 #elif DATA_SIZE == 2
 154                   "movswl (%%eax), %0\n"
 155 #else
 156 #error unsupported size
 157 #endif
 158                   "2:\n"
 159                   : "=r" (res)
 160                   : "r" (ptr),
 161                   "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
 162                   "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
 163                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
 164                   "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
 165                   "i" (CPU_MMU_INDEX),
 166                   "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
 167                   : "%eax", "%ecx", "%edx", "memory", "cc");
 168     return res;
 169 }
 170 #endif
 171
 172 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
 173 {
 174     asm volatile ("movl %0, %%edx\n"
 175                   "movl %0, %%eax\n"
 176                   "shrl %3, %%edx\n"
 177                   "andl %4, %%eax\n"
 178                   "andl %2, %%edx\n"
 179                   "leal %5(%%edx, %%ebp), %%edx\n"
 180                   "cmpl (%%edx), %%eax\n"
 181                   "movl %0, %%eax\n"
 182                   "je 1f\n"
 183 #if DATA_SIZE == 1
 184                   "movzbl %b1, %%edx\n"
 185 #elif DATA_SIZE == 2
 186                   "movzwl %w1, %%edx\n"
 187 #elif DATA_SIZE == 4
 188                   "movl %1, %%edx\n"
 189 #else
 190 #error unsupported size
 191 #endif
 192                   "pushl %6\n"
 193                   "call %7\n"
 194                   "popl %%eax\n"
 195                   "jmp 2f\n"
 196                   "1:\n"
 197                   "addl 8(%%edx), %%eax\n"
 198 #if DATA_SIZE == 1
 199                   "movb %b1, (%%eax)\n"
 200 #elif DATA_SIZE == 2
 201                   "movw %w1, (%%eax)\n"
 202 #elif DATA_SIZE == 4
 203                   "movl %1, (%%eax)\n"
 204 #else
 205 #error unsupported size
 206 #endif
 207                   "2:\n"
 208                   :
 209                   : "r" (ptr),
 210 /* NOTE: 'q' would be needed as constraint, but we could not use it
 211    with T1 ! */
 212                   "r" (v),
 213                   "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
 214                   "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
 215                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
 216                   "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
 217                   "i" (CPU_MMU_INDEX),
 218                   "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
 219                   : "%eax", "%ecx", "%edx", "memory", "cc");
 220 }
 221
 222 #else
 223
 224 /* generic load/store macros */
 225
 226 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
 227 {
 228     int index;
 229     RES_TYPE res;
 230     target_ulong addr;
 231     unsigned long physaddr;
 232     int mmu_idx;
 233
 234     addr = ptr;
 235     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 236     mmu_idx = CPU_MMU_INDEX;
 237     if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
 238                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
 239         res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
 240     } else {
 241         physaddr = addr + env->tlb_table[mmu_idx][index].addend;
 242         res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
 243     }
 244     return res;
 245 }
 246
 247 #if DATA_SIZE <= 2
 248 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
 249 {
 250     int res, index;
 251     target_ulong addr;
 252     unsigned long physaddr;
 253     int mmu_idx;
 254
 255     addr = ptr;
 256     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 257     mmu_idx = CPU_MMU_INDEX;
 258     if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
 259                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
 260         res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
 261     } else {
 262         physaddr = addr + env->tlb_table[mmu_idx][index].addend;
 263         res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
 264     }
 265     return res;
 266 }
 267 #endif
 268
 269 #if ACCESS_TYPE != (NB_MMU_MODES + 1)
 270
 271 /* generic store macro */
 272
 273 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
 274 {
 275     int index;
 276     target_ulong addr;
 277     unsigned long physaddr;
 278     int mmu_idx;
 279
 280     addr = ptr;
 281     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 282     mmu_idx = CPU_MMU_INDEX;
 283     if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_write !=
 284                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
 285         glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
 286     } else {
 287         physaddr = addr + env->tlb_table[mmu_idx][index].addend;
 288         glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
 289     }
 290 }
 291
 292 #endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
 293
 294 #endif /* !asm */
 295
 296 #if ACCESS_TYPE != (NB_MMU_MODES + 1)
 297
 298 #if DATA_SIZE == 8
 299 static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
 300 {
 301     union {
 302         float64 d;
 303         uint64_t i;
 304     } u;
 305     u.i = glue(ldq, MEMSUFFIX)(ptr);
 306     return u.d;
 307 }
 308
 309 static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
 310 {
 311     union {
 312         float64 d;
 313         uint64_t i;
 314     } u;
 315     u.d = v;
 316     glue(stq, MEMSUFFIX)(ptr, u.i);
 317 }
 318 #endif /* DATA_SIZE == 8 */
 319
 320 #if DATA_SIZE == 4
 321 static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
 322 {
 323     union {
 324         float32 f;
 325         uint32_t i;
 326     } u;
 327     u.i = glue(ldl, MEMSUFFIX)(ptr);
 328     return u.f;
 329 }
 330
 331 static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
 332 {
 333     union {
 334         float32 f;
 335         uint32_t i;
 336     } u;
 337     u.f = v;
 338     glue(stl, MEMSUFFIX)(ptr, u.i);
 339 }
 340 #endif /* DATA_SIZE == 4 */
 341
 342 #endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
 343
 344 #undef RES_TYPE
 345 #undef DATA_TYPE
 346 #undef DATA_STYPE
 347 #undef SUFFIX
 348 #undef USUFFIX
 349 #undef DATA_SIZE
 350 #undef CPU_MMU_INDEX
 351 #undef MMUSUFFIX
 352 #undef ADDR_READ