hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 //#define DEBUG_IRQ_COUNT
  26 //#define DEBUG_IRQ
  27
  28 #ifdef DEBUG_IRQ
  29 #define DPRINTF(fmt, args...) \
  30 do { printf("IRQ: " fmt , ##args); } while (0)
  31 #else
  32 #define DPRINTF(fmt, args...)
  33 #endif
  34
  35 /*
  36  * Registers of interrupt controller in sun4m.
  37  *
  38  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  39  * produced as NCR89C105. See
  40  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  41  *
  42  * There is a system master controller and one for each cpu.
  43  *
  44  */
  45
  46 #define MAX_CPUS 16
  47 #define MAX_PILS 16
  48
  49 typedef struct SLAVIO_INTCTLState {
  50     uint32_t intreg_pending[MAX_CPUS];
  51     uint32_t intregm_pending;
  52     uint32_t intregm_disabled;
  53     uint32_t target_cpu;
  54 #ifdef DEBUG_IRQ_COUNT
  55     uint64_t irq_count[32];
  56 #endif
  57     qemu_irq *cpu_irqs[MAX_CPUS];
  58     const uint32_t *intbit_to_level;
  59     uint32_t cputimer_bit;
  60     uint32_t pil_out[MAX_CPUS];
  61 } SLAVIO_INTCTLState;
  62
  63 #define INTCTL_MAXADDR 0xf
  64 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  65 #define INTCTLM_MAXADDR 0x13
  66 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
  67 #define INTCTLM_MASK 0x1f
  68 static void slavio_check_interrupts(void *opaque);
  69
  70 // per-cpu interrupt controller
  71 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  72 {
  73     SLAVIO_INTCTLState *s = opaque;
  74     uint32_t saddr;
  75     int cpu;
  76
  77     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
  78     saddr = (addr & INTCTL_MAXADDR) >> 2;
  79     switch (saddr) {
  80     case 0:
  81         return s->intreg_pending[cpu];
  82     default:
  83         break;
  84     }
  85     return 0;
  86 }
  87
  88 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  89 {
  90     SLAVIO_INTCTLState *s = opaque;
  91     uint32_t saddr;
  92     int cpu;
  93
  94     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
  95     saddr = (addr & INTCTL_MAXADDR) >> 2;
  96     switch (saddr) {
  97     case 1: // clear pending softints
  98         if (val & 0x4000)
  99             val |= 80000000;
 100         val &= 0xfffe0000;
 101         s->intreg_pending[cpu] &= ~val;
 102         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 103         break;
 104     case 2: // set softint
 105         val &= 0xfffe0000;
 106         s->intreg_pending[cpu] |= val;
 107         slavio_check_interrupts(s);
 108         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 109         break;
 110     default:
 111         break;
 112     }
 113 }
 114
 115 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
 116     slavio_intctl_mem_readl,
 117     slavio_intctl_mem_readl,
 118     slavio_intctl_mem_readl,
 119 };
 120
 121 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 122     slavio_intctl_mem_writel,
 123     slavio_intctl_mem_writel,
 124     slavio_intctl_mem_writel,
 125 };
 126
 127 // master system interrupt controller
 128 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 129 {
 130     SLAVIO_INTCTLState *s = opaque;
 131     uint32_t saddr;
 132
 133     saddr = (addr & INTCTLM_MAXADDR) >> 2;
 134     switch (saddr) {
 135     case 0:
 136         return s->intregm_pending & 0x7fffffff;
 137     case 1:
 138         return s->intregm_disabled;
 139     case 4:
 140         return s->target_cpu;
 141     default:
 142         break;
 143     }
 144     return 0;
 145 }
 146
 147 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 148 {
 149     SLAVIO_INTCTLState *s = opaque;
 150     uint32_t saddr;
 151
 152     saddr = (addr & INTCTLM_MASK) >> 2;
 153     switch (saddr) {
 154     case 2: // clear (enable)
 155         // Force clear unused bits
 156         val &= ~0x4fb2007f;
 157         s->intregm_disabled &= ~val;
 158         DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 159         slavio_check_interrupts(s);
 160         break;
 161     case 3: // set (disable, clear pending)
 162         // Force clear unused bits
 163         val &= ~0x4fb2007f;
 164         s->intregm_disabled |= val;
 165         s->intregm_pending &= ~val;
 166         DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 167         break;
 168     case 4:
 169         s->target_cpu = val & (MAX_CPUS - 1);
 170         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 171         break;
 172     default:
 173         break;
 174     }
 175 }
 176
 177 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
 178     slavio_intctlm_mem_readl,
 179     slavio_intctlm_mem_readl,
 180     slavio_intctlm_mem_readl,
 181 };
 182
 183 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
 184     slavio_intctlm_mem_writel,
 185     slavio_intctlm_mem_writel,
 186     slavio_intctlm_mem_writel,
 187 };
 188
 189 void slavio_pic_info(void *opaque)
 190 {
 191     SLAVIO_INTCTLState *s = opaque;
 192     int i;
 193
 194     for (i = 0; i < MAX_CPUS; i++) {
 195         term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
 196     }
 197     term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
 198 }
 199
 200 void slavio_irq_info(void *opaque)
 201 {
 202 #ifndef DEBUG_IRQ_COUNT
 203     term_printf("irq statistic code not compiled.\n");
 204 #else
 205     SLAVIO_INTCTLState *s = opaque;
 206     int i;
 207     int64_t count;
 208
 209     term_printf("IRQ statistics:\n");
 210     for (i = 0; i < 32; i++) {
 211         count = s->irq_count[i];
 212         if (count > 0)
 213             term_printf("%2d: %" PRId64 "\n", i, count);
 214     }
 215 #endif
 216 }
 217
 218 static void raise_pil(SLAVIO_INTCTLState *s, unsigned int pil,
 219                       unsigned int cpu)
 220 {
 221     qemu_irq irq;
 222     unsigned int oldmax;
 223
 224     irq = s->cpu_irqs[cpu][pil];
 225
 226 #ifdef DEBUG_IRQ_COUNT
 227     s->irq_count[pil]++;
 228 #endif
 229     oldmax = s->pil_out[cpu];
 230     if (oldmax > 0 && oldmax != pil)
 231         qemu_irq_lower(s->cpu_irqs[cpu][oldmax]);
 232     s->pil_out[cpu] = pil;
 233     if (pil > 0)
 234         qemu_irq_raise(irq);
 235     DPRINTF("cpu %d pil %d\n", cpu, pil);
 236 }
 237
 238 static void slavio_check_interrupts(void *opaque)
 239 {
 240     SLAVIO_INTCTLState *s = opaque;
 241     uint32_t pending = s->intregm_pending;
 242     unsigned int i, j, max = 0;
 243
 244     pending &= ~s->intregm_disabled;
 245
 246     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
 247     for (i = 0; i < MAX_CPUS; i++) {
 248         max = 0;
 249         if (pending && !(s->intregm_disabled & 0x80000000) &&
 250             (i == s->target_cpu)) {
 251             for (j = 0; j < 32; j++) {
 252                 if (pending & (1 << j)) {
 253                     if (max < s->intbit_to_level[j])
 254                         max = s->intbit_to_level[j];
 255                 }
 256             }
 257         }
 258         for (j = 17; j < 32; j++) {
 259             if (s->intreg_pending[i] & (1 << j)) {
 260                 if (max < j - 16)
 261                     max = j - 16;
 262             }
 263         }
 264         raise_pil(s, max, i);
 265     }
 266 }
 267
 268 /*
 269  * "irq" here is the bit number in the system interrupt register to
 270  * separate serial and keyboard interrupts sharing a level.
 271  */
 272 static void slavio_set_irq(void *opaque, int irq, int level)
 273 {
 274     SLAVIO_INTCTLState *s = opaque;
 275     uint32_t mask = 1 << irq;
 276     uint32_t pil = s->intbit_to_level[irq];
 277
 278     DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
 279             level);
 280     if (pil > 0) {
 281         if (level) {
 282             s->intregm_pending |= mask;
 283             s->intreg_pending[s->target_cpu] |= 1 << pil;
 284         } else {
 285             s->intregm_pending &= ~mask;
 286             s->intreg_pending[s->target_cpu] &= ~(1 << pil);
 287         }
 288         slavio_check_interrupts(s);
 289     }
 290 }
 291
 292 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 293 {
 294     SLAVIO_INTCTLState *s = opaque;
 295
 296     DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
 297
 298     if (level)
 299         s->intreg_pending[cpu] |= s->cputimer_bit;
 300     else
 301         s->intreg_pending[cpu] &= ~s->cputimer_bit;
 302
 303     slavio_check_interrupts(s);
 304 }
 305
 306 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 307 {
 308     SLAVIO_INTCTLState *s = opaque;
 309     int i;
 310
 311     for (i = 0; i < MAX_CPUS; i++) {
 312         qemu_put_be32s(f, &s->intreg_pending[i]);
 313     }
 314     qemu_put_be32s(f, &s->intregm_pending);
 315     qemu_put_be32s(f, &s->intregm_disabled);
 316     qemu_put_be32s(f, &s->target_cpu);
 317 }
 318
 319 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
 320 {
 321     SLAVIO_INTCTLState *s = opaque;
 322     int i;
 323
 324     if (version_id != 1)
 325         return -EINVAL;
 326
 327     for (i = 0; i < MAX_CPUS; i++) {
 328         qemu_get_be32s(f, &s->intreg_pending[i]);
 329     }
 330     qemu_get_be32s(f, &s->intregm_pending);
 331     qemu_get_be32s(f, &s->intregm_disabled);
 332     qemu_get_be32s(f, &s->target_cpu);
 333     return 0;
 334 }
 335
 336 static void slavio_intctl_reset(void *opaque)
 337 {
 338     SLAVIO_INTCTLState *s = opaque;
 339     int i;
 340
 341     for (i = 0; i < MAX_CPUS; i++) {
 342         s->intreg_pending[i] = 0;
 343     }
 344     s->intregm_disabled = ~0xffb2007f;
 345     s->intregm_pending = 0;
 346     s->target_cpu = 0;
 347 }
 348
 349 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
 350                          const uint32_t *intbit_to_level,
 351                          qemu_irq **irq, qemu_irq **cpu_irq,
 352                          qemu_irq **parent_irq, unsigned int cputimer)
 353 {
 354     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
 355     SLAVIO_INTCTLState *s;
 356
 357     s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
 358     if (!s)
 359         return NULL;
 360
 361     s->intbit_to_level = intbit_to_level;
 362     for (i = 0; i < MAX_CPUS; i++) {
 363         slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
 364         cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
 365                                      slavio_intctl_io_memory);
 366         s->cpu_irqs[i] = parent_irq[i];
 367     }
 368
 369     slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
 370     cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
 371
 372     register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
 373     qemu_register_reset(slavio_intctl_reset, s);
 374     *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
 375
 376     *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
 377     s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
 378     slavio_intctl_reset(s);
 379     return s;
 380 }
 381