target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "config.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #include "cpu-defs.h"
  38
  39 #include "softfloat.h"
  40
  41 #if defined(__i386__) && !defined(CONFIG_SOFTMMU)
  42 #define USE_CODE_COPY
  43 #endif
  44
  45 #define R_EAX 0
  46 #define R_ECX 1
  47 #define R_EDX 2
  48 #define R_EBX 3
  49 #define R_ESP 4
  50 #define R_EBP 5
  51 #define R_ESI 6
  52 #define R_EDI 7
  53
  54 #define R_AL 0
  55 #define R_CL 1
  56 #define R_DL 2
  57 #define R_BL 3
  58 #define R_AH 4
  59 #define R_CH 5
  60 #define R_DH 6
  61 #define R_BH 7
  62
  63 #define R_ES 0
  64 #define R_CS 1
  65 #define R_SS 2
  66 #define R_DS 3
  67 #define R_FS 4
  68 #define R_GS 5
  69
  70 /* segment descriptor fields */
  71 #define DESC_G_MASK     (1 << 23)
  72 #define DESC_B_SHIFT    22
  73 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  74 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  75 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  76 #define DESC_AVL_MASK   (1 << 20)
  77 #define DESC_P_MASK     (1 << 15)
  78 #define DESC_DPL_SHIFT  13
  79 #define DESC_S_MASK     (1 << 12)
  80 #define DESC_TYPE_SHIFT 8
  81 #define DESC_A_MASK     (1 << 8)
  82
  83 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  84 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  85 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  86
  87 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  88 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  89
  90 #define DESC_TSS_BUSY_MASK (1 << 9)
  91
  92 /* eflags masks */
  93 #define CC_C    0x0001
  94 #define CC_P    0x0004
  95 #define CC_A    0x0010
  96 #define CC_Z    0x0040
  97 #define CC_S    0x0080
  98 #define CC_O    0x0800
  99
 100 #define TF_SHIFT   8
 101 #define IOPL_SHIFT 12
 102 #define VM_SHIFT   17
 103
 104 #define TF_MASK                 0x00000100
 105 #define IF_MASK                 0x00000200
 106 #define DF_MASK                 0x00000400
 107 #define IOPL_MASK               0x00003000
 108 #define NT_MASK                 0x00004000
 109 #define RF_MASK                 0x00010000
 110 #define VM_MASK                 0x00020000
 111 #define AC_MASK                 0x00040000
 112 #define VIF_MASK                0x00080000
 113 #define VIP_MASK                0x00100000
 114 #define ID_MASK                 0x00200000
 115
 116 /* hidden flags - used internally by qemu to represent additionnal cpu
 117    states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
 118    using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
 119    with eflags. */
 120 /* current cpl */
 121 #define HF_CPL_SHIFT         0
 122 /* true if soft mmu is being used */
 123 #define HF_SOFTMMU_SHIFT     2
 124 /* true if hardware interrupts must be disabled for next instruction */
 125 #define HF_INHIBIT_IRQ_SHIFT 3
 126 /* 16 or 32 segments */
 127 #define HF_CS32_SHIFT        4
 128 #define HF_SS32_SHIFT        5
 129 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 130 #define HF_ADDSEG_SHIFT      6
 131 /* copy of CR0.PE (protected mode) */
 132 #define HF_PE_SHIFT          7
 133 #define HF_TF_SHIFT          8 /* must be same as eflags */
 134 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 135 #define HF_EM_SHIFT         10
 136 #define HF_TS_SHIFT         11
 137 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 138 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 139 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 140 #define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
 141 #define HF_VM_SHIFT         17 /* must be same as eflags */
 142
 143 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 144 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 145 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 146 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 147 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 148 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 149 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 150 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 151 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 152 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 153 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 154 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 155 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 156 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 157
 158 #define CR0_PE_MASK  (1 << 0)
 159 #define CR0_MP_MASK  (1 << 1)
 160 #define CR0_EM_MASK  (1 << 2)
 161 #define CR0_TS_MASK  (1 << 3)
 162 #define CR0_ET_MASK  (1 << 4)
 163 #define CR0_NE_MASK  (1 << 5)
 164 #define CR0_WP_MASK  (1 << 16)
 165 #define CR0_AM_MASK  (1 << 18)
 166 #define CR0_PG_MASK  (1 << 31)
 167
 168 #define CR4_VME_MASK  (1 << 0)
 169 #define CR4_PVI_MASK  (1 << 1)
 170 #define CR4_TSD_MASK  (1 << 2)
 171 #define CR4_DE_MASK   (1 << 3)
 172 #define CR4_PSE_MASK  (1 << 4)
 173 #define CR4_PAE_MASK  (1 << 5)
 174 #define CR4_PGE_MASK  (1 << 7)
 175 #define CR4_PCE_MASK  (1 << 8)
 176 #define CR4_OSFXSR_MASK (1 << 9)
 177 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 178
 179 #define PG_PRESENT_BIT  0
 180 #define PG_RW_BIT       1
 181 #define PG_USER_BIT     2
 182 #define PG_PWT_BIT      3
 183 #define PG_PCD_BIT      4
 184 #define PG_ACCESSED_BIT 5
 185 #define PG_DIRTY_BIT    6
 186 #define PG_PSE_BIT      7
 187 #define PG_GLOBAL_BIT   8
 188
 189 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 190 #define PG_RW_MASK       (1 << PG_RW_BIT)
 191 #define PG_USER_MASK     (1 << PG_USER_BIT)
 192 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 193 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 194 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 195 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 196 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 197 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 198
 199 #define PG_ERROR_W_BIT     1
 200
 201 #define PG_ERROR_P_MASK    0x01
 202 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 203 #define PG_ERROR_U_MASK    0x04
 204 #define PG_ERROR_RSVD_MASK 0x08
 205
 206 #define MSR_IA32_APICBASE               0x1b
 207 #define MSR_IA32_APICBASE_BSP           (1<<8)
 208 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 209 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 210
 211 #define MSR_IA32_SYSENTER_CS            0x174
 212 #define MSR_IA32_SYSENTER_ESP           0x175
 213 #define MSR_IA32_SYSENTER_EIP           0x176
 214
 215 #define MSR_EFER                        0xc0000080
 216
 217 #define MSR_EFER_SCE   (1 << 0)
 218 #define MSR_EFER_LME   (1 << 8)
 219 #define MSR_EFER_LMA   (1 << 10)
 220 #define MSR_EFER_NXE   (1 << 11)
 221 #define MSR_EFER_FFXSR (1 << 14)
 222
 223 #define MSR_STAR                        0xc0000081
 224 #define MSR_LSTAR                       0xc0000082
 225 #define MSR_CSTAR                       0xc0000083
 226 #define MSR_FMASK                       0xc0000084
 227 #define MSR_FSBASE                      0xc0000100
 228 #define MSR_GSBASE                      0xc0000101
 229 #define MSR_KERNELGSBASE                0xc0000102
 230
 231 /* cpuid_features bits */
 232 #define CPUID_FP87 (1 << 0)
 233 #define CPUID_VME  (1 << 1)
 234 #define CPUID_DE   (1 << 2)
 235 #define CPUID_PSE  (1 << 3)
 236 #define CPUID_TSC  (1 << 4)
 237 #define CPUID_MSR  (1 << 5)
 238 #define CPUID_PAE  (1 << 6)
 239 #define CPUID_MCE  (1 << 7)
 240 #define CPUID_CX8  (1 << 8)
 241 #define CPUID_APIC (1 << 9)
 242 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 243 #define CPUID_MTRR (1 << 12)
 244 #define CPUID_PGE  (1 << 13)
 245 #define CPUID_MCA  (1 << 14)
 246 #define CPUID_CMOV (1 << 15)
 247 /* ... */
 248 #define CPUID_MMX  (1 << 23)
 249 #define CPUID_FXSR (1 << 24)
 250 #define CPUID_SSE  (1 << 25)
 251 #define CPUID_SSE2 (1 << 26)
 252
 253 #define CPUID_EXT_SS3      (1 << 0)
 254 #define CPUID_EXT_MONITOR  (1 << 3)
 255 #define CPUID_EXT_CX16     (1 << 13)
 256
 257 #define CPUID_EXT2_SYSCALL (1 << 11)
 258 #define CPUID_EXT2_NX      (1 << 20)
 259 #define CPUID_EXT2_LM      (1 << 29)
 260
 261 #define EXCP00_DIVZ     0
 262 #define EXCP01_SSTP     1
 263 #define EXCP02_NMI      2
 264 #define EXCP03_INT3     3
 265 #define EXCP04_INTO     4
 266 #define EXCP05_BOUND    5
 267 #define EXCP06_ILLOP    6
 268 #define EXCP07_PREX     7
 269 #define EXCP08_DBLE     8
 270 #define EXCP09_XERR     9
 271 #define EXCP0A_TSS      10
 272 #define EXCP0B_NOSEG    11
 273 #define EXCP0C_STACK    12
 274 #define EXCP0D_GPF      13
 275 #define EXCP0E_PAGE     14
 276 #define EXCP10_COPR     16
 277 #define EXCP11_ALGN     17
 278 #define EXCP12_MCHK     18
 279
 280 enum {
 281     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 282     CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
 283
 284     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 285     CC_OP_MULW,
 286     CC_OP_MULL,
 287     CC_OP_MULQ,
 288
 289     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 290     CC_OP_ADDW,
 291     CC_OP_ADDL,
 292     CC_OP_ADDQ,
 293
 294     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 295     CC_OP_ADCW,
 296     CC_OP_ADCL,
 297     CC_OP_ADCQ,
 298
 299     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 300     CC_OP_SUBW,
 301     CC_OP_SUBL,
 302     CC_OP_SUBQ,
 303
 304     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 305     CC_OP_SBBW,
 306     CC_OP_SBBL,
 307     CC_OP_SBBQ,
 308
 309     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 310     CC_OP_LOGICW,
 311     CC_OP_LOGICL,
 312     CC_OP_LOGICQ,
 313
 314     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 315     CC_OP_INCW,
 316     CC_OP_INCL,
 317     CC_OP_INCQ,
 318
 319     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 320     CC_OP_DECW,
 321     CC_OP_DECL,
 322     CC_OP_DECQ,
 323
 324     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 325     CC_OP_SHLW,
 326     CC_OP_SHLL,
 327     CC_OP_SHLQ,
 328
 329     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 330     CC_OP_SARW,
 331     CC_OP_SARL,
 332     CC_OP_SARQ,
 333
 334     CC_OP_NB,
 335 };
 336
 337 #ifdef FLOATX80
 338 #define USE_X86LDOUBLE
 339 #endif
 340
 341 #ifdef USE_X86LDOUBLE
 342 typedef floatx80 CPU86_LDouble;
 343 #else
 344 typedef float64 CPU86_LDouble;
 345 #endif
 346
 347 typedef struct SegmentCache {
 348     uint32_t selector;
 349     target_ulong base;
 350     uint32_t limit;
 351     uint32_t flags;
 352 } SegmentCache;
 353
 354 typedef union {
 355     uint8_t _b[16];
 356     uint16_t _w[8];
 357     uint32_t _l[4];
 358     uint64_t _q[2];
 359     float32 _s[4];
 360     float64 _d[2];
 361 } XMMReg;
 362
 363 typedef union {
 364     uint8_t _b[8];
 365     uint16_t _w[2];
 366     uint32_t _l[1];
 367     uint64_t q;
 368 } MMXReg;
 369
 370 #ifdef WORDS_BIGENDIAN
 371 #define XMM_B(n) _b[15 - (n)]
 372 #define XMM_W(n) _w[7 - (n)]
 373 #define XMM_L(n) _l[3 - (n)]
 374 #define XMM_S(n) _s[3 - (n)]
 375 #define XMM_Q(n) _q[1 - (n)]
 376 #define XMM_D(n) _d[1 - (n)]
 377
 378 #define MMX_B(n) _b[7 - (n)]
 379 #define MMX_W(n) _w[3 - (n)]
 380 #define MMX_L(n) _l[1 - (n)]
 381 #else
 382 #define XMM_B(n) _b[n]
 383 #define XMM_W(n) _w[n]
 384 #define XMM_L(n) _l[n]
 385 #define XMM_S(n) _s[n]
 386 #define XMM_Q(n) _q[n]
 387 #define XMM_D(n) _d[n]
 388
 389 #define MMX_B(n) _b[n]
 390 #define MMX_W(n) _w[n]
 391 #define MMX_L(n) _l[n]
 392 #endif
 393 #define MMX_Q(n) q
 394
 395 #ifdef TARGET_X86_64
 396 #define CPU_NB_REGS 16
 397 #else
 398 #define CPU_NB_REGS 8
 399 #endif
 400
 401 typedef struct CPUX86State {
 402 #if TARGET_LONG_BITS > HOST_LONG_BITS
 403     /* temporaries if we cannot store them in host registers */
 404     target_ulong t0, t1, t2;
 405 #endif
 406
 407     /* standard registers */
 408     target_ulong regs[CPU_NB_REGS];
 409     target_ulong eip;
 410     target_ulong eflags; /* eflags register. During CPU emulation, CC
 411                         flags and DF are set to zero because they are
 412                         stored elsewhere */
 413
 414     /* emulator internal eflags handling */
 415     target_ulong cc_src;
 416     target_ulong cc_dst;
 417     uint32_t cc_op;
 418     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 419     uint32_t hflags; /* hidden flags, see HF_xxx constants */
 420
 421     /* segments */
 422     SegmentCache segs[6]; /* selector values */
 423     SegmentCache ldt;
 424     SegmentCache tr;
 425     SegmentCache gdt; /* only base and limit are used */
 426     SegmentCache idt; /* only base and limit are used */
 427
 428     target_ulong cr[5]; /* NOTE: cr1 is unused */
 429     uint32_t a20_mask;
 430
 431     /* FPU state */
 432     unsigned int fpstt; /* top of stack index */
 433     unsigned int fpus;
 434     unsigned int fpuc;
 435     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 436     union {
 437 #ifdef USE_X86LDOUBLE
 438         CPU86_LDouble d __attribute__((aligned(16)));
 439 #else
 440         CPU86_LDouble d;
 441 #endif
 442         MMXReg mmx;
 443     } fpregs[8];
 444
 445     /* emulator internal variables */
 446     float_status fp_status;
 447     CPU86_LDouble ft0;
 448     union {
 449         float f;
 450         double d;
 451         int i32;
 452         int64_t i64;
 453     } fp_convert;
 454
 455     float_status sse_status;
 456     uint32_t mxcsr;
 457     XMMReg xmm_regs[CPU_NB_REGS];
 458     XMMReg xmm_t0;
 459     MMXReg mmx_t0;
 460
 461     /* sysenter registers */
 462     uint32_t sysenter_cs;
 463     uint32_t sysenter_esp;
 464     uint32_t sysenter_eip;
 465 #ifdef TARGET_X86_64
 466     target_ulong efer;
 467     target_ulong star;
 468     target_ulong lstar;
 469     target_ulong cstar;
 470     target_ulong fmask;
 471     target_ulong kernelgsbase;
 472 #endif
 473
 474     /* temporary data for USE_CODE_COPY mode */
 475 #ifdef USE_CODE_COPY
 476     uint32_t tmp0;
 477     uint32_t saved_esp;
 478     int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
 479 #endif
 480
 481     /* exception/interrupt handling */
 482     jmp_buf jmp_env;
 483     int exception_index;
 484     int error_code;
 485     int exception_is_int;
 486     target_ulong exception_next_eip;
 487     struct TranslationBlock *current_tb; /* currently executing TB */
 488     target_ulong dr[8]; /* debug registers */
 489     int interrupt_request;
 490     int user_mode_only; /* user mode only simulation */
 491
 492     /* soft mmu support */
 493     /* in order to avoid passing too many arguments to the memory
 494        write helpers, we store some rarely used information in the CPU
 495        context) */
 496     unsigned long mem_write_pc; /* host pc at which the memory was
 497                                    written */
 498     target_ulong mem_write_vaddr; /* target virtual addr at which the
 499                                      memory was written */
 500     /* 0 = kernel, 1 = user */
 501     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
 502     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
 503
 504     /* from this point: preserved by CPU reset */
 505     /* ice debug support */
 506     target_ulong breakpoints[MAX_BREAKPOINTS];
 507     int nb_breakpoints;
 508     int singlestep_enabled;
 509
 510     /* processor features (e.g. for CPUID insn) */
 511     uint32_t cpuid_vendor1;
 512     uint32_t cpuid_vendor2;
 513     uint32_t cpuid_vendor3;
 514     uint32_t cpuid_version;
 515     uint32_t cpuid_features;
 516     uint32_t cpuid_ext_features;
 517
 518 #ifdef USE_KQEMU
 519     int kqemu_enabled;
 520 #endif
 521     /* in order to simplify APIC support, we leave this pointer to the
 522        user */
 523     struct APICState *apic_state;
 524     /* user data */
 525     void *opaque;
 526 } CPUX86State;
 527
 528 CPUX86State *cpu_x86_init(void);
 529 int cpu_x86_exec(CPUX86State *s);
 530 void cpu_x86_close(CPUX86State *s);
 531 int cpu_get_pic_interrupt(CPUX86State *s);
 532 /* MSDOS compatibility mode FPU exception support */
 533 void cpu_set_ferr(CPUX86State *s);
 534
 535 /* this function must always be used to load data in the segment
 536    cache: it synchronizes the hflags with the segment cache values */
 537 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 538                                           int seg_reg, unsigned int selector,
 539                                           uint32_t base, unsigned int limit,
 540                                           unsigned int flags)
 541 {
 542     SegmentCache *sc;
 543     unsigned int new_hflags;
 544
 545     sc = &env->segs[seg_reg];
 546     sc->selector = selector;
 547     sc->base = base;
 548     sc->limit = limit;
 549     sc->flags = flags;
 550
 551     /* update the hidden flags */
 552     {
 553         if (seg_reg == R_CS) {
 554 #ifdef TARGET_X86_64
 555             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 556                 /* long mode */
 557                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 558                 env->hflags &= ~(HF_ADDSEG_MASK);
 559             } else
 560 #endif
 561             {
 562                 /* legacy / compatibility case */
 563                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 564                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 565                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 566                     new_hflags;
 567             }
 568         }
 569         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 570             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 571         if (env->hflags & HF_CS64_MASK) {
 572             /* zero base assumed for DS, ES and SS in long mode */
 573         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 574                    (env->eflags & VM_MASK) ||
 575                    !(env->hflags & HF_CS32_MASK)) {
 576             /* XXX: try to avoid this test. The problem comes from the
 577                fact that is real mode or vm86 mode we only modify the
 578                'base' and 'selector' fields of the segment cache to go
 579                faster. A solution may be to force addseg to one in
 580                translate-i386.c. */
 581             new_hflags |= HF_ADDSEG_MASK;
 582         } else {
 583             new_hflags |= ((env->segs[R_DS].base |
 584                             env->segs[R_ES].base |
 585                             env->segs[R_SS].base) != 0) <<
 586                 HF_ADDSEG_SHIFT;
 587         }
 588         env->hflags = (env->hflags &
 589                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 590     }
 591 }
 592
 593 /* wrapper, just in case memory mappings must be changed */
 594 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 595 {
 596 #if HF_CPL_MASK == 3
 597     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 598 #else
 599 #error HF_CPL_MASK is hardcoded
 600 #endif
 601 }
 602
 603 /* used for debug or cpu save/restore */
 604 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
 605 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
 606
 607 /* the following helpers are only usable in user mode simulation as
 608    they can trigger unexpected exceptions */
 609 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 610 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
 611 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
 612
 613 /* you can call this signal handler from your SIGBUS and SIGSEGV
 614    signal handlers to inform the virtual CPU of exceptions. non zero
 615    is returned if the signal was handled by the virtual CPU.  */
 616 struct siginfo;
 617 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
 618                            void *puc);
 619 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 620
 621 uint64_t cpu_get_tsc(CPUX86State *env);
 622
 623 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
 624 uint64_t cpu_get_apic_base(CPUX86State *env);
 625 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
 626 #ifndef NO_CPU_IO_DEFS
 627 uint8_t cpu_get_apic_tpr(CPUX86State *env);
 628 #endif
 629
 630 /* will be suppressed */
 631 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 632
 633 /* used to debug */
 634 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 635 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 636
 637 #define TARGET_PAGE_BITS 12
 638 #include "cpu-all.h"
 639
 640 #endif /* CPU_I386_H */