4 * Copyright (c) 2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Based on OpenPic implementations:
27 * - Intel GW80314 I/O compagnion chip developper's manual
28 * - Motorola MPC8245 & MPC8540 user manuals.
29 * - Motorola MCP750 (aka Raven) programmer manual.
30 * - Motorola Harrier programmer manuel
32 * Serial interrupts, as implemented in Raven chipset are not supported yet.
37 //#define DEBUG_OPENPIC
40 #define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
42 #define DPRINTF(fmt, args...) do { } while (0)
44 #define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0)
46 #define USE_MPCxxx /* Intel model is broken, for now */
48 #if defined (USE_INTEL_GW80314)
49 /* Intel GW80314 I/O Companion chip */
59 #define VID (0x00000000)
61 #define OPENPIC_LITTLE_ENDIAN 1
62 #define OPENPIC_BIG_ENDIAN 0
64 #elif defined(USE_MPCxxx)
74 #define VID 0x03 /* MPIC version ID */
75 #define VENI 0x00000000 /* Vendor ID */
82 #define OPENPIC_LITTLE_ENDIAN 1
83 #define OPENPIC_BIG_ENDIAN 0
86 #error "Please select which OpenPic implementation is to be emulated"
89 #if (OPENPIC_BIG_ENDIAN && !TARGET_WORDS_BIGENDIAN) || \
90 (OPENPIC_LITTLE_ENDIAN && TARGET_WORDS_BIGENDIAN)
94 /* Interrupt definitions */
95 #define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */
96 #define IRQ_ERR (EXT_IRQ + 1) /* Error IRQ */
97 #define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */
99 #define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */
100 #define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */
102 #define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */
103 #define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */
106 #define BF_WIDTH(_bits_) \
107 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
109 static inline void set_bit (uint32_t *field
, int bit
)
111 field
[bit
>> 5] |= 1 << (bit
& 0x1F);
114 static inline void reset_bit (uint32_t *field
, int bit
)
116 field
[bit
>> 5] &= ~(1 << (bit
& 0x1F));
119 static inline int test_bit (uint32_t *field
, int bit
)
121 return (field
[bit
>> 5] & 1 << (bit
& 0x1F)) != 0;
131 typedef struct IRQ_queue_t
{
132 uint32_t queue
[BF_WIDTH(MAX_IRQ
)];
137 typedef struct IRQ_src_t
{
138 uint32_t ipvp
; /* IRQ vector/priority register */
139 uint32_t ide
; /* IRQ destination register */
142 int pending
; /* TRUE if IRQ is pending */
152 #define IPVP_PRIORITY_MASK (0x1F << 16)
153 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
154 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
155 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
157 typedef struct IRQ_dst_t
{
158 uint32_t pctp
; /* CPU current task priority */
159 uint32_t pcsr
; /* CPU sensitivity register */
161 IRQ_queue_t servicing
;
162 CPUState
*env
; /* Needed if we did SMP */
168 /* Global registers */
169 uint32_t frep
; /* Feature reporting register */
170 uint32_t glbc
; /* Global configuration register */
171 uint32_t micr
; /* MPIC interrupt configuration register */
172 uint32_t veni
; /* Vendor identification register */
173 uint32_t spve
; /* Spurious vector register */
174 uint32_t tifr
; /* Timer frequency reporting register */
175 /* Source registers */
176 IRQ_src_t src
[MAX_IRQ
];
177 /* Local registers per output pin */
178 IRQ_dst_t dst
[MAX_CPU
];
180 /* Timer registers */
182 uint32_t ticc
; /* Global timer current count register */
183 uint32_t tibc
; /* Global timer base count register */
186 /* Doorbell registers */
187 uint32_t dar
; /* Doorbell activate register */
189 uint32_t dmr
; /* Doorbell messaging register */
190 } doorbells
[MAX_DBL
];
193 /* Mailbox registers */
195 uint32_t mbr
; /* Mailbox register */
196 } mailboxes
[MAX_MAILBOXES
];
200 static inline void IRQ_setbit (IRQ_queue_t
*q
, int n_IRQ
)
202 set_bit(q
->queue
, n_IRQ
);
205 static inline void IRQ_resetbit (IRQ_queue_t
*q
, int n_IRQ
)
207 reset_bit(q
->queue
, n_IRQ
);
210 static inline int IRQ_testbit (IRQ_queue_t
*q
, int n_IRQ
)
212 return test_bit(q
->queue
, n_IRQ
);
215 static void IRQ_check (openpic_t
*opp
, IRQ_queue_t
*q
)
222 for (i
= 0; i
< MAX_IRQ
; i
++) {
223 if (IRQ_testbit(q
, i
)) {
224 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
225 i
, IPVP_PRIORITY(opp
->src
[i
].ipvp
), priority
);
226 if (IPVP_PRIORITY(opp
->src
[i
].ipvp
) > priority
) {
228 priority
= IPVP_PRIORITY(opp
->src
[i
].ipvp
);
233 q
->priority
= priority
;
236 static int IRQ_get_next (openpic_t
*opp
, IRQ_queue_t
*q
)
246 static void IRQ_local_pipe (openpic_t
*opp
, int n_CPU
, int n_IRQ
)
252 dst
= &opp
->dst
[n_CPU
];
253 src
= &opp
->src
[n_IRQ
];
254 priority
= IPVP_PRIORITY(src
->ipvp
);
255 if (priority
<= dst
->pctp
) {
256 /* Too low priority */
259 if (IRQ_testbit(&dst
->raised
, n_IRQ
)) {
263 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
264 IRQ_setbit(&dst
->raised
, n_IRQ
);
265 if (priority
> dst
->raised
.priority
) {
266 IRQ_get_next(opp
, &dst
->raised
);
267 DPRINTF("Raise CPU IRQ\n");
268 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HARD
);
272 /* update pic state because registers for n_IRQ have changed value */
273 static void openpic_update_irq(openpic_t
*opp
, int n_IRQ
)
278 src
= &opp
->src
[n_IRQ
];
284 if (test_bit(&src
->ipvp
, IPVP_MASK
)) {
285 /* Interrupt source is disabled */
288 if (IPVP_PRIORITY(src
->ipvp
) == 0) {
289 /* Priority set to zero */
292 if (test_bit(&src
->ipvp
, IPVP_ACTIVITY
)) {
293 /* IRQ already active */
296 if (src
->ide
== 0x00000000) {
301 if (!test_bit(&src
->ipvp
, IPVP_MODE
) ||
302 src
->ide
== (1 << src
->last_cpu
)) {
303 /* Directed delivery mode */
304 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
305 if (test_bit(&src
->ide
, i
))
306 IRQ_local_pipe(opp
, i
, n_IRQ
);
309 /* Distributed delivery mode */
310 /* XXX: incorrect code */
311 for (i
= src
->last_cpu
; i
< src
->last_cpu
; i
++) {
314 if (test_bit(&src
->ide
, i
)) {
315 IRQ_local_pipe(opp
, i
, n_IRQ
);
323 void openpic_set_irq(openpic_t
*opp
, int n_IRQ
, int level
)
327 src
= &opp
->src
[n_IRQ
];
328 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
329 n_IRQ
, level
, src
->ipvp
);
330 if (test_bit(&src
->ipvp
, IPVP_SENSE
)) {
331 /* level-sensitive irq */
332 src
->pending
= level
;
334 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
336 /* edge-sensitive irq */
340 openpic_update_irq(opp
, n_IRQ
);
343 static void openpic_reset (openpic_t
*opp
)
347 opp
->glbc
= 0x80000000;
348 /* Initialise controller registers */
349 opp
->frep
= ((EXT_IRQ
- 1) << 16) | ((MAX_CPU
- 1) << 8) | VID
;
351 opp
->spve
= 0x000000FF;
352 opp
->tifr
= 0x003F7A00;
354 opp
->micr
= 0x00000000;
355 /* Initialise IRQ sources */
356 for (i
= 0; i
< MAX_IRQ
; i
++) {
357 opp
->src
[i
].ipvp
= 0xA0000000;
358 opp
->src
[i
].ide
= 0x00000000;
360 /* Initialise IRQ destinations */
361 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
362 opp
->dst
[i
].pctp
= 0x0000000F;
363 opp
->dst
[i
].pcsr
= 0x00000000;
364 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
365 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
367 /* Initialise timers */
368 for (i
= 0; i
< MAX_TMR
; i
++) {
369 opp
->timers
[i
].ticc
= 0x00000000;
370 opp
->timers
[i
].tibc
= 0x80000000;
372 /* Initialise doorbells */
374 opp
->dar
= 0x00000000;
375 for (i
= 0; i
< MAX_DBL
; i
++) {
376 opp
->doorbells
[i
].dmr
= 0x00000000;
379 /* Initialise mailboxes */
381 for (i
= 0; i
< MAX_MBX
; i
++) { /* ? */
382 opp
->mailboxes
[i
].mbr
= 0x00000000;
385 /* Go out of RESET state */
386 opp
->glbc
= 0x00000000;
389 static inline uint32_t read_IRQreg (openpic_t
*opp
, int n_IRQ
, uint32_t reg
)
395 retval
= opp
->src
[n_IRQ
].ipvp
;
398 retval
= opp
->src
[n_IRQ
].ide
;
405 static inline void write_IRQreg (openpic_t
*opp
, int n_IRQ
,
406 uint32_t reg
, uint32_t val
)
412 /* NOTE: not fully accurate for special IRQs, but simple and
414 /* ACTIVITY bit is read-only */
415 opp
->src
[n_IRQ
].ipvp
=
416 (opp
->src
[n_IRQ
].ipvp
& 0x40000000) |
418 openpic_update_irq(opp
, n_IRQ
);
419 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
420 n_IRQ
, val
, opp
->src
[n_IRQ
].ipvp
);
423 tmp
= val
& 0xC0000000;
424 tmp
|= val
& ((1 << MAX_CPU
) - 1);
425 opp
->src
[n_IRQ
].ide
= tmp
;
426 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ
, opp
->src
[n_IRQ
].ide
);
431 #if 0 // Code provision for Intel model
433 static uint32_t read_doorbell_register (openpic_t
*opp
,
434 int n_dbl
, uint32_t offset
)
439 case DBL_IPVP_OFFSET
:
440 retval
= read_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IPVP
);
443 retval
= read_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IDE
);
446 retval
= opp
->doorbells
[n_dbl
].dmr
;
453 static void write_doorbell_register (penpic_t
*opp
, int n_dbl
,
454 uint32_t offset
, uint32_t value
)
457 case DBL_IVPR_OFFSET
:
458 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IPVP
, value
);
461 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IDE
, value
);
464 opp
->doorbells
[n_dbl
].dmr
= value
;
471 static uint32_t read_mailbox_register (openpic_t
*opp
,
472 int n_mbx
, uint32_t offset
)
478 retval
= opp
->mailboxes
[n_mbx
].mbr
;
480 case MBX_IVPR_OFFSET
:
481 retval
= read_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IPVP
);
484 retval
= read_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IDE
);
491 static void write_mailbox_register (openpic_t
*opp
, int n_mbx
,
492 uint32_t address
, uint32_t value
)
496 opp
->mailboxes
[n_mbx
].mbr
= value
;
498 case MBX_IVPR_OFFSET
:
499 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IPVP
, value
);
502 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IDE
, value
);
507 #endif /* 0 : Code provision for Intel model */
509 static void openpic_gbl_write (void *opaque
, uint32_t addr
, uint32_t val
)
511 openpic_t
*opp
= opaque
;
513 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
516 #if defined OPENPIC_SWAP
521 case 0x00: /* FREP */
523 case 0x20: /* GLBC */
524 if (val
& 0x80000000)
526 opp
->glbc
= val
& ~0x80000000;
528 case 0x80: /* VENI */
530 case 0x90: /* PINT */
531 /* XXX: Should be able to reset any CPU */
533 DPRINTF("Reset CPU IRQ\n");
534 // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
538 case 0xA0: /* IPI_IPVP */
544 idx
= (addr
- 0xA0) >> 4;
545 write_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IPVP
, val
);
549 case 0xE0: /* SPVE */
550 opp
->spve
= val
& 0x000000FF;
552 case 0xF0: /* TIFR */
560 static uint32_t openpic_gbl_read (void *opaque
, uint32_t addr
)
562 openpic_t
*opp
= opaque
;
565 DPRINTF("%s: addr %08x\n", __func__
, addr
);
571 case 0x00: /* FREP */
574 case 0x20: /* GLBC */
577 case 0x80: /* VENI */
580 case 0x90: /* PINT */
584 case 0xA0: /* IPI_IPVP */
590 idx
= (addr
- 0xA0) >> 4;
591 retval
= read_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IPVP
);
595 case 0xE0: /* SPVE */
598 case 0xF0: /* TIFR */
604 DPRINTF("%s: => %08x\n", __func__
, retval
);
605 #if defined OPENPIC_SWAP
606 retval
= bswap32(retval
);
612 static void openpic_timer_write (void *opaque
, uint32_t addr
, uint32_t val
)
614 openpic_t
*opp
= opaque
;
617 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
620 #if defined OPENPIC_SWAP
625 idx
= (addr
& 0xFFF0) >> 6;
628 case 0x00: /* TICC */
630 case 0x10: /* TIBC */
631 if ((opp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
632 (val
& 0x80000000) == 0 &&
633 (opp
->timers
[idx
].tibc
& 0x80000000) != 0)
634 opp
->timers
[idx
].ticc
&= ~0x80000000;
635 opp
->timers
[idx
].tibc
= val
;
637 case 0x20: /* TIVP */
638 write_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IPVP
, val
);
640 case 0x30: /* TIDE */
641 write_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IDE
, val
);
646 static uint32_t openpic_timer_read (void *opaque
, uint32_t addr
)
648 openpic_t
*opp
= opaque
;
652 DPRINTF("%s: addr %08x\n", __func__
, addr
);
658 idx
= (addr
& 0xFFF0) >> 6;
661 case 0x00: /* TICC */
662 retval
= opp
->timers
[idx
].ticc
;
664 case 0x10: /* TIBC */
665 retval
= opp
->timers
[idx
].tibc
;
667 case 0x20: /* TIPV */
668 retval
= read_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IPVP
);
670 case 0x30: /* TIDE */
671 retval
= read_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IDE
);
674 DPRINTF("%s: => %08x\n", __func__
, retval
);
675 #if defined OPENPIC_SWAP
676 retval
= bswap32(retval
);
682 static void openpic_src_write (void *opaque
, uint32_t addr
, uint32_t val
)
684 openpic_t
*opp
= opaque
;
687 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
690 #if defined OPENPIC_SWAP
693 addr
= addr
& 0xFFF0;
696 /* EXDE / IFEDE / IEEDE */
697 write_IRQreg(opp
, idx
, IRQ_IDE
, val
);
699 /* EXVP / IFEVP / IEEVP */
700 write_IRQreg(opp
, idx
, IRQ_IPVP
, val
);
704 static uint32_t openpic_src_read (void *opaque
, uint32_t addr
)
706 openpic_t
*opp
= opaque
;
710 DPRINTF("%s: addr %08x\n", __func__
, addr
);
714 addr
= addr
& 0xFFF0;
717 /* EXDE / IFEDE / IEEDE */
718 retval
= read_IRQreg(opp
, idx
, IRQ_IDE
);
720 /* EXVP / IFEVP / IEEVP */
721 retval
= read_IRQreg(opp
, idx
, IRQ_IPVP
);
723 DPRINTF("%s: => %08x\n", __func__
, retval
);
724 #if defined OPENPIC_SWAP
725 retval
= tswap32(retval
);
731 static void openpic_cpu_write (void *opaque
, uint32_t addr
, uint32_t val
)
733 openpic_t
*opp
= opaque
;
738 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
741 #if defined OPENPIC_SWAP
746 dst
= &opp
->dst
[idx
];
750 case 0x40: /* PIPD */
754 idx
= (addr
- 0x40) >> 4;
755 write_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IDE
, val
);
756 openpic_set_irq(opp
, IRQ_IPI0
+ idx
, 1);
757 openpic_set_irq(opp
, IRQ_IPI0
+ idx
, 0);
760 case 0x80: /* PCTP */
761 dst
->pctp
= val
& 0x0000000F;
763 case 0x90: /* WHOAMI */
764 /* Read-only register */
766 case 0xA0: /* PIAC */
767 /* Read-only register */
769 case 0xB0: /* PEOI */
771 n_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
772 IRQ_resetbit(&dst
->servicing
, n_IRQ
);
773 dst
->servicing
.next
= -1;
774 src
= &opp
->src
[n_IRQ
];
775 /* Set up next servicing IRQ */
776 IRQ_get_next(opp
, &dst
->servicing
);
777 /* Check queued interrupts. */
778 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
780 src
= &opp
->src
[n_IRQ
];
781 if (IPVP_PRIORITY(src
->ipvp
) > dst
->servicing
.priority
) {
782 DPRINTF("Raise CPU IRQ\n");
783 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HARD
);
792 static uint32_t openpic_cpu_read (void *opaque
, uint32_t addr
)
794 openpic_t
*opp
= opaque
;
800 DPRINTF("%s: addr %08x\n", __func__
, addr
);
806 dst
= &opp
->dst
[idx
];
809 case 0x80: /* PCTP */
812 case 0x90: /* WHOAMI */
815 case 0xA0: /* PIAC */
816 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
817 DPRINTF("PIAC: irq=%d\n", n_IRQ
);
819 /* No more interrupt pending */
822 src
= &opp
->src
[n_IRQ
];
823 if (!test_bit(&src
->ipvp
, IPVP_ACTIVITY
) ||
824 !(IPVP_PRIORITY(src
->ipvp
) > dst
->pctp
)) {
825 /* - Spurious level-sensitive IRQ
826 * - Priorities has been changed
827 * and the pending IRQ isn't allowed anymore
829 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
830 retval
= IPVP_VECTOR(opp
->spve
);
832 /* IRQ enter servicing state */
833 IRQ_setbit(&dst
->servicing
, n_IRQ
);
834 retval
= IPVP_VECTOR(src
->ipvp
);
836 IRQ_resetbit(&dst
->raised
, n_IRQ
);
837 dst
->raised
.next
= -1;
838 if (!test_bit(&src
->ipvp
, IPVP_SENSE
)) {
839 /* edge-sensitive IRQ */
840 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
845 case 0xB0: /* PEOI */
851 idx
= (addr
- 0x40) >> 4;
852 retval
= read_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IDE
);
858 DPRINTF("%s: => %08x\n", __func__
, retval
);
859 #if defined OPENPIC_SWAP
860 retval
= bswap32(retval
);
866 static void openpic_buggy_write (void *opaque
,
867 target_phys_addr_t addr
, uint32_t val
)
869 printf("Invalid OPENPIC write access !\n");
872 static uint32_t openpic_buggy_read (void *opaque
, target_phys_addr_t addr
)
874 printf("Invalid OPENPIC read access !\n");
879 static void openpic_writel (void *opaque
,
880 target_phys_addr_t addr
, uint32_t val
)
882 openpic_t
*opp
= opaque
;
885 DPRINTF("%s: offset %08x val: %08x\n", __func__
, (int)addr
, val
);
887 /* Global registers */
888 openpic_gbl_write(opp
, addr
, val
);
889 } else if (addr
< 0x10000) {
890 /* Timers registers */
891 openpic_timer_write(opp
, addr
, val
);
892 } else if (addr
< 0x20000) {
893 /* Source registers */
894 openpic_src_write(opp
, addr
, val
);
897 openpic_cpu_write(opp
, addr
, val
);
901 static uint32_t openpic_readl (void *opaque
,target_phys_addr_t addr
)
903 openpic_t
*opp
= opaque
;
907 DPRINTF("%s: offset %08x\n", __func__
, (int)addr
);
909 /* Global registers */
910 retval
= openpic_gbl_read(opp
, addr
);
911 } else if (addr
< 0x10000) {
912 /* Timers registers */
913 retval
= openpic_timer_read(opp
, addr
);
914 } else if (addr
< 0x20000) {
915 /* Source registers */
916 retval
= openpic_src_read(opp
, addr
);
919 retval
= openpic_cpu_read(opp
, addr
);
925 static CPUWriteMemoryFunc
*openpic_write
[] = {
926 &openpic_buggy_write
,
927 &openpic_buggy_write
,
931 static CPUReadMemoryFunc
*openpic_read
[] = {
937 static void openpic_map(PCIDevice
*pci_dev
, int region_num
,
938 uint32_t addr
, uint32_t size
, int type
)
942 DPRINTF("Map OpenPIC\n");
943 opp
= (openpic_t
*)pci_dev
;
944 /* Global registers */
945 DPRINTF("Register OPENPIC gbl %08x => %08x\n",
946 addr
+ 0x1000, addr
+ 0x1000 + 0x100);
947 /* Timer registers */
948 DPRINTF("Register OPENPIC timer %08x => %08x\n",
949 addr
+ 0x1100, addr
+ 0x1100 + 0x40 * MAX_TMR
);
950 /* Interrupt source registers */
951 DPRINTF("Register OPENPIC src %08x => %08x\n",
952 addr
+ 0x10000, addr
+ 0x10000 + 0x20 * (EXT_IRQ
+ 2));
953 /* Per CPU registers */
954 DPRINTF("Register OPENPIC dst %08x => %08x\n",
955 addr
+ 0x20000, addr
+ 0x20000 + 0x1000 * MAX_CPU
);
956 cpu_register_physical_memory(addr
, 0x40000, opp
->mem_index
);
957 #if 0 // Don't implement ISU for now
958 opp_io_memory
= cpu_register_io_memory(0, openpic_src_read
,
960 cpu_register_physical_memory(isu_base
, 0x20 * (EXT_IRQ
+ 2),
965 openpic_t
*openpic_init (PCIBus
*bus
, int *pmem_index
, int nb_cpus
)
971 /* XXX: for now, only one CPU is supported */
975 opp
= (openpic_t
*)pci_register_device(bus
, "OpenPIC", sizeof(openpic_t
),
979 pci_conf
= opp
->pci_dev
.config
;
980 pci_conf
[0x00] = 0x14; // IBM MPIC2
981 pci_conf
[0x01] = 0x10;
982 pci_conf
[0x02] = 0xFF;
983 pci_conf
[0x03] = 0xFF;
984 pci_conf
[0x0a] = 0x80; // PIC
985 pci_conf
[0x0b] = 0x08;
986 pci_conf
[0x0e] = 0x00; // header_type
987 pci_conf
[0x3d] = 0x00; // no interrupt pin
989 /* Register I/O spaces */
990 pci_register_io_region((PCIDevice
*)opp
, 0, 0x40000,
991 PCI_ADDRESS_SPACE_MEM
, &openpic_map
);
993 opp
= qemu_mallocz(sizeof(openpic_t
));
996 opp
->mem_index
= cpu_register_io_memory(0, openpic_read
,
999 // isu_base &= 0xFFFC0000;
1000 opp
->nb_cpus
= nb_cpus
;
1002 for (i
= 0; i
< EXT_IRQ
; i
++) {
1003 opp
->src
[i
].type
= IRQ_EXTERNAL
;
1005 for (; i
< IRQ_TIM0
; i
++) {
1006 opp
->src
[i
].type
= IRQ_SPECIAL
;
1013 for (; i
< m
; i
++) {
1014 opp
->src
[i
].type
= IRQ_TIMER
;
1016 for (; i
< MAX_IRQ
; i
++) {
1017 opp
->src
[i
].type
= IRQ_INTERNAL
;
1021 *pmem_index
= opp
->mem_index
;