hw/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug NE2000 card */
  27 //#define DEBUG_NE2000
  28
  29 #define MAX_ETH_FRAME_SIZE 1514
  30
  31 #define E8390_CMD       0x00  /* The command register (for all pages) */
  32 /* Page 0 register offsets. */
  33 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  34 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  35 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  36 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  37 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  38 #define EN0_TSR         0x04    /* Transmit status reg RD */
  39 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  40 #define EN0_NCR         0x05    /* Number of collision reg RD */
  41 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  42 #define EN0_FIFO        0x06    /* FIFO RD */
  43 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  44 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  45 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  46 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  47 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  48 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  49 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  50 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  51 #define EN0_RSR         0x0c    /* rx status reg RD */
  52 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  53 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  54 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  55 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  56 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  57 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  58 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  59
  60 #define EN1_PHYS        0x11
  61 #define EN1_CURPAG      0x17
  62 #define EN1_MULT        0x18
  63
  64 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  65 #define E8390_STOP      0x01    /* Stop and reset the chip */
  66 #define E8390_START     0x02    /* Start the chip, clear reset */
  67 #define E8390_TRANS     0x04    /* Transmit a frame */
  68 #define E8390_RREAD     0x08    /* Remote read */
  69 #define E8390_RWRITE    0x10    /* Remote write  */
  70 #define E8390_NODMA     0x20    /* Remote DMA */
  71 #define E8390_PAGE0     0x00    /* Select page chip registers */
  72 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  73 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  74
  75 /* Bits in EN0_ISR - Interrupt status register */
  76 #define ENISR_RX        0x01    /* Receiver, no error */
  77 #define ENISR_TX        0x02    /* Transmitter, no error */
  78 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  79 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
  80 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
  81 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
  82 #define ENISR_RDC       0x40    /* remote dma complete */
  83 #define ENISR_RESET     0x80    /* Reset completed */
  84 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
  85
  86 /* Bits in received packet status byte and EN0_RSR*/
  87 #define ENRSR_RXOK      0x01    /* Received a good packet */
  88 #define ENRSR_CRC       0x02    /* CRC error */
  89 #define ENRSR_FAE       0x04    /* frame alignment error */
  90 #define ENRSR_FO        0x08    /* FIFO overrun */
  91 #define ENRSR_MPA       0x10    /* missed pkt */
  92 #define ENRSR_PHY       0x20    /* physical/multicast address */
  93 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
  94 #define ENRSR_DEF       0x80    /* deferring */
  95
  96 /* Transmitted packet status, EN0_TSR. */
  97 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
  98 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
  99 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 100 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 101 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 102 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 103 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 104 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 105
 106 #define NE2000_PMEM_SIZE    (32*1024)
 107 #define NE2000_PMEM_START   (16*1024)
 108 #define NE2000_PMEM_END     (NE2000_PMEM_SIZE+NE2000_PMEM_START)
 109 #define NE2000_MEM_SIZE     NE2000_PMEM_END
 110
 111 typedef struct NE2000State {
 112     uint8_t cmd;
 113     uint32_t start;
 114     uint32_t stop;
 115     uint8_t boundary;
 116     uint8_t tsr;
 117     uint8_t tpsr;
 118     uint16_t tcnt;
 119     uint16_t rcnt;
 120     uint32_t rsar;
 121     uint8_t rsr;
 122     uint8_t isr;
 123     uint8_t dcfg;
 124     uint8_t imr;
 125     uint8_t phys[6]; /* mac address */
 126     uint8_t curpag;
 127     uint8_t mult[8]; /* multicast mask array */
 128     int irq;
 129     PCIDevice *pci_dev;
 130     NetDriverState *nd;
 131     uint8_t mem[NE2000_MEM_SIZE];
 132 } NE2000State;
 133
 134 static void ne2000_reset(NE2000State *s)
 135 {
 136     int i;
 137
 138     s->isr = ENISR_RESET;
 139     memcpy(s->mem, s->nd->macaddr, 6);
 140     s->mem[14] = 0x57;
 141     s->mem[15] = 0x57;
 142
 143     /* duplicate prom data */
 144     for(i = 15;i >= 0; i--) {
 145         s->mem[2 * i] = s->mem[i];
 146         s->mem[2 * i + 1] = s->mem[i];
 147     }
 148 }
 149
 150 static void ne2000_update_irq(NE2000State *s)
 151 {
 152     int isr;
 153     isr = s->isr & s->imr;
 154 #if defined(DEBUG_NE2000)
 155     printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
 156            s->irq, isr ? 1 : 0, s->isr, s->imr);
 157 #endif
 158     if (s->irq == 16) {
 159         /* PCI irq */
 160         pci_set_irq(s->pci_dev, 0, (isr != 0));
 161     } else {
 162         /* ISA irq */
 163         pic_set_irq(s->irq, (isr != 0));
 164     }
 165 }
 166
 167 /* return the max buffer size if the NE2000 can receive more data */
 168 static int ne2000_can_receive(void *opaque)
 169 {
 170     NE2000State *s = opaque;
 171     int avail, index, boundary;
 172
 173     if (s->cmd & E8390_STOP)
 174         return 0;
 175     index = s->curpag << 8;
 176     boundary = s->boundary << 8;
 177     if (index < boundary)
 178         avail = boundary - index;
 179     else
 180         avail = (s->stop - s->start) - (index - boundary);
 181     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 182         return 0;
 183     return MAX_ETH_FRAME_SIZE;
 184 }
 185
 186 #define MIN_BUF_SIZE 60
 187
 188 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
 189 {
 190     NE2000State *s = opaque;
 191     uint8_t *p;
 192     int total_len, next, avail, len, index;
 193     uint8_t buf1[60];
 194
 195 #if defined(DEBUG_NE2000)
 196     printf("NE2000: received len=%d\n", size);
 197 #endif
 198
 199     /* if too small buffer, then expand it */
 200     if (size < MIN_BUF_SIZE) {
 201         memcpy(buf1, buf, size);
 202         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 203         buf = buf1;
 204         size = MIN_BUF_SIZE;
 205     }
 206
 207     index = s->curpag << 8;
 208     /* 4 bytes for header */
 209     total_len = size + 4;
 210     /* address for next packet (4 bytes for CRC) */
 211     next = index + ((total_len + 4 + 255) & ~0xff);
 212     if (next >= s->stop)
 213         next -= (s->stop - s->start);
 214     /* prepare packet header */
 215     p = s->mem + index;
 216     s->rsr = ENRSR_RXOK; /* receive status */
 217     /* XXX: check this */
 218     if (buf[0] & 0x01)
 219         s->rsr |= ENRSR_PHY;
 220     p[0] = s->rsr;
 221     p[1] = next >> 8;
 222     p[2] = total_len;
 223     p[3] = total_len >> 8;
 224     index += 4;
 225
 226     /* write packet data */
 227     while (size > 0) {
 228         avail = s->stop - index;
 229         len = size;
 230         if (len > avail)
 231             len = avail;
 232         memcpy(s->mem + index, buf, len);
 233         buf += len;
 234         index += len;
 235         if (index == s->stop)
 236             index = s->start;
 237         size -= len;
 238     }
 239     s->curpag = next >> 8;
 240
 241     /* now we can signal we have receive something */
 242     s->isr |= ENISR_RX;
 243     ne2000_update_irq(s);
 244 }
 245
 246 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 247 {
 248     NE2000State *s = opaque;
 249     int offset, page, index;
 250
 251     addr &= 0xf;
 252 #ifdef DEBUG_NE2000
 253     printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
 254 #endif
 255     if (addr == E8390_CMD) {
 256         /* control register */
 257         s->cmd = val;
 258         if (val & E8390_START) {
 259             s->isr &= ~ENISR_RESET;
 260             /* test specific case: zero length transfert */
 261             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 262                 s->rcnt == 0) {
 263                 s->isr |= ENISR_RDC;
 264                 ne2000_update_irq(s);
 265             }
 266             if (val & E8390_TRANS) {
 267                 index = (s->tpsr << 8);
 268                 /* XXX: next 2 lines are a hack to make netware 3.11 work */
 269                 if (index >= NE2000_PMEM_END)
 270                     index -= NE2000_PMEM_SIZE;
 271                 /* fail safe: check range on the transmitted length  */
 272                 if (index + s->tcnt <= NE2000_PMEM_END) {
 273                     qemu_send_packet(s->nd, s->mem + index, s->tcnt);
 274                 }
 275                 /* signal end of transfert */
 276                 s->tsr = ENTSR_PTX;
 277                 s->isr |= ENISR_TX;
 278                 s->cmd &= ~E8390_TRANS;
 279                 ne2000_update_irq(s);
 280             }
 281         }
 282     } else {
 283         page = s->cmd >> 6;
 284         offset = addr | (page << 4);
 285         switch(offset) {
 286         case EN0_STARTPG:
 287             s->start = val << 8;
 288             break;
 289         case EN0_STOPPG:
 290             s->stop = val << 8;
 291             break;
 292         case EN0_BOUNDARY:
 293             s->boundary = val;
 294             break;
 295         case EN0_IMR:
 296             s->imr = val;
 297             ne2000_update_irq(s);
 298             break;
 299         case EN0_TPSR:
 300             s->tpsr = val;
 301             break;
 302         case EN0_TCNTLO:
 303             s->tcnt = (s->tcnt & 0xff00) | val;
 304             break;
 305         case EN0_TCNTHI:
 306             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 307             break;
 308         case EN0_RSARLO:
 309             s->rsar = (s->rsar & 0xff00) | val;
 310             break;
 311         case EN0_RSARHI:
 312             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 313             break;
 314         case EN0_RCNTLO:
 315             s->rcnt = (s->rcnt & 0xff00) | val;
 316             break;
 317         case EN0_RCNTHI:
 318             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 319             break;
 320         case EN0_DCFG:
 321             s->dcfg = val;
 322             break;
 323         case EN0_ISR:
 324             s->isr &= ~(val & 0x7f);
 325             ne2000_update_irq(s);
 326             break;
 327         case EN1_PHYS ... EN1_PHYS + 5:
 328             s->phys[offset - EN1_PHYS] = val;
 329             break;
 330         case EN1_CURPAG:
 331             s->curpag = val;
 332             break;
 333         case EN1_MULT ... EN1_MULT + 7:
 334             s->mult[offset - EN1_MULT] = val;
 335             break;
 336         }
 337     }
 338 }
 339
 340 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 341 {
 342     NE2000State *s = opaque;
 343     int offset, page, ret;
 344
 345     addr &= 0xf;
 346     if (addr == E8390_CMD) {
 347         ret = s->cmd;
 348     } else {
 349         page = s->cmd >> 6;
 350         offset = addr | (page << 4);
 351         switch(offset) {
 352         case EN0_TSR:
 353             ret = s->tsr;
 354             break;
 355         case EN0_BOUNDARY:
 356             ret = s->boundary;
 357             break;
 358         case EN0_ISR:
 359             ret = s->isr;
 360             break;
 361         case EN0_RSARLO:
 362             ret = s->rsar & 0x00ff;
 363             break;
 364         case EN0_RSARHI:
 365             ret = s->rsar >> 8;
 366             break;
 367         case EN1_PHYS ... EN1_PHYS + 5:
 368             ret = s->phys[offset - EN1_PHYS];
 369             break;
 370         case EN1_CURPAG:
 371             ret = s->curpag;
 372             break;
 373         case EN1_MULT ... EN1_MULT + 7:
 374             ret = s->mult[offset - EN1_MULT];
 375             break;
 376         case EN0_RSR:
 377             ret = s->rsr;
 378             break;
 379         default:
 380             ret = 0x00;
 381             break;
 382         }
 383     }
 384 #ifdef DEBUG_NE2000
 385     printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
 386 #endif
 387     return ret;
 388 }
 389
 390 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
 391                                      uint32_t val)
 392 {
 393     if (addr < 32 ||
 394         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 395         s->mem[addr] = val;
 396     }
 397 }
 398
 399 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
 400                                      uint32_t val)
 401 {
 402     addr &= ~1; /* XXX: check exact behaviour if not even */
 403     if (addr < 32 ||
 404         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 405         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
 406     }
 407 }
 408
 409 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
 410                                      uint32_t val)
 411 {
 412     addr &= ~1; /* XXX: check exact behaviour if not even */
 413     if (addr < 32 ||
 414         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 415         cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
 416     }
 417 }
 418
 419 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
 420 {
 421     if (addr < 32 ||
 422         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 423         return s->mem[addr];
 424     } else {
 425         return 0xff;
 426     }
 427 }
 428
 429 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
 430 {
 431     addr &= ~1; /* XXX: check exact behaviour if not even */
 432     if (addr < 32 ||
 433         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 434         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
 435     } else {
 436         return 0xffff;
 437     }
 438 }
 439
 440 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
 441 {
 442     addr &= ~1; /* XXX: check exact behaviour if not even */
 443     if (addr < 32 ||
 444         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 445         return le32_to_cpupu((uint32_t *)(s->mem + addr));
 446     } else {
 447         return 0xffffffff;
 448     }
 449 }
 450
 451 static inline void ne2000_dma_update(NE2000State *s, int len)
 452 {
 453     s->rsar += len;
 454     /* wrap */
 455     /* XXX: check what to do if rsar > stop */
 456     if (s->rsar == s->stop)
 457         s->rsar = s->start;
 458
 459     if (s->rcnt <= len) {
 460         s->rcnt = 0;
 461         /* signal end of transfert */
 462         s->isr |= ENISR_RDC;
 463         ne2000_update_irq(s);
 464     } else {
 465         s->rcnt -= len;
 466     }
 467 }
 468
 469 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 470 {
 471     NE2000State *s = opaque;
 472
 473 #ifdef DEBUG_NE2000
 474     printf("NE2000: asic write val=0x%04x\n", val);
 475 #endif
 476     if (s->rcnt == 0)
 477         return;
 478     if (s->dcfg & 0x01) {
 479         /* 16 bit access */
 480         ne2000_mem_writew(s, s->rsar, val);
 481         ne2000_dma_update(s, 2);
 482     } else {
 483         /* 8 bit access */
 484         ne2000_mem_writeb(s, s->rsar, val);
 485         ne2000_dma_update(s, 1);
 486     }
 487 }
 488
 489 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 490 {
 491     NE2000State *s = opaque;
 492     int ret;
 493
 494     if (s->dcfg & 0x01) {
 495         /* 16 bit access */
 496         ret = ne2000_mem_readw(s, s->rsar);
 497         ne2000_dma_update(s, 2);
 498     } else {
 499         /* 8 bit access */
 500         ret = ne2000_mem_readb(s, s->rsar);
 501         ne2000_dma_update(s, 1);
 502     }
 503 #ifdef DEBUG_NE2000
 504     printf("NE2000: asic read val=0x%04x\n", ret);
 505 #endif
 506     return ret;
 507 }
 508
 509 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 510 {
 511     NE2000State *s = opaque;
 512
 513 #ifdef DEBUG_NE2000
 514     printf("NE2000: asic writel val=0x%04x\n", val);
 515 #endif
 516     if (s->rcnt == 0)
 517         return;
 518     /* 32 bit access */
 519     ne2000_mem_writel(s, s->rsar, val);
 520     ne2000_dma_update(s, 4);
 521 }
 522
 523 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
 524 {
 525     NE2000State *s = opaque;
 526     int ret;
 527
 528     /* 32 bit access */
 529     ret = ne2000_mem_readl(s, s->rsar);
 530     ne2000_dma_update(s, 4);
 531 #ifdef DEBUG_NE2000
 532     printf("NE2000: asic readl val=0x%04x\n", ret);
 533 #endif
 534     return ret;
 535 }
 536
 537 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 538 {
 539     /* nothing to do (end of reset pulse) */
 540 }
 541
 542 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 543 {
 544     NE2000State *s = opaque;
 545     ne2000_reset(s);
 546     return 0;
 547 }
 548
 549 static void ne2000_save(QEMUFile* f,void* opaque)
 550 {
 551         NE2000State* s=(NE2000State*)opaque;
 552
 553         qemu_put_8s(f, &s->cmd);
 554         qemu_put_be32s(f, &s->start);
 555         qemu_put_be32s(f, &s->stop);
 556         qemu_put_8s(f, &s->boundary);
 557         qemu_put_8s(f, &s->tsr);
 558         qemu_put_8s(f, &s->tpsr);
 559         qemu_put_be16s(f, &s->tcnt);
 560         qemu_put_be16s(f, &s->rcnt);
 561         qemu_put_be32s(f, &s->rsar);
 562         qemu_put_8s(f, &s->rsr);
 563         qemu_put_8s(f, &s->isr);
 564         qemu_put_8s(f, &s->dcfg);
 565         qemu_put_8s(f, &s->imr);
 566         qemu_put_buffer(f, s->phys, 6);
 567         qemu_put_8s(f, &s->curpag);
 568         qemu_put_buffer(f, s->mult, 8);
 569         qemu_put_be32s(f, &s->irq);
 570         qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
 571 }
 572
 573 static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
 574 {
 575         NE2000State* s=(NE2000State*)opaque;
 576
 577         if (version_id != 1)
 578             return -EINVAL;
 579
 580         qemu_get_8s(f, &s->cmd);
 581         qemu_get_be32s(f, &s->start);
 582         qemu_get_be32s(f, &s->stop);
 583         qemu_get_8s(f, &s->boundary);
 584         qemu_get_8s(f, &s->tsr);
 585         qemu_get_8s(f, &s->tpsr);
 586         qemu_get_be16s(f, &s->tcnt);
 587         qemu_get_be16s(f, &s->rcnt);
 588         qemu_get_be32s(f, &s->rsar);
 589         qemu_get_8s(f, &s->rsr);
 590         qemu_get_8s(f, &s->isr);
 591         qemu_get_8s(f, &s->dcfg);
 592         qemu_get_8s(f, &s->imr);
 593         qemu_get_buffer(f, s->phys, 6);
 594         qemu_get_8s(f, &s->curpag);
 595         qemu_get_buffer(f, s->mult, 8);
 596         qemu_get_be32s(f, &s->irq);
 597         qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
 598
 599         return 0;
 600 }
 601
 602 void isa_ne2000_init(int base, int irq, NetDriverState *nd)
 603 {
 604     NE2000State *s;
 605
 606     s = qemu_mallocz(sizeof(NE2000State));
 607     if (!s)
 608         return;
 609
 610     register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
 611     register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
 612
 613     register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 614     register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 615     register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 616     register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 617
 618     register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 619     register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 620     s->irq = irq;
 621     s->nd = nd;
 622
 623     ne2000_reset(s);
 624
 625     qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
 626
 627     register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
 628
 629 }
 630
 631 /***********************************************************/
 632 /* PCI NE2000 definitions */
 633
 634 typedef struct PCINE2000State {
 635     PCIDevice dev;
 636     NE2000State ne2000;
 637 } PCINE2000State;
 638
 639 static void ne2000_map(PCIDevice *pci_dev, int region_num,
 640                        uint32_t addr, uint32_t size, int type)
 641 {
 642     PCINE2000State *d = (PCINE2000State *)pci_dev;
 643     NE2000State *s = &d->ne2000;
 644
 645     register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
 646     register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
 647
 648     register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 649     register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 650     register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 651     register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 652     register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
 653     register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
 654
 655     register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 656     register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 657 }
 658
 659 void pci_ne2000_init(PCIBus *bus, NetDriverState *nd)
 660 {
 661     PCINE2000State *d;
 662     NE2000State *s;
 663     uint8_t *pci_conf;
 664
 665     d = (PCINE2000State *)pci_register_device(bus,
 666                                               "NE2000", sizeof(PCINE2000State),
 667                                               -1,
 668                                               NULL, NULL);
 669     pci_conf = d->dev.config;
 670     pci_conf[0x00] = 0xec; // Realtek 8029
 671     pci_conf[0x01] = 0x10;
 672     pci_conf[0x02] = 0x29;
 673     pci_conf[0x03] = 0x80;
 674     pci_conf[0x0a] = 0x00; // ethernet network controller
 675     pci_conf[0x0b] = 0x02;
 676     pci_conf[0x0e] = 0x00; // header_type
 677     pci_conf[0x3d] = 1; // interrupt pin 0
 678
 679     pci_register_io_region(&d->dev, 0, 0x100,
 680                            PCI_ADDRESS_SPACE_IO, ne2000_map);
 681     s = &d->ne2000;
 682     s->irq = 16; // PCI interrupt
 683     s->pci_dev = (PCIDevice *)d;
 684     s->nd = nd;
 685     ne2000_reset(s);
 686     qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
 687
 688     /* XXX: instance number ? */
 689     register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
 690     register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load,
 691                     &d->dev);
 692 }