cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #include "exec.h"
  22 #include "disas.h"
  23
  24 #if !defined(CONFIG_SOFTMMU)
  25 #undef EAX
  26 #undef ECX
  27 #undef EDX
  28 #undef EBX
  29 #undef ESP
  30 #undef EBP
  31 #undef ESI
  32 #undef EDI
  33 #undef EIP
  34 #include <signal.h>
  35 #include <sys/ucontext.h>
  36 #endif
  37
  38 int tb_invalidated_flag;
  39
  40 //#define DEBUG_EXEC
  41 //#define DEBUG_SIGNAL
  42
  43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
  44 /* XXX: unify with i386 target */
  45 void cpu_loop_exit(void)
  46 {
  47     longjmp(env->jmp_env, 1);
  48 }
  49 #endif
  50
  51 /* exit the current TB from a signal handler. The host registers are
  52    restored in a state compatible with the CPU emulator
  53  */
  54 void cpu_resume_from_signal(CPUState *env1, void *puc)
  55 {
  56 #if !defined(CONFIG_SOFTMMU)
  57     struct ucontext *uc = puc;
  58 #endif
  59
  60     env = env1;
  61
  62     /* XXX: restore cpu registers saved in host registers */
  63
  64 #if !defined(CONFIG_SOFTMMU)
  65     if (puc) {
  66         /* XXX: use siglongjmp ? */
  67         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  68     }
  69 #endif
  70     longjmp(env->jmp_env, 1);
  71 }
  72
  73 /* main execution loop */
  74
  75 int cpu_exec(CPUState *env1)
  76 {
  77     int saved_T0, saved_T1, saved_T2;
  78     CPUState *saved_env;
  79 #ifdef reg_EAX
  80     int saved_EAX;
  81 #endif
  82 #ifdef reg_ECX
  83     int saved_ECX;
  84 #endif
  85 #ifdef reg_EDX
  86     int saved_EDX;
  87 #endif
  88 #ifdef reg_EBX
  89     int saved_EBX;
  90 #endif
  91 #ifdef reg_ESP
  92     int saved_ESP;
  93 #endif
  94 #ifdef reg_EBP
  95     int saved_EBP;
  96 #endif
  97 #ifdef reg_ESI
  98     int saved_ESI;
  99 #endif
 100 #ifdef reg_EDI
 101     int saved_EDI;
 102 #endif
 103 #ifdef __sparc__
 104     int saved_i7, tmp_T0;
 105 #endif
 106     int code_gen_size, ret, interrupt_request;
 107     void (*gen_func)(void);
 108     TranslationBlock *tb, **ptb;
 109     target_ulong cs_base, pc;
 110     uint8_t *tc_ptr;
 111     unsigned int flags;
 112
 113     /* first we save global registers */
 114     saved_env = env;
 115     env = env1;
 116     saved_T0 = T0;
 117     saved_T1 = T1;
 118     saved_T2 = T2;
 119 #ifdef __sparc__
 120     /* we also save i7 because longjmp may not restore it */
 121     asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
 122 #endif
 123
 124 #if defined(TARGET_I386)
 125 #ifdef reg_EAX
 126     saved_EAX = EAX;
 127 #endif
 128 #ifdef reg_ECX
 129     saved_ECX = ECX;
 130 #endif
 131 #ifdef reg_EDX
 132     saved_EDX = EDX;
 133 #endif
 134 #ifdef reg_EBX
 135     saved_EBX = EBX;
 136 #endif
 137 #ifdef reg_ESP
 138     saved_ESP = ESP;
 139 #endif
 140 #ifdef reg_EBP
 141     saved_EBP = EBP;
 142 #endif
 143 #ifdef reg_ESI
 144     saved_ESI = ESI;
 145 #endif
 146 #ifdef reg_EDI
 147     saved_EDI = EDI;
 148 #endif
 149
 150     env_to_regs();
 151     /* put eflags in CPU temporary format */
 152     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 153     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 154     CC_OP = CC_OP_EFLAGS;
 155     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 156 #elif defined(TARGET_ARM)
 157     {
 158         unsigned int psr;
 159         psr = env->cpsr;
 160         env->CF = (psr >> 29) & 1;
 161         env->NZF = (psr & 0xc0000000) ^ 0x40000000;
 162         env->VF = (psr << 3) & 0x80000000;
 163         env->QF = (psr >> 27) & 1;
 164         env->cpsr = psr & ~CACHED_CPSR_BITS;
 165     }
 166 #elif defined(TARGET_SPARC)
 167 #elif defined(TARGET_PPC)
 168 #else
 169 #error unsupported target CPU
 170 #endif
 171     env->exception_index = -1;
 172
 173     /* prepare setjmp context for exception handling */
 174     for(;;) {
 175         if (setjmp(env->jmp_env) == 0) {
 176             env->current_tb = NULL;
 177             /* if an exception is pending, we execute it here */
 178             if (env->exception_index >= 0) {
 179                 if (env->exception_index >= EXCP_INTERRUPT) {
 180                     /* exit request from the cpu execution loop */
 181                     ret = env->exception_index;
 182                     break;
 183                 } else if (env->user_mode_only) {
 184                     /* if user mode only, we simulate a fake exception
 185                        which will be hanlded outside the cpu execution
 186                        loop */
 187 #if defined(TARGET_I386)
 188                     do_interrupt_user(env->exception_index,
 189                                       env->exception_is_int,
 190                                       env->error_code,
 191                                       env->exception_next_eip);
 192 #endif
 193                     ret = env->exception_index;
 194                     break;
 195                 } else {
 196 #if defined(TARGET_I386)
 197                     /* simulate a real cpu exception. On i386, it can
 198                        trigger new exceptions, but we do not handle
 199                        double or triple faults yet. */
 200                     do_interrupt(env->exception_index,
 201                                  env->exception_is_int,
 202                                  env->error_code,
 203                                  env->exception_next_eip, 0);
 204 #elif defined(TARGET_PPC)
 205                     do_interrupt(env);
 206 #elif defined(TARGET_SPARC)
 207                     do_interrupt(env->exception_index);
 208 #endif
 209                 }
 210                 env->exception_index = -1;
 211             }
 212 #ifdef USE_KQEMU
 213             if (kqemu_is_ok(env) && env->interrupt_request == 0) {
 214                 int ret;
 215                 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 216                 ret = kqemu_cpu_exec(env);
 217                 /* put eflags in CPU temporary format */
 218                 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 219                 DF = 1 - (2 * ((env->eflags >> 10) & 1));
 220                 CC_OP = CC_OP_EFLAGS;
 221                 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 222                 if (ret == 1) {
 223                     /* exception */
 224                     longjmp(env->jmp_env, 1);
 225                 } else if (ret == 2) {
 226                     /* softmmu execution needed */
 227                 } else {
 228                     if (env->interrupt_request != 0) {
 229                         /* hardware interrupt will be executed just after */
 230                     } else {
 231                         /* otherwise, we restart */
 232                         longjmp(env->jmp_env, 1);
 233                     }
 234                 }
 235             }
 236 #endif
 237
 238             T0 = 0; /* force lookup of first TB */
 239             for(;;) {
 240 #ifdef __sparc__
 241                 /* g1 can be modified by some libc? functions */
 242                 tmp_T0 = T0;
 243 #endif
 244                 interrupt_request = env->interrupt_request;
 245                 if (__builtin_expect(interrupt_request, 0)) {
 246 #if defined(TARGET_I386)
 247                     /* if hardware interrupt pending, we execute it */
 248                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 249                         (env->eflags & IF_MASK) &&
 250                         !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 251                         int intno;
 252                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 253                         intno = cpu_get_pic_interrupt(env);
 254                         if (loglevel & CPU_LOG_TB_IN_ASM) {
 255                             fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
 256                         }
 257                         do_interrupt(intno, 0, 0, 0, 1);
 258                         /* ensure that no TB jump will be modified as
 259                            the program flow was changed */
 260 #ifdef __sparc__
 261                         tmp_T0 = 0;
 262 #else
 263                         T0 = 0;
 264 #endif
 265                     }
 266 #elif defined(TARGET_PPC)
 267 #if 0
 268                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
 269                         cpu_ppc_reset(env);
 270                     }
 271 #endif
 272                     if (msr_ee != 0) {
 273                     if ((interrupt_request & CPU_INTERRUPT_HARD)) {
 274                             /* Raise it */
 275                             env->exception_index = EXCP_EXTERNAL;
 276                             env->error_code = 0;
 277                             do_interrupt(env);
 278                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 279                         } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
 280                             /* Raise it */
 281                             env->exception_index = EXCP_DECR;
 282                             env->error_code = 0;
 283                             do_interrupt(env);
 284                             env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 285                         }
 286                     }
 287 #elif defined(TARGET_SPARC)
 288                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 289                         (env->psret != 0)) {
 290                         int pil = env->interrupt_index & 15;
 291                         int type = env->interrupt_index & 0xf0;
 292
 293                         if (((type == TT_EXTINT) &&
 294                              (pil == 15 || pil > env->psrpil)) ||
 295                             type != TT_EXTINT) {
 296                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 297                             do_interrupt(env->interrupt_index);
 298                             env->interrupt_index = 0;
 299                         }
 300                     } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
 301                         //do_interrupt(0, 0, 0, 0, 0);
 302                         env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 303                     }
 304 #endif
 305                     if (interrupt_request & CPU_INTERRUPT_EXITTB) {
 306                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 307                         /* ensure that no TB jump will be modified as
 308                            the program flow was changed */
 309 #ifdef __sparc__
 310                         tmp_T0 = 0;
 311 #else
 312                         T0 = 0;
 313 #endif
 314                     }
 315                     if (interrupt_request & CPU_INTERRUPT_EXIT) {
 316                         env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
 317                         env->exception_index = EXCP_INTERRUPT;
 318                         cpu_loop_exit();
 319                     }
 320                 }
 321 #ifdef DEBUG_EXEC
 322                 if ((loglevel & CPU_LOG_EXEC)) {
 323 #if defined(TARGET_I386)
 324                     /* restore flags in standard format */
 325                     env->regs[R_EAX] = EAX;
 326                     env->regs[R_EBX] = EBX;
 327                     env->regs[R_ECX] = ECX;
 328                     env->regs[R_EDX] = EDX;
 329                     env->regs[R_ESI] = ESI;
 330                     env->regs[R_EDI] = EDI;
 331                     env->regs[R_EBP] = EBP;
 332                     env->regs[R_ESP] = ESP;
 333                     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 334                     cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
 335                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 336 #elif defined(TARGET_ARM)
 337                     env->cpsr = compute_cpsr();
 338                     cpu_dump_state(env, logfile, fprintf, 0);
 339                     env->cpsr &= ~CACHED_CPSR_BITS;
 340 #elif defined(TARGET_SPARC)
 341                     cpu_dump_state (env, logfile, fprintf, 0);
 342 #elif defined(TARGET_PPC)
 343                     cpu_dump_state(env, logfile, fprintf, 0);
 344 #else
 345 #error unsupported target CPU
 346 #endif
 347                 }
 348 #endif
 349                 /* we record a subset of the CPU state. It will
 350                    always be the same before a given translated block
 351                    is executed. */
 352 #if defined(TARGET_I386)
 353                 flags = env->hflags;
 354                 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
 355                 cs_base = env->segs[R_CS].base;
 356                 pc = cs_base + env->eip;
 357 #elif defined(TARGET_ARM)
 358                 flags = env->thumb | (env->vfp.vec_len << 1)
 359                         | (env->vfp.vec_stride << 4);
 360                 cs_base = 0;
 361                 pc = env->regs[15];
 362 #elif defined(TARGET_SPARC)
 363                 flags = 0;
 364                 cs_base = env->npc;
 365                 pc = env->pc;
 366 #elif defined(TARGET_PPC)
 367                 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | (msr_se << MSR_SE);
 368                 cs_base = 0;
 369                 pc = env->nip;
 370 #else
 371 #error unsupported CPU
 372 #endif
 373                 tb = tb_find(&ptb, pc, cs_base,
 374                              flags);
 375                 if (!tb) {
 376                     TranslationBlock **ptb1;
 377                     unsigned int h;
 378                     target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
 379
 380
 381                     spin_lock(&tb_lock);
 382
 383                     tb_invalidated_flag = 0;
 384
 385                     regs_to_env(); /* XXX: do it just before cpu_gen_code() */
 386
 387                     /* find translated block using physical mappings */
 388                     phys_pc = get_phys_addr_code(env, pc);
 389                     phys_page1 = phys_pc & TARGET_PAGE_MASK;
 390                     phys_page2 = -1;
 391                     h = tb_phys_hash_func(phys_pc);
 392                     ptb1 = &tb_phys_hash[h];
 393                     for(;;) {
 394                         tb = *ptb1;
 395                         if (!tb)
 396                             goto not_found;
 397                         if (tb->pc == pc &&
 398                             tb->page_addr[0] == phys_page1 &&
 399                             tb->cs_base == cs_base &&
 400                             tb->flags == flags) {
 401                             /* check next page if needed */
 402                             if (tb->page_addr[1] != -1) {
 403                                 virt_page2 = (pc & TARGET_PAGE_MASK) +
 404                                     TARGET_PAGE_SIZE;
 405                                 phys_page2 = get_phys_addr_code(env, virt_page2);
 406                                 if (tb->page_addr[1] == phys_page2)
 407                                     goto found;
 408                             } else {
 409                                 goto found;
 410                             }
 411                         }
 412                         ptb1 = &tb->phys_hash_next;
 413                     }
 414                 not_found:
 415                     /* if no translated code available, then translate it now */
 416                     tb = tb_alloc(pc);
 417                     if (!tb) {
 418                         /* flush must be done */
 419                         tb_flush(env);
 420                         /* cannot fail at this point */
 421                         tb = tb_alloc(pc);
 422                         /* don't forget to invalidate previous TB info */
 423                         ptb = &tb_hash[tb_hash_func(pc)];
 424                         T0 = 0;
 425                     }
 426                     tc_ptr = code_gen_ptr;
 427                     tb->tc_ptr = tc_ptr;
 428                     tb->cs_base = cs_base;
 429                     tb->flags = flags;
 430                     cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
 431                     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
 432
 433                     /* check next page if needed */
 434                     virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
 435                     phys_page2 = -1;
 436                     if ((pc & TARGET_PAGE_MASK) != virt_page2) {
 437                         phys_page2 = get_phys_addr_code(env, virt_page2);
 438                     }
 439                     tb_link_phys(tb, phys_pc, phys_page2);
 440
 441                 found:
 442                     if (tb_invalidated_flag) {
 443                         /* as some TB could have been invalidated because
 444                            of memory exceptions while generating the code, we
 445                            must recompute the hash index here */
 446                         ptb = &tb_hash[tb_hash_func(pc)];
 447                         while (*ptb != NULL)
 448                             ptb = &(*ptb)->hash_next;
 449                         T0 = 0;
 450                     }
 451                     /* we add the TB in the virtual pc hash table */
 452                     *ptb = tb;
 453                     tb->hash_next = NULL;
 454                     tb_link(tb);
 455                     spin_unlock(&tb_lock);
 456                 }
 457 #ifdef DEBUG_EXEC
 458                 if ((loglevel & CPU_LOG_EXEC)) {
 459                     fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
 460                             (long)tb->tc_ptr, tb->pc,
 461                             lookup_symbol(tb->pc));
 462                 }
 463 #endif
 464 #ifdef __sparc__
 465                 T0 = tmp_T0;
 466 #endif
 467                 /* see if we can patch the calling TB. */
 468                 {
 469                     if (T0 != 0
 470 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
 471                     && (tb->cflags & CF_CODE_COPY) ==
 472                     (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
 473 #endif
 474                     ) {
 475                     spin_lock(&tb_lock);
 476                     tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
 477 #if defined(USE_CODE_COPY)
 478                     /* propagates the FP use info */
 479                     ((TranslationBlock *)(T0 & ~3))->cflags |=
 480                         (tb->cflags & CF_FP_USED);
 481 #endif
 482                     spin_unlock(&tb_lock);
 483                 }
 484                 }
 485                 tc_ptr = tb->tc_ptr;
 486                 env->current_tb = tb;
 487                 /* execute the generated code */
 488                 gen_func = (void *)tc_ptr;
 489 #if defined(__sparc__)
 490                 __asm__ __volatile__("call      %0\n\t"
 491                                      "mov       %%o7,%%i0"
 492                                      : /* no outputs */
 493                                      : "r" (gen_func)
 494                                      : "i0", "i1", "i2", "i3", "i4", "i5");
 495 #elif defined(__arm__)
 496                 asm volatile ("mov pc, %0\n\t"
 497                               ".global exec_loop\n\t"
 498                               "exec_loop:\n\t"
 499                               : /* no outputs */
 500                               : "r" (gen_func)
 501                               : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
 502 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
 503 {
 504     if (!(tb->cflags & CF_CODE_COPY)) {
 505         if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
 506             save_native_fp_state(env);
 507         }
 508         gen_func();
 509     } else {
 510         if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
 511             restore_native_fp_state(env);
 512         }
 513         /* we work with native eflags */
 514         CC_SRC = cc_table[CC_OP].compute_all();
 515         CC_OP = CC_OP_EFLAGS;
 516         asm(".globl exec_loop\n"
 517             "\n"
 518             "debug1:\n"
 519             "    pushl %%ebp\n"
 520             "    fs movl %10, %9\n"
 521             "    fs movl %11, %%eax\n"
 522             "    andl $0x400, %%eax\n"
 523             "    fs orl %8, %%eax\n"
 524             "    pushl %%eax\n"
 525             "    popf\n"
 526             "    fs movl %%esp, %12\n"
 527             "    fs movl %0, %%eax\n"
 528             "    fs movl %1, %%ecx\n"
 529             "    fs movl %2, %%edx\n"
 530             "    fs movl %3, %%ebx\n"
 531             "    fs movl %4, %%esp\n"
 532             "    fs movl %5, %%ebp\n"
 533             "    fs movl %6, %%esi\n"
 534             "    fs movl %7, %%edi\n"
 535             "    fs jmp *%9\n"
 536             "exec_loop:\n"
 537             "    fs movl %%esp, %4\n"
 538             "    fs movl %12, %%esp\n"
 539             "    fs movl %%eax, %0\n"
 540             "    fs movl %%ecx, %1\n"
 541             "    fs movl %%edx, %2\n"
 542             "    fs movl %%ebx, %3\n"
 543             "    fs movl %%ebp, %5\n"
 544             "    fs movl %%esi, %6\n"
 545             "    fs movl %%edi, %7\n"
 546             "    pushf\n"
 547             "    popl %%eax\n"
 548             "    movl %%eax, %%ecx\n"
 549             "    andl $0x400, %%ecx\n"
 550             "    shrl $9, %%ecx\n"
 551             "    andl $0x8d5, %%eax\n"
 552             "    fs movl %%eax, %8\n"
 553             "    movl $1, %%eax\n"
 554             "    subl %%ecx, %%eax\n"
 555             "    fs movl %%eax, %11\n"
 556             "    fs movl %9, %%ebx\n" /* get T0 value */
 557             "    popl %%ebp\n"
 558             :
 559             : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
 560             "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
 561             "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
 562             "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
 563             "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
 564             "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
 565             "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
 566             "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
 567             "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
 568             "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
 569             "a" (gen_func),
 570             "m" (*(uint8_t *)offsetof(CPUState, df)),
 571             "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
 572             : "%ecx", "%edx"
 573             );
 574     }
 575 }
 576 #elif defined(__ia64)
 577                 struct fptr {
 578                         void *ip;
 579                         void *gp;
 580                 } fp;
 581
 582                 fp.ip = tc_ptr;
 583                 fp.gp = code_gen_buffer + 2 * (1 << 20);
 584                 (*(void (*)(void)) &fp)();
 585 #else
 586                 gen_func();
 587 #endif
 588                 env->current_tb = NULL;
 589                 /* reset soft MMU for next block (it can currently
 590                    only be set by a memory fault) */
 591 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
 592                 if (env->hflags & HF_SOFTMMU_MASK) {
 593                     env->hflags &= ~HF_SOFTMMU_MASK;
 594                     /* do not allow linking to another block */
 595                     T0 = 0;
 596                 }
 597 #endif
 598             }
 599         } else {
 600             env_to_regs();
 601         }
 602     } /* for(;;) */
 603
 604
 605 #if defined(TARGET_I386)
 606 #if defined(USE_CODE_COPY)
 607     if (env->native_fp_regs) {
 608         save_native_fp_state(env);
 609     }
 610 #endif
 611     /* restore flags in standard format */
 612     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 613
 614     /* restore global registers */
 615 #ifdef reg_EAX
 616     EAX = saved_EAX;
 617 #endif
 618 #ifdef reg_ECX
 619     ECX = saved_ECX;
 620 #endif
 621 #ifdef reg_EDX
 622     EDX = saved_EDX;
 623 #endif
 624 #ifdef reg_EBX
 625     EBX = saved_EBX;
 626 #endif
 627 #ifdef reg_ESP
 628     ESP = saved_ESP;
 629 #endif
 630 #ifdef reg_EBP
 631     EBP = saved_EBP;
 632 #endif
 633 #ifdef reg_ESI
 634     ESI = saved_ESI;
 635 #endif
 636 #ifdef reg_EDI
 637     EDI = saved_EDI;
 638 #endif
 639 #elif defined(TARGET_ARM)
 640     env->cpsr = compute_cpsr();
 641     /* XXX: Save/restore host fpu exception state?.  */
 642 #elif defined(TARGET_SPARC)
 643 #elif defined(TARGET_PPC)
 644 #else
 645 #error unsupported target CPU
 646 #endif
 647 #ifdef __sparc__
 648     asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
 649 #endif
 650     T0 = saved_T0;
 651     T1 = saved_T1;
 652     T2 = saved_T2;
 653     env = saved_env;
 654     return ret;
 655 }
 656
 657 /* must only be called from the generated code as an exception can be
 658    generated */
 659 void tb_invalidate_page_range(target_ulong start, target_ulong end)
 660 {
 661     /* XXX: cannot enable it yet because it yields to MMU exception
 662        where NIP != read address on PowerPC */
 663 #if 0
 664     target_ulong phys_addr;
 665     phys_addr = get_phys_addr_code(env, start);
 666     tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
 667 #endif
 668 }
 669
 670 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
 671
 672 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 673 {
 674     CPUX86State *saved_env;
 675
 676     saved_env = env;
 677     env = s;
 678     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 679         selector &= 0xffff;
 680         cpu_x86_load_seg_cache(env, seg_reg, selector,
 681                                (selector << 4), 0xffff, 0);
 682     } else {
 683         load_seg(seg_reg, selector);
 684     }
 685     env = saved_env;
 686 }
 687
 688 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
 689 {
 690     CPUX86State *saved_env;
 691
 692     saved_env = env;
 693     env = s;
 694
 695     helper_fsave((target_ulong)ptr, data32);
 696
 697     env = saved_env;
 698 }
 699
 700 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
 701 {
 702     CPUX86State *saved_env;
 703
 704     saved_env = env;
 705     env = s;
 706
 707     helper_frstor((target_ulong)ptr, data32);
 708
 709     env = saved_env;
 710 }
 711
 712 #endif /* TARGET_I386 */
 713
 714 #if !defined(CONFIG_SOFTMMU)
 715
 716 #if defined(TARGET_I386)
 717
 718 /* 'pc' is the host PC at which the exception was raised. 'address' is
 719    the effective address of the memory exception. 'is_write' is 1 if a
 720    write caused the exception and otherwise 0'. 'old_set' is the
 721    signal set which should be restored */
 722 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 723                                     int is_write, sigset_t *old_set,
 724                                     void *puc)
 725 {
 726     TranslationBlock *tb;
 727     int ret;
 728
 729     if (cpu_single_env)
 730         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 731 #if defined(DEBUG_SIGNAL)
 732     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 733                 pc, address, is_write, *(unsigned long *)old_set);
 734 #endif
 735     /* XXX: locking issue */
 736     if (is_write && page_unprotect(address, pc, puc)) {
 737         return 1;
 738     }
 739
 740     /* see if it is an MMU fault */
 741     ret = cpu_x86_handle_mmu_fault(env, address, is_write,
 742                                    ((env->hflags & HF_CPL_MASK) == 3), 0);
 743     if (ret < 0)
 744         return 0; /* not an MMU fault */
 745     if (ret == 0)
 746         return 1; /* the MMU fault was handled without causing real CPU fault */
 747     /* now we have a real cpu fault */
 748     tb = tb_find_pc(pc);
 749     if (tb) {
 750         /* the PC is inside the translated code. It means that we have
 751            a virtual CPU fault */
 752         cpu_restore_state(tb, env, pc, puc);
 753     }
 754     if (ret == 1) {
 755 #if 0
 756         printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 757                env->eip, env->cr[2], env->error_code);
 758 #endif
 759         /* we restore the process signal mask as the sigreturn should
 760            do it (XXX: use sigsetjmp) */
 761         sigprocmask(SIG_SETMASK, old_set, NULL);
 762         raise_exception_err(EXCP0E_PAGE, env->error_code);
 763     } else {
 764         /* activate soft MMU for this block */
 765         env->hflags |= HF_SOFTMMU_MASK;
 766         cpu_resume_from_signal(env, puc);
 767     }
 768     /* never comes here */
 769     return 1;
 770 }
 771
 772 #elif defined(TARGET_ARM)
 773 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 774                                     int is_write, sigset_t *old_set,
 775                                     void *puc)
 776 {
 777     TranslationBlock *tb;
 778     int ret;
 779
 780     if (cpu_single_env)
 781         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 782 #if defined(DEBUG_SIGNAL)
 783     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 784            pc, address, is_write, *(unsigned long *)old_set);
 785 #endif
 786     /* XXX: locking issue */
 787     if (is_write && page_unprotect(address, pc, puc)) {
 788         return 1;
 789     }
 790     /* see if it is an MMU fault */
 791     ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
 792     if (ret < 0)
 793         return 0; /* not an MMU fault */
 794     if (ret == 0)
 795         return 1; /* the MMU fault was handled without causing real CPU fault */
 796     /* now we have a real cpu fault */
 797     tb = tb_find_pc(pc);
 798     if (tb) {
 799         /* the PC is inside the translated code. It means that we have
 800            a virtual CPU fault */
 801         cpu_restore_state(tb, env, pc, puc);
 802     }
 803     /* we restore the process signal mask as the sigreturn should
 804        do it (XXX: use sigsetjmp) */
 805     sigprocmask(SIG_SETMASK, old_set, NULL);
 806     cpu_loop_exit();
 807 }
 808 #elif defined(TARGET_SPARC)
 809 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 810                                     int is_write, sigset_t *old_set,
 811                                     void *puc)
 812 {
 813     TranslationBlock *tb;
 814     int ret;
 815
 816     if (cpu_single_env)
 817         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 818 #if defined(DEBUG_SIGNAL)
 819     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 820            pc, address, is_write, *(unsigned long *)old_set);
 821 #endif
 822     /* XXX: locking issue */
 823     if (is_write && page_unprotect(address, pc, puc)) {
 824         return 1;
 825     }
 826     /* see if it is an MMU fault */
 827     ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
 828     if (ret < 0)
 829         return 0; /* not an MMU fault */
 830     if (ret == 0)
 831         return 1; /* the MMU fault was handled without causing real CPU fault */
 832     /* now we have a real cpu fault */
 833     tb = tb_find_pc(pc);
 834     if (tb) {
 835         /* the PC is inside the translated code. It means that we have
 836            a virtual CPU fault */
 837         cpu_restore_state(tb, env, pc, puc);
 838     }
 839     /* we restore the process signal mask as the sigreturn should
 840        do it (XXX: use sigsetjmp) */
 841     sigprocmask(SIG_SETMASK, old_set, NULL);
 842     cpu_loop_exit();
 843 }
 844 #elif defined (TARGET_PPC)
 845 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 846                                     int is_write, sigset_t *old_set,
 847                                     void *puc)
 848 {
 849     TranslationBlock *tb;
 850     int ret;
 851
 852     if (cpu_single_env)
 853         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 854 #if defined(DEBUG_SIGNAL)
 855     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 856            pc, address, is_write, *(unsigned long *)old_set);
 857 #endif
 858     /* XXX: locking issue */
 859     if (is_write && page_unprotect(address, pc, puc)) {
 860         return 1;
 861     }
 862
 863     /* see if it is an MMU fault */
 864     ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
 865     if (ret < 0)
 866         return 0; /* not an MMU fault */
 867     if (ret == 0)
 868         return 1; /* the MMU fault was handled without causing real CPU fault */
 869
 870     /* now we have a real cpu fault */
 871     tb = tb_find_pc(pc);
 872     if (tb) {
 873         /* the PC is inside the translated code. It means that we have
 874            a virtual CPU fault */
 875         cpu_restore_state(tb, env, pc, puc);
 876     }
 877     if (ret == 1) {
 878 #if 0
 879         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
 880                env->nip, env->error_code, tb);
 881 #endif
 882     /* we restore the process signal mask as the sigreturn should
 883        do it (XXX: use sigsetjmp) */
 884         sigprocmask(SIG_SETMASK, old_set, NULL);
 885         do_raise_exception_err(env->exception_index, env->error_code);
 886     } else {
 887         /* activate soft MMU for this block */
 888         cpu_resume_from_signal(env, puc);
 889     }
 890     /* never comes here */
 891     return 1;
 892 }
 893 #else
 894 #error unsupported target CPU
 895 #endif
 896
 897 #if defined(__i386__)
 898
 899 #if defined(USE_CODE_COPY)
 900 static void cpu_send_trap(unsigned long pc, int trap,
 901                           struct ucontext *uc)
 902 {
 903     TranslationBlock *tb;
 904
 905     if (cpu_single_env)
 906         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 907     /* now we have a real cpu fault */
 908     tb = tb_find_pc(pc);
 909     if (tb) {
 910         /* the PC is inside the translated code. It means that we have
 911            a virtual CPU fault */
 912         cpu_restore_state(tb, env, pc, uc);
 913     }
 914     sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
 915     raise_exception_err(trap, env->error_code);
 916 }
 917 #endif
 918
 919 int cpu_signal_handler(int host_signum, struct siginfo *info,
 920                        void *puc)
 921 {
 922     struct ucontext *uc = puc;
 923     unsigned long pc;
 924     int trapno;
 925
 926 #ifndef REG_EIP
 927 /* for glibc 2.1 */
 928 #define REG_EIP    EIP
 929 #define REG_ERR    ERR
 930 #define REG_TRAPNO TRAPNO
 931 #endif
 932     pc = uc->uc_mcontext.gregs[REG_EIP];
 933     trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
 934 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
 935     if (trapno == 0x00 || trapno == 0x05) {
 936         /* send division by zero or bound exception */
 937         cpu_send_trap(pc, trapno, uc);
 938         return 1;
 939     } else
 940 #endif
 941         return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 942                                  trapno == 0xe ?
 943                                  (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 944                                  &uc->uc_sigmask, puc);
 945 }
 946
 947 #elif defined(__x86_64__)
 948
 949 int cpu_signal_handler(int host_signum, struct siginfo *info,
 950                        void *puc)
 951 {
 952     struct ucontext *uc = puc;
 953     unsigned long pc;
 954
 955     pc = uc->uc_mcontext.gregs[REG_RIP];
 956     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 957                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
 958                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 959                              &uc->uc_sigmask, puc);
 960 }
 961
 962 #elif defined(__powerpc__)
 963
 964 /***********************************************************************
 965  * signal context platform-specific definitions
 966  * From Wine
 967  */
 968 #ifdef linux
 969 /* All Registers access - only for local access */
 970 # define REG_sig(reg_name, context)             ((context)->uc_mcontext.regs->reg_name)
 971 /* Gpr Registers access  */
 972 # define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 973 # define IAR_sig(context)                       REG_sig(nip, context)   /* Program counter */
 974 # define MSR_sig(context)                       REG_sig(msr, context)   /* Machine State Register (Supervisor) */
 975 # define CTR_sig(context)                       REG_sig(ctr, context)   /* Count register */
 976 # define XER_sig(context)                       REG_sig(xer, context) /* User's integer exception register */
 977 # define LR_sig(context)                        REG_sig(link, context) /* Link register */
 978 # define CR_sig(context)                        REG_sig(ccr, context) /* Condition register */
 979 /* Float Registers access  */
 980 # define FLOAT_sig(reg_num, context)            (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
 981 # define FPSCR_sig(context)                     (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
 982 /* Exception Registers access */
 983 # define DAR_sig(context)                       REG_sig(dar, context)
 984 # define DSISR_sig(context)                     REG_sig(dsisr, context)
 985 # define TRAP_sig(context)                      REG_sig(trap, context)
 986 #endif /* linux */
 987
 988 #ifdef __APPLE__
 989 # include <sys/ucontext.h>
 990 typedef struct ucontext SIGCONTEXT;
 991 /* All Registers access - only for local access */
 992 # define REG_sig(reg_name, context)             ((context)->uc_mcontext->ss.reg_name)
 993 # define FLOATREG_sig(reg_name, context)        ((context)->uc_mcontext->fs.reg_name)
 994 # define EXCEPREG_sig(reg_name, context)        ((context)->uc_mcontext->es.reg_name)
 995 # define VECREG_sig(reg_name, context)          ((context)->uc_mcontext->vs.reg_name)
 996 /* Gpr Registers access */
 997 # define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
 998 # define IAR_sig(context)                       REG_sig(srr0, context)  /* Program counter */
 999 # define MSR_sig(context)                       REG_sig(srr1, context)  /* Machine State Register (Supervisor) */
1000 # define CTR_sig(context)                       REG_sig(ctr, context)
1001 # define XER_sig(context)                       REG_sig(xer, context) /* Link register */
1002 # define LR_sig(context)                        REG_sig(lr, context)  /* User's integer exception register */
1003 # define CR_sig(context)                        REG_sig(cr, context)  /* Condition register */
1004 /* Float Registers access */
1005 # define FLOAT_sig(reg_num, context)            FLOATREG_sig(fpregs[reg_num], context)
1006 # define FPSCR_sig(context)                     ((double)FLOATREG_sig(fpscr, context))
1007 /* Exception Registers access */
1008 # define DAR_sig(context)                       EXCEPREG_sig(dar, context)     /* Fault registers for coredump */
1009 # define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
1010 # define TRAP_sig(context)                      EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1011 #endif /* __APPLE__ */
1012
1013 int cpu_signal_handler(int host_signum, struct siginfo *info,
1014                        void *puc)
1015 {
1016     struct ucontext *uc = puc;
1017     unsigned long pc;
1018     int is_write;
1019
1020     pc = IAR_sig(uc);
1021     is_write = 0;
1022 #if 0
1023     /* ppc 4xx case */
1024     if (DSISR_sig(uc) & 0x00800000)
1025         is_write = 1;
1026 #else
1027     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1028         is_write = 1;
1029 #endif
1030     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1031                              is_write, &uc->uc_sigmask, puc);
1032 }
1033
1034 #elif defined(__alpha__)
1035
1036 int cpu_signal_handler(int host_signum, struct siginfo *info,
1037                            void *puc)
1038 {
1039     struct ucontext *uc = puc;
1040     uint32_t *pc = uc->uc_mcontext.sc_pc;
1041     uint32_t insn = *pc;
1042     int is_write = 0;
1043
1044     /* XXX: need kernel patch to get write flag faster */
1045     switch (insn >> 26) {
1046     case 0x0d: // stw
1047     case 0x0e: // stb
1048     case 0x0f: // stq_u
1049     case 0x24: // stf
1050     case 0x25: // stg
1051     case 0x26: // sts
1052     case 0x27: // stt
1053     case 0x2c: // stl
1054     case 0x2d: // stq
1055     case 0x2e: // stl_c
1056     case 0x2f: // stq_c
1057         is_write = 1;
1058     }
1059
1060     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1061                              is_write, &uc->uc_sigmask, puc);
1062 }
1063 #elif defined(__sparc__)
1064
1065 int cpu_signal_handler(int host_signum, struct siginfo *info,
1066                        void *puc)
1067 {
1068     uint32_t *regs = (uint32_t *)(info + 1);
1069     void *sigmask = (regs + 20);
1070     unsigned long pc;
1071     int is_write;
1072     uint32_t insn;
1073
1074     /* XXX: is there a standard glibc define ? */
1075     pc = regs[1];
1076     /* XXX: need kernel patch to get write flag faster */
1077     is_write = 0;
1078     insn = *(uint32_t *)pc;
1079     if ((insn >> 30) == 3) {
1080       switch((insn >> 19) & 0x3f) {
1081       case 0x05: // stb
1082       case 0x06: // sth
1083       case 0x04: // st
1084       case 0x07: // std
1085       case 0x24: // stf
1086       case 0x27: // stdf
1087       case 0x25: // stfsr
1088         is_write = 1;
1089         break;
1090       }
1091     }
1092     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1093                              is_write, sigmask, NULL);
1094 }
1095
1096 #elif defined(__arm__)
1097
1098 int cpu_signal_handler(int host_signum, struct siginfo *info,
1099                        void *puc)
1100 {
1101     struct ucontext *uc = puc;
1102     unsigned long pc;
1103     int is_write;
1104
1105     pc = uc->uc_mcontext.gregs[R15];
1106     /* XXX: compute is_write */
1107     is_write = 0;
1108     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1109                              is_write,
1110                              &uc->uc_sigmask);
1111 }
1112
1113 #elif defined(__mc68000)
1114
1115 int cpu_signal_handler(int host_signum, struct siginfo *info,
1116                        void *puc)
1117 {
1118     struct ucontext *uc = puc;
1119     unsigned long pc;
1120     int is_write;
1121
1122     pc = uc->uc_mcontext.gregs[16];
1123     /* XXX: compute is_write */
1124     is_write = 0;
1125     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1126                              is_write,
1127                              &uc->uc_sigmask, puc);
1128 }
1129
1130 #elif defined(__ia64)
1131
1132 #ifndef __ISR_VALID
1133   /* This ought to be in <bits/siginfo.h>... */
1134 # define __ISR_VALID    1
1135 # define si_flags       _sifields._sigfault._si_pad0
1136 #endif
1137
1138 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1139 {
1140     struct ucontext *uc = puc;
1141     unsigned long ip;
1142     int is_write = 0;
1143
1144     ip = uc->uc_mcontext.sc_ip;
1145     switch (host_signum) {
1146       case SIGILL:
1147       case SIGFPE:
1148       case SIGSEGV:
1149       case SIGBUS:
1150       case SIGTRAP:
1151           if (info->si_code && (info->si_flags & __ISR_VALID))
1152               /* ISR.W (write-access) is bit 33:  */
1153               is_write = (info->si_isr >> 33) & 1;
1154           break;
1155
1156       default:
1157           break;
1158     }
1159     return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1160                              is_write,
1161                              &uc->uc_sigmask, puc);
1162 }
1163
1164 #else
1165
1166 #error host CPU specific signal handler needed
1167
1168 #endif
1169
1170 #endif /* !defined(CONFIG_SOFTMMU) */