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[qemu/qemu_0_9_1_stable.git] / alpha-dis.c
blobe7a4fb4029e81a7c7864ee7fbe929b746fee511a
1 /* alpha-dis.c -- Disassemble Alpha AXP instructions
2 Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Richard Henderson <rth@tamu.edu>,
4 patterned after the PPC opcode handling written by Ian Lance Taylor.
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include <stdio.h>
24 #include "dis-asm.h"
25
26 #define ATTRIBUTE_UNUSED __attribute__((unused))
27 #define _(x) x
28
29 /* The opcode table is an array of struct alpha_opcode. */
30
31 struct alpha_opcode
32 {
33 /* The opcode name. */
34 const char *name;
35
36 /* The opcode itself. Those bits which will be filled in with
37 operands are zeroes. */
38 unsigned opcode;
39
40 /* The opcode mask. This is used by the disassembler. This is a
41 mask containing ones indicating those bits which must match the
42 opcode field, and zeroes indicating those bits which need not
43 match (and are presumably filled in by operands). */
44 unsigned mask;
45
46 /* One bit flags for the opcode. These are primarily used to
47 indicate specific processors and environments support the
48 instructions. The defined values are listed below. */
49 unsigned flags;
50
51 /* An array of operand codes. Each code is an index into the
52 operand table. They appear in the order which the operands must
53 appear in assembly code, and are terminated by a zero. */
54 unsigned char operands[4];
55 };
56
57 /* The table itself is sorted by major opcode number, and is otherwise
58 in the order in which the disassembler should consider
59 instructions. */
60 extern const struct alpha_opcode alpha_opcodes[];
61 extern const unsigned alpha_num_opcodes;
62
63 /* Values defined for the flags field of a struct alpha_opcode. */
64
65 /* CPU Availability */
66 #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
67 #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */
68 #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */
69 #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */
70 #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */
71 #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */
72 #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */
73
74 #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
75
76 /* A macro to extract the major opcode from an instruction. */
77 #define AXP_OP(i) (((i) >> 26) & 0x3F)
78
79 /* The total number of major opcodes. */
80 #define AXP_NOPS 0x40
81
82 \f
83 /* The operands table is an array of struct alpha_operand. */
84
85 struct alpha_operand
86 {
87 /* The number of bits in the operand. */
88 unsigned int bits : 5;
89
90 /* How far the operand is left shifted in the instruction. */
91 unsigned int shift : 5;
92
93 /* The default relocation type for this operand. */
94 signed int default_reloc : 16;
95
96 /* One bit syntax flags. */
97 unsigned int flags : 16;
98
99 /* Insertion function. This is used by the assembler. To insert an
100 operand value into an instruction, check this field.
101
102 If it is NULL, execute
103 i |= (op & ((1 << o->bits) - 1)) << o->shift;
104 (i is the instruction which we are filling in, o is a pointer to
105 this structure, and op is the opcode value; this assumes twos
106 complement arithmetic).
107
108 If this field is not NULL, then simply call it with the
109 instruction and the operand value. It will return the new value
110 of the instruction. If the ERRMSG argument is not NULL, then if
111 the operand value is illegal, *ERRMSG will be set to a warning
112 string (the operand will be inserted in any case). If the
113 operand value is legal, *ERRMSG will be unchanged (most operands
114 can accept any value). */
115 unsigned (*insert) PARAMS ((unsigned instruction, int op,
116 const char **errmsg));
117
118 /* Extraction function. This is used by the disassembler. To
119 extract this operand type from an instruction, check this field.
120
121 If it is NULL, compute
122 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
123 if ((o->flags & AXP_OPERAND_SIGNED) != 0
124 && (op & (1 << (o->bits - 1))) != 0)
125 op -= 1 << o->bits;
126 (i is the instruction, o is a pointer to this structure, and op
127 is the result; this assumes twos complement arithmetic).
128
129 If this field is not NULL, then simply call it with the
130 instruction value. It will return the value of the operand. If
131 the INVALID argument is not NULL, *INVALID will be set to
132 non-zero if this operand type can not actually be extracted from
133 this operand (i.e., the instruction does not match). If the
134 operand is valid, *INVALID will not be changed. */
135 int (*extract) PARAMS ((unsigned instruction, int *invalid));
136 };
137
138 /* Elements in the table are retrieved by indexing with values from
139 the operands field of the alpha_opcodes table. */
140
141 extern const struct alpha_operand alpha_operands[];
142 extern const unsigned alpha_num_operands;
143
144 /* Values defined for the flags field of a struct alpha_operand. */
145
146 /* Mask for selecting the type for typecheck purposes */
147 #define AXP_OPERAND_TYPECHECK_MASK \
148 (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \
149 AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \
150 AXP_OPERAND_UNSIGNED)
151
152 /* This operand does not actually exist in the assembler input. This
153 is used to support extended mnemonics, for which two operands fields
154 are identical. The assembler should call the insert function with
155 any op value. The disassembler should call the extract function,
156 ignore the return value, and check the value placed in the invalid
157 argument. */
158 #define AXP_OPERAND_FAKE 01
159
160 /* The operand should be wrapped in parentheses rather than separated
161 from the previous by a comma. This is used for the load and store
162 instructions which want their operands to look like "Ra,disp(Rb)". */
163 #define AXP_OPERAND_PARENS 02
164
165 /* Used in combination with PARENS, this supresses the supression of
166 the comma. This is used for "jmp Ra,(Rb),hint". */
167 #define AXP_OPERAND_COMMA 04
168
169 /* This operand names an integer register. */
170 #define AXP_OPERAND_IR 010
171
172 /* This operand names a floating point register. */
173 #define AXP_OPERAND_FPR 020
174
175 /* This operand is a relative branch displacement. The disassembler
176 prints these symbolically if possible. */
177 #define AXP_OPERAND_RELATIVE 040
178
179 /* This operand takes signed values. */
180 #define AXP_OPERAND_SIGNED 0100
181
182 /* This operand takes unsigned values. This exists primarily so that
183 a flags value of 0 can be treated as end-of-arguments. */
184 #define AXP_OPERAND_UNSIGNED 0200
185
186 /* Supress overflow detection on this field. This is used for hints. */
187 #define AXP_OPERAND_NOOVERFLOW 0400
188
189 /* Mask for optional argument default value. */
190 #define AXP_OPERAND_OPTIONAL_MASK 07000
191
192 /* This operand defaults to zero. This is used for jump hints. */
193 #define AXP_OPERAND_DEFAULT_ZERO 01000
194
195 /* This operand should default to the first (real) operand and is used
196 in conjunction with AXP_OPERAND_OPTIONAL. This allows
197 "and $0,3,$0" to be written as "and $0,3", etc. I don't like
198 it, but it's what DEC does. */
199 #define AXP_OPERAND_DEFAULT_FIRST 02000
200
201 /* Similarly, this operand should default to the second (real) operand.
202 This allows "negl $0" instead of "negl $0,$0". */
203 #define AXP_OPERAND_DEFAULT_SECOND 04000
204
205 \f
206 /* Register common names */
207
208 #define AXP_REG_V0 0
209 #define AXP_REG_T0 1
210 #define AXP_REG_T1 2
211 #define AXP_REG_T2 3
212 #define AXP_REG_T3 4
213 #define AXP_REG_T4 5
214 #define AXP_REG_T5 6
215 #define AXP_REG_T6 7
216 #define AXP_REG_T7 8
217 #define AXP_REG_S0 9
218 #define AXP_REG_S1 10
219 #define AXP_REG_S2 11
220 #define AXP_REG_S3 12
221 #define AXP_REG_S4 13
222 #define AXP_REG_S5 14
223 #define AXP_REG_FP 15
224 #define AXP_REG_A0 16
225 #define AXP_REG_A1 17
226 #define AXP_REG_A2 18
227 #define AXP_REG_A3 19
228 #define AXP_REG_A4 20
229 #define AXP_REG_A5 21
230 #define AXP_REG_T8 22
231 #define AXP_REG_T9 23
232 #define AXP_REG_T10 24
233 #define AXP_REG_T11 25
234 #define AXP_REG_RA 26
235 #define AXP_REG_PV 27
236 #define AXP_REG_T12 27
237 #define AXP_REG_AT 28
238 #define AXP_REG_GP 29
239 #define AXP_REG_SP 30
240 #define AXP_REG_ZERO 31
241
242 #define bfd_mach_alpha_ev4 0x10
243 #define bfd_mach_alpha_ev5 0x20
244 #define bfd_mach_alpha_ev6 0x30
245
246 enum bfd_reloc_code_real {
247 BFD_RELOC_23_PCREL_S2,
248 BFD_RELOC_ALPHA_HINT
249 };
250
251 /* This file holds the Alpha AXP opcode table. The opcode table includes
252 almost all of the extended instruction mnemonics. This permits the
253 disassembler to use them, and simplifies the assembler logic, at the
254 cost of increasing the table size. The table is strictly constant
255 data, so the compiler should be able to put it in the text segment.
256
257 This file also holds the operand table. All knowledge about inserting
258 and extracting operands from instructions is kept in this file.
259
260 The information for the base instruction set was compiled from the
261 _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
262 version 2.
263
264 The information for the post-ev5 architecture extensions BWX, CIX and
265 MAX came from version 3 of this same document, which is also available
266 on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
267 /literature/alphahb2.pdf
268
269 The information for the EV4 PALcode instructions was compiled from
270 _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
271 Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
272 revision dated June 1994.
273
274 The information for the EV5 PALcode instructions was compiled from
275 _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
276 Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */
277 \f
278 /* Local insertion and extraction functions */
279
280 static unsigned insert_rba PARAMS((unsigned, int, const char **));
281 static unsigned insert_rca PARAMS((unsigned, int, const char **));
282 static unsigned insert_za PARAMS((unsigned, int, const char **));
283 static unsigned insert_zb PARAMS((unsigned, int, const char **));
284 static unsigned insert_zc PARAMS((unsigned, int, const char **));
285 static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
286 static unsigned insert_jhint PARAMS((unsigned, int, const char **));
287 static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **));
288
289 static int extract_rba PARAMS((unsigned, int *));
290 static int extract_rca PARAMS((unsigned, int *));
291 static int extract_za PARAMS((unsigned, int *));
292 static int extract_zb PARAMS((unsigned, int *));
293 static int extract_zc PARAMS((unsigned, int *));
294 static int extract_bdisp PARAMS((unsigned, int *));
295 static int extract_jhint PARAMS((unsigned, int *));
296 static int extract_ev6hwjhint PARAMS((unsigned, int *));
297
298 \f
299 /* The operands table */
300
301 const struct alpha_operand alpha_operands[] =
302 {
303 /* The fields are bits, shift, insert, extract, flags */
304 /* The zero index is used to indicate end-of-list */
305 #define UNUSED 0
306 { 0, 0, 0, 0, 0, 0 },
307
308 /* The plain integer register fields */
309 #define RA (UNUSED + 1)
310 { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
311 #define RB (RA + 1)
312 { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
313 #define RC (RB + 1)
314 { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
315
316 /* The plain fp register fields */
317 #define FA (RC + 1)
318 { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
319 #define FB (FA + 1)
320 { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
321 #define FC (FB + 1)
322 { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
323
324 /* The integer registers when they are ZERO */
325 #define ZA (FC + 1)
326 { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
327 #define ZB (ZA + 1)
328 { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
329 #define ZC (ZB + 1)
330 { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
331
332 /* The RB field when it needs parentheses */
333 #define PRB (ZC + 1)
334 { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
335
336 /* The RB field when it needs parentheses _and_ a preceding comma */
337 #define CPRB (PRB + 1)
338 { 5, 16, 0,
339 AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
340
341 /* The RB field when it must be the same as the RA field */
342 #define RBA (CPRB + 1)
343 { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
344
345 /* The RC field when it must be the same as the RB field */
346 #define RCA (RBA + 1)
347 { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
348
349 /* The RC field when it can *default* to RA */
350 #define DRC1 (RCA + 1)
351 { 5, 0, 0,
352 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
353
354 /* The RC field when it can *default* to RB */
355 #define DRC2 (DRC1 + 1)
356 { 5, 0, 0,
357 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
358
359 /* The FC field when it can *default* to RA */
360 #define DFC1 (DRC2 + 1)
361 { 5, 0, 0,
362 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
363
364 /* The FC field when it can *default* to RB */
365 #define DFC2 (DFC1 + 1)
366 { 5, 0, 0,
367 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
368
369 /* The unsigned 8-bit literal of Operate format insns */
370 #define LIT (DFC2 + 1)
371 { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
372
373 /* The signed 16-bit displacement of Memory format insns. From here
374 we can't tell what relocation should be used, so don't use a default. */
375 #define MDISP (LIT + 1)
376 { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
377
378 /* The signed "23-bit" aligned displacement of Branch format insns */
379 #define BDISP (MDISP + 1)
380 { 21, 0, BFD_RELOC_23_PCREL_S2,
381 AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
382
383 /* The 26-bit PALcode function */
384 #define PALFN (BDISP + 1)
385 { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
386
387 /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
388 #define JMPHINT (PALFN + 1)
389 { 14, 0, BFD_RELOC_ALPHA_HINT,
390 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
391 insert_jhint, extract_jhint },
392
393 /* The optional hint to RET/JSR_COROUTINE */
394 #define RETHINT (JMPHINT + 1)
395 { 14, 0, -RETHINT,
396 AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
397
398 /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
399 #define EV4HWDISP (RETHINT + 1)
400 #define EV6HWDISP (EV4HWDISP)
401 { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
402
403 /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
404 #define EV4HWINDEX (EV4HWDISP + 1)
405 { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
406
407 /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
408 that occur in DEC PALcode. */
409 #define EV4EXTHWINDEX (EV4HWINDEX + 1)
410 { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
411
412 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
413 #define EV5HWDISP (EV4EXTHWINDEX + 1)
414 { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
415
416 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
417 #define EV5HWINDEX (EV5HWDISP + 1)
418 { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
419
420 /* The 16-bit combined index/scoreboard mask for the ev6
421 hw_m[ft]pr (pal19/pal1d) insns */
422 #define EV6HWINDEX (EV5HWINDEX + 1)
423 { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
424
425 /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
426 #define EV6HWJMPHINT (EV6HWINDEX+ 1)
427 { 8, 0, -EV6HWJMPHINT,
428 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
429 insert_ev6hwjhint, extract_ev6hwjhint }
430 };
431
432 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
433
434 /* The RB field when it is the same as the RA field in the same insn.
435 This operand is marked fake. The insertion function just copies
436 the RA field into the RB field, and the extraction function just
437 checks that the fields are the same. */
438
439 /*ARGSUSED*/
440 static unsigned
441 insert_rba(insn, value, errmsg)
442 unsigned insn;
443 int value ATTRIBUTE_UNUSED;
444 const char **errmsg ATTRIBUTE_UNUSED;
445 {
446 return insn | (((insn >> 21) & 0x1f) << 16);
447 }
448
449 static int
450 extract_rba(insn, invalid)
451 unsigned insn;
452 int *invalid;
453 {
454 if (invalid != (int *) NULL
455 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
456 *invalid = 1;
457 return 0;
458 }
459
460
461 /* The same for the RC field */
462
463 /*ARGSUSED*/
464 static unsigned
465 insert_rca(insn, value, errmsg)
466 unsigned insn;
467 int value ATTRIBUTE_UNUSED;
468 const char **errmsg ATTRIBUTE_UNUSED;
469 {
470 return insn | ((insn >> 21) & 0x1f);
471 }
472
473 static int
474 extract_rca(insn, invalid)
475 unsigned insn;
476 int *invalid;
477 {
478 if (invalid != (int *) NULL
479 && ((insn >> 21) & 0x1f) != (insn & 0x1f))
480 *invalid = 1;
481 return 0;
482 }
483
484
485 /* Fake arguments in which the registers must be set to ZERO */
486
487 /*ARGSUSED*/
488 static unsigned
489 insert_za(insn, value, errmsg)
490 unsigned insn;
491 int value ATTRIBUTE_UNUSED;
492 const char **errmsg ATTRIBUTE_UNUSED;
493 {
494 return insn | (31 << 21);
495 }
496
497 static int
498 extract_za(insn, invalid)
499 unsigned insn;
500 int *invalid;
501 {
502 if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
503 *invalid = 1;
504 return 0;
505 }
506
507 /*ARGSUSED*/
508 static unsigned
509 insert_zb(insn, value, errmsg)
510 unsigned insn;
511 int value ATTRIBUTE_UNUSED;
512 const char **errmsg ATTRIBUTE_UNUSED;
513 {
514 return insn | (31 << 16);
515 }
516
517 static int
518 extract_zb(insn, invalid)
519 unsigned insn;
520 int *invalid;
521 {
522 if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
523 *invalid = 1;
524 return 0;
525 }
526
527 /*ARGSUSED*/
528 static unsigned
529 insert_zc(insn, value, errmsg)
530 unsigned insn;
531 int value ATTRIBUTE_UNUSED;
532 const char **errmsg ATTRIBUTE_UNUSED;
533 {
534 return insn | 31;
535 }
536
537 static int
538 extract_zc(insn, invalid)
539 unsigned insn;
540 int *invalid;
541 {
542 if (invalid != (int *) NULL && (insn & 0x1f) != 31)
543 *invalid = 1;
544 return 0;
545 }
546
547
548 /* The displacement field of a Branch format insn. */
549
550 static unsigned
551 insert_bdisp(insn, value, errmsg)
552 unsigned insn;
553 int value;
554 const char **errmsg;
555 {
556 if (errmsg != (const char **)NULL && (value & 3))
557 *errmsg = _("branch operand unaligned");
558 return insn | ((value / 4) & 0x1FFFFF);
559 }
560
561 /*ARGSUSED*/
562 static int
563 extract_bdisp(insn, invalid)
564 unsigned insn;
565 int *invalid ATTRIBUTE_UNUSED;
566 {
567 return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
568 }
569
570
571 /* The hint field of a JMP/JSR insn. */
572
573 static unsigned
574 insert_jhint(insn, value, errmsg)
575 unsigned insn;
576 int value;
577 const char **errmsg;
578 {
579 if (errmsg != (const char **)NULL && (value & 3))
580 *errmsg = _("jump hint unaligned");
581 return insn | ((value / 4) & 0x3FFF);
582 }
583
584 /*ARGSUSED*/
585 static int
586 extract_jhint(insn, invalid)
587 unsigned insn;
588 int *invalid ATTRIBUTE_UNUSED;
589 {
590 return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
591 }
592
593 /* The hint field of an EV6 HW_JMP/JSR insn. */
594
595 static unsigned
596 insert_ev6hwjhint(insn, value, errmsg)
597 unsigned insn;
598 int value;
599 const char **errmsg;
600 {
601 if (errmsg != (const char **)NULL && (value & 3))
602 *errmsg = _("jump hint unaligned");
603 return insn | ((value / 4) & 0x1FFF);
604 }
605
606 /*ARGSUSED*/
607 static int
608 extract_ev6hwjhint(insn, invalid)
609 unsigned insn;
610 int *invalid ATTRIBUTE_UNUSED;
611 {
612 return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
613 }
614
615 \f
616 /* Macros used to form opcodes */
617
618 /* The main opcode */
619 #define OP(x) (((x) & 0x3F) << 26)
620 #define OP_MASK 0xFC000000
621
622 /* Branch format instructions */
623 #define BRA_(oo) OP(oo)
624 #define BRA_MASK OP_MASK
625 #define BRA(oo) BRA_(oo), BRA_MASK
626
627 /* Floating point format instructions */
628 #define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5))
629 #define FP_MASK (OP_MASK | 0xFFE0)
630 #define FP(oo,fff) FP_(oo,fff), FP_MASK
631
632 /* Memory format instructions */
633 #define MEM_(oo) OP(oo)
634 #define MEM_MASK OP_MASK
635 #define MEM(oo) MEM_(oo), MEM_MASK
636
637 /* Memory/Func Code format instructions */
638 #define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF))
639 #define MFC_MASK (OP_MASK | 0xFFFF)
640 #define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK
641
642 /* Memory/Branch format instructions */
643 #define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14))
644 #define MBR_MASK (OP_MASK | 0xC000)
645 #define MBR(oo,h) MBR_(oo,h), MBR_MASK
646
647 /* Operate format instructions. The OPRL variant specifies a
648 literal second argument. */
649 #define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5))
650 #define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000)
651 #define OPR_MASK (OP_MASK | 0x1FE0)
652 #define OPR(oo,ff) OPR_(oo,ff), OPR_MASK
653 #define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK
654
655 /* Generic PALcode format instructions */
656 #define PCD_(oo) OP(oo)
657 #define PCD_MASK OP_MASK
658 #define PCD(oo) PCD_(oo), PCD_MASK
659
660 /* Specific PALcode instructions */
661 #define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF))
662 #define SPCD_MASK 0xFFFFFFFF
663 #define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK
664
665 /* Hardware memory (hw_{ld,st}) instructions */
666 #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
667 #define EV4HWMEM_MASK (OP_MASK | 0xF000)
668 #define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK
669
670 #define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))
671 #define EV5HWMEM_MASK (OP_MASK | 0xF800)
672 #define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK
673
674 #define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
675 #define EV6HWMEM_MASK (OP_MASK | 0xF000)
676 #define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK
677
678 #define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13))
679 #define EV6HWMBR_MASK (OP_MASK | 0xE000)
680 #define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK
681
682 /* Abbreviations for instruction subsets. */
683 #define BASE AXP_OPCODE_BASE
684 #define EV4 AXP_OPCODE_EV4
685 #define EV5 AXP_OPCODE_EV5
686 #define EV6 AXP_OPCODE_EV6
687 #define BWX AXP_OPCODE_BWX
688 #define CIX AXP_OPCODE_CIX
689 #define MAX AXP_OPCODE_MAX
690
691 /* Common combinations of arguments */
692 #define ARG_NONE { 0 }
693 #define ARG_BRA { RA, BDISP }
694 #define ARG_FBRA { FA, BDISP }
695 #define ARG_FP { FA, FB, DFC1 }
696 #define ARG_FPZ1 { ZA, FB, DFC1 }
697 #define ARG_MEM { RA, MDISP, PRB }
698 #define ARG_FMEM { FA, MDISP, PRB }
699 #define ARG_OPR { RA, RB, DRC1 }
700 #define ARG_OPRL { RA, LIT, DRC1 }
701 #define ARG_OPRZ1 { ZA, RB, DRC1 }
702 #define ARG_OPRLZ1 { ZA, LIT, RC }
703 #define ARG_PCD { PALFN }
704 #define ARG_EV4HWMEM { RA, EV4HWDISP, PRB }
705 #define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX }
706 #define ARG_EV5HWMEM { RA, EV5HWDISP, PRB }
707 #define ARG_EV6HWMEM { RA, EV6HWDISP, PRB }
708 \f
709 /* The opcode table.
710
711 The format of the opcode table is:
712
713 NAME OPCODE MASK { OPERANDS }
714
715 NAME is the name of the instruction.
716
717 OPCODE is the instruction opcode.
718
719 MASK is the opcode mask; this is used to tell the disassembler
720 which bits in the actual opcode must match OPCODE.
721
722 OPERANDS is the list of operands.
723
724 The preceding macros merge the text of the OPCODE and MASK fields.
725
726 The disassembler reads the table in order and prints the first
727 instruction which matches, so this table is sorted to put more
728 specific instructions before more general instructions.
729
730 Otherwise, it is sorted by major opcode and minor function code.
731
732 There are three classes of not-really-instructions in this table:
733
734 ALIAS is another name for another instruction. Some of
735 these come from the Architecture Handbook, some
736 come from the original gas opcode tables. In all
737 cases, the functionality of the opcode is unchanged.
738
739 PSEUDO a stylized code form endorsed by Chapter A.4 of the
740 Architecture Handbook.
741
742 EXTRA a stylized code form found in the original gas tables.
743
744 And two annotations:
745
746 EV56 BUT opcodes that are officially introduced as of the ev56,
747 but with defined results on previous implementations.
748
749 EV56 UNA opcodes that were introduced as of the ev56 with
750 presumably undefined results on previous implementations
751 that were not assigned to a particular extension.
752 */
753
754 const struct alpha_opcode alpha_opcodes[] = {
755 { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE },
756 { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE },
757 { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE },
758 { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE },
759 { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE },
760 { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE },
761 { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE },
762 { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE },
763 { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE },
764 { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE },
765 { "call_pal", PCD(0x00), BASE, ARG_PCD },
766 { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */
767
768 { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */
769 { "lda", MEM(0x08), BASE, ARG_MEM },
770 { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */
771 { "ldah", MEM(0x09), BASE, ARG_MEM },
772 { "ldbu", MEM(0x0A), BWX, ARG_MEM },
773 { "unop", MEM_(0x0B) | (30 << 16),
774 MEM_MASK, BASE, { ZA } }, /* pseudo */
775 { "ldq_u", MEM(0x0B), BASE, ARG_MEM },
776 { "ldwu", MEM(0x0C), BWX, ARG_MEM },
777 { "stw", MEM(0x0D), BWX, ARG_MEM },
778 { "stb", MEM(0x0E), BWX, ARG_MEM },
779 { "stq_u", MEM(0x0F), BASE, ARG_MEM },
780
781 { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */
782 { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */
783 { "addl", OPR(0x10,0x00), BASE, ARG_OPR },
784 { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL },
785 { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR },
786 { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL },
787 { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */
788 { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */
789 { "subl", OPR(0x10,0x09), BASE, ARG_OPR },
790 { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL },
791 { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR },
792 { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL },
793 { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR },
794 { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL },
795 { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR },
796 { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL },
797 { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR },
798 { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL },
799 { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR },
800 { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL },
801 { "addq", OPR(0x10,0x20), BASE, ARG_OPR },
802 { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL },
803 { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR },
804 { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL },
805 { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */
806 { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */
807 { "subq", OPR(0x10,0x29), BASE, ARG_OPR },
808 { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL },
809 { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR },
810 { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL },
811 { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR },
812 { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL },
813 { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR },
814 { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL },
815 { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR },
816 { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL },
817 { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR },
818 { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL },
819 { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR },
820 { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL },
821 { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */
822 { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */
823 { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR },
824 { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL },
825 { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR },
826 { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL },
827 { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR },
828 { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL },
829 { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */
830 { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */
831 { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR },
832 { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL },
833 { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR },
834 { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL },
835
836 { "and", OPR(0x11,0x00), BASE, ARG_OPR },
837 { "and", OPRL(0x11,0x00), BASE, ARG_OPRL },
838 { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */
839 { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */
840 { "bic", OPR(0x11,0x08), BASE, ARG_OPR },
841 { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL },
842 { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR },
843 { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL },
844 { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR },
845 { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL },
846 { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
847 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
848 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
849 { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
850 { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
851 { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */
852 { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */
853 { "bis", OPR(0x11,0x20), BASE, ARG_OPR },
854 { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL },
855 { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR },
856 { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL },
857 { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR },
858 { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL },
859 { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */
860 { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */
861 { "ornot", OPR(0x11,0x28), BASE, ARG_OPR },
862 { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL },
863 { "xor", OPR(0x11,0x40), BASE, ARG_OPR },
864 { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL },
865 { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR },
866 { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL },
867 { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR },
868 { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL },
869 { "eqv", OPR(0x11,0x48), BASE, ARG_OPR },
870 { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL },
871 { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */
872 { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */
873 { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */
874 { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */
875 { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR },
876 { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL },
877 { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR },
878 { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL },
879 { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
880 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */
881
882 { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR },
883 { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL },
884 { "extbl", OPR(0x12,0x06), BASE, ARG_OPR },
885 { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL },
886 { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR },
887 { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL },
888 { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR },
889 { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL },
890 { "extwl", OPR(0x12,0x16), BASE, ARG_OPR },
891 { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL },
892 { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR },
893 { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL },
894 { "mskll", OPR(0x12,0x22), BASE, ARG_OPR },
895 { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL },
896 { "extll", OPR(0x12,0x26), BASE, ARG_OPR },
897 { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL },
898 { "insll", OPR(0x12,0x2B), BASE, ARG_OPR },
899 { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL },
900 { "zap", OPR(0x12,0x30), BASE, ARG_OPR },
901 { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL },
902 { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR },
903 { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL },
904 { "mskql", OPR(0x12,0x32), BASE, ARG_OPR },
905 { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL },
906 { "srl", OPR(0x12,0x34), BASE, ARG_OPR },
907 { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL },
908 { "extql", OPR(0x12,0x36), BASE, ARG_OPR },
909 { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL },
910 { "sll", OPR(0x12,0x39), BASE, ARG_OPR },
911 { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL },
912 { "insql", OPR(0x12,0x3B), BASE, ARG_OPR },
913 { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL },
914 { "sra", OPR(0x12,0x3C), BASE, ARG_OPR },
915 { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL },
916 { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR },
917 { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL },
918 { "inswh", OPR(0x12,0x57), BASE, ARG_OPR },
919 { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL },
920 { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR },
921 { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL },
922 { "msklh", OPR(0x12,0x62), BASE, ARG_OPR },
923 { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL },
924 { "inslh", OPR(0x12,0x67), BASE, ARG_OPR },
925 { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL },
926 { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR },
927 { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL },
928 { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR },
929 { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL },
930 { "insqh", OPR(0x12,0x77), BASE, ARG_OPR },
931 { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL },
932 { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR },
933 { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL },
934
935 { "mull", OPR(0x13,0x00), BASE, ARG_OPR },
936 { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL },
937 { "mulq", OPR(0x13,0x20), BASE, ARG_OPR },
938 { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL },
939 { "umulh", OPR(0x13,0x30), BASE, ARG_OPR },
940 { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL },
941 { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR },
942 { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL },
943 { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR },
944 { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL },
945
946 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
947 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
948 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
949 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
950 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
951 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
952 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
953 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 },
954 { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 },
955 { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 },
956 { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 },
957 { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 },
958 { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 },
959 { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 },
960 { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 },
961 { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 },
962 { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 },
963 { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 },
964 { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 },
965 { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 },
966 { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 },
967 { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 },
968 { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 },
969 { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 },
970 { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 },
971 { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 },
972 { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 },
973 { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 },
974 { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 },
975 { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 },
976 { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 },
977 { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 },
978 { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 },
979 { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 },
980 { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 },
981 { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 },
982 { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 },
983 { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 },
984 { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 },
985 { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 },
986 { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 },
987 { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 },
988 { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 },
989 { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 },
990 { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 },
991 { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 },
992 { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 },
993 { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 },
994 { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 },
995 { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 },
996 { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 },
997
998 { "addf/c", FP(0x15,0x000), BASE, ARG_FP },
999 { "subf/c", FP(0x15,0x001), BASE, ARG_FP },
1000 { "mulf/c", FP(0x15,0x002), BASE, ARG_FP },
1001 { "divf/c", FP(0x15,0x003), BASE, ARG_FP },
1002 { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 },
1003 { "addg/c", FP(0x15,0x020), BASE, ARG_FP },
1004 { "subg/c", FP(0x15,0x021), BASE, ARG_FP },
1005 { "mulg/c", FP(0x15,0x022), BASE, ARG_FP },
1006 { "divg/c", FP(0x15,0x023), BASE, ARG_FP },
1007 { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 },
1008 { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 },
1009 { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 },
1010 { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 },
1011 { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 },
1012 { "addf", FP(0x15,0x080), BASE, ARG_FP },
1013 { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */
1014 { "subf", FP(0x15,0x081), BASE, ARG_FP },
1015 { "mulf", FP(0x15,0x082), BASE, ARG_FP },
1016 { "divf", FP(0x15,0x083), BASE, ARG_FP },
1017 { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 },
1018 { "addg", FP(0x15,0x0A0), BASE, ARG_FP },
1019 { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
1020 { "subg", FP(0x15,0x0A1), BASE, ARG_FP },
1021 { "mulg", FP(0x15,0x0A2), BASE, ARG_FP },
1022 { "divg", FP(0x15,0x0A3), BASE, ARG_FP },
1023 { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP },
1024 { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP },
1025 { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP },
1026 { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 },
1027 { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 },
1028 { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 },
1029 { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 },
1030 { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 },
1031 { "addf/uc", FP(0x15,0x100), BASE, ARG_FP },
1032 { "subf/uc", FP(0x15,0x101), BASE, ARG_FP },
1033 { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP },
1034 { "divf/uc", FP(0x15,0x103), BASE, ARG_FP },
1035 { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 },
1036 { "addg/uc", FP(0x15,0x120), BASE, ARG_FP },
1037 { "subg/uc", FP(0x15,0x121), BASE, ARG_FP },
1038 { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP },
1039 { "divg/uc", FP(0x15,0x123), BASE, ARG_FP },
1040 { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 },
1041 { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 },
1042 { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 },
1043 { "addf/u", FP(0x15,0x180), BASE, ARG_FP },
1044 { "subf/u", FP(0x15,0x181), BASE, ARG_FP },
1045 { "mulf/u", FP(0x15,0x182), BASE, ARG_FP },
1046 { "divf/u", FP(0x15,0x183), BASE, ARG_FP },
1047 { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 },
1048 { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP },
1049 { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP },
1050 { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP },
1051 { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP },
1052 { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 },
1053 { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 },
1054 { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 },
1055 { "addf/sc", FP(0x15,0x400), BASE, ARG_FP },
1056 { "subf/sc", FP(0x15,0x401), BASE, ARG_FP },
1057 { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP },
1058 { "divf/sc", FP(0x15,0x403), BASE, ARG_FP },
1059 { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 },
1060 { "addg/sc", FP(0x15,0x420), BASE, ARG_FP },
1061 { "subg/sc", FP(0x15,0x421), BASE, ARG_FP },
1062 { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP },
1063 { "divg/sc", FP(0x15,0x423), BASE, ARG_FP },
1064 { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 },
1065 { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 },
1066 { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 },
1067 { "addf/s", FP(0x15,0x480), BASE, ARG_FP },
1068 { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */
1069 { "subf/s", FP(0x15,0x481), BASE, ARG_FP },
1070 { "mulf/s", FP(0x15,0x482), BASE, ARG_FP },
1071 { "divf/s", FP(0x15,0x483), BASE, ARG_FP },
1072 { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 },
1073 { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP },
1074 { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */
1075 { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP },
1076 { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP },
1077 { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP },
1078 { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP },
1079 { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP },
1080 { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP },
1081 { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 },
1082 { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 },
1083 { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 },
1084 { "addf/suc", FP(0x15,0x500), BASE, ARG_FP },
1085 { "subf/suc", FP(0x15,0x501), BASE, ARG_FP },
1086 { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP },
1087 { "divf/suc", FP(0x15,0x503), BASE, ARG_FP },
1088 { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 },
1089 { "addg/suc", FP(0x15,0x520), BASE, ARG_FP },
1090 { "subg/suc", FP(0x15,0x521), BASE, ARG_FP },
1091 { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP },
1092 { "divg/suc", FP(0x15,0x523), BASE, ARG_FP },
1093 { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 },
1094 { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 },
1095 { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 },
1096 { "addf/su", FP(0x15,0x580), BASE, ARG_FP },
1097 { "subf/su", FP(0x15,0x581), BASE, ARG_FP },
1098 { "mulf/su", FP(0x15,0x582), BASE, ARG_FP },
1099 { "divf/su", FP(0x15,0x583), BASE, ARG_FP },
1100 { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 },
1101 { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP },
1102 { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP },
1103 { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP },
1104 { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP },
1105 { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 },
1106 { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 },
1107 { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 },
1108
1109 { "adds/c", FP(0x16,0x000), BASE, ARG_FP },
1110 { "subs/c", FP(0x16,0x001), BASE, ARG_FP },
1111 { "muls/c", FP(0x16,0x002), BASE, ARG_FP },
1112 { "divs/c", FP(0x16,0x003), BASE, ARG_FP },
1113 { "addt/c", FP(0x16,0x020), BASE, ARG_FP },
1114 { "subt/c", FP(0x16,0x021), BASE, ARG_FP },
1115 { "mult/c", FP(0x16,0x022), BASE, ARG_FP },
1116 { "divt/c", FP(0x16,0x023), BASE, ARG_FP },
1117 { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 },
1118 { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 },
1119 { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 },
1120 { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 },
1121 { "adds/m", FP(0x16,0x040), BASE, ARG_FP },
1122 { "subs/m", FP(0x16,0x041), BASE, ARG_FP },
1123 { "muls/m", FP(0x16,0x042), BASE, ARG_FP },
1124 { "divs/m", FP(0x16,0x043), BASE, ARG_FP },
1125 { "addt/m", FP(0x16,0x060), BASE, ARG_FP },
1126 { "subt/m", FP(0x16,0x061), BASE, ARG_FP },
1127 { "mult/m", FP(0x16,0x062), BASE, ARG_FP },
1128 { "divt/m", FP(0x16,0x063), BASE, ARG_FP },
1129 { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 },
1130 { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 },
1131 { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 },
1132 { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 },
1133 { "adds", FP(0x16,0x080), BASE, ARG_FP },
1134 { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */
1135 { "subs", FP(0x16,0x081), BASE, ARG_FP },
1136 { "muls", FP(0x16,0x082), BASE, ARG_FP },
1137 { "divs", FP(0x16,0x083), BASE, ARG_FP },
1138 { "addt", FP(0x16,0x0A0), BASE, ARG_FP },
1139 { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
1140 { "subt", FP(0x16,0x0A1), BASE, ARG_FP },
1141 { "mult", FP(0x16,0x0A2), BASE, ARG_FP },
1142 { "divt", FP(0x16,0x0A3), BASE, ARG_FP },
1143 { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP },
1144 { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP },
1145 { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP },
1146 { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP },
1147 { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 },
1148 { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 },
1149 { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 },
1150 { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 },
1151 { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP },
1152 { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP },
1153 { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP },
1154 { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP },
1155 { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP },
1156 { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP },
1157 { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP },
1158 { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP },
1159 { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 },
1160 { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 },
1161 { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 },
1162 { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 },
1163 { "adds/uc", FP(0x16,0x100), BASE, ARG_FP },
1164 { "subs/uc", FP(0x16,0x101), BASE, ARG_FP },
1165 { "muls/uc", FP(0x16,0x102), BASE, ARG_FP },
1166 { "divs/uc", FP(0x16,0x103), BASE, ARG_FP },
1167 { "addt/uc", FP(0x16,0x120), BASE, ARG_FP },
1168 { "subt/uc", FP(0x16,0x121), BASE, ARG_FP },
1169 { "mult/uc", FP(0x16,0x122), BASE, ARG_FP },
1170 { "divt/uc", FP(0x16,0x123), BASE, ARG_FP },
1171 { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 },
1172 { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 },
1173 { "adds/um", FP(0x16,0x140), BASE, ARG_FP },
1174 { "subs/um", FP(0x16,0x141), BASE, ARG_FP },
1175 { "muls/um", FP(0x16,0x142), BASE, ARG_FP },
1176 { "divs/um", FP(0x16,0x143), BASE, ARG_FP },
1177 { "addt/um", FP(0x16,0x160), BASE, ARG_FP },
1178 { "subt/um", FP(0x16,0x161), BASE, ARG_FP },
1179 { "mult/um", FP(0x16,0x162), BASE, ARG_FP },
1180 { "divt/um", FP(0x16,0x163), BASE, ARG_FP },
1181 { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 },
1182 { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 },
1183 { "adds/u", FP(0x16,0x180), BASE, ARG_FP },
1184 { "subs/u", FP(0x16,0x181), BASE, ARG_FP },
1185 { "muls/u", FP(0x16,0x182), BASE, ARG_FP },
1186 { "divs/u", FP(0x16,0x183), BASE, ARG_FP },
1187 { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP },
1188 { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP },
1189 { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP },
1190 { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP },
1191 { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 },
1192 { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 },
1193 { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP },
1194 { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP },
1195 { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP },
1196 { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP },
1197 { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP },
1198 { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP },
1199 { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP },
1200 { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP },
1201 { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 },
1202 { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 },
1203 { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 },
1204 { "adds/suc", FP(0x16,0x500), BASE, ARG_FP },
1205 { "subs/suc", FP(0x16,0x501), BASE, ARG_FP },
1206 { "muls/suc", FP(0x16,0x502), BASE, ARG_FP },
1207 { "divs/suc", FP(0x16,0x503), BASE, ARG_FP },
1208 { "addt/suc", FP(0x16,0x520), BASE, ARG_FP },
1209 { "subt/suc", FP(0x16,0x521), BASE, ARG_FP },
1210 { "mult/suc", FP(0x16,0x522), BASE, ARG_FP },
1211 { "divt/suc", FP(0x16,0x523), BASE, ARG_FP },
1212 { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 },
1213 { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 },
1214 { "adds/sum", FP(0x16,0x540), BASE, ARG_FP },
1215 { "subs/sum", FP(0x16,0x541), BASE, ARG_FP },
1216 { "muls/sum", FP(0x16,0x542), BASE, ARG_FP },
1217 { "divs/sum", FP(0x16,0x543), BASE, ARG_FP },
1218 { "addt/sum", FP(0x16,0x560), BASE, ARG_FP },
1219 { "subt/sum", FP(0x16,0x561), BASE, ARG_FP },
1220 { "mult/sum", FP(0x16,0x562), BASE, ARG_FP },
1221 { "divt/sum", FP(0x16,0x563), BASE, ARG_FP },
1222 { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 },
1223 { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 },
1224 { "adds/su", FP(0x16,0x580), BASE, ARG_FP },
1225 { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */
1226 { "subs/su", FP(0x16,0x581), BASE, ARG_FP },
1227 { "muls/su", FP(0x16,0x582), BASE, ARG_FP },
1228 { "divs/su", FP(0x16,0x583), BASE, ARG_FP },
1229 { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP },
1230 { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */
1231 { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP },
1232 { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP },
1233 { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP },
1234 { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP },
1235 { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP },
1236 { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP },
1237 { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP },
1238 { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 },
1239 { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 },
1240 { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP },
1241 { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP },
1242 { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP },
1243 { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP },
1244 { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP },
1245 { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP },
1246 { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP },
1247 { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP },
1248 { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 },
1249 { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 },
1250 { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 },
1251 { "adds/suic", FP(0x16,0x700), BASE, ARG_FP },
1252 { "subs/suic", FP(0x16,0x701), BASE, ARG_FP },
1253 { "muls/suic", FP(0x16,0x702), BASE, ARG_FP },
1254 { "divs/suic", FP(0x16,0x703), BASE, ARG_FP },
1255 { "addt/suic", FP(0x16,0x720), BASE, ARG_FP },
1256 { "subt/suic", FP(0x16,0x721), BASE, ARG_FP },
1257 { "mult/suic", FP(0x16,0x722), BASE, ARG_FP },
1258 { "divt/suic", FP(0x16,0x723), BASE, ARG_FP },
1259 { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 },
1260 { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 },
1261 { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 },
1262 { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 },
1263 { "adds/suim", FP(0x16,0x740), BASE, ARG_FP },
1264 { "subs/suim", FP(0x16,0x741), BASE, ARG_FP },
1265 { "muls/suim", FP(0x16,0x742), BASE, ARG_FP },
1266 { "divs/suim", FP(0x16,0x743), BASE, ARG_FP },
1267 { "addt/suim", FP(0x16,0x760), BASE, ARG_FP },
1268 { "subt/suim", FP(0x16,0x761), BASE, ARG_FP },
1269 { "mult/suim", FP(0x16,0x762), BASE, ARG_FP },
1270 { "divt/suim", FP(0x16,0x763), BASE, ARG_FP },
1271 { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 },
1272 { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 },
1273 { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 },
1274 { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 },
1275 { "adds/sui", FP(0x16,0x780), BASE, ARG_FP },
1276 { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */
1277 { "subs/sui", FP(0x16,0x781), BASE, ARG_FP },
1278 { "muls/sui", FP(0x16,0x782), BASE, ARG_FP },
1279 { "divs/sui", FP(0x16,0x783), BASE, ARG_FP },
1280 { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP },
1281 { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */
1282 { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP },
1283 { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP },
1284 { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP },
1285 { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 },
1286 { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 },
1287 { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 },
1288 { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 },
1289 { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP },
1290 { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP },
1291 { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP },
1292 { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP },
1293 { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP },
1294 { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP },
1295 { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP },
1296 { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP },
1297 { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 },
1298 { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 },
1299 { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 },
1300 { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 },
1301
1302 { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 },
1303 { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */
1304 { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */
1305 { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */
1306 { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
1307 { "cpys", FP(0x17,0x020), BASE, ARG_FP },
1308 { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
1309 { "cpysn", FP(0x17,0x021), BASE, ARG_FP },
1310 { "cpyse", FP(0x17,0x022), BASE, ARG_FP },
1311 { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } },
1312 { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } },
1313 { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP },
1314 { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP },
1315 { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP },
1316 { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP },
1317 { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP },
1318 { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP },
1319 { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 },
1320 { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 },
1321 { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 },
1322
1323 { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE },
1324 { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */
1325 { "excb", MFC(0x18,0x0400), BASE, ARG_NONE },
1326 { "mb", MFC(0x18,0x4000), BASE, ARG_NONE },
1327 { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE },
1328 { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } },
1329 { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } },
1330 { "rpcc", MFC(0x18,0xC000), BASE, { RA } },
1331 { "rc", MFC(0x18,0xE000), BASE, { RA } },
1332 { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */
1333 { "rs", MFC(0x18,0xF000), BASE, { RA } },
1334 { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */
1335 { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */
1336
1337 { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1338 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1339 { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
1340 { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
1341 { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
1342 { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
1343 { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
1344 { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
1345 { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
1346 { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
1347 { "pal19", PCD(0x19), BASE, ARG_PCD },
1348
1349 { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */
1350 BASE, { ZA, CPRB } },
1351 { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
1352 { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
1353 { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
1354 0xFFFFFFFF, BASE, { 0 } },
1355 { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
1356 { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
1357 { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
1358
1359 { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1360 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1361 { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
1362 { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1363 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1364 { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
1365 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1366 { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1367 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1368 { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1369 { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1370 { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1371 { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1372 { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1373 { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1374 { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1375 { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1376 { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
1377 { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1378 { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1379 { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1380 { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1381 { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1382 { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1383 { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1384 { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1385 { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1386 { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1387 { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1388 { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1389 { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1390 { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1391 { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1392 { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1393 { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1394 { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1395 { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1396 { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1397 { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
1398 { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1399 { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1400 { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
1401 { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
1402 { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1403 { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1404 { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1405 { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1406 { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1407 { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1408 { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1409 { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1410 { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1411 { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
1412 { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1413 { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1414 { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1415 { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1416 { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1417 { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1418 { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1419 { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1420 { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1421 { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1422 { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1423 { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1424 { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
1425 { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1426 { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1427 { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
1428 { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1429 { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1430 { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1431 { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1432 { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1433 { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1434 { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1435 { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1436 { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1437 { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1438 { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1439 { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
1440 { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1441 { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1442 { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1443 { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1444 { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1445 { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1446 { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1447 { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1448 { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1449 { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1450 { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1451 { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1452 { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1453 { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1454 { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1455 { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1456 { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1457 { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1458 { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1459 { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1460 { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
1461 { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1462 { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1463 { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
1464 { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
1465 { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1466 { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1467 { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1468 { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1469 { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1470 { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1471 { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1472 { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1473 { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1474 { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
1475 { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1476 { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1477 { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1478 { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1479 { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1480 { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1481 { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1482 { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1483 { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1484 { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1485 { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1486 { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1487 { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1488 { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1489 { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1490 { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1491 { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1492 { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1493 { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1494 { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1495 { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1496 { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1497 { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1498 { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1499 { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1500 { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1501 { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1502 { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1503 { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1504 { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1505 { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1506 { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1507 { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1508 { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1509 { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1510 { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1511 { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1512 { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1513 { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1514 { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1515 { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1516 { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1517 { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1518 { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1519 { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1520 { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1521 { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1522 { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1523 { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1524 { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1525 { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1526 { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1527 { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1528 { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1529 { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1530 { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1531 { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1532 { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1533 { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1534 { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1535 { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1536 { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1537 { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1538 { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1539 { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1540 { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1541 { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1542 { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1543 { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1544 { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1545 { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1546 { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1547 { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1548 { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1549 { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1550 { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1551 { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1552 { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1553 { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1554 { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1555 { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1556 { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1557 { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1558 { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1559 { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1560 { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1561 { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1562 { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1563 { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1564 { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1565 { "pal1b", PCD(0x1B), BASE, ARG_PCD },
1566
1567 { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
1568 { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
1569 { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
1570 { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR },
1571 { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
1572 { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
1573 { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
1574 { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
1575 { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
1576 { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
1577 { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR },
1578 { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL },
1579 { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR },
1580 { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL },
1581 { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR },
1582 { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
1583 { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR },
1584 { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
1585 { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR },
1586 { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
1587 { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR },
1588 { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
1589 { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR },
1590 { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
1591 { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR },
1592 { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
1593 { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
1594 { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
1595
1596 { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1597 { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1598 { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1599 { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
1600 { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
1601 { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
1602 { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
1603 { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
1604 { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
1605 { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
1606 { "pal1d", PCD(0x1D), BASE, ARG_PCD },
1607
1608 { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
1609 { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
1610 { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1611 { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1612 { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1613 { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1614 { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1615 { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1616 { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1617 { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1618 { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1619 { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1620 { "pal1e", PCD(0x1E), BASE, ARG_PCD },
1621
1622 { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1623 { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1624 { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
1625 { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1626 { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1627 { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
1628 { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1629 { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1630 { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1631 { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1632 { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1633 { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1634 { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1635 { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
1636 { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1637 { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1638 { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1639 { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1640 { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1641 { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1642 { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1643 { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1644 { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1645 { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1646 { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1647 { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1648 { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1649 { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1650 { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1651 { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1652 { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
1653 { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1654 { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1655 { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1656 { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1657 { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1658 { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1659 { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
1660 { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1661 { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1662 { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
1663 { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1664 { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1665 { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1666 { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1667 { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1668 { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1669 { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1670 { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
1671 { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1672 { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1673 { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1674 { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1675 { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1676 { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1677 { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1678 { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1679 { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1680 { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1681 { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1682 { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
1683 { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1684 { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1685 { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1686 { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1687 { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1688 { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1689 { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
1690 { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1691 { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1692 { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1693 { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1694 { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1695 { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1696 { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1697 { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1698 { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1699 { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1700 { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1701 { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1702 { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1703 { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1704 { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1705 { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1706 { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1707 { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1708 { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1709 { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1710 { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1711 { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1712 { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1713 { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1714 { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1715 { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1716 { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1717 { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1718 { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1719 { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1720 { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1721 { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1722 { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1723 { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1724 { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1725 { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1726 { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1727 { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1728 { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1729 { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1730 { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1731 { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1732 { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1733 { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1734 { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1735 { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1736 { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1737 { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1738 { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1739 { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1740 { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1741 { "pal1f", PCD(0x1F), BASE, ARG_PCD },
1742
1743 { "ldf", MEM(0x20), BASE, ARG_FMEM },
1744 { "ldg", MEM(0x21), BASE, ARG_FMEM },
1745 { "lds", MEM(0x22), BASE, ARG_FMEM },
1746 { "ldt", MEM(0x23), BASE, ARG_FMEM },
1747 { "stf", MEM(0x24), BASE, ARG_FMEM },
1748 { "stg", MEM(0x25), BASE, ARG_FMEM },
1749 { "sts", MEM(0x26), BASE, ARG_FMEM },
1750 { "stt", MEM(0x27), BASE, ARG_FMEM },
1751
1752 { "ldl", MEM(0x28), BASE, ARG_MEM },
1753 { "ldq", MEM(0x29), BASE, ARG_MEM },
1754 { "ldl_l", MEM(0x2A), BASE, ARG_MEM },
1755 { "ldq_l", MEM(0x2B), BASE, ARG_MEM },
1756 { "stl", MEM(0x2C), BASE, ARG_MEM },
1757 { "stq", MEM(0x2D), BASE, ARG_MEM },
1758 { "stl_c", MEM(0x2E), BASE, ARG_MEM },
1759 { "stq_c", MEM(0x2F), BASE, ARG_MEM },
1760
1761 { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */
1762 { "br", BRA(0x30), BASE, ARG_BRA },
1763 { "fbeq", BRA(0x31), BASE, ARG_FBRA },
1764 { "fblt", BRA(0x32), BASE, ARG_FBRA },
1765 { "fble", BRA(0x33), BASE, ARG_FBRA },
1766 { "bsr", BRA(0x34), BASE, ARG_BRA },
1767 { "fbne", BRA(0x35), BASE, ARG_FBRA },
1768 { "fbge", BRA(0x36), BASE, ARG_FBRA },
1769 { "fbgt", BRA(0x37), BASE, ARG_FBRA },
1770 { "blbc", BRA(0x38), BASE, ARG_BRA },
1771 { "beq", BRA(0x39), BASE, ARG_BRA },
1772 { "blt", BRA(0x3A), BASE, ARG_BRA },
1773 { "ble", BRA(0x3B), BASE, ARG_BRA },
1774 { "blbs", BRA(0x3C), BASE, ARG_BRA },
1775 { "bne", BRA(0x3D), BASE, ARG_BRA },
1776 { "bge", BRA(0x3E), BASE, ARG_BRA },
1777 { "bgt", BRA(0x3F), BASE, ARG_BRA },
1778 };
1779
1780 const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);
1781
1782 /* OSF register names. */
1783
1784 static const char * const osf_regnames[64] = {
1785 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
1786 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
1787 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
1788 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
1789 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
1790 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1791 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1792 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
1793 };
1794
1795 /* VMS register names. */
1796
1797 static const char * const vms_regnames[64] = {
1798 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
1799 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
1800 "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
1801 "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ",
1802 "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
1803 "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
1804 "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
1805 "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ"
1806 };
1807
1808 /* Disassemble Alpha instructions. */
1809
1810 int
1811 print_insn_alpha (memaddr, info)
1812 bfd_vma memaddr;
1813 struct disassemble_info *info;
1814 {
1815 static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
1816 const char * const * regnames;
1817 const struct alpha_opcode *opcode, *opcode_end;
1818 const unsigned char *opindex;
1819 unsigned insn, op, isa_mask;
1820 int need_comma;
1821
1822 /* Initialize the majorop table the first time through */
1823 if (!opcode_index[0])
1824 {
1825 opcode = alpha_opcodes;
1826 opcode_end = opcode + alpha_num_opcodes;
1827
1828 for (op = 0; op < AXP_NOPS; ++op)
1829 {
1830 opcode_index[op] = opcode;
1831 while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
1832 ++opcode;
1833 }
1834 opcode_index[op] = opcode;
1835 }
1836
1837 if (info->flavour == bfd_target_evax_flavour)
1838 regnames = vms_regnames;
1839 else
1840 regnames = osf_regnames;
1841
1842 isa_mask = AXP_OPCODE_NOPAL;
1843 switch (info->mach)
1844 {
1845 case bfd_mach_alpha_ev4:
1846 isa_mask |= AXP_OPCODE_EV4;
1847 break;
1848 case bfd_mach_alpha_ev5:
1849 isa_mask |= AXP_OPCODE_EV5;
1850 break;
1851 case bfd_mach_alpha_ev6:
1852 isa_mask |= AXP_OPCODE_EV6;
1853 break;
1854 }
1855
1856 /* Read the insn into a host word */
1857 {
1858 bfd_byte buffer[4];
1859 int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
1860 if (status != 0)
1861 {
1862 (*info->memory_error_func) (status, memaddr, info);
1863 return -1;
1864 }
1865 insn = bfd_getl32 (buffer);
1866 }
1867
1868 /* Get the major opcode of the instruction. */
1869 op = AXP_OP (insn);
1870
1871 /* Find the first match in the opcode table. */
1872 opcode_end = opcode_index[op + 1];
1873 for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
1874 {
1875 if ((insn ^ opcode->opcode) & opcode->mask)
1876 continue;
1877
1878 if (!(opcode->flags & isa_mask))
1879 continue;
1880
1881 /* Make two passes over the operands. First see if any of them
1882 have extraction functions, and, if they do, make sure the
1883 instruction is valid. */
1884 {
1885 int invalid = 0;
1886 for (opindex = opcode->operands; *opindex != 0; opindex++)
1887 {
1888 const struct alpha_operand *operand = alpha_operands + *opindex;
1889 if (operand->extract)
1890 (*operand->extract) (insn, &invalid);
1891 }
1892 if (invalid)
1893 continue;
1894 }
1895
1896 /* The instruction is valid. */
1897 goto found;
1898 }
1899
1900 /* No instruction found */
1901 (*info->fprintf_func) (info->stream, ".long %#08x", insn);
1902
1903 return 4;
1904
1905 found:
1906 (*info->fprintf_func) (info->stream, "%s", opcode->name);
1907 if (opcode->operands[0] != 0)
1908 (*info->fprintf_func) (info->stream, "\t");
1909
1910 /* Now extract and print the operands. */
1911 need_comma = 0;
1912 for (opindex = opcode->operands; *opindex != 0; opindex++)
1913 {
1914 const struct alpha_operand *operand = alpha_operands + *opindex;
1915 int value;
1916
1917 /* Operands that are marked FAKE are simply ignored. We
1918 already made sure that the extract function considered
1919 the instruction to be valid. */
1920 if ((operand->flags & AXP_OPERAND_FAKE) != 0)
1921 continue;
1922
1923 /* Extract the value from the instruction. */
1924 if (operand->extract)
1925 value = (*operand->extract) (insn, (int *) NULL);
1926 else
1927 {
1928 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
1929 if (operand->flags & AXP_OPERAND_SIGNED)
1930 {
1931 int signbit = 1 << (operand->bits - 1);
1932 value = (value ^ signbit) - signbit;
1933 }
1934 }
1935
1936 if (need_comma &&
1937 ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
1938 != AXP_OPERAND_PARENS))
1939 {
1940 (*info->fprintf_func) (info->stream, ",");
1941 }
1942 if (operand->flags & AXP_OPERAND_PARENS)
1943 (*info->fprintf_func) (info->stream, "(");
1944
1945 /* Print the operand as directed by the flags. */
1946 if (operand->flags & AXP_OPERAND_IR)
1947 (*info->fprintf_func) (info->stream, "%s", regnames[value]);
1948 else if (operand->flags & AXP_OPERAND_FPR)
1949 (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
1950 else if (operand->flags & AXP_OPERAND_RELATIVE)
1951 (*info->print_address_func) (memaddr + 4 + value, info);
1952 else if (operand->flags & AXP_OPERAND_SIGNED)
1953 (*info->fprintf_func) (info->stream, "%d", value);
1954 else
1955 (*info->fprintf_func) (info->stream, "%#x", value);
1956
1957 if (operand->flags & AXP_OPERAND_PARENS)
1958 (*info->fprintf_func) (info->stream, ")");
1959 need_comma = 1;
1960 }
1961
1962 return 4;
1963 }
Stable branch of Qemu 0.9.1