hw/sun4m.c

   1 /*
   2  * QEMU Sun4m System Emulator
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 //#define DEBUG_IRQ
  26
  27 /*
  28  * Sun4m architecture was used in the following machines:
  29  *
  30  * SPARCserver 6xxMP/xx
  31  * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
  32  * SPARCstation LX/ZX (4/30)
  33  * SPARCstation Voyager
  34  * SPARCstation 10/xx, SPARCserver 10/xx
  35  * SPARCstation 5, SPARCserver 5
  36  * SPARCstation 20/xx, SPARCserver 20
  37  * SPARCstation 4
  38  *
  39  * See for example: http://www.sunhelp.org/faq/sunref1.html
  40  */
  41
  42 #ifdef DEBUG_IRQ
  43 #define DPRINTF(fmt, args...)                           \
  44     do { printf("CPUIRQ: " fmt , ##args); } while (0)
  45 #else
  46 #define DPRINTF(fmt, args...)
  47 #endif
  48
  49 #define KERNEL_LOAD_ADDR     0x00004000
  50 #define CMDLINE_ADDR         0x007ff000
  51 #define INITRD_LOAD_ADDR     0x00800000
  52 #define PROM_SIZE_MAX        (256 * 1024)
  53 #define PROM_ADDR            0xffd00000
  54 #define PROM_FILENAME        "openbios-sparc32"
  55
  56 #define MAX_CPUS 16
  57 #define MAX_PILS 16
  58
  59 struct hwdef {
  60     target_phys_addr_t iommu_base, slavio_base;
  61     target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
  62     target_phys_addr_t serial_base, fd_base;
  63     target_phys_addr_t dma_base, esp_base, le_base;
  64     target_phys_addr_t tcx_base, cs_base, power_base;
  65     long vram_size, nvram_size;
  66     // IRQ numbers are not PIL ones, but master interrupt controller register
  67     // bit numbers
  68     int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
  69     int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
  70     int machine_id; // For NVRAM
  71     uint32_t intbit_to_level[32];
  72 };
  73
  74 /* TSC handling */
  75
  76 uint64_t cpu_get_tsc()
  77 {
  78     return qemu_get_clock(vm_clock);
  79 }
  80
  81 int DMA_get_channel_mode (int nchan)
  82 {
  83     return 0;
  84 }
  85 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  86 {
  87     return 0;
  88 }
  89 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  90 {
  91     return 0;
  92 }
  93 void DMA_hold_DREQ (int nchan) {}
  94 void DMA_release_DREQ (int nchan) {}
  95 void DMA_schedule(int nchan) {}
  96 void DMA_run (void) {}
  97 void DMA_init (int high_page_enable) {}
  98 void DMA_register_channel (int nchan,
  99                            DMA_transfer_handler transfer_handler,
 100                            void *opaque)
 101 {
 102 }
 103
 104 static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
 105 {
 106     m48t59_write(nvram, addr++, (value >> 8) & 0xff);
 107     m48t59_write(nvram, addr++, value & 0xff);
 108 }
 109
 110 static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
 111 {
 112     m48t59_write(nvram, addr++, value >> 24);
 113     m48t59_write(nvram, addr++, (value >> 16) & 0xff);
 114     m48t59_write(nvram, addr++, (value >> 8) & 0xff);
 115     m48t59_write(nvram, addr++, value & 0xff);
 116 }
 117
 118 static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
 119                        const unsigned char *str, uint32_t max)
 120 {
 121     unsigned int i;
 122
 123     for (i = 0; i < max && str[i] != '\0'; i++) {
 124         m48t59_write(nvram, addr + i, str[i]);
 125     }
 126     m48t59_write(nvram, addr + max - 1, '\0');
 127 }
 128
 129 static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
 130                                 const unsigned char *str)
 131 {
 132     uint32_t len;
 133
 134     len = strlen(str) + 1;
 135     nvram_set_string(nvram, addr, str, len);
 136
 137     return addr + len;
 138 }
 139
 140 static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
 141                                     uint32_t end)
 142 {
 143     unsigned int i, sum;
 144
 145     // Length divided by 16
 146     m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
 147     m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
 148     // Checksum
 149     sum = m48t59_read(nvram, start);
 150     for (i = 0; i < 14; i++) {
 151         sum += m48t59_read(nvram, start + 2 + i);
 152         sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
 153     }
 154     m48t59_write(nvram, start + 1, sum & 0xff);
 155 }
 156
 157 extern int nographic;
 158
 159 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
 160                        int boot_device, uint32_t RAM_size,
 161                        uint32_t kernel_size,
 162                        int width, int height, int depth,
 163                        int machine_id)
 164 {
 165     unsigned char tmp = 0;
 166     unsigned int i, j;
 167     uint32_t start, end;
 168
 169     // Try to match PPC NVRAM
 170     nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 171     nvram_set_lword(nvram,  0x10, 0x00000001); /* structure v1 */
 172     // NVRAM_size, arch not applicable
 173     m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
 174     m48t59_write(nvram, 0x2E, 0);
 175     m48t59_write(nvram, 0x2F, nographic & 0xff);
 176     nvram_set_lword(nvram,  0x30, RAM_size);
 177     m48t59_write(nvram, 0x34, boot_device & 0xff);
 178     nvram_set_lword(nvram,  0x38, KERNEL_LOAD_ADDR);
 179     nvram_set_lword(nvram,  0x3C, kernel_size);
 180     if (cmdline) {
 181         strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
 182         nvram_set_lword(nvram,  0x40, CMDLINE_ADDR);
 183         nvram_set_lword(nvram,  0x44, strlen(cmdline));
 184     }
 185     // initrd_image, initrd_size passed differently
 186     nvram_set_word(nvram,   0x54, width);
 187     nvram_set_word(nvram,   0x56, height);
 188     nvram_set_word(nvram,   0x58, depth);
 189
 190     // OpenBIOS nvram variables
 191     // Variable partition
 192     start = 252;
 193     m48t59_write(nvram, start, 0x70);
 194     nvram_set_string(nvram, start + 4, "system", 12);
 195
 196     end = start + 16;
 197     for (i = 0; i < nb_prom_envs; i++)
 198         end = nvram_set_var(nvram, end, prom_envs[i]);
 199
 200     m48t59_write(nvram, end++ , 0);
 201     end = start + ((end - start + 15) & ~15);
 202     nvram_finish_partition(nvram, start, end);
 203
 204     // free partition
 205     start = end;
 206     m48t59_write(nvram, start, 0x7f);
 207     nvram_set_string(nvram, start + 4, "free", 12);
 208
 209     end = 0x1fd0;
 210     nvram_finish_partition(nvram, start, end);
 211
 212     // Sun4m specific use
 213     start = i = 0x1fd8;
 214     m48t59_write(nvram, i++, 0x01);
 215     m48t59_write(nvram, i++, machine_id);
 216     j = 0;
 217     m48t59_write(nvram, i++, macaddr[j++]);
 218     m48t59_write(nvram, i++, macaddr[j++]);
 219     m48t59_write(nvram, i++, macaddr[j++]);
 220     m48t59_write(nvram, i++, macaddr[j++]);
 221     m48t59_write(nvram, i++, macaddr[j++]);
 222     m48t59_write(nvram, i, macaddr[j]);
 223
 224     /* Calculate checksum */
 225     for (i = start; i < start + 15; i++) {
 226         tmp ^= m48t59_read(nvram, i);
 227     }
 228     m48t59_write(nvram, start + 15, tmp);
 229 }
 230
 231 static void *slavio_intctl;
 232
 233 void pic_info()
 234 {
 235     slavio_pic_info(slavio_intctl);
 236 }
 237
 238 void irq_info()
 239 {
 240     slavio_irq_info(slavio_intctl);
 241 }
 242
 243 static void cpu_set_irq(void *opaque, int irq, int level)
 244 {
 245     CPUState *env = opaque;
 246
 247     if (level) {
 248         DPRINTF("Raise CPU IRQ %d\n", irq);
 249
 250         env->halted = 0;
 251
 252         if (env->interrupt_index == 0 ||
 253             ((env->interrupt_index & ~15) == TT_EXTINT &&
 254              (env->interrupt_index & 15) < irq)) {
 255             env->interrupt_index = TT_EXTINT | irq;
 256             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 257         } else {
 258             DPRINTF("Not triggered, pending exception %d\n",
 259                     env->interrupt_index);
 260         }
 261     } else {
 262         DPRINTF("Lower CPU IRQ %d\n", irq);
 263     }
 264 }
 265
 266 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 267 {
 268 }
 269
 270 static void *slavio_misc;
 271
 272 void qemu_system_powerdown(void)
 273 {
 274     slavio_set_power_fail(slavio_misc, 1);
 275 }
 276
 277 static void main_cpu_reset(void *opaque)
 278 {
 279     CPUState *env = opaque;
 280
 281     cpu_reset(env);
 282     env->halted = 0;
 283 }
 284
 285 static void secondary_cpu_reset(void *opaque)
 286 {
 287     CPUState *env = opaque;
 288
 289     cpu_reset(env);
 290     env->halted = 1;
 291 }
 292
 293 static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
 294                            DisplayState *ds, const char *cpu_model)
 295
 296 {
 297     CPUState *env, *envs[MAX_CPUS];
 298     unsigned int i;
 299     void *iommu, *espdma, *ledma, *main_esp, *nvram;
 300     const sparc_def_t *def;
 301     qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
 302         *espdma_irq, *ledma_irq;
 303
 304     /* init CPUs */
 305     sparc_find_by_name(cpu_model, &def);
 306     if (def == NULL) {
 307         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 308         exit(1);
 309     }
 310
 311     for(i = 0; i < smp_cpus; i++) {
 312         env = cpu_init();
 313         cpu_sparc_register(env, def);
 314         envs[i] = env;
 315         if (i == 0) {
 316             qemu_register_reset(main_cpu_reset, env);
 317         } else {
 318             qemu_register_reset(secondary_cpu_reset, env);
 319             env->halted = 1;
 320         }
 321         register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
 322         cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
 323     }
 324
 325     for (i = smp_cpus; i < MAX_CPUS; i++)
 326         cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
 327
 328     /* allocate RAM */
 329     cpu_register_physical_memory(0, RAM_size, 0);
 330
 331     iommu = iommu_init(hwdef->iommu_base);
 332     slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
 333                                        hwdef->intctl_base + 0x10000ULL,
 334                                        &hwdef->intbit_to_level[0],
 335                                        &slavio_irq, &slavio_cpu_irq,
 336                                        cpu_irqs,
 337                                        hwdef->clock_irq);
 338
 339     espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
 340                               iommu, &espdma_irq);
 341     ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
 342                              slavio_irq[hwdef->le_irq], iommu, &ledma_irq);
 343
 344     if (graphic_depth != 8 && graphic_depth != 24) {
 345         fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
 346         exit (1);
 347     }
 348     tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
 349              hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
 350
 351     if (nd_table[0].model == NULL
 352         || strcmp(nd_table[0].model, "lance") == 0) {
 353         lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq);
 354     } else if (strcmp(nd_table[0].model, "?") == 0) {
 355         fprintf(stderr, "qemu: Supported NICs: lance\n");
 356         exit (1);
 357     } else {
 358         fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 359         exit (1);
 360     }
 361
 362     nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
 363                         hwdef->nvram_size, 8);
 364     for (i = 0; i < MAX_CPUS; i++) {
 365         slavio_timer_init(hwdef->counter_base +
 366                           (target_phys_addr_t)(i * TARGET_PAGE_SIZE),
 367                            slavio_cpu_irq[i], 0);
 368     }
 369     slavio_timer_init(hwdef->counter_base + 0x10000ULL,
 370                       slavio_irq[hwdef->clock1_irq], 2);
 371     slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);
 372     // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
 373     // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
 374     slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
 375                        serial_hds[1], serial_hds[0]);
 376     fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table);
 377     main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq);
 378
 379     for (i = 0; i < MAX_DISKS; i++) {
 380         if (bs_table[i]) {
 381             esp_scsi_attach(main_esp, bs_table[i], i);
 382         }
 383     }
 384
 385     slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,
 386                                    slavio_irq[hwdef->me_irq]);
 387     if (hwdef->cs_base != (target_phys_addr_t)-1)
 388         cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
 389
 390     return nvram;
 391 }
 392
 393 static void sun4m_load_kernel(long vram_size, int RAM_size, int boot_device,
 394                               const char *kernel_filename,
 395                               const char *kernel_cmdline,
 396                               const char *initrd_filename,
 397                               int machine_id,
 398                               void *nvram)
 399 {
 400     int ret, linux_boot;
 401     char buf[1024];
 402     unsigned int i;
 403     long prom_offset, initrd_size, kernel_size;
 404
 405     linux_boot = (kernel_filename != NULL);
 406
 407     prom_offset = RAM_size + vram_size;
 408     cpu_register_physical_memory(PROM_ADDR,
 409                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
 410                                  prom_offset | IO_MEM_ROM);
 411
 412     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
 413     ret = load_elf(buf, 0, NULL, NULL, NULL);
 414     if (ret < 0) {
 415         fprintf(stderr, "qemu: could not load prom '%s'\n",
 416                 buf);
 417         exit(1);
 418     }
 419
 420     kernel_size = 0;
 421     if (linux_boot) {
 422         kernel_size = load_elf(kernel_filename, -0xf0000000, NULL, NULL, NULL);
 423         if (kernel_size < 0)
 424             kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 425         if (kernel_size < 0)
 426             kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 427         if (kernel_size < 0) {
 428             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 429                     kernel_filename);
 430             exit(1);
 431         }
 432
 433         /* load initrd */
 434         initrd_size = 0;
 435         if (initrd_filename) {
 436             initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
 437             if (initrd_size < 0) {
 438                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 439                         initrd_filename);
 440                 exit(1);
 441             }
 442         }
 443         if (initrd_size > 0) {
 444             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 445                 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
 446                     == 0x48647253) { // HdrS
 447                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 448                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
 449                     break;
 450                 }
 451             }
 452         }
 453     }
 454     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
 455                boot_device, RAM_size, kernel_size, graphic_width,
 456                graphic_height, graphic_depth, machine_id);
 457 }
 458
 459 static const struct hwdef hwdefs[] = {
 460     /* SS-5 */
 461     {
 462         .iommu_base   = 0x10000000,
 463         .tcx_base     = 0x50000000,
 464         .cs_base      = 0x6c000000,
 465         .slavio_base  = 0x70000000,
 466         .ms_kb_base   = 0x71000000,
 467         .serial_base  = 0x71100000,
 468         .nvram_base   = 0x71200000,
 469         .fd_base      = 0x71400000,
 470         .counter_base = 0x71d00000,
 471         .intctl_base  = 0x71e00000,
 472         .dma_base     = 0x78400000,
 473         .esp_base     = 0x78800000,
 474         .le_base      = 0x78c00000,
 475         .power_base   = 0x7a000000,
 476         .vram_size    = 0x00100000,
 477         .nvram_size   = 0x2000,
 478         .esp_irq = 18,
 479         .le_irq = 16,
 480         .clock_irq = 7,
 481         .clock1_irq = 19,
 482         .ms_kb_irq = 14,
 483         .ser_irq = 15,
 484         .fd_irq = 22,
 485         .me_irq = 30,
 486         .cs_irq = 5,
 487         .machine_id = 0x80,
 488         .intbit_to_level = {
 489             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
 490             6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
 491         },
 492     },
 493     /* SS-10 */
 494     {
 495         .iommu_base   = 0xfe0000000ULL,
 496         .tcx_base     = 0xe20000000ULL,
 497         .cs_base      = -1,
 498         .slavio_base  = 0xff0000000ULL,
 499         .ms_kb_base   = 0xff1000000ULL,
 500         .serial_base  = 0xff1100000ULL,
 501         .nvram_base   = 0xff1200000ULL,
 502         .fd_base      = 0xff1700000ULL,
 503         .counter_base = 0xff1300000ULL,
 504         .intctl_base  = 0xff1400000ULL,
 505         .dma_base     = 0xef0400000ULL,
 506         .esp_base     = 0xef0800000ULL,
 507         .le_base      = 0xef0c00000ULL,
 508         .power_base   = 0xefa000000ULL,
 509         .vram_size    = 0x00100000,
 510         .nvram_size   = 0x2000,
 511         .esp_irq = 18,
 512         .le_irq = 16,
 513         .clock_irq = 7,
 514         .clock1_irq = 19,
 515         .ms_kb_irq = 14,
 516         .ser_irq = 15,
 517         .fd_irq = 22,
 518         .me_irq = 30,
 519         .cs_irq = -1,
 520         .machine_id = 0x72,
 521         .intbit_to_level = {
 522             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
 523             6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
 524         },
 525     },
 526 };
 527
 528 static void sun4m_common_init(int RAM_size, int boot_device, DisplayState *ds,
 529                               const char *kernel_filename, const char *kernel_cmdline,
 530                               const char *initrd_filename, const char *cpu_model,
 531                               unsigned int machine, int max_ram)
 532 {
 533     void *nvram;
 534
 535     if ((unsigned int)RAM_size > (unsigned int)max_ram) {
 536         fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
 537                 (unsigned int)RAM_size / (1024 * 1024),
 538                 (unsigned int)max_ram / (1024 * 1024));
 539         exit(1);
 540     }
 541     nvram = sun4m_hw_init(&hwdefs[machine], RAM_size, ds, cpu_model);
 542
 543     sun4m_load_kernel(hwdefs[machine].vram_size, RAM_size, boot_device,
 544                       kernel_filename, kernel_cmdline, initrd_filename,
 545                       hwdefs[machine].machine_id, nvram);
 546 }
 547
 548 /* SPARCstation 5 hardware initialisation */
 549 static void ss5_init(int RAM_size, int vga_ram_size, int boot_device,
 550                        DisplayState *ds, const char **fd_filename, int snapshot,
 551                        const char *kernel_filename, const char *kernel_cmdline,
 552                        const char *initrd_filename, const char *cpu_model)
 553 {
 554     if (cpu_model == NULL)
 555         cpu_model = "Fujitsu MB86904";
 556     sun4m_common_init(RAM_size, boot_device, ds, kernel_filename,
 557                       kernel_cmdline, initrd_filename, cpu_model,
 558                       0, 0x10000000);
 559 }
 560
 561 /* SPARCstation 10 hardware initialisation */
 562 static void ss10_init(int RAM_size, int vga_ram_size, int boot_device,
 563                             DisplayState *ds, const char **fd_filename, int snapshot,
 564                             const char *kernel_filename, const char *kernel_cmdline,
 565                             const char *initrd_filename, const char *cpu_model)
 566 {
 567     if (cpu_model == NULL)
 568         cpu_model = "TI SuperSparc II";
 569     sun4m_common_init(RAM_size, boot_device, ds, kernel_filename,
 570                       kernel_cmdline, initrd_filename, cpu_model,
 571                       1, PROM_ADDR); // XXX prom overlap, actually first 4GB ok
 572 }
 573
 574 QEMUMachine ss5_machine = {
 575     "SS-5",
 576     "Sun4m platform, SPARCstation 5",
 577     ss5_init,
 578 };
 579
 580 QEMUMachine ss10_machine = {
 581     "SS-10",
 582     "Sun4m platform, SPARCstation 10",
 583     ss10_init,
 584 };