hw/slavio_misc.c

   1 /*
   2  * QEMU Sparc SLAVIO aux io port emulation
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "sysemu.h"
  27
  28 /* debug misc */
  29 //#define DEBUG_MISC
  30
  31 /*
  32  * This is the auxio port, chip control and system control part of
  33  * chip STP2001 (Slave I/O), also produced as NCR89C105. See
  34  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  35  *
  36  * This also includes the PMC CPU idle controller.
  37  */
  38
  39 #ifdef DEBUG_MISC
  40 #define MISC_DPRINTF(fmt, args...) \
  41 do { printf("MISC: " fmt , ##args); } while (0)
  42 #else
  43 #define MISC_DPRINTF(fmt, args...)
  44 #endif
  45
  46 typedef struct MiscState {
  47     qemu_irq irq;
  48     uint8_t config;
  49     uint8_t aux1, aux2;
  50     uint8_t diag, mctrl;
  51     uint32_t sysctrl;
  52     uint16_t leds;
  53 } MiscState;
  54
  55 #define MISC_SIZE 1
  56 #define SYSCTRL_MAXADDR 3
  57 #define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
  58 #define LED_MAXADDR 2
  59 #define LED_SIZE (LED_MAXADDR + 1)
  60
  61 #define MISC_MASK 0x0fff0000
  62 #define MISC_LEDS 0x01600000
  63 #define MISC_CFG  0x01800000
  64 #define MISC_AUX1 0x01900000
  65 #define MISC_AUX2 0x01910000
  66 #define MISC_DIAG 0x01a00000
  67 #define MISC_MDM  0x01b00000
  68 #define MISC_SYS  0x01f00000
  69 #define MISC_PWR  0x0a000000
  70
  71 #define AUX2_PWROFF    0x01
  72 #define AUX2_PWRINTCLR 0x02
  73 #define AUX2_PWRFAIL   0x20
  74
  75 #define CFG_PWRINTEN   0x08
  76
  77 #define SYS_RESET      0x01
  78 #define SYS_RESETSTAT  0x02
  79
  80 static void slavio_misc_update_irq(void *opaque)
  81 {
  82     MiscState *s = opaque;
  83
  84     if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
  85         MISC_DPRINTF("Raise IRQ\n");
  86         qemu_irq_raise(s->irq);
  87     } else {
  88         MISC_DPRINTF("Lower IRQ\n");
  89         qemu_irq_lower(s->irq);
  90     }
  91 }
  92
  93 static void slavio_misc_reset(void *opaque)
  94 {
  95     MiscState *s = opaque;
  96
  97     // Diagnostic and system control registers not cleared in reset
  98     s->config = s->aux1 = s->aux2 = s->mctrl = 0;
  99 }
 100
 101 void slavio_set_power_fail(void *opaque, int power_failing)
 102 {
 103     MiscState *s = opaque;
 104
 105     MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
 106     if (power_failing && (s->config & CFG_PWRINTEN)) {
 107         s->aux2 |= AUX2_PWRFAIL;
 108     } else {
 109         s->aux2 &= ~AUX2_PWRFAIL;
 110     }
 111     slavio_misc_update_irq(s);
 112 }
 113
 114 static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
 115                                    uint32_t val)
 116 {
 117     MiscState *s = opaque;
 118
 119     switch (addr & MISC_MASK) {
 120     case MISC_CFG:
 121         MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
 122         s->config = val & 0xff;
 123         slavio_misc_update_irq(s);
 124         break;
 125     case MISC_AUX1:
 126         MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
 127         s->aux1 = val & 0xff;
 128         break;
 129     case MISC_AUX2:
 130         val &= AUX2_PWRINTCLR | AUX2_PWROFF;
 131         MISC_DPRINTF("Write aux2 %2.2x\n", val);
 132         val |= s->aux2 & AUX2_PWRFAIL;
 133         if (val & AUX2_PWRINTCLR) // Clear Power Fail int
 134             val &= AUX2_PWROFF;
 135         s->aux2 = val;
 136         if (val & AUX2_PWROFF)
 137             qemu_system_shutdown_request();
 138         slavio_misc_update_irq(s);
 139         break;
 140     case MISC_DIAG:
 141         MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
 142         s->diag = val & 0xff;
 143         break;
 144     case MISC_MDM:
 145         MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
 146         s->mctrl = val & 0xff;
 147         break;
 148     case MISC_PWR:
 149         MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
 150         cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
 151         break;
 152     }
 153 }
 154
 155 static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
 156 {
 157     MiscState *s = opaque;
 158     uint32_t ret = 0;
 159
 160     switch (addr & MISC_MASK) {
 161     case MISC_CFG:
 162         ret = s->config;
 163         MISC_DPRINTF("Read config %2.2x\n", ret);
 164         break;
 165     case MISC_AUX1:
 166         ret = s->aux1;
 167         MISC_DPRINTF("Read aux1 %2.2x\n", ret);
 168         break;
 169     case MISC_AUX2:
 170         ret = s->aux2;
 171         MISC_DPRINTF("Read aux2 %2.2x\n", ret);
 172         break;
 173     case MISC_DIAG:
 174         ret = s->diag;
 175         MISC_DPRINTF("Read diag %2.2x\n", ret);
 176         break;
 177     case MISC_MDM:
 178         ret = s->mctrl;
 179         MISC_DPRINTF("Read modem control %2.2x\n", ret);
 180         break;
 181     case MISC_PWR:
 182         MISC_DPRINTF("Read power management %2.2x\n", ret);
 183         break;
 184     }
 185     return ret;
 186 }
 187
 188 static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
 189     slavio_misc_mem_readb,
 190     slavio_misc_mem_readb,
 191     slavio_misc_mem_readb,
 192 };
 193
 194 static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
 195     slavio_misc_mem_writeb,
 196     slavio_misc_mem_writeb,
 197     slavio_misc_mem_writeb,
 198 };
 199
 200 static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
 201 {
 202     MiscState *s = opaque;
 203     uint32_t ret = 0, saddr;
 204
 205     saddr = addr & SYSCTRL_MAXADDR;
 206     switch (saddr) {
 207     case 0:
 208         ret = s->sysctrl;
 209         break;
 210     default:
 211         break;
 212     }
 213     MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
 214                  ret);
 215     return ret;
 216 }
 217
 218 static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
 219                                       uint32_t val)
 220 {
 221     MiscState *s = opaque;
 222     uint32_t saddr;
 223
 224     saddr = addr & SYSCTRL_MAXADDR;
 225     MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " =  %x\n", addr,
 226                  val);
 227     switch (saddr) {
 228     case 0:
 229         if (val & SYS_RESET) {
 230             s->sysctrl = SYS_RESETSTAT;
 231             qemu_system_reset_request();
 232         }
 233         break;
 234     default:
 235         break;
 236     }
 237 }
 238
 239 static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
 240     slavio_sysctrl_mem_readl,
 241     slavio_sysctrl_mem_readl,
 242     slavio_sysctrl_mem_readl,
 243 };
 244
 245 static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
 246     slavio_sysctrl_mem_writel,
 247     slavio_sysctrl_mem_writel,
 248     slavio_sysctrl_mem_writel,
 249 };
 250
 251 static uint32_t slavio_led_mem_reads(void *opaque, target_phys_addr_t addr)
 252 {
 253     MiscState *s = opaque;
 254     uint32_t ret = 0, saddr;
 255
 256     saddr = addr & LED_MAXADDR;
 257     switch (saddr) {
 258     case 0:
 259         ret = s->leds;
 260         break;
 261     default:
 262         break;
 263     }
 264     MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
 265                  ret);
 266     return ret;
 267 }
 268
 269 static void slavio_led_mem_writes(void *opaque, target_phys_addr_t addr,
 270                                   uint32_t val)
 271 {
 272     MiscState *s = opaque;
 273     uint32_t saddr;
 274
 275     saddr = addr & LED_MAXADDR;
 276     MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " =  %x\n", addr,
 277                  val);
 278     switch (saddr) {
 279     case 0:
 280         s->sysctrl = val;
 281         break;
 282     default:
 283         break;
 284     }
 285 }
 286
 287 static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
 288     slavio_led_mem_reads,
 289     slavio_led_mem_reads,
 290     slavio_led_mem_reads,
 291 };
 292
 293 static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
 294     slavio_led_mem_writes,
 295     slavio_led_mem_writes,
 296     slavio_led_mem_writes,
 297 };
 298
 299 static void slavio_misc_save(QEMUFile *f, void *opaque)
 300 {
 301     MiscState *s = opaque;
 302     int tmp;
 303     uint8_t tmp8;
 304
 305     tmp = 0;
 306     qemu_put_be32s(f, &tmp); /* ignored, was IRQ.  */
 307     qemu_put_8s(f, &s->config);
 308     qemu_put_8s(f, &s->aux1);
 309     qemu_put_8s(f, &s->aux2);
 310     qemu_put_8s(f, &s->diag);
 311     qemu_put_8s(f, &s->mctrl);
 312     tmp8 = s->sysctrl & 0xff;
 313     qemu_put_8s(f, &tmp8);
 314 }
 315
 316 static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
 317 {
 318     MiscState *s = opaque;
 319     int tmp;
 320     uint8_t tmp8;
 321
 322     if (version_id != 1)
 323         return -EINVAL;
 324
 325     qemu_get_be32s(f, &tmp);
 326     qemu_get_8s(f, &s->config);
 327     qemu_get_8s(f, &s->aux1);
 328     qemu_get_8s(f, &s->aux2);
 329     qemu_get_8s(f, &s->diag);
 330     qemu_get_8s(f, &s->mctrl);
 331     qemu_get_8s(f, &tmp8);
 332     s->sysctrl = (uint32_t)tmp8;
 333     return 0;
 334 }
 335
 336 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
 337                        qemu_irq irq)
 338 {
 339     int slavio_misc_io_memory;
 340     MiscState *s;
 341
 342     s = qemu_mallocz(sizeof(MiscState));
 343     if (!s)
 344         return NULL;
 345
 346     /* 8 bit registers */
 347     slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
 348                                                    slavio_misc_mem_write, s);
 349     // Slavio control
 350     cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE,
 351                                  slavio_misc_io_memory);
 352     // AUX 1
 353     cpu_register_physical_memory(base + MISC_AUX1, MISC_SIZE,
 354                                  slavio_misc_io_memory);
 355     // AUX 2
 356     cpu_register_physical_memory(base + MISC_AUX2, MISC_SIZE,
 357                                  slavio_misc_io_memory);
 358     // Diagnostics
 359     cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE,
 360                                  slavio_misc_io_memory);
 361     // Modem control
 362     cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE,
 363                                  slavio_misc_io_memory);
 364     // Power management
 365     cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
 366
 367     /* 16 bit registers */
 368     slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read,
 369                                                    slavio_led_mem_write, s);
 370     /* ss600mp diag LEDs */
 371     cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE,
 372                                  slavio_misc_io_memory);
 373
 374     /* 32 bit registers */
 375     slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
 376                                                    slavio_sysctrl_mem_write,
 377                                                    s);
 378     // System control
 379     cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE,
 380                                  slavio_misc_io_memory);
 381
 382     s->irq = irq;
 383
 384     register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
 385                     s);
 386     qemu_register_reset(slavio_misc_reset, s);
 387     slavio_misc_reset(s);
 388     return s;
 389 }