hw/slavio_timer.c

   1 /*
   2  * QEMU Sparc SLAVIO timer controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "qemu-timer.h"
  27
  28 //#define DEBUG_TIMER
  29
  30 #ifdef DEBUG_TIMER
  31 #define DPRINTF(fmt, args...) \
  32 do { printf("TIMER: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 /*
  38  * Registers of hardware timer in sun4m.
  39  *
  40  * This is the timer/counter part of chip STP2001 (Slave I/O), also
  41  * produced as NCR89C105. See
  42  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  43  *
  44  * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  45  * are zero. Bit 31 is 1 when count has been reached.
  46  *
  47  * Per-CPU timers interrupt local CPU, system timer uses normal
  48  * interrupt routing.
  49  *
  50  */
  51
  52 #define MAX_CPUS 16
  53
  54 typedef struct SLAVIO_TIMERState {
  55     qemu_irq irq;
  56     ptimer_state *timer;
  57     uint32_t count, counthigh, reached;
  58     uint64_t limit;
  59     // processor only
  60     int running;
  61     struct SLAVIO_TIMERState *master;
  62     int slave_index;
  63     // system only
  64     struct SLAVIO_TIMERState *slave[MAX_CPUS];
  65     uint32_t slave_mode;
  66 } SLAVIO_TIMERState;
  67
  68 #define TIMER_MAXADDR 0x1f
  69 #define SYS_TIMER_SIZE 0x14
  70 #define CPU_TIMER_SIZE 0x10
  71
  72 #define SYS_TIMER_OFFSET      0x10000ULL
  73 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
  74
  75 #define TIMER_LIMIT         0
  76 #define TIMER_COUNTER       1
  77 #define TIMER_COUNTER_NORST 2
  78 #define TIMER_STATUS        3
  79 #define TIMER_MODE          4
  80
  81 #define TIMER_COUNT_MASK32 0xfffffe00
  82 #define TIMER_LIMIT_MASK32 0x7fffffff
  83 #define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
  84 #define TIMER_MAX_COUNT32  0x7ffffe00ULL
  85 #define TIMER_REACHED      0x80000000
  86 #define TIMER_PERIOD       500ULL // 500ns
  87 #define LIMIT_TO_PERIODS(l) ((l) >> 9)
  88 #define PERIODS_TO_LIMIT(l) ((l) << 9)
  89
  90 static int slavio_timer_is_user(SLAVIO_TIMERState *s)
  91 {
  92     return s->master && (s->master->slave_mode & (1 << s->slave_index));
  93 }
  94
  95 // Update count, set irq, update expire_time
  96 // Convert from ptimer countdown units
  97 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
  98 {
  99     uint64_t count;
 100
 101     count = s->limit - PERIODS_TO_LIMIT(ptimer_get_count(s->timer));
 102     DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit,
 103             s->counthigh, s->count);
 104     s->count = count & TIMER_COUNT_MASK32;
 105     s->counthigh = count >> 32;
 106 }
 107
 108 // timer callback
 109 static void slavio_timer_irq(void *opaque)
 110 {
 111     SLAVIO_TIMERState *s = opaque;
 112
 113     slavio_timer_get_out(s);
 114     DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
 115     if (!slavio_timer_is_user(s)) {
 116         s->reached = TIMER_REACHED;
 117         qemu_irq_raise(s->irq);
 118     }
 119 }
 120
 121 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
 122 {
 123     SLAVIO_TIMERState *s = opaque;
 124     uint32_t saddr, ret;
 125
 126     saddr = (addr & TIMER_MAXADDR) >> 2;
 127     switch (saddr) {
 128     case TIMER_LIMIT:
 129         // read limit (system counter mode) or read most signifying
 130         // part of counter (user mode)
 131         if (slavio_timer_is_user(s)) {
 132             // read user timer MSW
 133             slavio_timer_get_out(s);
 134             ret = s->counthigh;
 135         } else {
 136             // read limit
 137             // clear irq
 138             qemu_irq_lower(s->irq);
 139             s->reached = 0;
 140             ret = s->limit & TIMER_LIMIT_MASK32;
 141         }
 142         break;
 143     case TIMER_COUNTER:
 144         // read counter and reached bit (system mode) or read lsbits
 145         // of counter (user mode)
 146         slavio_timer_get_out(s);
 147         if (slavio_timer_is_user(s)) // read user timer LSW
 148             ret = s->count & TIMER_COUNT_MASK32;
 149         else // read limit
 150             ret = (s->count & TIMER_MAX_COUNT32) | s->reached;
 151         break;
 152     case TIMER_STATUS:
 153         // only available in processor counter/timer
 154         // read start/stop status
 155         ret = s->running;
 156         break;
 157     case TIMER_MODE:
 158         // only available in system counter
 159         // read user/system mode
 160         ret = s->slave_mode;
 161         break;
 162     default:
 163         DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
 164         ret = 0;
 165         break;
 166     }
 167     DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
 168
 169     return ret;
 170 }
 171
 172 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
 173                                     uint32_t val)
 174 {
 175     SLAVIO_TIMERState *s = opaque;
 176     uint32_t saddr;
 177     int reload = 0;
 178
 179     DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
 180     saddr = (addr & TIMER_MAXADDR) >> 2;
 181     switch (saddr) {
 182     case TIMER_LIMIT:
 183         if (slavio_timer_is_user(s)) {
 184             // set user counter MSW, reset counter
 185             qemu_irq_lower(s->irq);
 186             s->limit = TIMER_MAX_COUNT64;
 187             DPRINTF("processor %d user timer reset\n", s->slave_index);
 188             ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
 189         } else {
 190             // set limit, reset counter
 191             qemu_irq_lower(s->irq);
 192             s->limit = val & TIMER_MAX_COUNT32;
 193             if (!s->limit)
 194                 s->limit = TIMER_MAX_COUNT32;
 195             ptimer_set_limit(s->timer, s->limit >> 9, 1);
 196         }
 197         break;
 198     case TIMER_COUNTER:
 199         if (slavio_timer_is_user(s)) {
 200             // set user counter LSW, reset counter
 201             qemu_irq_lower(s->irq);
 202             s->limit = TIMER_MAX_COUNT64;
 203             DPRINTF("processor %d user timer reset\n", s->slave_index);
 204             ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
 205         } else
 206             DPRINTF("not user timer\n");
 207         break;
 208     case TIMER_COUNTER_NORST:
 209         // set limit without resetting counter
 210         s->limit = val & TIMER_MAX_COUNT32;
 211         if (!s->limit)
 212             s->limit = TIMER_MAX_COUNT32;
 213         ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), reload);
 214         break;
 215     case TIMER_STATUS:
 216         if (slavio_timer_is_user(s)) {
 217             // start/stop user counter
 218             if ((val & 1) && !s->running) {
 219                 DPRINTF("processor %d user timer started\n", s->slave_index);
 220                 ptimer_run(s->timer, 0);
 221                 s->running = 1;
 222             } else if (!(val & 1) && s->running) {
 223                 DPRINTF("processor %d user timer stopped\n", s->slave_index);
 224                 ptimer_stop(s->timer);
 225                 s->running = 0;
 226             }
 227         }
 228         break;
 229     case TIMER_MODE:
 230         if (s->master == NULL) {
 231             unsigned int i;
 232
 233             for (i = 0; i < MAX_CPUS; i++) {
 234                 if (val & (1 << i)) {
 235                     qemu_irq_lower(s->slave[i]->irq);
 236                     s->slave[i]->limit = -1ULL;
 237                 }
 238                 if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
 239                     ptimer_stop(s->slave[i]->timer);
 240                     ptimer_set_limit(s->slave[i]->timer,
 241                                      LIMIT_TO_PERIODS(s->slave[i]->limit), 1);
 242                     DPRINTF("processor %d timer changed\n",
 243                             s->slave[i]->slave_index);
 244                     ptimer_run(s->slave[i]->timer, 0);
 245                 }
 246             }
 247             s->slave_mode = val & ((1 << MAX_CPUS) - 1);
 248         } else
 249             DPRINTF("not system timer\n");
 250         break;
 251     default:
 252         DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
 253         break;
 254     }
 255 }
 256
 257 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
 258     slavio_timer_mem_readl,
 259     slavio_timer_mem_readl,
 260     slavio_timer_mem_readl,
 261 };
 262
 263 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
 264     slavio_timer_mem_writel,
 265     slavio_timer_mem_writel,
 266     slavio_timer_mem_writel,
 267 };
 268
 269 static void slavio_timer_save(QEMUFile *f, void *opaque)
 270 {
 271     SLAVIO_TIMERState *s = opaque;
 272
 273     qemu_put_be64s(f, &s->limit);
 274     qemu_put_be32s(f, &s->count);
 275     qemu_put_be32s(f, &s->counthigh);
 276     qemu_put_be32(f, 0); // Was irq
 277     qemu_put_be32s(f, &s->reached);
 278     qemu_put_be32s(f, &s->running);
 279     qemu_put_be32s(f, 0); // Was mode
 280     qemu_put_ptimer(f, s->timer);
 281 }
 282
 283 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
 284 {
 285     SLAVIO_TIMERState *s = opaque;
 286     uint32_t tmp;
 287
 288     if (version_id != 2)
 289         return -EINVAL;
 290
 291     qemu_get_be64s(f, &s->limit);
 292     qemu_get_be32s(f, &s->count);
 293     qemu_get_be32s(f, &s->counthigh);
 294     qemu_get_be32s(f, &tmp); // Was irq
 295     qemu_get_be32s(f, &s->reached);
 296     qemu_get_be32s(f, &s->running);
 297     qemu_get_be32s(f, &tmp); // Was mode
 298     qemu_get_ptimer(f, s->timer);
 299
 300     return 0;
 301 }
 302
 303 static void slavio_timer_reset(void *opaque)
 304 {
 305     SLAVIO_TIMERState *s = opaque;
 306
 307     if (slavio_timer_is_user(s))
 308         s->limit = TIMER_MAX_COUNT64;
 309     else
 310         s->limit = TIMER_MAX_COUNT32;
 311     s->count = 0;
 312     s->reached = 0;
 313     ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
 314     ptimer_run(s->timer, 0);
 315     s->running = 1;
 316     qemu_irq_lower(s->irq);
 317 }
 318
 319 static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
 320                                             qemu_irq irq,
 321                                             SLAVIO_TIMERState *master,
 322                                             int slave_index)
 323 {
 324     int slavio_timer_io_memory;
 325     SLAVIO_TIMERState *s;
 326     QEMUBH *bh;
 327
 328     s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
 329     if (!s)
 330         return s;
 331     s->irq = irq;
 332     s->master = master;
 333     s->slave_index = slave_index;
 334     bh = qemu_bh_new(slavio_timer_irq, s);
 335     s->timer = ptimer_init(bh);
 336     ptimer_set_period(s->timer, TIMER_PERIOD);
 337
 338     slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
 339                                                     slavio_timer_mem_write, s);
 340     if (master)
 341         cpu_register_physical_memory(addr, CPU_TIMER_SIZE,
 342                                      slavio_timer_io_memory);
 343     else
 344         cpu_register_physical_memory(addr, SYS_TIMER_SIZE,
 345                                      slavio_timer_io_memory);
 346     register_savevm("slavio_timer", addr, 2, slavio_timer_save,
 347                     slavio_timer_load, s);
 348     qemu_register_reset(slavio_timer_reset, s);
 349     slavio_timer_reset(s);
 350
 351     return s;
 352 }
 353
 354 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
 355                            qemu_irq *cpu_irqs)
 356 {
 357     SLAVIO_TIMERState *master;
 358     unsigned int i;
 359
 360     master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0);
 361
 362     for (i = 0; i < MAX_CPUS; i++) {
 363         master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
 364                                              CPU_TIMER_OFFSET(i),
 365                                              cpu_irqs[i], master, i);
 366     }
 367 }