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Fix taddcctv and tsubcctv (David Matthews)
[qemu/qemu_0_9_1_stable.git] / vl.h
blobaa7590063e74fdb457724a19fddb0916404f3c00
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef likely
97 #if __GNUC__ < 3
98 #define __builtin_expect(x, n) (x)
99 #endif
100
101 #define likely(x) __builtin_expect(!!(x), 1)
102 #define unlikely(x) __builtin_expect(!!(x), 0)
103 #endif
104
105 #ifndef MIN
106 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
107 #endif
108 #ifndef MAX
109 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
110 #endif
111
112 #ifndef always_inline
113 #if (__GNUC__ < 3) || defined(__APPLE__)
114 #define always_inline inline
115 #else
116 #define always_inline __attribute__ (( always_inline )) inline
117 #endif
118 #endif
119
120 /* cutils.c */
121 void pstrcpy(char *buf, int buf_size, const char *str);
122 char *pstrcat(char *buf, int buf_size, const char *s);
123 int strstart(const char *str, const char *val, const char **ptr);
124 int stristart(const char *str, const char *val, const char **ptr);
125
126 /* vl.c */
127 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
128
129 void hw_error(const char *fmt, ...);
130
131 extern const char *bios_dir;
132 extern const char *bios_name;
133
134 extern int vm_running;
135 extern const char *qemu_name;
136
137 typedef struct vm_change_state_entry VMChangeStateEntry;
138 typedef void VMChangeStateHandler(void *opaque, int running);
139 typedef void VMStopHandler(void *opaque, int reason);
140
141 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
142 void *opaque);
143 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
144
145 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
146 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
147
148 void vm_start(void);
149 void vm_stop(int reason);
150
151 typedef void QEMUResetHandler(void *opaque);
152
153 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
154 void qemu_system_reset_request(void);
155 void qemu_system_shutdown_request(void);
156 void qemu_system_powerdown_request(void);
157 #if !defined(TARGET_SPARC)
158 // Please implement a power failure function to signal the OS
159 #define qemu_system_powerdown() do{}while(0)
160 #else
161 void qemu_system_powerdown(void);
162 #endif
163
164 void main_loop_wait(int timeout);
165
166 extern int ram_size;
167 extern int bios_size;
168 extern int rtc_utc;
169 extern int cirrus_vga_enabled;
170 extern int vmsvga_enabled;
171 extern int graphic_width;
172 extern int graphic_height;
173 extern int graphic_depth;
174 extern const char *keyboard_layout;
175 extern int kqemu_allowed;
176 extern int win2k_install_hack;
177 extern int alt_grab;
178 extern int usb_enabled;
179 extern int smp_cpus;
180 extern int cursor_hide;
181 extern int graphic_rotate;
182 extern int no_quit;
183 extern int semihosting_enabled;
184 extern int autostart;
185 extern int old_param;
186 extern const char *bootp_filename;
187
188 #define MAX_OPTION_ROMS 16
189 extern const char *option_rom[MAX_OPTION_ROMS];
190 extern int nb_option_roms;
191
192 #ifdef TARGET_SPARC
193 #define MAX_PROM_ENVS 128
194 extern const char *prom_envs[MAX_PROM_ENVS];
195 extern unsigned int nb_prom_envs;
196 #endif
197
198 /* XXX: make it dynamic */
199 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
200 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
201 #define BIOS_SIZE ((512 + 32) * 1024)
202 #elif defined(TARGET_MIPS)
203 #define BIOS_SIZE (4 * 1024 * 1024)
204 #endif
205
206 /* keyboard/mouse support */
207
208 #define MOUSE_EVENT_LBUTTON 0x01
209 #define MOUSE_EVENT_RBUTTON 0x02
210 #define MOUSE_EVENT_MBUTTON 0x04
211
212 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
213 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
214
215 typedef struct QEMUPutMouseEntry {
216 QEMUPutMouseEvent *qemu_put_mouse_event;
217 void *qemu_put_mouse_event_opaque;
218 int qemu_put_mouse_event_absolute;
219 char *qemu_put_mouse_event_name;
220
221 /* used internally by qemu for handling mice */
222 struct QEMUPutMouseEntry *next;
223 } QEMUPutMouseEntry;
224
225 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
226 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
227 void *opaque, int absolute,
228 const char *name);
229 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
230
231 void kbd_put_keycode(int keycode);
232 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
233 int kbd_mouse_is_absolute(void);
234
235 void do_info_mice(void);
236 void do_mouse_set(int index);
237
238 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
239 constants) */
240 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
241 #define QEMU_KEY_BACKSPACE 0x007f
242 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
243 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
244 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
245 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
246 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
247 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
248 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
249 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
250 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
251
252 #define QEMU_KEY_CTRL_UP 0xe400
253 #define QEMU_KEY_CTRL_DOWN 0xe401
254 #define QEMU_KEY_CTRL_LEFT 0xe402
255 #define QEMU_KEY_CTRL_RIGHT 0xe403
256 #define QEMU_KEY_CTRL_HOME 0xe404
257 #define QEMU_KEY_CTRL_END 0xe405
258 #define QEMU_KEY_CTRL_PAGEUP 0xe406
259 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
260
261 void kbd_put_keysym(int keysym);
262
263 /* async I/O support */
264
265 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
266 typedef int IOCanRWHandler(void *opaque);
267 typedef void IOHandler(void *opaque);
268
269 int qemu_set_fd_handler2(int fd,
270 IOCanRWHandler *fd_read_poll,
271 IOHandler *fd_read,
272 IOHandler *fd_write,
273 void *opaque);
274 int qemu_set_fd_handler(int fd,
275 IOHandler *fd_read,
276 IOHandler *fd_write,
277 void *opaque);
278
279 /* Polling handling */
280
281 /* return TRUE if no sleep should be done afterwards */
282 typedef int PollingFunc(void *opaque);
283
284 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
285 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
286
287 #ifdef _WIN32
288 /* Wait objects handling */
289 typedef void WaitObjectFunc(void *opaque);
290
291 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
292 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
293 #endif
294
295 typedef struct QEMUBH QEMUBH;
296
297 /* character device */
298
299 #define CHR_EVENT_BREAK 0 /* serial break char */
300 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
301 #define CHR_EVENT_RESET 2 /* new connection established */
302
303
304 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
305 typedef struct {
306 int speed;
307 int parity;
308 int data_bits;
309 int stop_bits;
310 } QEMUSerialSetParams;
311
312 #define CHR_IOCTL_SERIAL_SET_BREAK 2
313
314 #define CHR_IOCTL_PP_READ_DATA 3
315 #define CHR_IOCTL_PP_WRITE_DATA 4
316 #define CHR_IOCTL_PP_READ_CONTROL 5
317 #define CHR_IOCTL_PP_WRITE_CONTROL 6
318 #define CHR_IOCTL_PP_READ_STATUS 7
319 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
320 #define CHR_IOCTL_PP_EPP_READ 9
321 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
322 #define CHR_IOCTL_PP_EPP_WRITE 11
323
324 typedef void IOEventHandler(void *opaque, int event);
325
326 typedef struct CharDriverState {
327 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
328 void (*chr_update_read_handler)(struct CharDriverState *s);
329 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
330 IOEventHandler *chr_event;
331 IOCanRWHandler *chr_can_read;
332 IOReadHandler *chr_read;
333 void *handler_opaque;
334 void (*chr_send_event)(struct CharDriverState *chr, int event);
335 void (*chr_close)(struct CharDriverState *chr);
336 void *opaque;
337 int focus;
338 QEMUBH *bh;
339 } CharDriverState;
340
341 CharDriverState *qemu_chr_open(const char *filename);
342 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
343 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
344 void qemu_chr_send_event(CharDriverState *s, int event);
345 void qemu_chr_add_handlers(CharDriverState *s,
346 IOCanRWHandler *fd_can_read,
347 IOReadHandler *fd_read,
348 IOEventHandler *fd_event,
349 void *opaque);
350 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
351 void qemu_chr_reset(CharDriverState *s);
352 int qemu_chr_can_read(CharDriverState *s);
353 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
354
355 /* consoles */
356
357 typedef struct DisplayState DisplayState;
358 typedef struct TextConsole TextConsole;
359
360 typedef void (*vga_hw_update_ptr)(void *);
361 typedef void (*vga_hw_invalidate_ptr)(void *);
362 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
363
364 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
365 vga_hw_invalidate_ptr invalidate,
366 vga_hw_screen_dump_ptr screen_dump,
367 void *opaque);
368 void vga_hw_update(void);
369 void vga_hw_invalidate(void);
370 void vga_hw_screen_dump(const char *filename);
371
372 int is_graphic_console(void);
373 CharDriverState *text_console_init(DisplayState *ds, const char *p);
374 void console_select(unsigned int index);
375
376 /* serial ports */
377
378 #define MAX_SERIAL_PORTS 4
379
380 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
381
382 /* parallel ports */
383
384 #define MAX_PARALLEL_PORTS 3
385
386 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
387
388 struct ParallelIOArg {
389 void *buffer;
390 int count;
391 };
392
393 /* VLANs support */
394
395 typedef struct VLANClientState VLANClientState;
396
397 struct VLANClientState {
398 IOReadHandler *fd_read;
399 /* Packets may still be sent if this returns zero. It's used to
400 rate-limit the slirp code. */
401 IOCanRWHandler *fd_can_read;
402 void *opaque;
403 struct VLANClientState *next;
404 struct VLANState *vlan;
405 char info_str[256];
406 };
407
408 typedef struct VLANState {
409 int id;
410 VLANClientState *first_client;
411 struct VLANState *next;
412 unsigned int nb_guest_devs, nb_host_devs;
413 } VLANState;
414
415 VLANState *qemu_find_vlan(int id);
416 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
417 IOReadHandler *fd_read,
418 IOCanRWHandler *fd_can_read,
419 void *opaque);
420 int qemu_can_send_packet(VLANClientState *vc);
421 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
422 void qemu_handler_true(void *opaque);
423
424 void do_info_network(void);
425
426 /* TAP win32 */
427 int tap_win32_init(VLANState *vlan, const char *ifname);
428
429 /* NIC info */
430
431 #define MAX_NICS 8
432
433 typedef struct NICInfo {
434 uint8_t macaddr[6];
435 const char *model;
436 VLANState *vlan;
437 } NICInfo;
438
439 extern int nb_nics;
440 extern NICInfo nd_table[MAX_NICS];
441
442 /* timers */
443
444 typedef struct QEMUClock QEMUClock;
445 typedef struct QEMUTimer QEMUTimer;
446 typedef void QEMUTimerCB(void *opaque);
447
448 /* The real time clock should be used only for stuff which does not
449 change the virtual machine state, as it is run even if the virtual
450 machine is stopped. The real time clock has a frequency of 1000
451 Hz. */
452 extern QEMUClock *rt_clock;
453
454 /* The virtual clock is only run during the emulation. It is stopped
455 when the virtual machine is stopped. Virtual timers use a high
456 precision clock, usually cpu cycles (use ticks_per_sec). */
457 extern QEMUClock *vm_clock;
458
459 int64_t qemu_get_clock(QEMUClock *clock);
460
461 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
462 void qemu_free_timer(QEMUTimer *ts);
463 void qemu_del_timer(QEMUTimer *ts);
464 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
465 int qemu_timer_pending(QEMUTimer *ts);
466
467 extern int64_t ticks_per_sec;
468
469 int64_t cpu_get_ticks(void);
470 void cpu_enable_ticks(void);
471 void cpu_disable_ticks(void);
472
473 /* VM Load/Save */
474
475 typedef struct QEMUFile QEMUFile;
476
477 QEMUFile *qemu_fopen(const char *filename, const char *mode);
478 void qemu_fflush(QEMUFile *f);
479 void qemu_fclose(QEMUFile *f);
480 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
481 void qemu_put_byte(QEMUFile *f, int v);
482 void qemu_put_be16(QEMUFile *f, unsigned int v);
483 void qemu_put_be32(QEMUFile *f, unsigned int v);
484 void qemu_put_be64(QEMUFile *f, uint64_t v);
485 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
486 int qemu_get_byte(QEMUFile *f);
487 unsigned int qemu_get_be16(QEMUFile *f);
488 unsigned int qemu_get_be32(QEMUFile *f);
489 uint64_t qemu_get_be64(QEMUFile *f);
490
491 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
492 {
493 qemu_put_be64(f, *pv);
494 }
495
496 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
497 {
498 qemu_put_be32(f, *pv);
499 }
500
501 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
502 {
503 qemu_put_be16(f, *pv);
504 }
505
506 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
507 {
508 qemu_put_byte(f, *pv);
509 }
510
511 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
512 {
513 *pv = qemu_get_be64(f);
514 }
515
516 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
517 {
518 *pv = qemu_get_be32(f);
519 }
520
521 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
522 {
523 *pv = qemu_get_be16(f);
524 }
525
526 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
527 {
528 *pv = qemu_get_byte(f);
529 }
530
531 #if TARGET_LONG_BITS == 64
532 #define qemu_put_betl qemu_put_be64
533 #define qemu_get_betl qemu_get_be64
534 #define qemu_put_betls qemu_put_be64s
535 #define qemu_get_betls qemu_get_be64s
536 #else
537 #define qemu_put_betl qemu_put_be32
538 #define qemu_get_betl qemu_get_be32
539 #define qemu_put_betls qemu_put_be32s
540 #define qemu_get_betls qemu_get_be32s
541 #endif
542
543 int64_t qemu_ftell(QEMUFile *f);
544 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
545
546 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
547 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
548
549 int register_savevm(const char *idstr,
550 int instance_id,
551 int version_id,
552 SaveStateHandler *save_state,
553 LoadStateHandler *load_state,
554 void *opaque);
555 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
556 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
557
558 void cpu_save(QEMUFile *f, void *opaque);
559 int cpu_load(QEMUFile *f, void *opaque, int version_id);
560
561 void do_savevm(const char *name);
562 void do_loadvm(const char *name);
563 void do_delvm(const char *name);
564 void do_info_snapshots(void);
565
566 /* bottom halves */
567 typedef void QEMUBHFunc(void *opaque);
568
569 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
570 void qemu_bh_schedule(QEMUBH *bh);
571 void qemu_bh_cancel(QEMUBH *bh);
572 void qemu_bh_delete(QEMUBH *bh);
573 int qemu_bh_poll(void);
574
575 /* block.c */
576 typedef struct BlockDriverState BlockDriverState;
577 typedef struct BlockDriver BlockDriver;
578
579 extern BlockDriver bdrv_raw;
580 extern BlockDriver bdrv_host_device;
581 extern BlockDriver bdrv_cow;
582 extern BlockDriver bdrv_qcow;
583 extern BlockDriver bdrv_vmdk;
584 extern BlockDriver bdrv_cloop;
585 extern BlockDriver bdrv_dmg;
586 extern BlockDriver bdrv_bochs;
587 extern BlockDriver bdrv_vpc;
588 extern BlockDriver bdrv_vvfat;
589 extern BlockDriver bdrv_qcow2;
590 extern BlockDriver bdrv_parallels;
591
592 typedef struct BlockDriverInfo {
593 /* in bytes, 0 if irrelevant */
594 int cluster_size;
595 /* offset at which the VM state can be saved (0 if not possible) */
596 int64_t vm_state_offset;
597 } BlockDriverInfo;
598
599 typedef struct QEMUSnapshotInfo {
600 char id_str[128]; /* unique snapshot id */
601 /* the following fields are informative. They are not needed for
602 the consistency of the snapshot */
603 char name[256]; /* user choosen name */
604 uint32_t vm_state_size; /* VM state info size */
605 uint32_t date_sec; /* UTC date of the snapshot */
606 uint32_t date_nsec;
607 uint64_t vm_clock_nsec; /* VM clock relative to boot */
608 } QEMUSnapshotInfo;
609
610 #define BDRV_O_RDONLY 0x0000
611 #define BDRV_O_RDWR 0x0002
612 #define BDRV_O_ACCESS 0x0003
613 #define BDRV_O_CREAT 0x0004 /* create an empty file */
614 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
615 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
616 use a disk image format on top of
617 it (default for
618 bdrv_file_open()) */
619
620 void bdrv_init(void);
621 BlockDriver *bdrv_find_format(const char *format_name);
622 int bdrv_create(BlockDriver *drv,
623 const char *filename, int64_t size_in_sectors,
624 const char *backing_file, int flags);
625 BlockDriverState *bdrv_new(const char *device_name);
626 void bdrv_delete(BlockDriverState *bs);
627 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
628 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
629 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
630 BlockDriver *drv);
631 void bdrv_close(BlockDriverState *bs);
632 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
633 uint8_t *buf, int nb_sectors);
634 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
635 const uint8_t *buf, int nb_sectors);
636 int bdrv_pread(BlockDriverState *bs, int64_t offset,
637 void *buf, int count);
638 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
639 const void *buf, int count);
640 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
641 int64_t bdrv_getlength(BlockDriverState *bs);
642 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
643 int bdrv_commit(BlockDriverState *bs);
644 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
645 /* async block I/O */
646 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
647 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
648
649 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
650 uint8_t *buf, int nb_sectors,
651 BlockDriverCompletionFunc *cb, void *opaque);
652 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
653 const uint8_t *buf, int nb_sectors,
654 BlockDriverCompletionFunc *cb, void *opaque);
655 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
656
657 void qemu_aio_init(void);
658 void qemu_aio_poll(void);
659 void qemu_aio_flush(void);
660 void qemu_aio_wait_start(void);
661 void qemu_aio_wait(void);
662 void qemu_aio_wait_end(void);
663
664 int qemu_key_check(BlockDriverState *bs, const char *name);
665
666 /* Ensure contents are flushed to disk. */
667 void bdrv_flush(BlockDriverState *bs);
668
669 #define BDRV_TYPE_HD 0
670 #define BDRV_TYPE_CDROM 1
671 #define BDRV_TYPE_FLOPPY 2
672 #define BIOS_ATA_TRANSLATION_AUTO 0
673 #define BIOS_ATA_TRANSLATION_NONE 1
674 #define BIOS_ATA_TRANSLATION_LBA 2
675 #define BIOS_ATA_TRANSLATION_LARGE 3
676 #define BIOS_ATA_TRANSLATION_RECHS 4
677
678 void bdrv_set_geometry_hint(BlockDriverState *bs,
679 int cyls, int heads, int secs);
680 void bdrv_set_type_hint(BlockDriverState *bs, int type);
681 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
682 void bdrv_get_geometry_hint(BlockDriverState *bs,
683 int *pcyls, int *pheads, int *psecs);
684 int bdrv_get_type_hint(BlockDriverState *bs);
685 int bdrv_get_translation_hint(BlockDriverState *bs);
686 int bdrv_is_removable(BlockDriverState *bs);
687 int bdrv_is_read_only(BlockDriverState *bs);
688 int bdrv_is_inserted(BlockDriverState *bs);
689 int bdrv_media_changed(BlockDriverState *bs);
690 int bdrv_is_locked(BlockDriverState *bs);
691 void bdrv_set_locked(BlockDriverState *bs, int locked);
692 void bdrv_eject(BlockDriverState *bs, int eject_flag);
693 void bdrv_set_change_cb(BlockDriverState *bs,
694 void (*change_cb)(void *opaque), void *opaque);
695 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
696 void bdrv_info(void);
697 BlockDriverState *bdrv_find(const char *name);
698 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
699 int bdrv_is_encrypted(BlockDriverState *bs);
700 int bdrv_set_key(BlockDriverState *bs, const char *key);
701 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
702 void *opaque);
703 const char *bdrv_get_device_name(BlockDriverState *bs);
704 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
705 const uint8_t *buf, int nb_sectors);
706 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
707
708 void bdrv_get_backing_filename(BlockDriverState *bs,
709 char *filename, int filename_size);
710 int bdrv_snapshot_create(BlockDriverState *bs,
711 QEMUSnapshotInfo *sn_info);
712 int bdrv_snapshot_goto(BlockDriverState *bs,
713 const char *snapshot_id);
714 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
715 int bdrv_snapshot_list(BlockDriverState *bs,
716 QEMUSnapshotInfo **psn_info);
717 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
718
719 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
720 int path_is_absolute(const char *path);
721 void path_combine(char *dest, int dest_size,
722 const char *base_path,
723 const char *filename);
724
725 #ifndef QEMU_TOOL
726
727 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
728 int boot_device,
729 DisplayState *ds, const char **fd_filename, int snapshot,
730 const char *kernel_filename, const char *kernel_cmdline,
731 const char *initrd_filename, const char *cpu_model);
732
733 typedef struct QEMUMachine {
734 const char *name;
735 const char *desc;
736 QEMUMachineInitFunc *init;
737 struct QEMUMachine *next;
738 } QEMUMachine;
739
740 int qemu_register_machine(QEMUMachine *m);
741
742 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
743
744 #if defined(TARGET_PPC)
745 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
746 #endif
747
748 #if defined(TARGET_MIPS)
749 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
750 #endif
751
752 #include "hw/irq.h"
753
754 /* ISA bus */
755
756 extern target_phys_addr_t isa_mem_base;
757
758 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
759 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
760
761 int register_ioport_read(int start, int length, int size,
762 IOPortReadFunc *func, void *opaque);
763 int register_ioport_write(int start, int length, int size,
764 IOPortWriteFunc *func, void *opaque);
765 void isa_unassign_ioport(int start, int length);
766
767 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
768
769 /* PCI bus */
770
771 extern target_phys_addr_t pci_mem_base;
772
773 typedef struct PCIBus PCIBus;
774 typedef struct PCIDevice PCIDevice;
775
776 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
777 uint32_t address, uint32_t data, int len);
778 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
779 uint32_t address, int len);
780 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
781 uint32_t addr, uint32_t size, int type);
782
783 #define PCI_ADDRESS_SPACE_MEM 0x00
784 #define PCI_ADDRESS_SPACE_IO 0x01
785 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
786
787 typedef struct PCIIORegion {
788 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
789 uint32_t size;
790 uint8_t type;
791 PCIMapIORegionFunc *map_func;
792 } PCIIORegion;
793
794 #define PCI_ROM_SLOT 6
795 #define PCI_NUM_REGIONS 7
796
797 #define PCI_DEVICES_MAX 64
798
799 #define PCI_VENDOR_ID 0x00 /* 16 bits */
800 #define PCI_DEVICE_ID 0x02 /* 16 bits */
801 #define PCI_COMMAND 0x04 /* 16 bits */
802 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
803 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
804 #define PCI_CLASS_DEVICE 0x0a /* Device class */
805 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
806 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
807 #define PCI_MIN_GNT 0x3e /* 8 bits */
808 #define PCI_MAX_LAT 0x3f /* 8 bits */
809
810 struct PCIDevice {
811 /* PCI config space */
812 uint8_t config[256];
813
814 /* the following fields are read only */
815 PCIBus *bus;
816 int devfn;
817 char name[64];
818 PCIIORegion io_regions[PCI_NUM_REGIONS];
819
820 /* do not access the following fields */
821 PCIConfigReadFunc *config_read;
822 PCIConfigWriteFunc *config_write;
823 /* ??? This is a PC-specific hack, and should be removed. */
824 int irq_index;
825
826 /* IRQ objects for the INTA-INTD pins. */
827 qemu_irq *irq;
828
829 /* Current IRQ levels. Used internally by the generic PCI code. */
830 int irq_state[4];
831 };
832
833 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
834 int instance_size, int devfn,
835 PCIConfigReadFunc *config_read,
836 PCIConfigWriteFunc *config_write);
837
838 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
839 uint32_t size, int type,
840 PCIMapIORegionFunc *map_func);
841
842 uint32_t pci_default_read_config(PCIDevice *d,
843 uint32_t address, int len);
844 void pci_default_write_config(PCIDevice *d,
845 uint32_t address, uint32_t val, int len);
846 void pci_device_save(PCIDevice *s, QEMUFile *f);
847 int pci_device_load(PCIDevice *s, QEMUFile *f);
848
849 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
850 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
851 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
852 qemu_irq *pic, int devfn_min, int nirq);
853
854 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
855 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
856 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
857 int pci_bus_num(PCIBus *s);
858 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
859
860 void pci_info(void);
861 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
862 pci_map_irq_fn map_irq, const char *name);
863
864 /* prep_pci.c */
865 PCIBus *pci_prep_init(qemu_irq *pic);
866
867 /* grackle_pci.c */
868 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
869
870 /* unin_pci.c */
871 PCIBus *pci_pmac_init(qemu_irq *pic);
872
873 /* apb_pci.c */
874 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
875 qemu_irq *pic);
876
877 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
878
879 /* piix_pci.c */
880 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
881 void i440fx_set_smm(PCIDevice *d, int val);
882 int piix3_init(PCIBus *bus, int devfn);
883 void i440fx_init_memory_mappings(PCIDevice *d);
884
885 int piix4_init(PCIBus *bus, int devfn);
886
887 /* openpic.c */
888 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
889 enum {
890 OPENPIC_OUTPUT_INT = 0, /* IRQ */
891 OPENPIC_OUTPUT_CINT, /* critical IRQ */
892 OPENPIC_OUTPUT_MCK, /* Machine check event */
893 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
894 OPENPIC_OUTPUT_RESET, /* Core reset event */
895 OPENPIC_OUTPUT_NB,
896 };
897 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
898 qemu_irq **irqs, qemu_irq irq_out);
899
900 /* heathrow_pic.c */
901 qemu_irq *heathrow_pic_init(int *pmem_index);
902
903 /* gt64xxx.c */
904 PCIBus *pci_gt64120_init(qemu_irq *pic);
905
906 #ifdef HAS_AUDIO
907 struct soundhw {
908 const char *name;
909 const char *descr;
910 int enabled;
911 int isa;
912 union {
913 int (*init_isa) (AudioState *s, qemu_irq *pic);
914 int (*init_pci) (PCIBus *bus, AudioState *s);
915 } init;
916 };
917
918 extern struct soundhw soundhw[];
919 #endif
920
921 /* vga.c */
922
923 #ifndef TARGET_SPARC
924 #define VGA_RAM_SIZE (8192 * 1024)
925 #else
926 #define VGA_RAM_SIZE (9 * 1024 * 1024)
927 #endif
928
929 struct DisplayState {
930 uint8_t *data;
931 int linesize;
932 int depth;
933 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
934 int width;
935 int height;
936 void *opaque;
937 QEMUTimer *gui_timer;
938
939 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
940 void (*dpy_resize)(struct DisplayState *s, int w, int h);
941 void (*dpy_refresh)(struct DisplayState *s);
942 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
943 int dst_x, int dst_y, int w, int h);
944 void (*dpy_fill)(struct DisplayState *s, int x, int y,
945 int w, int h, uint32_t c);
946 void (*mouse_set)(int x, int y, int on);
947 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
948 uint8_t *image, uint8_t *mask);
949 };
950
951 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
952 {
953 s->dpy_update(s, x, y, w, h);
954 }
955
956 static inline void dpy_resize(DisplayState *s, int w, int h)
957 {
958 s->dpy_resize(s, w, h);
959 }
960
961 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
962 unsigned long vga_ram_offset, int vga_ram_size);
963 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
964 unsigned long vga_ram_offset, int vga_ram_size,
965 unsigned long vga_bios_offset, int vga_bios_size);
966 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
967 unsigned long vga_ram_offset, int vga_ram_size,
968 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
969 int it_shift);
970
971 /* cirrus_vga.c */
972 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
973 unsigned long vga_ram_offset, int vga_ram_size);
974 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
975 unsigned long vga_ram_offset, int vga_ram_size);
976
977 /* vmware_vga.c */
978 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
979 unsigned long vga_ram_offset, int vga_ram_size);
980
981 /* sdl.c */
982 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
983
984 /* cocoa.m */
985 void cocoa_display_init(DisplayState *ds, int full_screen);
986
987 /* vnc.c */
988 void vnc_display_init(DisplayState *ds);
989 void vnc_display_close(DisplayState *ds);
990 int vnc_display_open(DisplayState *ds, const char *display);
991 int vnc_display_password(DisplayState *ds, const char *password);
992 void do_info_vnc(void);
993
994 /* x_keymap.c */
995 extern uint8_t _translate_keycode(const int key);
996
997 /* ide.c */
998 #define MAX_DISKS 4
999
1000 extern BlockDriverState *bs_table[MAX_DISKS + 1];
1001 extern BlockDriverState *sd_bdrv;
1002 extern BlockDriverState *mtd_bdrv;
1003
1004 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1005 BlockDriverState *hd0, BlockDriverState *hd1);
1006 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1007 int secondary_ide_enabled);
1008 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1009 qemu_irq *pic);
1010 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1011 qemu_irq *pic);
1012 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
1013
1014 /* cdrom.c */
1015 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1016 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1017
1018 /* ds1225y.c */
1019 typedef struct ds1225y_t ds1225y_t;
1020 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1021
1022 /* es1370.c */
1023 int es1370_init (PCIBus *bus, AudioState *s);
1024
1025 /* sb16.c */
1026 int SB16_init (AudioState *s, qemu_irq *pic);
1027
1028 /* adlib.c */
1029 int Adlib_init (AudioState *s, qemu_irq *pic);
1030
1031 /* gus.c */
1032 int GUS_init (AudioState *s, qemu_irq *pic);
1033
1034 /* dma.c */
1035 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1036 int DMA_get_channel_mode (int nchan);
1037 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1038 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1039 void DMA_hold_DREQ (int nchan);
1040 void DMA_release_DREQ (int nchan);
1041 void DMA_schedule(int nchan);
1042 void DMA_run (void);
1043 void DMA_init (int high_page_enable);
1044 void DMA_register_channel (int nchan,
1045 DMA_transfer_handler transfer_handler,
1046 void *opaque);
1047 /* fdc.c */
1048 #define MAX_FD 2
1049 extern BlockDriverState *fd_table[MAX_FD];
1050
1051 typedef struct fdctrl_t fdctrl_t;
1052
1053 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1054 target_phys_addr_t io_base,
1055 BlockDriverState **fds);
1056 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1057
1058 /* eepro100.c */
1059
1060 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1061 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1062 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1063
1064 /* ne2000.c */
1065
1066 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1067 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1068
1069 /* rtl8139.c */
1070
1071 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1072
1073 /* pcnet.c */
1074
1075 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1076 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1077 qemu_irq irq, qemu_irq *reset);
1078
1079 /* vmmouse.c */
1080 void *vmmouse_init(void *m);
1081
1082 /* vmport.c */
1083 #ifdef TARGET_I386
1084 void vmport_init(CPUState *env);
1085 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1086 #endif
1087
1088 /* pckbd.c */
1089
1090 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1091 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1092 target_phys_addr_t base, int it_shift);
1093
1094 /* mc146818rtc.c */
1095
1096 typedef struct RTCState RTCState;
1097
1098 RTCState *rtc_init(int base, qemu_irq irq);
1099 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1100 void rtc_set_memory(RTCState *s, int addr, int val);
1101 void rtc_set_date(RTCState *s, const struct tm *tm);
1102
1103 /* serial.c */
1104
1105 typedef struct SerialState SerialState;
1106 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1107 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1108 qemu_irq irq, CharDriverState *chr,
1109 int ioregister);
1110 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1111 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1112 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1113 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1114 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1115 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1116
1117 /* parallel.c */
1118
1119 typedef struct ParallelState ParallelState;
1120 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1121 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1122
1123 /* i8259.c */
1124
1125 typedef struct PicState2 PicState2;
1126 extern PicState2 *isa_pic;
1127 void pic_set_irq(int irq, int level);
1128 void pic_set_irq_new(void *opaque, int irq, int level);
1129 qemu_irq *i8259_init(qemu_irq parent_irq);
1130 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1131 void *alt_irq_opaque);
1132 int pic_read_irq(PicState2 *s);
1133 void pic_update_irq(PicState2 *s);
1134 uint32_t pic_intack_read(PicState2 *s);
1135 void pic_info(void);
1136 void irq_info(void);
1137
1138 /* APIC */
1139 typedef struct IOAPICState IOAPICState;
1140
1141 int apic_init(CPUState *env);
1142 int apic_accept_pic_intr(CPUState *env);
1143 int apic_get_interrupt(CPUState *env);
1144 IOAPICState *ioapic_init(void);
1145 void ioapic_set_irq(void *opaque, int vector, int level);
1146
1147 /* i8254.c */
1148
1149 #define PIT_FREQ 1193182
1150
1151 typedef struct PITState PITState;
1152
1153 PITState *pit_init(int base, qemu_irq irq);
1154 void pit_set_gate(PITState *pit, int channel, int val);
1155 int pit_get_gate(PITState *pit, int channel);
1156 int pit_get_initial_count(PITState *pit, int channel);
1157 int pit_get_mode(PITState *pit, int channel);
1158 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1159
1160 /* jazz_led.c */
1161 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1162
1163 /* pcspk.c */
1164 void pcspk_init(PITState *);
1165 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1166
1167 #include "hw/i2c.h"
1168
1169 #include "hw/smbus.h"
1170
1171 /* acpi.c */
1172 extern int acpi_enabled;
1173 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1174 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1175 void acpi_bios_init(void);
1176
1177 /* Axis ETRAX. */
1178 extern QEMUMachine bareetraxfs_machine;
1179
1180 /* pc.c */
1181 extern QEMUMachine pc_machine;
1182 extern QEMUMachine isapc_machine;
1183 extern int fd_bootchk;
1184
1185 void ioport_set_a20(int enable);
1186 int ioport_get_a20(void);
1187
1188 /* ppc.c */
1189 extern QEMUMachine prep_machine;
1190 extern QEMUMachine core99_machine;
1191 extern QEMUMachine heathrow_machine;
1192 extern QEMUMachine ref405ep_machine;
1193 extern QEMUMachine taihu_machine;
1194
1195 /* mips_r4k.c */
1196 extern QEMUMachine mips_machine;
1197
1198 /* mips_malta.c */
1199 extern QEMUMachine mips_malta_machine;
1200
1201 /* mips_int.c */
1202 extern void cpu_mips_irq_init_cpu(CPUState *env);
1203
1204 /* mips_pica61.c */
1205 extern QEMUMachine mips_pica61_machine;
1206
1207 /* mips_timer.c */
1208 extern void cpu_mips_clock_init(CPUState *);
1209 extern void cpu_mips_irqctrl_init (void);
1210
1211 /* shix.c */
1212 extern QEMUMachine shix_machine;
1213
1214 /* r2d.c */
1215 extern QEMUMachine r2d_machine;
1216
1217 #ifdef TARGET_PPC
1218 /* PowerPC hardware exceptions management helpers */
1219 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1220 typedef struct clk_setup_t clk_setup_t;
1221 struct clk_setup_t {
1222 clk_setup_cb cb;
1223 void *opaque;
1224 };
1225 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1226 {
1227 if (clk->cb != NULL)
1228 (*clk->cb)(clk->opaque, freq);
1229 }
1230
1231 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1232 /* Embedded PowerPC DCR management */
1233 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1234 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1235 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1236 int (*dcr_write_error)(int dcrn));
1237 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1238 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1239 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1240 /* Embedded PowerPC reset */
1241 void ppc40x_core_reset (CPUState *env);
1242 void ppc40x_chip_reset (CPUState *env);
1243 void ppc40x_system_reset (CPUState *env);
1244 #endif
1245 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1246
1247 extern CPUWriteMemoryFunc *PPC_io_write[];
1248 extern CPUReadMemoryFunc *PPC_io_read[];
1249 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1250
1251 /* sun4m.c */
1252 extern QEMUMachine ss5_machine, ss10_machine;
1253
1254 /* iommu.c */
1255 void *iommu_init(target_phys_addr_t addr);
1256 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1257 uint8_t *buf, int len, int is_write);
1258 static inline void sparc_iommu_memory_read(void *opaque,
1259 target_phys_addr_t addr,
1260 uint8_t *buf, int len)
1261 {
1262 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1263 }
1264
1265 static inline void sparc_iommu_memory_write(void *opaque,
1266 target_phys_addr_t addr,
1267 uint8_t *buf, int len)
1268 {
1269 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1270 }
1271
1272 /* tcx.c */
1273 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1274 unsigned long vram_offset, int vram_size, int width, int height,
1275 int depth);
1276
1277 /* slavio_intctl.c */
1278 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1279 const uint32_t *intbit_to_level,
1280 qemu_irq **irq, qemu_irq **cpu_irq,
1281 qemu_irq **parent_irq, unsigned int cputimer);
1282 void slavio_pic_info(void *opaque);
1283 void slavio_irq_info(void *opaque);
1284
1285 /* loader.c */
1286 int get_image_size(const char *filename);
1287 int load_image(const char *filename, uint8_t *addr);
1288 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1289 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1290 int load_aout(const char *filename, uint8_t *addr);
1291 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1292
1293 /* slavio_timer.c */
1294 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1295 qemu_irq *cpu_irqs);
1296
1297 /* slavio_serial.c */
1298 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1299 CharDriverState *chr1, CharDriverState *chr2);
1300 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1301
1302 /* slavio_misc.c */
1303 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1304 qemu_irq irq);
1305 void slavio_set_power_fail(void *opaque, int power_failing);
1306
1307 /* esp.c */
1308 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1309 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1310 void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1311
1312 /* sparc32_dma.c */
1313 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1314 void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1315 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1316 uint8_t *buf, int len, int do_bswap);
1317 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1318 uint8_t *buf, int len, int do_bswap);
1319 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1320 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1321
1322 /* cs4231.c */
1323 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1324
1325 /* sun4u.c */
1326 extern QEMUMachine sun4u_machine;
1327
1328 /* NVRAM helpers */
1329 #include "hw/m48t59.h"
1330
1331 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1332 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1333 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1334 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1335 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1336 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1337 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1338 const unsigned char *str, uint32_t max);
1339 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1340 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1341 uint32_t start, uint32_t count);
1342 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1343 const unsigned char *arch,
1344 uint32_t RAM_size, int boot_device,
1345 uint32_t kernel_image, uint32_t kernel_size,
1346 const char *cmdline,
1347 uint32_t initrd_image, uint32_t initrd_size,
1348 uint32_t NVRAM_image,
1349 int width, int height, int depth);
1350
1351 /* adb.c */
1352
1353 #define MAX_ADB_DEVICES 16
1354
1355 #define ADB_MAX_OUT_LEN 16
1356
1357 typedef struct ADBDevice ADBDevice;
1358
1359 /* buf = NULL means polling */
1360 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1361 const uint8_t *buf, int len);
1362 typedef int ADBDeviceReset(ADBDevice *d);
1363
1364 struct ADBDevice {
1365 struct ADBBusState *bus;
1366 int devaddr;
1367 int handler;
1368 ADBDeviceRequest *devreq;
1369 ADBDeviceReset *devreset;
1370 void *opaque;
1371 };
1372
1373 typedef struct ADBBusState {
1374 ADBDevice devices[MAX_ADB_DEVICES];
1375 int nb_devices;
1376 int poll_index;
1377 } ADBBusState;
1378
1379 int adb_request(ADBBusState *s, uint8_t *buf_out,
1380 const uint8_t *buf, int len);
1381 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1382
1383 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1384 ADBDeviceRequest *devreq,
1385 ADBDeviceReset *devreset,
1386 void *opaque);
1387 void adb_kbd_init(ADBBusState *bus);
1388 void adb_mouse_init(ADBBusState *bus);
1389
1390 /* cuda.c */
1391
1392 extern ADBBusState adb_bus;
1393 int cuda_init(qemu_irq irq);
1394
1395 #include "hw/usb.h"
1396
1397 /* usb ports of the VM */
1398
1399 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1400 usb_attachfn attach);
1401
1402 #define VM_USB_HUB_SIZE 8
1403
1404 void do_usb_add(const char *devname);
1405 void do_usb_del(const char *devname);
1406 void usb_info(void);
1407
1408 /* scsi-disk.c */
1409 enum scsi_reason {
1410 SCSI_REASON_DONE, /* Command complete. */
1411 SCSI_REASON_DATA /* Transfer complete, more data required. */
1412 };
1413
1414 typedef struct SCSIDevice SCSIDevice;
1415 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1416 uint32_t arg);
1417
1418 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1419 int tcq,
1420 scsi_completionfn completion,
1421 void *opaque);
1422 void scsi_disk_destroy(SCSIDevice *s);
1423
1424 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1425 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1426 layer the completion routine may be called directly by
1427 scsi_{read,write}_data. */
1428 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1429 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1430 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1431 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1432
1433 /* lsi53c895a.c */
1434 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1435 void *lsi_scsi_init(PCIBus *bus, int devfn);
1436
1437 /* integratorcp.c */
1438 extern QEMUMachine integratorcp_machine;
1439
1440 /* versatilepb.c */
1441 extern QEMUMachine versatilepb_machine;
1442 extern QEMUMachine versatileab_machine;
1443
1444 /* realview.c */
1445 extern QEMUMachine realview_machine;
1446
1447 /* spitz.c */
1448 extern QEMUMachine akitapda_machine;
1449 extern QEMUMachine spitzpda_machine;
1450 extern QEMUMachine borzoipda_machine;
1451 extern QEMUMachine terrierpda_machine;
1452
1453 /* palm.c */
1454 extern QEMUMachine palmte_machine;
1455
1456 /* ps2.c */
1457 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1458 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1459 void ps2_write_mouse(void *, int val);
1460 void ps2_write_keyboard(void *, int val);
1461 uint32_t ps2_read_data(void *);
1462 void ps2_queue(void *, int b);
1463 void ps2_keyboard_set_translation(void *opaque, int mode);
1464 void ps2_mouse_fake_event(void *opaque);
1465
1466 /* smc91c111.c */
1467 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1468
1469 /* pl031.c */
1470 void pl031_init(uint32_t base, qemu_irq irq);
1471
1472 /* pl110.c */
1473 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1474
1475 /* pl011.c */
1476 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1477
1478 /* pl050.c */
1479 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1480
1481 /* pl080.c */
1482 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1483
1484 /* pl181.c */
1485 void pl181_init(uint32_t base, BlockDriverState *bd,
1486 qemu_irq irq0, qemu_irq irq1);
1487
1488 /* pl190.c */
1489 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1490
1491 /* arm-timer.c */
1492 void sp804_init(uint32_t base, qemu_irq irq);
1493 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1494
1495 /* arm_sysctl.c */
1496 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1497
1498 /* arm_gic.c */
1499 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1500
1501 /* arm_boot.c */
1502
1503 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1504 const char *kernel_cmdline, const char *initrd_filename,
1505 int board_id, target_phys_addr_t loader_start);
1506
1507 /* sh7750.c */
1508 struct SH7750State;
1509
1510 struct SH7750State *sh7750_init(CPUState * cpu);
1511
1512 typedef struct {
1513 /* The callback will be triggered if any of the designated lines change */
1514 uint16_t portamask_trigger;
1515 uint16_t portbmask_trigger;
1516 /* Return 0 if no action was taken */
1517 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1518 uint16_t * periph_pdtra,
1519 uint16_t * periph_portdira,
1520 uint16_t * periph_pdtrb,
1521 uint16_t * periph_portdirb);
1522 } sh7750_io_device;
1523
1524 int sh7750_register_io_device(struct SH7750State *s,
1525 sh7750_io_device * device);
1526 /* sh_timer.c */
1527 #define TMU012_FEAT_TOCR (1 << 0)
1528 #define TMU012_FEAT_3CHAN (1 << 1)
1529 #define TMU012_FEAT_EXTCLK (1 << 2)
1530 void tmu012_init(uint32_t base, int feat, uint32_t freq);
1531
1532 /* sh_serial.c */
1533 #define SH_SERIAL_FEAT_SCIF (1 << 0)
1534 void sh_serial_init (target_phys_addr_t base, int feat,
1535 uint32_t freq, CharDriverState *chr);
1536
1537 /* tc58128.c */
1538 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1539
1540 /* NOR flash devices */
1541 #define MAX_PFLASH 4
1542 extern BlockDriverState *pflash_table[MAX_PFLASH];
1543 typedef struct pflash_t pflash_t;
1544
1545 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1546 BlockDriverState *bs,
1547 uint32_t sector_len, int nb_blocs, int width,
1548 uint16_t id0, uint16_t id1,
1549 uint16_t id2, uint16_t id3);
1550
1551 /* nand.c */
1552 struct nand_flash_s;
1553 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1554 void nand_done(struct nand_flash_s *s);
1555 void nand_setpins(struct nand_flash_s *s,
1556 int cle, int ale, int ce, int wp, int gnd);
1557 void nand_getpins(struct nand_flash_s *s, int *rb);
1558 void nand_setio(struct nand_flash_s *s, uint8_t value);
1559 uint8_t nand_getio(struct nand_flash_s *s);
1560
1561 #define NAND_MFR_TOSHIBA 0x98
1562 #define NAND_MFR_SAMSUNG 0xec
1563 #define NAND_MFR_FUJITSU 0x04
1564 #define NAND_MFR_NATIONAL 0x8f
1565 #define NAND_MFR_RENESAS 0x07
1566 #define NAND_MFR_STMICRO 0x20
1567 #define NAND_MFR_HYNIX 0xad
1568 #define NAND_MFR_MICRON 0x2c
1569
1570 /* ecc.c */
1571 struct ecc_state_s {
1572 uint8_t cp; /* Column parity */
1573 uint16_t lp[2]; /* Line parity */
1574 uint16_t count;
1575 };
1576
1577 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1578 void ecc_reset(struct ecc_state_s *s);
1579 void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1580 void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1581
1582 /* GPIO */
1583 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1584
1585 /* ads7846.c */
1586 struct ads7846_state_s;
1587 uint32_t ads7846_read(void *opaque);
1588 void ads7846_write(void *opaque, uint32_t value);
1589 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1590
1591 /* max111x.c */
1592 struct max111x_s;
1593 uint32_t max111x_read(void *opaque);
1594 void max111x_write(void *opaque, uint32_t value);
1595 struct max111x_s *max1110_init(qemu_irq cb);
1596 struct max111x_s *max1111_init(qemu_irq cb);
1597 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1598
1599 /* PCMCIA/Cardbus */
1600
1601 struct pcmcia_socket_s {
1602 qemu_irq irq;
1603 int attached;
1604 const char *slot_string;
1605 const char *card_string;
1606 };
1607
1608 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1609 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1610 void pcmcia_info(void);
1611
1612 struct pcmcia_card_s {
1613 void *state;
1614 struct pcmcia_socket_s *slot;
1615 int (*attach)(void *state);
1616 int (*detach)(void *state);
1617 const uint8_t *cis;
1618 int cis_len;
1619
1620 /* Only valid if attached */
1621 uint8_t (*attr_read)(void *state, uint32_t address);
1622 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1623 uint16_t (*common_read)(void *state, uint32_t address);
1624 void (*common_write)(void *state, uint32_t address, uint16_t value);
1625 uint16_t (*io_read)(void *state, uint32_t address);
1626 void (*io_write)(void *state, uint32_t address, uint16_t value);
1627 };
1628
1629 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1630 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1631 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1632 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1633 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1634 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1635 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1636 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1637 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1638 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1639 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1640 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1641 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1642 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1643 #define CISTPL_END 0xff /* Tuple End */
1644 #define CISTPL_ENDMARK 0xff
1645
1646 /* dscm1xxxx.c */
1647 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1648
1649 /* ptimer.c */
1650 typedef struct ptimer_state ptimer_state;
1651 typedef void (*ptimer_cb)(void *opaque);
1652
1653 ptimer_state *ptimer_init(QEMUBH *bh);
1654 void ptimer_set_period(ptimer_state *s, int64_t period);
1655 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1656 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1657 uint64_t ptimer_get_count(ptimer_state *s);
1658 void ptimer_set_count(ptimer_state *s, uint64_t count);
1659 void ptimer_run(ptimer_state *s, int oneshot);
1660 void ptimer_stop(ptimer_state *s);
1661 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1662 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1663
1664 #include "hw/pxa.h"
1665
1666 #include "hw/omap.h"
1667
1668 /* mcf_uart.c */
1669 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1670 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1671 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1672 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1673 CharDriverState *chr);
1674
1675 /* mcf_intc.c */
1676 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1677
1678 /* mcf_fec.c */
1679 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1680
1681 /* mcf5206.c */
1682 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1683
1684 /* an5206.c */
1685 extern QEMUMachine an5206_machine;
1686
1687 /* mcf5208.c */
1688 extern QEMUMachine mcf5208evb_machine;
1689
1690 #include "gdbstub.h"
1691
1692 #endif /* defined(QEMU_TOOL) */
1693
1694 /* monitor.c */
1695 void monitor_init(CharDriverState *hd, int show_banner);
1696 void term_puts(const char *str);
1697 void term_vprintf(const char *fmt, va_list ap);
1698 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1699 void term_print_filename(const char *filename);
1700 void term_flush(void);
1701 void term_print_help(void);
1702 void monitor_readline(const char *prompt, int is_password,
1703 char *buf, int buf_size);
1704
1705 /* readline.c */
1706 typedef void ReadLineFunc(void *opaque, const char *str);
1707
1708 extern int completion_index;
1709 void add_completion(const char *str);
1710 void readline_handle_byte(int ch);
1711 void readline_find_completion(const char *cmdline);
1712 const char *readline_get_history(unsigned int index);
1713 void readline_start(const char *prompt, int is_password,
1714 ReadLineFunc *readline_func, void *opaque);
1715
1716 void kqemu_record_dump(void);
1717
1718 #endif /* VL_H */
Stable branch of Qemu 0.9.1