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Make the PowerPC MMU model, exception model and input bus model
[qemu/qemu_0_9_1_stable.git] / target-ppc / translate_init.c
blob62c0802018a6736cbc405c1aaffd2c7583daccb5
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "host-utils.h"
28
29 //#define PPC_DUMP_CPU
30 //#define PPC_DEBUG_SPR
31 //#define PPC_DEBUG_IRQ
32
33 struct ppc_def_t {
34 const unsigned char *name;
35 uint32_t pvr;
36 uint64_t insns_flags;
37 uint64_t msr_mask;
38 powerpc_mmu_t mmu_model;
39 powerpc_excp_t excp_model;
40 powerpc_input_t bus_model;
41 uint32_t flags;
42 int bfd_mach;
43 void (*init_proc)(CPUPPCState *env);
44 int (*check_pow)(CPUPPCState *env);
45 };
46
47 /* For user-mode emulation, we don't emulate any IRQ controller */
48 #if defined(CONFIG_USER_ONLY)
49 #define PPC_IRQ_INIT_FN(name) \
50 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
51 { \
52 }
53 #else
54 #define PPC_IRQ_INIT_FN(name) \
55 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
56 #endif
57
58 PPC_IRQ_INIT_FN(40x);
59 PPC_IRQ_INIT_FN(6xx);
60 PPC_IRQ_INIT_FN(970);
61
62 /* Generic callbacks:
63 * do nothing but store/retrieve spr value
64 */
65 #ifdef PPC_DUMP_SPR_ACCESSES
66 static void spr_read_generic (void *opaque, int sprn)
67 {
68 gen_op_load_dump_spr(sprn);
69 }
70
71 static void spr_write_generic (void *opaque, int sprn)
72 {
73 gen_op_store_dump_spr(sprn);
74 }
75 #else
76 static void spr_read_generic (void *opaque, int sprn)
77 {
78 gen_op_load_spr(sprn);
79 }
80
81 static void spr_write_generic (void *opaque, int sprn)
82 {
83 gen_op_store_spr(sprn);
84 }
85 #endif
86
87 #if !defined(CONFIG_USER_ONLY)
88 static void spr_write_clear (void *opaque, int sprn)
89 {
90 gen_op_mask_spr(sprn);
91 }
92 #endif
93
94 /* SPR common to all PowerPC */
95 /* XER */
96 static void spr_read_xer (void *opaque, int sprn)
97 {
98 gen_op_load_xer();
99 }
100
101 static void spr_write_xer (void *opaque, int sprn)
102 {
103 gen_op_store_xer();
104 }
105
106 /* LR */
107 static void spr_read_lr (void *opaque, int sprn)
108 {
109 gen_op_load_lr();
110 }
111
112 static void spr_write_lr (void *opaque, int sprn)
113 {
114 gen_op_store_lr();
115 }
116
117 /* CTR */
118 static void spr_read_ctr (void *opaque, int sprn)
119 {
120 gen_op_load_ctr();
121 }
122
123 static void spr_write_ctr (void *opaque, int sprn)
124 {
125 gen_op_store_ctr();
126 }
127
128 /* User read access to SPR */
129 /* USPRx */
130 /* UMMCRx */
131 /* UPMCx */
132 /* USIA */
133 /* UDECR */
134 static void spr_read_ureg (void *opaque, int sprn)
135 {
136 gen_op_load_spr(sprn + 0x10);
137 }
138
139 /* SPR common to all non-embedded PowerPC */
140 /* DECR */
141 #if !defined(CONFIG_USER_ONLY)
142 static void spr_read_decr (void *opaque, int sprn)
143 {
144 gen_op_load_decr();
145 }
146
147 static void spr_write_decr (void *opaque, int sprn)
148 {
149 gen_op_store_decr();
150 }
151 #endif
152
153 /* SPR common to all non-embedded PowerPC, except 601 */
154 /* Time base */
155 static void spr_read_tbl (void *opaque, int sprn)
156 {
157 gen_op_load_tbl();
158 }
159
160 static void spr_read_tbu (void *opaque, int sprn)
161 {
162 gen_op_load_tbu();
163 }
164
165 __attribute__ (( unused ))
166 static void spr_read_atbl (void *opaque, int sprn)
167 {
168 gen_op_load_atbl();
169 }
170
171 __attribute__ (( unused ))
172 static void spr_read_atbu (void *opaque, int sprn)
173 {
174 gen_op_load_atbu();
175 }
176
177 #if !defined(CONFIG_USER_ONLY)
178 static void spr_write_tbl (void *opaque, int sprn)
179 {
180 gen_op_store_tbl();
181 }
182
183 static void spr_write_tbu (void *opaque, int sprn)
184 {
185 gen_op_store_tbu();
186 }
187
188 __attribute__ (( unused ))
189 static void spr_write_atbl (void *opaque, int sprn)
190 {
191 gen_op_store_atbl();
192 }
193
194 __attribute__ (( unused ))
195 static void spr_write_atbu (void *opaque, int sprn)
196 {
197 gen_op_store_atbu();
198 }
199 #endif
200
201 #if !defined(CONFIG_USER_ONLY)
202 /* IBAT0U...IBAT0U */
203 /* IBAT0L...IBAT7L */
204 static void spr_read_ibat (void *opaque, int sprn)
205 {
206 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
207 }
208
209 static void spr_read_ibat_h (void *opaque, int sprn)
210 {
211 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
212 }
213
214 static void spr_write_ibatu (void *opaque, int sprn)
215 {
216 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
217 }
218
219 static void spr_write_ibatu_h (void *opaque, int sprn)
220 {
221 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
222 }
223
224 static void spr_write_ibatl (void *opaque, int sprn)
225 {
226 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
227 }
228
229 static void spr_write_ibatl_h (void *opaque, int sprn)
230 {
231 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
232 }
233
234 /* DBAT0U...DBAT7U */
235 /* DBAT0L...DBAT7L */
236 static void spr_read_dbat (void *opaque, int sprn)
237 {
238 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
239 }
240
241 static void spr_read_dbat_h (void *opaque, int sprn)
242 {
243 gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
244 }
245
246 static void spr_write_dbatu (void *opaque, int sprn)
247 {
248 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
249 }
250
251 static void spr_write_dbatu_h (void *opaque, int sprn)
252 {
253 gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4);
254 }
255
256 static void spr_write_dbatl (void *opaque, int sprn)
257 {
258 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
259 }
260
261 static void spr_write_dbatl_h (void *opaque, int sprn)
262 {
263 gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4);
264 }
265
266 /* SDR1 */
267 static void spr_read_sdr1 (void *opaque, int sprn)
268 {
269 gen_op_load_sdr1();
270 }
271
272 static void spr_write_sdr1 (void *opaque, int sprn)
273 {
274 gen_op_store_sdr1();
275 }
276
277 /* 64 bits PowerPC specific SPRs */
278 /* ASR */
279 #if defined(TARGET_PPC64)
280 __attribute__ (( unused ))
281 static void spr_read_asr (void *opaque, int sprn)
282 {
283 gen_op_load_asr();
284 }
285
286 __attribute__ (( unused ))
287 static void spr_write_asr (void *opaque, int sprn)
288 {
289 gen_op_store_asr();
290 }
291 #endif
292 #endif
293
294 /* PowerPC 601 specific registers */
295 /* RTC */
296 static void spr_read_601_rtcl (void *opaque, int sprn)
297 {
298 gen_op_load_601_rtcl();
299 }
300
301 static void spr_read_601_rtcu (void *opaque, int sprn)
302 {
303 gen_op_load_601_rtcu();
304 }
305
306 #if !defined(CONFIG_USER_ONLY)
307 static void spr_write_601_rtcu (void *opaque, int sprn)
308 {
309 gen_op_store_601_rtcu();
310 }
311
312 static void spr_write_601_rtcl (void *opaque, int sprn)
313 {
314 gen_op_store_601_rtcl();
315 }
316
317 static void spr_write_hid0_601 (void *opaque, int sprn)
318 {
319 DisasContext *ctx = opaque;
320
321 gen_op_store_hid0_601();
322 /* Must stop the translation as endianness may have changed */
323 GEN_STOP(ctx);
324 }
325 #endif
326
327 /* Unified bats */
328 #if !defined(CONFIG_USER_ONLY)
329 static void spr_read_601_ubat (void *opaque, int sprn)
330 {
331 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
332 }
333
334 static void spr_write_601_ubatu (void *opaque, int sprn)
335 {
336 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
337 }
338
339 static void spr_write_601_ubatl (void *opaque, int sprn)
340 {
341 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
342 }
343 #endif
344
345 /* PowerPC 40x specific registers */
346 #if !defined(CONFIG_USER_ONLY)
347 static void spr_read_40x_pit (void *opaque, int sprn)
348 {
349 gen_op_load_40x_pit();
350 }
351
352 static void spr_write_40x_pit (void *opaque, int sprn)
353 {
354 gen_op_store_40x_pit();
355 }
356
357 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
358 {
359 DisasContext *ctx = opaque;
360
361 gen_op_store_40x_dbcr0();
362 /* We must stop translation as we may have rebooted */
363 GEN_STOP(ctx);
364 }
365
366 static void spr_write_40x_sler (void *opaque, int sprn)
367 {
368 gen_op_store_40x_sler();
369 }
370
371 static void spr_write_booke_tcr (void *opaque, int sprn)
372 {
373 gen_op_store_booke_tcr();
374 }
375
376 static void spr_write_booke_tsr (void *opaque, int sprn)
377 {
378 gen_op_store_booke_tsr();
379 }
380 #endif
381
382 /* PowerPC 403 specific registers */
383 /* PBL1 / PBU1 / PBL2 / PBU2 */
384 #if !defined(CONFIG_USER_ONLY)
385 static void spr_read_403_pbr (void *opaque, int sprn)
386 {
387 gen_op_load_403_pb(sprn - SPR_403_PBL1);
388 }
389
390 static void spr_write_403_pbr (void *opaque, int sprn)
391 {
392 gen_op_store_403_pb(sprn - SPR_403_PBL1);
393 }
394
395 static void spr_write_pir (void *opaque, int sprn)
396 {
397 gen_op_store_pir();
398 }
399 #endif
400
401 #if !defined(CONFIG_USER_ONLY)
402 /* Callback used to write the exception vector base */
403 static void spr_write_excp_prefix (void *opaque, int sprn)
404 {
405 gen_op_store_excp_prefix();
406 gen_op_store_spr(sprn);
407 }
408
409 static void spr_write_excp_vector (void *opaque, int sprn)
410 {
411 DisasContext *ctx = opaque;
412
413 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
414 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
415 gen_op_store_spr(sprn);
416 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
417 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
418 gen_op_store_spr(sprn);
419 } else {
420 printf("Trying to write an unknown exception vector %d %03x\n",
421 sprn, sprn);
422 GEN_EXCP_PRIVREG(ctx);
423 }
424 }
425 #endif
426
427 #if defined(CONFIG_USER_ONLY)
428 #define spr_register(env, num, name, uea_read, uea_write, \
429 oea_read, oea_write, initial_value) \
430 do { \
431 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
432 } while (0)
433 static inline void _spr_register (CPUPPCState *env, int num,
434 const unsigned char *name,
435 void (*uea_read)(void *opaque, int sprn),
436 void (*uea_write)(void *opaque, int sprn),
437 target_ulong initial_value)
438 #else
439 static inline void spr_register (CPUPPCState *env, int num,
440 const unsigned char *name,
441 void (*uea_read)(void *opaque, int sprn),
442 void (*uea_write)(void *opaque, int sprn),
443 void (*oea_read)(void *opaque, int sprn),
444 void (*oea_write)(void *opaque, int sprn),
445 target_ulong initial_value)
446 #endif
447 {
448 ppc_spr_t *spr;
449
450 spr = &env->spr_cb[num];
451 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
452 #if !defined(CONFIG_USER_ONLY)
453 spr->oea_read != NULL || spr->oea_write != NULL ||
454 #endif
455 spr->uea_read != NULL || spr->uea_write != NULL) {
456 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
457 exit(1);
458 }
459 #if defined(PPC_DEBUG_SPR)
460 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
461 initial_value);
462 #endif
463 spr->name = name;
464 spr->uea_read = uea_read;
465 spr->uea_write = uea_write;
466 #if !defined(CONFIG_USER_ONLY)
467 spr->oea_read = oea_read;
468 spr->oea_write = oea_write;
469 #endif
470 env->spr[num] = initial_value;
471 }
472
473 /* Generic PowerPC SPRs */
474 static void gen_spr_generic (CPUPPCState *env)
475 {
476 /* Integer processing */
477 spr_register(env, SPR_XER, "XER",
478 &spr_read_xer, &spr_write_xer,
479 &spr_read_xer, &spr_write_xer,
480 0x00000000);
481 /* Branch contol */
482 spr_register(env, SPR_LR, "LR",
483 &spr_read_lr, &spr_write_lr,
484 &spr_read_lr, &spr_write_lr,
485 0x00000000);
486 spr_register(env, SPR_CTR, "CTR",
487 &spr_read_ctr, &spr_write_ctr,
488 &spr_read_ctr, &spr_write_ctr,
489 0x00000000);
490 /* Interrupt processing */
491 spr_register(env, SPR_SRR0, "SRR0",
492 SPR_NOACCESS, SPR_NOACCESS,
493 &spr_read_generic, &spr_write_generic,
494 0x00000000);
495 spr_register(env, SPR_SRR1, "SRR1",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499 /* Processor control */
500 spr_register(env, SPR_SPRG0, "SPRG0",
501 SPR_NOACCESS, SPR_NOACCESS,
502 &spr_read_generic, &spr_write_generic,
503 0x00000000);
504 spr_register(env, SPR_SPRG1, "SPRG1",
505 SPR_NOACCESS, SPR_NOACCESS,
506 &spr_read_generic, &spr_write_generic,
507 0x00000000);
508 spr_register(env, SPR_SPRG2, "SPRG2",
509 SPR_NOACCESS, SPR_NOACCESS,
510 &spr_read_generic, &spr_write_generic,
511 0x00000000);
512 spr_register(env, SPR_SPRG3, "SPRG3",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_generic, &spr_write_generic,
515 0x00000000);
516 }
517
518 /* SPR common to all non-embedded PowerPC, including 601 */
519 static void gen_spr_ne_601 (CPUPPCState *env)
520 {
521 /* Exception processing */
522 spr_register(env, SPR_DSISR, "DSISR",
523 SPR_NOACCESS, SPR_NOACCESS,
524 &spr_read_generic, &spr_write_generic,
525 0x00000000);
526 spr_register(env, SPR_DAR, "DAR",
527 SPR_NOACCESS, SPR_NOACCESS,
528 &spr_read_generic, &spr_write_generic,
529 0x00000000);
530 /* Timer */
531 spr_register(env, SPR_DECR, "DECR",
532 SPR_NOACCESS, SPR_NOACCESS,
533 &spr_read_decr, &spr_write_decr,
534 0x00000000);
535 /* Memory management */
536 spr_register(env, SPR_SDR1, "SDR1",
537 SPR_NOACCESS, SPR_NOACCESS,
538 &spr_read_sdr1, &spr_write_sdr1,
539 0x00000000);
540 }
541
542 /* BATs 0-3 */
543 static void gen_low_BATs (CPUPPCState *env)
544 {
545 #if !defined(CONFIG_USER_ONLY)
546 spr_register(env, SPR_IBAT0U, "IBAT0U",
547 SPR_NOACCESS, SPR_NOACCESS,
548 &spr_read_ibat, &spr_write_ibatu,
549 0x00000000);
550 spr_register(env, SPR_IBAT0L, "IBAT0L",
551 SPR_NOACCESS, SPR_NOACCESS,
552 &spr_read_ibat, &spr_write_ibatl,
553 0x00000000);
554 spr_register(env, SPR_IBAT1U, "IBAT1U",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_ibat, &spr_write_ibatu,
557 0x00000000);
558 spr_register(env, SPR_IBAT1L, "IBAT1L",
559 SPR_NOACCESS, SPR_NOACCESS,
560 &spr_read_ibat, &spr_write_ibatl,
561 0x00000000);
562 spr_register(env, SPR_IBAT2U, "IBAT2U",
563 SPR_NOACCESS, SPR_NOACCESS,
564 &spr_read_ibat, &spr_write_ibatu,
565 0x00000000);
566 spr_register(env, SPR_IBAT2L, "IBAT2L",
567 SPR_NOACCESS, SPR_NOACCESS,
568 &spr_read_ibat, &spr_write_ibatl,
569 0x00000000);
570 spr_register(env, SPR_IBAT3U, "IBAT3U",
571 SPR_NOACCESS, SPR_NOACCESS,
572 &spr_read_ibat, &spr_write_ibatu,
573 0x00000000);
574 spr_register(env, SPR_IBAT3L, "IBAT3L",
575 SPR_NOACCESS, SPR_NOACCESS,
576 &spr_read_ibat, &spr_write_ibatl,
577 0x00000000);
578 spr_register(env, SPR_DBAT0U, "DBAT0U",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_dbat, &spr_write_dbatu,
581 0x00000000);
582 spr_register(env, SPR_DBAT0L, "DBAT0L",
583 SPR_NOACCESS, SPR_NOACCESS,
584 &spr_read_dbat, &spr_write_dbatl,
585 0x00000000);
586 spr_register(env, SPR_DBAT1U, "DBAT1U",
587 SPR_NOACCESS, SPR_NOACCESS,
588 &spr_read_dbat, &spr_write_dbatu,
589 0x00000000);
590 spr_register(env, SPR_DBAT1L, "DBAT1L",
591 SPR_NOACCESS, SPR_NOACCESS,
592 &spr_read_dbat, &spr_write_dbatl,
593 0x00000000);
594 spr_register(env, SPR_DBAT2U, "DBAT2U",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_dbat, &spr_write_dbatu,
597 0x00000000);
598 spr_register(env, SPR_DBAT2L, "DBAT2L",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_dbat, &spr_write_dbatl,
601 0x00000000);
602 spr_register(env, SPR_DBAT3U, "DBAT3U",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_dbat, &spr_write_dbatu,
605 0x00000000);
606 spr_register(env, SPR_DBAT3L, "DBAT3L",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_dbat, &spr_write_dbatl,
609 0x00000000);
610 env->nb_BATs += 4;
611 #endif
612 }
613
614 /* BATs 4-7 */
615 static void gen_high_BATs (CPUPPCState *env)
616 {
617 #if !defined(CONFIG_USER_ONLY)
618 spr_register(env, SPR_IBAT4U, "IBAT4U",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_ibat_h, &spr_write_ibatu_h,
621 0x00000000);
622 spr_register(env, SPR_IBAT4L, "IBAT4L",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_ibat_h, &spr_write_ibatl_h,
625 0x00000000);
626 spr_register(env, SPR_IBAT5U, "IBAT5U",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_ibat_h, &spr_write_ibatu_h,
629 0x00000000);
630 spr_register(env, SPR_IBAT5L, "IBAT5L",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_ibat_h, &spr_write_ibatl_h,
633 0x00000000);
634 spr_register(env, SPR_IBAT6U, "IBAT6U",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_ibat_h, &spr_write_ibatu_h,
637 0x00000000);
638 spr_register(env, SPR_IBAT6L, "IBAT6L",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_ibat_h, &spr_write_ibatl_h,
641 0x00000000);
642 spr_register(env, SPR_IBAT7U, "IBAT7U",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_ibat_h, &spr_write_ibatu_h,
645 0x00000000);
646 spr_register(env, SPR_IBAT7L, "IBAT7L",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_ibat_h, &spr_write_ibatl_h,
649 0x00000000);
650 spr_register(env, SPR_DBAT4U, "DBAT4U",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_dbat_h, &spr_write_dbatu_h,
653 0x00000000);
654 spr_register(env, SPR_DBAT4L, "DBAT4L",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_dbat_h, &spr_write_dbatl_h,
657 0x00000000);
658 spr_register(env, SPR_DBAT5U, "DBAT5U",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_dbat_h, &spr_write_dbatu_h,
661 0x00000000);
662 spr_register(env, SPR_DBAT5L, "DBAT5L",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_dbat_h, &spr_write_dbatl_h,
665 0x00000000);
666 spr_register(env, SPR_DBAT6U, "DBAT6U",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_dbat_h, &spr_write_dbatu_h,
669 0x00000000);
670 spr_register(env, SPR_DBAT6L, "DBAT6L",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_dbat_h, &spr_write_dbatl_h,
673 0x00000000);
674 spr_register(env, SPR_DBAT7U, "DBAT7U",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_dbat_h, &spr_write_dbatu_h,
677 0x00000000);
678 spr_register(env, SPR_DBAT7L, "DBAT7L",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_dbat_h, &spr_write_dbatl_h,
681 0x00000000);
682 env->nb_BATs += 4;
683 #endif
684 }
685
686 /* Generic PowerPC time base */
687 static void gen_tbl (CPUPPCState *env)
688 {
689 spr_register(env, SPR_VTBL, "TBL",
690 &spr_read_tbl, SPR_NOACCESS,
691 &spr_read_tbl, SPR_NOACCESS,
692 0x00000000);
693 spr_register(env, SPR_TBL, "TBL",
694 SPR_NOACCESS, SPR_NOACCESS,
695 SPR_NOACCESS, &spr_write_tbl,
696 0x00000000);
697 spr_register(env, SPR_VTBU, "TBU",
698 &spr_read_tbu, SPR_NOACCESS,
699 &spr_read_tbu, SPR_NOACCESS,
700 0x00000000);
701 spr_register(env, SPR_TBU, "TBU",
702 SPR_NOACCESS, SPR_NOACCESS,
703 SPR_NOACCESS, &spr_write_tbu,
704 0x00000000);
705 }
706
707 /* Softare table search registers */
708 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
709 {
710 #if !defined(CONFIG_USER_ONLY)
711 env->nb_tlb = nb_tlbs;
712 env->nb_ways = nb_ways;
713 env->id_tlbs = 1;
714 spr_register(env, SPR_DMISS, "DMISS",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, SPR_NOACCESS,
717 0x00000000);
718 spr_register(env, SPR_DCMP, "DCMP",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_generic, SPR_NOACCESS,
721 0x00000000);
722 spr_register(env, SPR_HASH1, "HASH1",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_generic, SPR_NOACCESS,
725 0x00000000);
726 spr_register(env, SPR_HASH2, "HASH2",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, SPR_NOACCESS,
729 0x00000000);
730 spr_register(env, SPR_IMISS, "IMISS",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, SPR_NOACCESS,
733 0x00000000);
734 spr_register(env, SPR_ICMP, "ICMP",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, SPR_NOACCESS,
737 0x00000000);
738 spr_register(env, SPR_RPA, "RPA",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, &spr_write_generic,
741 0x00000000);
742 #endif
743 }
744
745 /* SPR common to MPC755 and G2 */
746 static void gen_spr_G2_755 (CPUPPCState *env)
747 {
748 /* SGPRs */
749 spr_register(env, SPR_SPRG4, "SPRG4",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_generic, &spr_write_generic,
752 0x00000000);
753 spr_register(env, SPR_SPRG5, "SPRG5",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 spr_register(env, SPR_SPRG6, "SPRG6",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_generic, &spr_write_generic,
760 0x00000000);
761 spr_register(env, SPR_SPRG7, "SPRG7",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_generic,
764 0x00000000);
765 /* External access control */
766 /* XXX : not implemented */
767 spr_register(env, SPR_EAR, "EAR",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_generic, &spr_write_generic,
770 0x00000000);
771 }
772
773 /* SPR common to all 7xx PowerPC implementations */
774 static void gen_spr_7xx (CPUPPCState *env)
775 {
776 /* Breakpoints */
777 /* XXX : not implemented */
778 spr_register(env, SPR_DABR, "DABR",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, &spr_write_generic,
781 0x00000000);
782 /* XXX : not implemented */
783 spr_register(env, SPR_IABR, "IABR",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_generic, &spr_write_generic,
786 0x00000000);
787 /* Cache management */
788 /* XXX : not implemented */
789 spr_register(env, SPR_ICTC, "ICTC",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_generic, &spr_write_generic,
792 0x00000000);
793 /* XXX : not implemented */
794 spr_register(env, SPR_L2CR, "L2CR",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_generic, &spr_write_generic,
797 0x00000000);
798 /* Performance monitors */
799 /* XXX : not implemented */
800 spr_register(env, SPR_MMCR0, "MMCR0",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_generic, &spr_write_generic,
803 0x00000000);
804 /* XXX : not implemented */
805 spr_register(env, SPR_MMCR1, "MMCR1",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_generic, &spr_write_generic,
808 0x00000000);
809 /* XXX : not implemented */
810 spr_register(env, SPR_PMC1, "PMC1",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_generic, &spr_write_generic,
813 0x00000000);
814 /* XXX : not implemented */
815 spr_register(env, SPR_PMC2, "PMC2",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_generic, &spr_write_generic,
818 0x00000000);
819 /* XXX : not implemented */
820 spr_register(env, SPR_PMC3, "PMC3",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_generic, &spr_write_generic,
823 0x00000000);
824 /* XXX : not implemented */
825 spr_register(env, SPR_PMC4, "PMC4",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_generic, &spr_write_generic,
828 0x00000000);
829 /* XXX : not implemented */
830 spr_register(env, SPR_SIAR, "SIAR",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_generic, SPR_NOACCESS,
833 0x00000000);
834 /* XXX : not implemented */
835 spr_register(env, SPR_UMMCR0, "UMMCR0",
836 &spr_read_ureg, SPR_NOACCESS,
837 &spr_read_ureg, SPR_NOACCESS,
838 0x00000000);
839 /* XXX : not implemented */
840 spr_register(env, SPR_UMMCR1, "UMMCR1",
841 &spr_read_ureg, SPR_NOACCESS,
842 &spr_read_ureg, SPR_NOACCESS,
843 0x00000000);
844 /* XXX : not implemented */
845 spr_register(env, SPR_UPMC1, "UPMC1",
846 &spr_read_ureg, SPR_NOACCESS,
847 &spr_read_ureg, SPR_NOACCESS,
848 0x00000000);
849 /* XXX : not implemented */
850 spr_register(env, SPR_UPMC2, "UPMC2",
851 &spr_read_ureg, SPR_NOACCESS,
852 &spr_read_ureg, SPR_NOACCESS,
853 0x00000000);
854 /* XXX : not implemented */
855 spr_register(env, SPR_UPMC3, "UPMC3",
856 &spr_read_ureg, SPR_NOACCESS,
857 &spr_read_ureg, SPR_NOACCESS,
858 0x00000000);
859 /* XXX : not implemented */
860 spr_register(env, SPR_UPMC4, "UPMC4",
861 &spr_read_ureg, SPR_NOACCESS,
862 &spr_read_ureg, SPR_NOACCESS,
863 0x00000000);
864 /* XXX : not implemented */
865 spr_register(env, SPR_USIAR, "USIAR",
866 &spr_read_ureg, SPR_NOACCESS,
867 &spr_read_ureg, SPR_NOACCESS,
868 0x00000000);
869 /* External access control */
870 /* XXX : not implemented */
871 spr_register(env, SPR_EAR, "EAR",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, &spr_write_generic,
874 0x00000000);
875 }
876
877 static void gen_spr_thrm (CPUPPCState *env)
878 {
879 /* Thermal management */
880 /* XXX : not implemented */
881 spr_register(env, SPR_THRM1, "THRM1",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, &spr_write_generic,
884 0x00000000);
885 /* XXX : not implemented */
886 spr_register(env, SPR_THRM2, "THRM2",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, &spr_write_generic,
889 0x00000000);
890 /* XXX : not implemented */
891 spr_register(env, SPR_THRM3, "THRM3",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, &spr_write_generic,
894 0x00000000);
895 }
896
897 /* SPR specific to PowerPC 604 implementation */
898 static void gen_spr_604 (CPUPPCState *env)
899 {
900 /* Processor identification */
901 spr_register(env, SPR_PIR, "PIR",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, &spr_write_pir,
904 0x00000000);
905 /* Breakpoints */
906 /* XXX : not implemented */
907 spr_register(env, SPR_IABR, "IABR",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 /* XXX : not implemented */
912 spr_register(env, SPR_DABR, "DABR",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916 /* Performance counters */
917 /* XXX : not implemented */
918 spr_register(env, SPR_MMCR0, "MMCR0",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 /* XXX : not implemented */
923 spr_register(env, SPR_MMCR1, "MMCR1",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
927 /* XXX : not implemented */
928 spr_register(env, SPR_PMC1, "PMC1",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_PMC2, "PMC2",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* XXX : not implemented */
938 spr_register(env, SPR_PMC3, "PMC3",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 /* XXX : not implemented */
943 spr_register(env, SPR_PMC4, "PMC4",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_SIAR, "SIAR",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, SPR_NOACCESS,
951 0x00000000);
952 /* XXX : not implemented */
953 spr_register(env, SPR_SDA, "SDA",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, SPR_NOACCESS,
956 0x00000000);
957 /* External access control */
958 /* XXX : not implemented */
959 spr_register(env, SPR_EAR, "EAR",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 }
964
965 /* SPR specific to PowerPC 603 implementation */
966 static void gen_spr_603 (CPUPPCState *env)
967 {
968 /* External access control */
969 /* XXX : not implemented */
970 spr_register(env, SPR_EAR, "EAR",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 }
975
976 /* SPR specific to PowerPC G2 implementation */
977 static void gen_spr_G2 (CPUPPCState *env)
978 {
979 /* Memory base address */
980 /* MBAR */
981 /* XXX : not implemented */
982 spr_register(env, SPR_MBAR, "MBAR",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986 /* System version register */
987 /* SVR */
988 /* XXX : TODO: initialize it to an appropriate value */
989 spr_register(env, SPR_SVR, "SVR",
990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, SPR_NOACCESS,
992 0x00000000);
993 /* Exception processing */
994 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
999 SPR_NOACCESS, SPR_NOACCESS,
1000 &spr_read_generic, &spr_write_generic,
1001 0x00000000);
1002 /* Breakpoints */
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_DABR, "DABR",
1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_DABR2, "DABR2",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_IABR, "IABR",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_IABR2, "IABR2",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, &spr_write_generic,
1022 0x00000000);
1023 /* XXX : not implemented */
1024 spr_register(env, SPR_IBCR, "IBCR",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_generic,
1027 0x00000000);
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_DBCR, "DBCR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 }
1034
1035 /* SPR specific to PowerPC 602 implementation */
1036 static void gen_spr_602 (CPUPPCState *env)
1037 {
1038 /* ESA registers */
1039 /* XXX : not implemented */
1040 spr_register(env, SPR_SER, "SER",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_SEBR, "SEBR",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_ESASRR, "ESASRR",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 /* Floating point status */
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_SP, "SP",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_LT, "LT",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, &spr_write_generic,
1064 0x00000000);
1065 /* Watchdog timer */
1066 /* XXX : not implemented */
1067 spr_register(env, SPR_TCR, "TCR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071 /* Interrupt base */
1072 spr_register(env, SPR_IBR, "IBR",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_IABR, "IABR",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081 }
1082
1083 /* SPR specific to PowerPC 601 implementation */
1084 static void gen_spr_601 (CPUPPCState *env)
1085 {
1086 /* Multiplication/division register */
1087 /* MQ */
1088 spr_register(env, SPR_MQ, "MQ",
1089 &spr_read_generic, &spr_write_generic,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
1092 /* RTC registers */
1093 spr_register(env, SPR_601_RTCU, "RTCU",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 SPR_NOACCESS, &spr_write_601_rtcu,
1096 0x00000000);
1097 spr_register(env, SPR_601_VRTCU, "RTCU",
1098 &spr_read_601_rtcu, SPR_NOACCESS,
1099 &spr_read_601_rtcu, SPR_NOACCESS,
1100 0x00000000);
1101 spr_register(env, SPR_601_RTCL, "RTCL",
1102 SPR_NOACCESS, SPR_NOACCESS,
1103 SPR_NOACCESS, &spr_write_601_rtcl,
1104 0x00000000);
1105 spr_register(env, SPR_601_VRTCL, "RTCL",
1106 &spr_read_601_rtcl, SPR_NOACCESS,
1107 &spr_read_601_rtcl, SPR_NOACCESS,
1108 0x00000000);
1109 /* Timer */
1110 #if 0 /* ? */
1111 spr_register(env, SPR_601_UDECR, "UDECR",
1112 &spr_read_decr, SPR_NOACCESS,
1113 &spr_read_decr, SPR_NOACCESS,
1114 0x00000000);
1115 #endif
1116 /* External access control */
1117 /* XXX : not implemented */
1118 spr_register(env, SPR_EAR, "EAR",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_generic, &spr_write_generic,
1121 0x00000000);
1122 /* Memory management */
1123 #if !defined(CONFIG_USER_ONLY)
1124 spr_register(env, SPR_IBAT0U, "IBAT0U",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_601_ubat, &spr_write_601_ubatu,
1127 0x00000000);
1128 spr_register(env, SPR_IBAT0L, "IBAT0L",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_601_ubat, &spr_write_601_ubatl,
1131 0x00000000);
1132 spr_register(env, SPR_IBAT1U, "IBAT1U",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_601_ubat, &spr_write_601_ubatu,
1135 0x00000000);
1136 spr_register(env, SPR_IBAT1L, "IBAT1L",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_601_ubat, &spr_write_601_ubatl,
1139 0x00000000);
1140 spr_register(env, SPR_IBAT2U, "IBAT2U",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_601_ubat, &spr_write_601_ubatu,
1143 0x00000000);
1144 spr_register(env, SPR_IBAT2L, "IBAT2L",
1145 SPR_NOACCESS, SPR_NOACCESS,
1146 &spr_read_601_ubat, &spr_write_601_ubatl,
1147 0x00000000);
1148 spr_register(env, SPR_IBAT3U, "IBAT3U",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_601_ubat, &spr_write_601_ubatu,
1151 0x00000000);
1152 spr_register(env, SPR_IBAT3L, "IBAT3L",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_601_ubat, &spr_write_601_ubatl,
1155 0x00000000);
1156 env->nb_BATs = 4;
1157 #endif
1158 }
1159
1160 static void gen_spr_74xx (CPUPPCState *env)
1161 {
1162 /* Processor identification */
1163 spr_register(env, SPR_PIR, "PIR",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_pir,
1166 0x00000000);
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_MMCR2, "MMCR2",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* XXX : not implemented */
1173 spr_register(env, SPR_UMMCR2, "UMMCR2",
1174 &spr_read_ureg, SPR_NOACCESS,
1175 &spr_read_ureg, SPR_NOACCESS,
1176 0x00000000);
1177 /* XXX: not implemented */
1178 spr_register(env, SPR_BAMR, "BAMR",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 /* XXX : not implemented */
1183 spr_register(env, SPR_UBAMR, "UBAMR",
1184 &spr_read_ureg, SPR_NOACCESS,
1185 &spr_read_ureg, SPR_NOACCESS,
1186 0x00000000);
1187 /* XXX : not implemented */
1188 spr_register(env, SPR_MSSCR0, "MSSCR0",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* Hardware implementation registers */
1193 /* XXX : not implemented */
1194 spr_register(env, SPR_HID0, "HID0",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198 /* XXX : not implemented */
1199 spr_register(env, SPR_HID1, "HID1",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_generic,
1202 0x00000000);
1203 /* Altivec */
1204 spr_register(env, SPR_VRSAVE, "VRSAVE",
1205 &spr_read_generic, &spr_write_generic,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
1208 }
1209
1210 static void gen_l3_ctrl (CPUPPCState *env)
1211 {
1212 /* L3CR */
1213 /* XXX : not implemented */
1214 spr_register(env, SPR_L3CR, "L3CR",
1215 SPR_NOACCESS, SPR_NOACCESS,
1216 &spr_read_generic, &spr_write_generic,
1217 0x00000000);
1218 /* L3ITCR0 */
1219 /* XXX : not implemented */
1220 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* L3ITCR1 */
1225 /* XXX : not implemented */
1226 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1229 0x00000000);
1230 /* L3ITCR2 */
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* L3ITCR3 */
1237 /* XXX : not implemented */
1238 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_generic, &spr_write_generic,
1241 0x00000000);
1242 /* L3OHCR */
1243 /* XXX : not implemented */
1244 spr_register(env, SPR_L3OHCR, "L3OHCR",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_generic, &spr_write_generic,
1247 0x00000000);
1248 /* L3PM */
1249 /* XXX : not implemented */
1250 spr_register(env, SPR_L3PM, "L3PM",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254 }
1255
1256 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1257 {
1258 #if !defined(CONFIG_USER_ONLY)
1259 env->nb_tlb = nb_tlbs;
1260 env->nb_ways = nb_ways;
1261 env->id_tlbs = 1;
1262 /* XXX : not implemented */
1263 spr_register(env, SPR_PTEHI, "PTEHI",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_generic, &spr_write_generic,
1266 0x00000000);
1267 /* XXX : not implemented */
1268 spr_register(env, SPR_PTELO, "PTELO",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1271 0x00000000);
1272 /* XXX : not implemented */
1273 spr_register(env, SPR_TLBMISS, "TLBMISS",
1274 SPR_NOACCESS, SPR_NOACCESS,
1275 &spr_read_generic, &spr_write_generic,
1276 0x00000000);
1277 #endif
1278 }
1279
1280 /* PowerPC BookE SPR */
1281 static void gen_spr_BookE (CPUPPCState *env)
1282 {
1283 /* Processor identification */
1284 spr_register(env, SPR_BOOKE_PIR, "PIR",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_pir,
1287 0x00000000);
1288 /* Interrupt processing */
1289 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 &spr_read_generic, &spr_write_generic,
1296 0x00000000);
1297 #if 0
1298 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1299 SPR_NOACCESS, SPR_NOACCESS,
1300 &spr_read_generic, &spr_write_generic,
1301 0x00000000);
1302 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1303 SPR_NOACCESS, SPR_NOACCESS,
1304 &spr_read_generic, &spr_write_generic,
1305 0x00000000);
1306 #endif
1307 /* Debug */
1308 /* XXX : not implemented */
1309 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1312 0x00000000);
1313 /* XXX : not implemented */
1314 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318 /* XXX : not implemented */
1319 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323 /* XXX : not implemented */
1324 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328 /* XXX : not implemented */
1329 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 /* XXX : not implemented */
1334 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 /* XXX : not implemented */
1349 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 /* XXX : not implemented */
1354 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 /* XXX : not implemented */
1359 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363 /* XXX : not implemented */
1364 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_clear,
1367 0x00000000);
1368 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372 spr_register(env, SPR_BOOKE_ESR, "ESR",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_generic,
1375 0x00000000);
1376 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_excp_prefix,
1379 0x00000000);
1380 /* Exception vectors */
1381 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_excp_vector,
1384 0x00000000);
1385 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1386 SPR_NOACCESS, SPR_NOACCESS,
1387 &spr_read_generic, &spr_write_excp_vector,
1388 0x00000000);
1389 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_excp_vector,
1392 0x00000000);
1393 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, &spr_write_excp_vector,
1396 0x00000000);
1397 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_excp_vector,
1400 0x00000000);
1401 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1402 SPR_NOACCESS, SPR_NOACCESS,
1403 &spr_read_generic, &spr_write_excp_vector,
1404 0x00000000);
1405 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1406 SPR_NOACCESS, SPR_NOACCESS,
1407 &spr_read_generic, &spr_write_excp_vector,
1408 0x00000000);
1409 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_excp_vector,
1412 0x00000000);
1413 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_excp_vector,
1416 0x00000000);
1417 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, &spr_write_excp_vector,
1420 0x00000000);
1421 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_excp_vector,
1424 0x00000000);
1425 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 &spr_read_generic, &spr_write_excp_vector,
1428 0x00000000);
1429 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_excp_vector,
1432 0x00000000);
1433 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1434 SPR_NOACCESS, SPR_NOACCESS,
1435 &spr_read_generic, &spr_write_excp_vector,
1436 0x00000000);
1437 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1438 SPR_NOACCESS, SPR_NOACCESS,
1439 &spr_read_generic, &spr_write_excp_vector,
1440 0x00000000);
1441 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_excp_vector,
1444 0x00000000);
1445 #if 0
1446 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_generic, &spr_write_excp_vector,
1449 0x00000000);
1450 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_excp_vector,
1453 0x00000000);
1454 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_excp_vector,
1457 0x00000000);
1458 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_excp_vector,
1461 0x00000000);
1462 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_excp_vector,
1465 0x00000000);
1466 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_excp_vector,
1469 0x00000000);
1470 #endif
1471 spr_register(env, SPR_BOOKE_PID, "PID",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475 spr_register(env, SPR_BOOKE_TCR, "TCR",
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_generic, &spr_write_booke_tcr,
1478 0x00000000);
1479 spr_register(env, SPR_BOOKE_TSR, "TSR",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_booke_tsr,
1482 0x00000000);
1483 /* Timer */
1484 spr_register(env, SPR_DECR, "DECR",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_decr, &spr_write_decr,
1487 0x00000000);
1488 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 SPR_NOACCESS, &spr_write_generic,
1491 0x00000000);
1492 /* SPRGs */
1493 spr_register(env, SPR_USPRG0, "USPRG0",
1494 &spr_read_generic, &spr_write_generic,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
1497 spr_register(env, SPR_SPRG4, "SPRG4",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501 spr_register(env, SPR_USPRG4, "USPRG4",
1502 &spr_read_ureg, SPR_NOACCESS,
1503 &spr_read_ureg, SPR_NOACCESS,
1504 0x00000000);
1505 spr_register(env, SPR_SPRG5, "SPRG5",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 spr_register(env, SPR_USPRG5, "USPRG5",
1510 &spr_read_ureg, SPR_NOACCESS,
1511 &spr_read_ureg, SPR_NOACCESS,
1512 0x00000000);
1513 spr_register(env, SPR_SPRG6, "SPRG6",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, &spr_write_generic,
1516 0x00000000);
1517 spr_register(env, SPR_USPRG6, "USPRG6",
1518 &spr_read_ureg, SPR_NOACCESS,
1519 &spr_read_ureg, SPR_NOACCESS,
1520 0x00000000);
1521 spr_register(env, SPR_SPRG7, "SPRG7",
1522 SPR_NOACCESS, SPR_NOACCESS,
1523 &spr_read_generic, &spr_write_generic,
1524 0x00000000);
1525 spr_register(env, SPR_USPRG7, "USPRG7",
1526 &spr_read_ureg, SPR_NOACCESS,
1527 &spr_read_ureg, SPR_NOACCESS,
1528 0x00000000);
1529 }
1530
1531 /* FSL storage control registers */
1532 static void gen_spr_BookE_FSL (CPUPPCState *env)
1533 {
1534 #if !defined(CONFIG_USER_ONLY)
1535 /* TLB assist registers */
1536 /* XXX : not implemented */
1537 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1540 0x00000000);
1541 /* XXX : not implemented */
1542 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1543 SPR_NOACCESS, SPR_NOACCESS,
1544 &spr_read_generic, &spr_write_generic,
1545 0x00000000);
1546 /* XXX : not implemented */
1547 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_generic,
1550 0x00000000);
1551 /* XXX : not implemented */
1552 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_generic,
1555 0x00000000);
1556 /* XXX : not implemented */
1557 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
1561 /* XXX : not implemented */
1562 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_generic, &spr_write_generic,
1565 0x00000000);
1566 /* XXX : not implemented */
1567 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 if (env->nb_pids > 1) {
1572 /* XXX : not implemented */
1573 spr_register(env, SPR_BOOKE_PID1, "PID1",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
1577 }
1578 if (env->nb_pids > 2) {
1579 /* XXX : not implemented */
1580 spr_register(env, SPR_BOOKE_PID2, "PID2",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00000000);
1584 }
1585 /* XXX : not implemented */
1586 spr_register(env, SPR_MMUCFG, "MMUCFG",
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, SPR_NOACCESS,
1589 0x00000000); /* TOFIX */
1590 /* XXX : not implemented */
1591 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000); /* TOFIX */
1595 switch (env->nb_ways) {
1596 case 4:
1597 /* XXX : not implemented */
1598 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, SPR_NOACCESS,
1601 0x00000000); /* TOFIX */
1602 /* Fallthru */
1603 case 3:
1604 /* XXX : not implemented */
1605 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, SPR_NOACCESS,
1608 0x00000000); /* TOFIX */
1609 /* Fallthru */
1610 case 2:
1611 /* XXX : not implemented */
1612 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1613 SPR_NOACCESS, SPR_NOACCESS,
1614 &spr_read_generic, SPR_NOACCESS,
1615 0x00000000); /* TOFIX */
1616 /* Fallthru */
1617 case 1:
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, SPR_NOACCESS,
1622 0x00000000); /* TOFIX */
1623 /* Fallthru */
1624 case 0:
1625 default:
1626 break;
1627 }
1628 #endif
1629 }
1630
1631 /* SPR specific to PowerPC 440 implementation */
1632 static void gen_spr_440 (CPUPPCState *env)
1633 {
1634 /* Cache control */
1635 /* XXX : not implemented */
1636 spr_register(env, SPR_440_DNV0, "DNV0",
1637 SPR_NOACCESS, SPR_NOACCESS,
1638 &spr_read_generic, &spr_write_generic,
1639 0x00000000);
1640 /* XXX : not implemented */
1641 spr_register(env, SPR_440_DNV1, "DNV1",
1642 SPR_NOACCESS, SPR_NOACCESS,
1643 &spr_read_generic, &spr_write_generic,
1644 0x00000000);
1645 /* XXX : not implemented */
1646 spr_register(env, SPR_440_DNV2, "DNV2",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, &spr_write_generic,
1649 0x00000000);
1650 /* XXX : not implemented */
1651 spr_register(env, SPR_440_DNV3, "DNV3",
1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, &spr_write_generic,
1654 0x00000000);
1655 /* XXX : not implemented */
1656 spr_register(env, SPR_440_DTV0, "DTV0",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, &spr_write_generic,
1659 0x00000000);
1660 /* XXX : not implemented */
1661 spr_register(env, SPR_440_DTV1, "DTV1",
1662 SPR_NOACCESS, SPR_NOACCESS,
1663 &spr_read_generic, &spr_write_generic,
1664 0x00000000);
1665 /* XXX : not implemented */
1666 spr_register(env, SPR_440_DTV2, "DTV2",
1667 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, &spr_write_generic,
1669 0x00000000);
1670 /* XXX : not implemented */
1671 spr_register(env, SPR_440_DTV3, "DTV3",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_generic,
1674 0x00000000);
1675 /* XXX : not implemented */
1676 spr_register(env, SPR_440_DVLIM, "DVLIM",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0x00000000);
1680 /* XXX : not implemented */
1681 spr_register(env, SPR_440_INV0, "INV0",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
1685 /* XXX : not implemented */
1686 spr_register(env, SPR_440_INV1, "INV1",
1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic,
1689 0x00000000);
1690 /* XXX : not implemented */
1691 spr_register(env, SPR_440_INV2, "INV2",
1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_440_INV3, "INV3",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700 /* XXX : not implemented */
1701 spr_register(env, SPR_440_ITV0, "ITV0",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000);
1705 /* XXX : not implemented */
1706 spr_register(env, SPR_440_ITV1, "ITV1",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 /* XXX : not implemented */
1711 spr_register(env, SPR_440_ITV2, "ITV2",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, &spr_write_generic,
1714 0x00000000);
1715 /* XXX : not implemented */
1716 spr_register(env, SPR_440_ITV3, "ITV3",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, &spr_write_generic,
1719 0x00000000);
1720 /* XXX : not implemented */
1721 spr_register(env, SPR_440_IVLIM, "IVLIM",
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_generic,
1724 0x00000000);
1725 /* Cache debug */
1726 /* XXX : not implemented */
1727 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1728 SPR_NOACCESS, SPR_NOACCESS,
1729 &spr_read_generic, SPR_NOACCESS,
1730 0x00000000);
1731 /* XXX : not implemented */
1732 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1733 SPR_NOACCESS, SPR_NOACCESS,
1734 &spr_read_generic, SPR_NOACCESS,
1735 0x00000000);
1736 /* XXX : not implemented */
1737 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1738 SPR_NOACCESS, SPR_NOACCESS,
1739 &spr_read_generic, SPR_NOACCESS,
1740 0x00000000);
1741 /* XXX : not implemented */
1742 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1743 SPR_NOACCESS, SPR_NOACCESS,
1744 &spr_read_generic, SPR_NOACCESS,
1745 0x00000000);
1746 /* XXX : not implemented */
1747 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1748 SPR_NOACCESS, SPR_NOACCESS,
1749 &spr_read_generic, SPR_NOACCESS,
1750 0x00000000);
1751 /* XXX : not implemented */
1752 spr_register(env, SPR_440_DBDR, "DBDR",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, &spr_write_generic,
1755 0x00000000);
1756 /* Processor control */
1757 spr_register(env, SPR_4xx_CCR0, "CCR0",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1762 SPR_NOACCESS, SPR_NOACCESS,
1763 &spr_read_generic, SPR_NOACCESS,
1764 0x00000000);
1765 /* Storage control */
1766 spr_register(env, SPR_440_MMUCR, "MMUCR",
1767 SPR_NOACCESS, SPR_NOACCESS,
1768 &spr_read_generic, &spr_write_generic,
1769 0x00000000);
1770 }
1771
1772 /* SPR shared between PowerPC 40x implementations */
1773 static void gen_spr_40x (CPUPPCState *env)
1774 {
1775 /* Cache */
1776 /* not emulated, as Qemu do not emulate caches */
1777 spr_register(env, SPR_40x_DCCR, "DCCR",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 /* not emulated, as Qemu do not emulate caches */
1782 spr_register(env, SPR_40x_ICCR, "ICCR",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, &spr_write_generic,
1785 0x00000000);
1786 /* not emulated, as Qemu do not emulate caches */
1787 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, SPR_NOACCESS,
1790 0x00000000);
1791 /* Exception */
1792 spr_register(env, SPR_40x_DEAR, "DEAR",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 spr_register(env, SPR_40x_ESR, "ESR",
1797 SPR_NOACCESS, SPR_NOACCESS,
1798 &spr_read_generic, &spr_write_generic,
1799 0x00000000);
1800 spr_register(env, SPR_40x_EVPR, "EVPR",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_excp_prefix,
1803 0x00000000);
1804 spr_register(env, SPR_40x_SRR2, "SRR2",
1805 &spr_read_generic, &spr_write_generic,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 spr_register(env, SPR_40x_SRR3, "SRR3",
1809 &spr_read_generic, &spr_write_generic,
1810 &spr_read_generic, &spr_write_generic,
1811 0x00000000);
1812 /* Timers */
1813 spr_register(env, SPR_40x_PIT, "PIT",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_40x_pit, &spr_write_40x_pit,
1816 0x00000000);
1817 spr_register(env, SPR_40x_TCR, "TCR",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_booke_tcr,
1820 0x00000000);
1821 spr_register(env, SPR_40x_TSR, "TSR",
1822 SPR_NOACCESS, SPR_NOACCESS,
1823 &spr_read_generic, &spr_write_booke_tsr,
1824 0x00000000);
1825 }
1826
1827 /* SPR specific to PowerPC 405 implementation */
1828 static void gen_spr_405 (CPUPPCState *env)
1829 {
1830 /* MMU */
1831 spr_register(env, SPR_40x_PID, "PID",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835 spr_register(env, SPR_4xx_CCR0, "CCR0",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, &spr_write_generic,
1838 0x00700000);
1839 /* Debug interface */
1840 /* XXX : not implemented */
1841 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, &spr_write_40x_dbcr0,
1844 0x00000000);
1845 /* XXX : not implemented */
1846 spr_register(env, SPR_405_DBCR1, "DBCR1",
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 &spr_read_generic, &spr_write_generic,
1849 0x00000000);
1850 /* XXX : not implemented */
1851 spr_register(env, SPR_40x_DBSR, "DBSR",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 &spr_read_generic, &spr_write_clear,
1854 /* Last reset was system reset */
1855 0x00000300);
1856 /* XXX : not implemented */
1857 spr_register(env, SPR_40x_DAC1, "DAC1",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00000000);
1861 spr_register(env, SPR_40x_DAC2, "DAC2",
1862 SPR_NOACCESS, SPR_NOACCESS,
1863 &spr_read_generic, &spr_write_generic,
1864 0x00000000);
1865 /* XXX : not implemented */
1866 spr_register(env, SPR_405_DVC1, "DVC1",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870 /* XXX : not implemented */
1871 spr_register(env, SPR_405_DVC2, "DVC2",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_40x_IAC1, "IAC1",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00000000);
1880 spr_register(env, SPR_40x_IAC2, "IAC2",
1881 SPR_NOACCESS, SPR_NOACCESS,
1882 &spr_read_generic, &spr_write_generic,
1883 0x00000000);
1884 /* XXX : not implemented */
1885 spr_register(env, SPR_405_IAC3, "IAC3",
1886 SPR_NOACCESS, SPR_NOACCESS,
1887 &spr_read_generic, &spr_write_generic,
1888 0x00000000);
1889 /* XXX : not implemented */
1890 spr_register(env, SPR_405_IAC4, "IAC4",
1891 SPR_NOACCESS, SPR_NOACCESS,
1892 &spr_read_generic, &spr_write_generic,
1893 0x00000000);
1894 /* Storage control */
1895 /* XXX: TODO: not implemented */
1896 spr_register(env, SPR_405_SLER, "SLER",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_40x_sler,
1899 0x00000000);
1900 spr_register(env, SPR_40x_ZPR, "ZPR",
1901 SPR_NOACCESS, SPR_NOACCESS,
1902 &spr_read_generic, &spr_write_generic,
1903 0x00000000);
1904 /* XXX : not implemented */
1905 spr_register(env, SPR_405_SU0R, "SU0R",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 /* SPRG */
1910 spr_register(env, SPR_USPRG0, "USPRG0",
1911 &spr_read_ureg, SPR_NOACCESS,
1912 &spr_read_ureg, SPR_NOACCESS,
1913 0x00000000);
1914 spr_register(env, SPR_SPRG4, "SPRG4",
1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, &spr_write_generic,
1917 0x00000000);
1918 spr_register(env, SPR_USPRG4, "USPRG4",
1919 &spr_read_ureg, SPR_NOACCESS,
1920 &spr_read_ureg, SPR_NOACCESS,
1921 0x00000000);
1922 spr_register(env, SPR_SPRG5, "SPRG5",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 spr_read_generic, &spr_write_generic,
1925 0x00000000);
1926 spr_register(env, SPR_USPRG5, "USPRG5",
1927 &spr_read_ureg, SPR_NOACCESS,
1928 &spr_read_ureg, SPR_NOACCESS,
1929 0x00000000);
1930 spr_register(env, SPR_SPRG6, "SPRG6",
1931 SPR_NOACCESS, SPR_NOACCESS,
1932 spr_read_generic, &spr_write_generic,
1933 0x00000000);
1934 spr_register(env, SPR_USPRG6, "USPRG6",
1935 &spr_read_ureg, SPR_NOACCESS,
1936 &spr_read_ureg, SPR_NOACCESS,
1937 0x00000000);
1938 spr_register(env, SPR_SPRG7, "SPRG7",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 spr_register(env, SPR_USPRG7, "USPRG7",
1943 &spr_read_ureg, SPR_NOACCESS,
1944 &spr_read_ureg, SPR_NOACCESS,
1945 0x00000000);
1946 }
1947
1948 /* SPR shared between PowerPC 401 & 403 implementations */
1949 static void gen_spr_401_403 (CPUPPCState *env)
1950 {
1951 /* Time base */
1952 spr_register(env, SPR_403_VTBL, "TBL",
1953 &spr_read_tbl, SPR_NOACCESS,
1954 &spr_read_tbl, SPR_NOACCESS,
1955 0x00000000);
1956 spr_register(env, SPR_403_TBL, "TBL",
1957 SPR_NOACCESS, SPR_NOACCESS,
1958 SPR_NOACCESS, &spr_write_tbl,
1959 0x00000000);
1960 spr_register(env, SPR_403_VTBU, "TBU",
1961 &spr_read_tbu, SPR_NOACCESS,
1962 &spr_read_tbu, SPR_NOACCESS,
1963 0x00000000);
1964 spr_register(env, SPR_403_TBU, "TBU",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 SPR_NOACCESS, &spr_write_tbu,
1967 0x00000000);
1968 /* Debug */
1969 /* not emulated, as Qemu do not emulate caches */
1970 spr_register(env, SPR_403_CDBCR, "CDBCR",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974 }
1975
1976 /* SPR specific to PowerPC 401 implementation */
1977 static void gen_spr_401 (CPUPPCState *env)
1978 {
1979 /* Debug interface */
1980 /* XXX : not implemented */
1981 spr_register(env, SPR_40x_DBCR0, "DBCR",
1982 SPR_NOACCESS, SPR_NOACCESS,
1983 &spr_read_generic, &spr_write_40x_dbcr0,
1984 0x00000000);
1985 /* XXX : not implemented */
1986 spr_register(env, SPR_40x_DBSR, "DBSR",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 &spr_read_generic, &spr_write_clear,
1989 /* Last reset was system reset */
1990 0x00000300);
1991 /* XXX : not implemented */
1992 spr_register(env, SPR_40x_DAC1, "DAC",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_40x_IAC1, "IAC",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 /* Storage control */
2002 /* XXX: TODO: not implemented */
2003 spr_register(env, SPR_405_SLER, "SLER",
2004 SPR_NOACCESS, SPR_NOACCESS,
2005 &spr_read_generic, &spr_write_40x_sler,
2006 0x00000000);
2007 /* not emulated, as Qemu never does speculative access */
2008 spr_register(env, SPR_40x_SGR, "SGR",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_generic,
2011 0xFFFFFFFF);
2012 /* not emulated, as Qemu do not emulate caches */
2013 spr_register(env, SPR_40x_DCWR, "DCWR",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0x00000000);
2017 }
2018
2019 static void gen_spr_401x2 (CPUPPCState *env)
2020 {
2021 gen_spr_401(env);
2022 spr_register(env, SPR_40x_PID, "PID",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 &spr_read_generic, &spr_write_generic,
2025 0x00000000);
2026 spr_register(env, SPR_40x_ZPR, "ZPR",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
2030 }
2031
2032 /* SPR specific to PowerPC 403 implementation */
2033 static void gen_spr_403 (CPUPPCState *env)
2034 {
2035 /* Debug interface */
2036 /* XXX : not implemented */
2037 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 &spr_read_generic, &spr_write_40x_dbcr0,
2040 0x00000000);
2041 /* XXX : not implemented */
2042 spr_register(env, SPR_40x_DBSR, "DBSR",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_clear,
2045 /* Last reset was system reset */
2046 0x00000300);
2047 /* XXX : not implemented */
2048 spr_register(env, SPR_40x_DAC1, "DAC1",
2049 SPR_NOACCESS, SPR_NOACCESS,
2050 &spr_read_generic, &spr_write_generic,
2051 0x00000000);
2052 /* XXX : not implemented */
2053 spr_register(env, SPR_40x_DAC2, "DAC2",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, &spr_write_generic,
2056 0x00000000);
2057 /* XXX : not implemented */
2058 spr_register(env, SPR_40x_IAC1, "IAC1",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062 /* XXX : not implemented */
2063 spr_register(env, SPR_40x_IAC2, "IAC2",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_generic, &spr_write_generic,
2066 0x00000000);
2067 }
2068
2069 static void gen_spr_403_real (CPUPPCState *env)
2070 {
2071 spr_register(env, SPR_403_PBL1, "PBL1",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_403_pbr, &spr_write_403_pbr,
2074 0x00000000);
2075 spr_register(env, SPR_403_PBU1, "PBU1",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_403_pbr, &spr_write_403_pbr,
2078 0x00000000);
2079 spr_register(env, SPR_403_PBL2, "PBL2",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_403_pbr, &spr_write_403_pbr,
2082 0x00000000);
2083 spr_register(env, SPR_403_PBU2, "PBU2",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_403_pbr, &spr_write_403_pbr,
2086 0x00000000);
2087 }
2088
2089 static void gen_spr_403_mmu (CPUPPCState *env)
2090 {
2091 /* MMU */
2092 spr_register(env, SPR_40x_PID, "PID",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00000000);
2096 spr_register(env, SPR_40x_ZPR, "ZPR",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_generic,
2099 0x00000000);
2100 }
2101
2102 /* SPR specific to PowerPC compression coprocessor extension */
2103 static void gen_spr_compress (CPUPPCState *env)
2104 {
2105 /* XXX : not implemented */
2106 spr_register(env, SPR_401_SKR, "SKR",
2107 SPR_NOACCESS, SPR_NOACCESS,
2108 &spr_read_generic, &spr_write_generic,
2109 0x00000000);
2110 }
2111
2112 #if defined (TARGET_PPC64)
2113 /* SPR specific to PowerPC 620 */
2114 static void gen_spr_620 (CPUPPCState *env)
2115 {
2116 /* XXX : not implemented */
2117 spr_register(env, SPR_620_PMR0, "PMR0",
2118 SPR_NOACCESS, SPR_NOACCESS,
2119 &spr_read_generic, &spr_write_generic,
2120 0x00000000);
2121 /* XXX : not implemented */
2122 spr_register(env, SPR_620_PMR1, "PMR1",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, &spr_write_generic,
2125 0x00000000);
2126 /* XXX : not implemented */
2127 spr_register(env, SPR_620_PMR2, "PMR2",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_generic,
2130 0x00000000);
2131 /* XXX : not implemented */
2132 spr_register(env, SPR_620_PMR3, "PMR3",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 /* XXX : not implemented */
2137 spr_register(env, SPR_620_PMR4, "PMR4",
2138 SPR_NOACCESS, SPR_NOACCESS,
2139 &spr_read_generic, &spr_write_generic,
2140 0x00000000);
2141 /* XXX : not implemented */
2142 spr_register(env, SPR_620_PMR5, "PMR5",
2143 SPR_NOACCESS, SPR_NOACCESS,
2144 &spr_read_generic, &spr_write_generic,
2145 0x00000000);
2146 /* XXX : not implemented */
2147 spr_register(env, SPR_620_PMR6, "PMR6",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_generic, &spr_write_generic,
2150 0x00000000);
2151 /* XXX : not implemented */
2152 spr_register(env, SPR_620_PMR7, "PMR7",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, &spr_write_generic,
2155 0x00000000);
2156 /* XXX : not implemented */
2157 spr_register(env, SPR_620_PMR8, "PMR8",
2158 SPR_NOACCESS, SPR_NOACCESS,
2159 &spr_read_generic, &spr_write_generic,
2160 0x00000000);
2161 /* XXX : not implemented */
2162 spr_register(env, SPR_620_PMR9, "PMR9",
2163 SPR_NOACCESS, SPR_NOACCESS,
2164 &spr_read_generic, &spr_write_generic,
2165 0x00000000);
2166 /* XXX : not implemented */
2167 spr_register(env, SPR_620_PMRA, "PMR10",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_generic, &spr_write_generic,
2170 0x00000000);
2171 /* XXX : not implemented */
2172 spr_register(env, SPR_620_PMRB, "PMR11",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, &spr_write_generic,
2175 0x00000000);
2176 /* XXX : not implemented */
2177 spr_register(env, SPR_620_PMRC, "PMR12",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00000000);
2181 /* XXX : not implemented */
2182 spr_register(env, SPR_620_PMRD, "PMR13",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 &spr_read_generic, &spr_write_generic,
2185 0x00000000);
2186 /* XXX : not implemented */
2187 spr_register(env, SPR_620_PMRE, "PMR14",
2188 SPR_NOACCESS, SPR_NOACCESS,
2189 &spr_read_generic, &spr_write_generic,
2190 0x00000000);
2191 /* XXX : not implemented */
2192 spr_register(env, SPR_620_PMRF, "PMR15",
2193 SPR_NOACCESS, SPR_NOACCESS,
2194 &spr_read_generic, &spr_write_generic,
2195 0x00000000);
2196 /* XXX : not implemented */
2197 spr_register(env, SPR_620_HID8, "HID8",
2198 SPR_NOACCESS, SPR_NOACCESS,
2199 &spr_read_generic, &spr_write_generic,
2200 0x00000000);
2201 /* XXX : not implemented */
2202 spr_register(env, SPR_620_HID9, "HID9",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_generic,
2205 0x00000000);
2206 }
2207 #endif /* defined (TARGET_PPC64) */
2208
2209 // XXX: TODO
2210 /*
2211 * AMR => SPR 29 (Power 2.04)
2212 * CTRL => SPR 136 (Power 2.04)
2213 * CTRL => SPR 152 (Power 2.04)
2214 * SCOMC => SPR 276 (64 bits ?)
2215 * SCOMD => SPR 277 (64 bits ?)
2216 * TBU40 => SPR 286 (Power 2.04 hypv)
2217 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2218 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2219 * HDSISR => SPR 306 (Power 2.04 hypv)
2220 * HDAR => SPR 307 (Power 2.04 hypv)
2221 * PURR => SPR 309 (Power 2.04 hypv)
2222 * HDEC => SPR 310 (Power 2.04 hypv)
2223 * HIOR => SPR 311 (hypv)
2224 * RMOR => SPR 312 (970)
2225 * HRMOR => SPR 313 (Power 2.04 hypv)
2226 * HSRR0 => SPR 314 (Power 2.04 hypv)
2227 * HSRR1 => SPR 315 (Power 2.04 hypv)
2228 * LPCR => SPR 316 (970)
2229 * LPIDR => SPR 317 (970)
2230 * SPEFSCR => SPR 512 (Power 2.04 emb)
2231 * EPR => SPR 702 (Power 2.04 emb)
2232 * perf => 768-783 (Power 2.04)
2233 * perf => 784-799 (Power 2.04)
2234 * PPR => SPR 896 (Power 2.04)
2235 * EPLC => SPR 947 (Power 2.04 emb)
2236 * EPSC => SPR 948 (Power 2.04 emb)
2237 * DABRX => 1015 (Power 2.04 hypv)
2238 * FPECR => SPR 1022 (?)
2239 * ... and more (thermal management, performance counters, ...)
2240 */
2241
2242 /*****************************************************************************/
2243 /* Exception vectors models */
2244 static void init_excp_4xx_real (CPUPPCState *env)
2245 {
2246 #if !defined(CONFIG_USER_ONLY)
2247 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2248 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2249 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2250 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2251 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2252 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2253 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2254 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2255 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2256 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2257 env->excp_prefix = 0x00000000UL;
2258 env->ivor_mask = 0x0000FFF0UL;
2259 env->ivpr_mask = 0xFFFF0000UL;
2260 /* Hardware reset vector */
2261 env->hreset_vector = 0xFFFFFFFCUL;
2262 #endif
2263 }
2264
2265 static void init_excp_4xx_softmmu (CPUPPCState *env)
2266 {
2267 #if !defined(CONFIG_USER_ONLY)
2268 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2269 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2270 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2271 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2272 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2273 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2274 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2275 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2276 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2277 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2278 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2279 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2280 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2281 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2282 env->excp_prefix = 0x00000000UL;
2283 env->ivor_mask = 0x0000FFF0UL;
2284 env->ivpr_mask = 0xFFFF0000UL;
2285 /* Hardware reset vector */
2286 env->hreset_vector = 0xFFFFFFFCUL;
2287 #endif
2288 }
2289
2290 static void init_excp_BookE (CPUPPCState *env)
2291 {
2292 #if !defined(CONFIG_USER_ONLY)
2293 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2294 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2295 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2296 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2297 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2298 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2299 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2300 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2301 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2302 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2303 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2304 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2305 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2306 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2307 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2308 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2309 env->excp_prefix = 0x00000000UL;
2310 env->ivor_mask = 0x0000FFE0UL;
2311 env->ivpr_mask = 0xFFFF0000UL;
2312 /* Hardware reset vector */
2313 env->hreset_vector = 0xFFFFFFFCUL;
2314 #endif
2315 }
2316
2317 static void init_excp_601 (CPUPPCState *env)
2318 {
2319 #if !defined(CONFIG_USER_ONLY)
2320 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2321 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2322 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2323 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2324 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2325 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2326 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2327 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2328 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2329 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2330 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2331 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2332 env->excp_prefix = 0xFFF00000UL;
2333 /* Hardware reset vector */
2334 env->hreset_vector = 0x00000100UL;
2335 #endif
2336 }
2337
2338 static void init_excp_602 (CPUPPCState *env)
2339 {
2340 #if !defined(CONFIG_USER_ONLY)
2341 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2342 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2343 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2344 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2345 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2346 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2347 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2348 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2349 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2350 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2351 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2352 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2353 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2354 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2355 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2356 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2357 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2358 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2359 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2360 env->excp_prefix = 0xFFF00000UL;
2361 /* Hardware reset vector */
2362 env->hreset_vector = 0xFFFFFFFCUL;
2363 #endif
2364 }
2365
2366 static void init_excp_603 (CPUPPCState *env)
2367 {
2368 #if !defined(CONFIG_USER_ONLY)
2369 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2370 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2371 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2372 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2373 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2374 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2375 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2376 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2377 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2378 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2379 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2380 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2381 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2382 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2383 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2384 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2385 env->excp_prefix = 0x00000000UL;
2386 /* Hardware reset vector */
2387 env->hreset_vector = 0xFFFFFFFCUL;
2388 #endif
2389 }
2390
2391 static void init_excp_G2 (CPUPPCState *env)
2392 {
2393 #if !defined(CONFIG_USER_ONLY)
2394 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2395 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2396 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2397 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2398 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2399 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2400 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2401 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2402 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2403 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2404 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2405 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2406 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2407 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2408 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2409 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2410 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2411 env->excp_prefix = 0x00000000UL;
2412 /* Hardware reset vector */
2413 env->hreset_vector = 0xFFFFFFFCUL;
2414 #endif
2415 }
2416
2417 static void init_excp_604 (CPUPPCState *env)
2418 {
2419 #if !defined(CONFIG_USER_ONLY)
2420 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2421 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2422 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2423 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2424 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2425 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2426 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2427 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2428 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2429 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2430 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2431 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2432 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2433 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2434 env->excp_prefix = 0x00000000UL;
2435 /* Hardware reset vector */
2436 env->hreset_vector = 0xFFFFFFFCUL;
2437 #endif
2438 }
2439
2440 #if defined(TARGET_PPC64)
2441 static void init_excp_620 (CPUPPCState *env)
2442 {
2443 #if !defined(CONFIG_USER_ONLY)
2444 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2445 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2446 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2447 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2448 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2449 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2450 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2451 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2452 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2453 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2454 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2455 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2456 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2457 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2458 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2459 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2460 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2461 env->excp_prefix = 0xFFF00000UL;
2462 /* Hardware reset vector */
2463 env->hreset_vector = 0x0000000000000100ULL;
2464 #endif
2465 }
2466 #endif /* defined(TARGET_PPC64) */
2467
2468 static void init_excp_7x0 (CPUPPCState *env)
2469 {
2470 #if !defined(CONFIG_USER_ONLY)
2471 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2472 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2473 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2474 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2475 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2476 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2477 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2478 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2479 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2480 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2481 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2482 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2483 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2484 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2485 env->excp_prefix = 0x00000000UL;
2486 /* Hardware reset vector */
2487 env->hreset_vector = 0xFFFFFFFCUL;
2488 #endif
2489 }
2490
2491 static void init_excp_750FX (CPUPPCState *env)
2492 {
2493 #if !defined(CONFIG_USER_ONLY)
2494 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2495 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2496 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2497 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2498 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2499 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2500 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2501 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2502 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2503 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2504 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2505 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2506 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2507 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2508 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2509 env->excp_prefix = 0x00000000UL;
2510 /* Hardware reset vector */
2511 env->hreset_vector = 0xFFFFFFFCUL;
2512 #endif
2513 }
2514
2515 /* XXX: Check if this is correct */
2516 static void init_excp_7x5 (CPUPPCState *env)
2517 {
2518 #if !defined(CONFIG_USER_ONLY)
2519 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2520 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2521 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2522 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2523 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2524 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2525 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2526 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2527 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2528 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2529 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2530 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2531 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2532 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2533 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2534 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2535 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2536 env->excp_prefix = 0x00000000UL;
2537 /* Hardware reset vector */
2538 env->hreset_vector = 0xFFFFFFFCUL;
2539 #endif
2540 }
2541
2542 static void init_excp_7400 (CPUPPCState *env)
2543 {
2544 #if !defined(CONFIG_USER_ONLY)
2545 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2546 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2547 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2548 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2549 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2550 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2551 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2552 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2553 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2554 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2555 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2556 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2557 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2558 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2559 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2560 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2561 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2562 env->excp_prefix = 0x00000000UL;
2563 /* Hardware reset vector */
2564 env->hreset_vector = 0xFFFFFFFCUL;
2565 #endif
2566 }
2567
2568 static void init_excp_7450 (CPUPPCState *env)
2569 {
2570 #if !defined(CONFIG_USER_ONLY)
2571 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2572 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2573 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2574 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2575 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2576 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2577 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2578 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2579 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2580 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2581 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2582 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2583 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2584 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2585 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2586 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2587 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2588 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2589 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2590 env->excp_prefix = 0x00000000UL;
2591 /* Hardware reset vector */
2592 env->hreset_vector = 0xFFFFFFFCUL;
2593 #endif
2594 }
2595
2596 #if defined (TARGET_PPC64)
2597 static void init_excp_970 (CPUPPCState *env)
2598 {
2599 #if !defined(CONFIG_USER_ONLY)
2600 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2601 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2602 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2603 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2604 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2605 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2606 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2607 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2608 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2609 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2610 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2611 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2612 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2613 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2614 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2615 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2616 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2617 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2618 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2619 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2620 env->excp_prefix = 0x00000000FFF00000ULL;
2621 /* Hardware reset vector */
2622 env->hreset_vector = 0x0000000000000100ULL;
2623 #endif
2624 }
2625 #endif
2626
2627 /*****************************************************************************/
2628 /* Power management enable checks */
2629 static int check_pow_none (CPUPPCState *env)
2630 {
2631 return 0;
2632 }
2633
2634 static int check_pow_nocheck (CPUPPCState *env)
2635 {
2636 return 1;
2637 }
2638
2639 static int check_pow_hid0 (CPUPPCState *env)
2640 {
2641 if (env->spr[SPR_HID0] & 0x00E00000)
2642 return 1;
2643
2644 return 0;
2645 }
2646
2647 /*****************************************************************************/
2648 /* PowerPC implementations definitions */
2649
2650 /* PowerPC 40x instruction set */
2651 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON | \
2652 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)
2653
2654 /* PowerPC 401 */
2655 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2656 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2657 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2658 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2659 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2660 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2661 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2662 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2663 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2664 #define check_pow_401 check_pow_nocheck
2665
2666 static void init_proc_401 (CPUPPCState *env)
2667 {
2668 gen_spr_40x(env);
2669 gen_spr_401_403(env);
2670 gen_spr_401(env);
2671 init_excp_4xx_real(env);
2672 env->dcache_line_size = 32;
2673 env->icache_line_size = 32;
2674 /* Allocate hardware IRQ controller */
2675 ppc40x_irq_init(env);
2676 }
2677
2678 /* PowerPC 401x2 */
2679 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2680 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2681 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2682 PPC_CACHE_DCBA | PPC_MFTB | \
2683 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2684 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2685 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2686 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2687 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2688 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2689 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2690 #define check_pow_401x2 check_pow_nocheck
2691
2692 static void init_proc_401x2 (CPUPPCState *env)
2693 {
2694 gen_spr_40x(env);
2695 gen_spr_401_403(env);
2696 gen_spr_401x2(env);
2697 gen_spr_compress(env);
2698 /* Memory management */
2699 #if !defined(CONFIG_USER_ONLY)
2700 env->nb_tlb = 64;
2701 env->nb_ways = 1;
2702 env->id_tlbs = 0;
2703 #endif
2704 init_excp_4xx_softmmu(env);
2705 env->dcache_line_size = 32;
2706 env->icache_line_size = 32;
2707 /* Allocate hardware IRQ controller */
2708 ppc40x_irq_init(env);
2709 }
2710
2711 /* PowerPC 401x3 */
2712 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2713 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2714 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2715 PPC_CACHE_DCBA | PPC_MFTB | \
2716 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2717 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2718 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2719 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2720 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2721 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2722 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2723 #define check_pow_401x3 check_pow_nocheck
2724
2725 __attribute__ (( unused ))
2726 static void init_proc_401x3 (CPUPPCState *env)
2727 {
2728 gen_spr_40x(env);
2729 gen_spr_401_403(env);
2730 gen_spr_401(env);
2731 gen_spr_401x2(env);
2732 gen_spr_compress(env);
2733 init_excp_4xx_softmmu(env);
2734 env->dcache_line_size = 32;
2735 env->icache_line_size = 32;
2736 /* Allocate hardware IRQ controller */
2737 ppc40x_irq_init(env);
2738 }
2739
2740 /* IOP480 */
2741 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2742 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2743 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2744 PPC_CACHE_DCBA | \
2745 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2746 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2747 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2748 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2749 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2750 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2751 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE)
2752 #define check_pow_IOP480 check_pow_nocheck
2753
2754 static void init_proc_IOP480 (CPUPPCState *env)
2755 {
2756 gen_spr_40x(env);
2757 gen_spr_401_403(env);
2758 gen_spr_401x2(env);
2759 gen_spr_compress(env);
2760 /* Memory management */
2761 #if !defined(CONFIG_USER_ONLY)
2762 env->nb_tlb = 64;
2763 env->nb_ways = 1;
2764 env->id_tlbs = 0;
2765 #endif
2766 init_excp_4xx_softmmu(env);
2767 env->dcache_line_size = 32;
2768 env->icache_line_size = 32;
2769 /* Allocate hardware IRQ controller */
2770 ppc40x_irq_init(env);
2771 }
2772
2773 /* PowerPC 403 */
2774 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2775 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2776 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2777 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2778 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2779 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2780 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2781 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2782 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2783 #define check_pow_403 check_pow_nocheck
2784
2785 static void init_proc_403 (CPUPPCState *env)
2786 {
2787 gen_spr_40x(env);
2788 gen_spr_401_403(env);
2789 gen_spr_403(env);
2790 gen_spr_403_real(env);
2791 init_excp_4xx_real(env);
2792 env->dcache_line_size = 32;
2793 env->icache_line_size = 32;
2794 /* Allocate hardware IRQ controller */
2795 ppc40x_irq_init(env);
2796 #if !defined(CONFIG_USER_ONLY)
2797 /* Hardware reset vector */
2798 env->hreset_vector = 0xFFFFFFFCUL;
2799 #endif
2800 }
2801
2802 /* PowerPC 403 GCX */
2803 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2804 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2805 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2806 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2807 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2808 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2809 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2810 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2811 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2812 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX)
2813 #define check_pow_403GCX check_pow_nocheck
2814
2815 static void init_proc_403GCX (CPUPPCState *env)
2816 {
2817 gen_spr_40x(env);
2818 gen_spr_401_403(env);
2819 gen_spr_403(env);
2820 gen_spr_403_real(env);
2821 gen_spr_403_mmu(env);
2822 /* Bus access control */
2823 /* not emulated, as Qemu never does speculative access */
2824 spr_register(env, SPR_40x_SGR, "SGR",
2825 SPR_NOACCESS, SPR_NOACCESS,
2826 &spr_read_generic, &spr_write_generic,
2827 0xFFFFFFFF);
2828 /* not emulated, as Qemu do not emulate caches */
2829 spr_register(env, SPR_40x_DCWR, "DCWR",
2830 SPR_NOACCESS, SPR_NOACCESS,
2831 &spr_read_generic, &spr_write_generic,
2832 0x00000000);
2833 /* Memory management */
2834 #if !defined(CONFIG_USER_ONLY)
2835 env->nb_tlb = 64;
2836 env->nb_ways = 1;
2837 env->id_tlbs = 0;
2838 #endif
2839 init_excp_4xx_softmmu(env);
2840 env->dcache_line_size = 32;
2841 env->icache_line_size = 32;
2842 /* Allocate hardware IRQ controller */
2843 ppc40x_irq_init(env);
2844 }
2845
2846 /* PowerPC 405 */
2847 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2848 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2849 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2850 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2851 PPC_405_MAC)
2852 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2853 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2854 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2855 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2856 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2857 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2858 POWERPC_FLAG_DE)
2859 #define check_pow_405 check_pow_nocheck
2860
2861 static void init_proc_405 (CPUPPCState *env)
2862 {
2863 /* Time base */
2864 gen_tbl(env);
2865 gen_spr_40x(env);
2866 gen_spr_405(env);
2867 /* Bus access control */
2868 /* not emulated, as Qemu never does speculative access */
2869 spr_register(env, SPR_40x_SGR, "SGR",
2870 SPR_NOACCESS, SPR_NOACCESS,
2871 &spr_read_generic, &spr_write_generic,
2872 0xFFFFFFFF);
2873 /* not emulated, as Qemu do not emulate caches */
2874 spr_register(env, SPR_40x_DCWR, "DCWR",
2875 SPR_NOACCESS, SPR_NOACCESS,
2876 &spr_read_generic, &spr_write_generic,
2877 0x00000000);
2878 /* Memory management */
2879 #if !defined(CONFIG_USER_ONLY)
2880 env->nb_tlb = 64;
2881 env->nb_ways = 1;
2882 env->id_tlbs = 0;
2883 #endif
2884 init_excp_4xx_softmmu(env);
2885 env->dcache_line_size = 32;
2886 env->icache_line_size = 32;
2887 /* Allocate hardware IRQ controller */
2888 ppc40x_irq_init(env);
2889 }
2890
2891 /* PowerPC 440 EP */
2892 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2893 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2894 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2895 PPC_440_SPEC | PPC_RFMCI)
2896 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2897 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2898 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2899 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2900 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2901 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2902 POWERPC_FLAG_DE)
2903 #define check_pow_440EP check_pow_nocheck
2904
2905 static void init_proc_440EP (CPUPPCState *env)
2906 {
2907 /* Time base */
2908 gen_tbl(env);
2909 gen_spr_BookE(env);
2910 gen_spr_440(env);
2911 /* XXX : not implemented */
2912 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2913 SPR_NOACCESS, SPR_NOACCESS,
2914 &spr_read_generic, &spr_write_generic,
2915 0x00000000);
2916 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2917 SPR_NOACCESS, SPR_NOACCESS,
2918 &spr_read_generic, &spr_write_generic,
2919 0x00000000);
2920 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2921 SPR_NOACCESS, SPR_NOACCESS,
2922 &spr_read_generic, &spr_write_generic,
2923 0x00000000);
2924 /* XXX : not implemented */
2925 spr_register(env, SPR_440_CCR1, "CCR1",
2926 SPR_NOACCESS, SPR_NOACCESS,
2927 &spr_read_generic, &spr_write_generic,
2928 0x00000000);
2929 /* Memory management */
2930 #if !defined(CONFIG_USER_ONLY)
2931 env->nb_tlb = 64;
2932 env->nb_ways = 1;
2933 env->id_tlbs = 0;
2934 #endif
2935 init_excp_BookE(env);
2936 env->dcache_line_size = 32;
2937 env->icache_line_size = 32;
2938 /* XXX: TODO: allocate internal IRQ controller */
2939 }
2940
2941 /* PowerPC 440 GP */
2942 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2943 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2944 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2945 PPC_405_MAC | PPC_440_SPEC)
2946 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2947 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2948 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2949 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2950 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2951 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2952 POWERPC_FLAG_DE)
2953 #define check_pow_440GP check_pow_nocheck
2954
2955 static void init_proc_440GP (CPUPPCState *env)
2956 {
2957 /* Time base */
2958 gen_tbl(env);
2959 gen_spr_BookE(env);
2960 gen_spr_440(env);
2961 /* Memory management */
2962 #if !defined(CONFIG_USER_ONLY)
2963 env->nb_tlb = 64;
2964 env->nb_ways = 1;
2965 env->id_tlbs = 0;
2966 #endif
2967 init_excp_BookE(env);
2968 env->dcache_line_size = 32;
2969 env->icache_line_size = 32;
2970 /* XXX: TODO: allocate internal IRQ controller */
2971 }
2972
2973 /* PowerPC 440x4 */
2974 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2975 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2976 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2977 PPC_440_SPEC)
2978 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2979 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2980 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2981 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2982 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2983 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
2984 POWERPC_FLAG_DE)
2985 #define check_pow_440x4 check_pow_nocheck
2986
2987 __attribute__ (( unused ))
2988 static void init_proc_440x4 (CPUPPCState *env)
2989 {
2990 /* Time base */
2991 gen_tbl(env);
2992 gen_spr_BookE(env);
2993 gen_spr_440(env);
2994 /* Memory management */
2995 #if !defined(CONFIG_USER_ONLY)
2996 env->nb_tlb = 64;
2997 env->nb_ways = 1;
2998 env->id_tlbs = 0;
2999 #endif
3000 init_excp_BookE(env);
3001 env->dcache_line_size = 32;
3002 env->icache_line_size = 32;
3003 /* XXX: TODO: allocate internal IRQ controller */
3004 }
3005
3006 /* PowerPC 440x5 */
3007 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
3008 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3009 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3010 PPC_440_SPEC | PPC_RFMCI)
3011 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3012 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3013 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3014 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3015 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3016 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3017 POWERPC_FLAG_DE)
3018 #define check_pow_440x5 check_pow_nocheck
3019
3020 static void init_proc_440x5 (CPUPPCState *env)
3021 {
3022 /* Time base */
3023 gen_tbl(env);
3024 gen_spr_BookE(env);
3025 gen_spr_440(env);
3026 /* XXX : not implemented */
3027 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3028 SPR_NOACCESS, SPR_NOACCESS,
3029 &spr_read_generic, &spr_write_generic,
3030 0x00000000);
3031 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3032 SPR_NOACCESS, SPR_NOACCESS,
3033 &spr_read_generic, &spr_write_generic,
3034 0x00000000);
3035 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3036 SPR_NOACCESS, SPR_NOACCESS,
3037 &spr_read_generic, &spr_write_generic,
3038 0x00000000);
3039 /* XXX : not implemented */
3040 spr_register(env, SPR_440_CCR1, "CCR1",
3041 SPR_NOACCESS, SPR_NOACCESS,
3042 &spr_read_generic, &spr_write_generic,
3043 0x00000000);
3044 /* Memory management */
3045 #if !defined(CONFIG_USER_ONLY)
3046 env->nb_tlb = 64;
3047 env->nb_ways = 1;
3048 env->id_tlbs = 0;
3049 #endif
3050 init_excp_BookE(env);
3051 env->dcache_line_size = 32;
3052 env->icache_line_size = 32;
3053 /* XXX: TODO: allocate internal IRQ controller */
3054 }
3055
3056 /* PowerPC 460 (guessed) */
3057 #define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | \
3058 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3059 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3060 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3061 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3062 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3063 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3064 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3065 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3066 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3067 POWERPC_FLAG_DE)
3068 #define check_pow_460 check_pow_nocheck
3069
3070 __attribute__ (( unused ))
3071 static void init_proc_460 (CPUPPCState *env)
3072 {
3073 /* Time base */
3074 gen_tbl(env);
3075 gen_spr_BookE(env);
3076 gen_spr_440(env);
3077 /* XXX : not implemented */
3078 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3079 SPR_NOACCESS, SPR_NOACCESS,
3080 &spr_read_generic, &spr_write_generic,
3081 0x00000000);
3082 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3083 SPR_NOACCESS, SPR_NOACCESS,
3084 &spr_read_generic, &spr_write_generic,
3085 0x00000000);
3086 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3087 SPR_NOACCESS, SPR_NOACCESS,
3088 &spr_read_generic, &spr_write_generic,
3089 0x00000000);
3090 /* XXX : not implemented */
3091 spr_register(env, SPR_440_CCR1, "CCR1",
3092 SPR_NOACCESS, SPR_NOACCESS,
3093 &spr_read_generic, &spr_write_generic,
3094 0x00000000);
3095 /* XXX : not implemented */
3096 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3097 &spr_read_generic, &spr_write_generic,
3098 &spr_read_generic, &spr_write_generic,
3099 0x00000000);
3100 /* Memory management */
3101 #if !defined(CONFIG_USER_ONLY)
3102 env->nb_tlb = 64;
3103 env->nb_ways = 1;
3104 env->id_tlbs = 0;
3105 #endif
3106 init_excp_BookE(env);
3107 env->dcache_line_size = 32;
3108 env->icache_line_size = 32;
3109 /* XXX: TODO: allocate internal IRQ controller */
3110 }
3111
3112 /* PowerPC 460F (guessed) */
3113 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
3114 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
3115 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
3116 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
3117 PPC_FLOAT_STFIWX | \
3118 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
3119 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
3120 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3121 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3122 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3123 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3124 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3125 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3126 POWERPC_FLAG_DE)
3127 #define check_pow_460F check_pow_nocheck
3128
3129 __attribute__ (( unused ))
3130 static void init_proc_460F (CPUPPCState *env)
3131 {
3132 /* Time base */
3133 gen_tbl(env);
3134 gen_spr_BookE(env);
3135 gen_spr_440(env);
3136 /* XXX : not implemented */
3137 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3138 SPR_NOACCESS, SPR_NOACCESS,
3139 &spr_read_generic, &spr_write_generic,
3140 0x00000000);
3141 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3142 SPR_NOACCESS, SPR_NOACCESS,
3143 &spr_read_generic, &spr_write_generic,
3144 0x00000000);
3145 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3146 SPR_NOACCESS, SPR_NOACCESS,
3147 &spr_read_generic, &spr_write_generic,
3148 0x00000000);
3149 /* XXX : not implemented */
3150 spr_register(env, SPR_440_CCR1, "CCR1",
3151 SPR_NOACCESS, SPR_NOACCESS,
3152 &spr_read_generic, &spr_write_generic,
3153 0x00000000);
3154 /* XXX : not implemented */
3155 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3156 &spr_read_generic, &spr_write_generic,
3157 &spr_read_generic, &spr_write_generic,
3158 0x00000000);
3159 /* Memory management */
3160 #if !defined(CONFIG_USER_ONLY)
3161 env->nb_tlb = 64;
3162 env->nb_ways = 1;
3163 env->id_tlbs = 0;
3164 #endif
3165 init_excp_BookE(env);
3166 env->dcache_line_size = 32;
3167 env->icache_line_size = 32;
3168 /* XXX: TODO: allocate internal IRQ controller */
3169 }
3170
3171 /* Generic BookE PowerPC */
3172 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
3173 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3174 PPC_CACHE_DCBA | \
3175 PPC_FLOAT | PPC_FLOAT_FSQRT | \
3176 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3177 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3178 PPC_BOOKE)
3179 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
3180 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
3181 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
3182 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
3183 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
3184 #define POWERPC_FLAG_BookE (POWERPC_FLAG_NONE)
3185 #define check_pow_BookE check_pow_nocheck
3186
3187 __attribute__ (( unused ))
3188 static void init_proc_BookE (CPUPPCState *env)
3189 {
3190 init_excp_BookE(env);
3191 env->dcache_line_size = 32;
3192 env->icache_line_size = 32;
3193 }
3194
3195 /* e200 core */
3196
3197 /* e300 core */
3198
3199 /* e500 core */
3200 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
3201 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
3202 PPC_CACHE_DCBA | \
3203 PPC_BOOKE | PPC_E500_VECTOR)
3204 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
3205 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
3206 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
3207 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
3208 #define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE)
3209 #define check_pow_e500 check_pow_hid0
3210
3211 __attribute__ (( unused ))
3212 static void init_proc_e500 (CPUPPCState *env)
3213 {
3214 /* Time base */
3215 gen_tbl(env);
3216 gen_spr_BookE(env);
3217 /* Memory management */
3218 gen_spr_BookE_FSL(env);
3219 #if !defined(CONFIG_USER_ONLY)
3220 env->nb_tlb = 64;
3221 env->nb_ways = 1;
3222 env->id_tlbs = 0;
3223 #endif
3224 init_excp_BookE(env);
3225 env->dcache_line_size = 32;
3226 env->icache_line_size = 32;
3227 /* XXX: TODO: allocate internal IRQ controller */
3228 }
3229
3230 /* e600 core */
3231
3232 /* Non-embedded PowerPC */
3233 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
3234 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | \
3235 PPC_CACHE | PPC_CACHE_ICBI | \
3236 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE)
3237 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
3238 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
3239 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3240 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3241 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
3242 PPC_SEGMENT)
3243
3244 /* POWER : same as 601, without mfmsr, mfsr */
3245 #if defined(TODO)
3246 #define POWERPC_INSNS_POWER (XXX_TODO)
3247 /* POWER RSC (from RAD6000) */
3248 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
3249 #endif /* TODO */
3250
3251 /* PowerPC 601 */
3252 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
3253 PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
3254 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
3255 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
3256 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
3257 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
3258 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
3259 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE)
3260 #define check_pow_601 check_pow_none
3261
3262 static void init_proc_601 (CPUPPCState *env)
3263 {
3264 gen_spr_ne_601(env);
3265 gen_spr_601(env);
3266 /* Hardware implementation registers */
3267 /* XXX : not implemented */
3268 spr_register(env, SPR_HID0, "HID0",
3269 SPR_NOACCESS, SPR_NOACCESS,
3270 &spr_read_generic, &spr_write_hid0_601,
3271 0x80010080);
3272 /* XXX : not implemented */
3273 spr_register(env, SPR_HID1, "HID1",
3274 SPR_NOACCESS, SPR_NOACCESS,
3275 &spr_read_generic, &spr_write_generic,
3276 0x00000000);
3277 /* XXX : not implemented */
3278 spr_register(env, SPR_601_HID2, "HID2",
3279 SPR_NOACCESS, SPR_NOACCESS,
3280 &spr_read_generic, &spr_write_generic,
3281 0x00000000);
3282 /* XXX : not implemented */
3283 spr_register(env, SPR_601_HID5, "HID5",
3284 SPR_NOACCESS, SPR_NOACCESS,
3285 &spr_read_generic, &spr_write_generic,
3286 0x00000000);
3287 /* XXX : not implemented */
3288 spr_register(env, SPR_601_HID15, "HID15",
3289 SPR_NOACCESS, SPR_NOACCESS,
3290 &spr_read_generic, &spr_write_generic,
3291 0x00000000);
3292 /* Memory management */
3293 #if !defined(CONFIG_USER_ONLY)
3294 env->nb_tlb = 64;
3295 env->nb_ways = 2;
3296 env->id_tlbs = 0;
3297 #endif
3298 init_excp_601(env);
3299 env->dcache_line_size = 64;
3300 env->icache_line_size = 64;
3301 /* Allocate hardware IRQ controller */
3302 ppc6xx_irq_init(env);
3303 }
3304
3305 /* PowerPC 602 */
3306 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3307 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3308 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3309 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
3310 PPC_SEGMENT | PPC_602_SPEC)
3311 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3312 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3313 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3314 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
3315 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
3316 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3317 POWERPC_FLAG_BE)
3318 #define check_pow_602 check_pow_hid0
3319
3320 static void init_proc_602 (CPUPPCState *env)
3321 {
3322 gen_spr_ne_601(env);
3323 gen_spr_602(env);
3324 /* Time base */
3325 gen_tbl(env);
3326 /* hardware implementation registers */
3327 /* XXX : not implemented */
3328 spr_register(env, SPR_HID0, "HID0",
3329 SPR_NOACCESS, SPR_NOACCESS,
3330 &spr_read_generic, &spr_write_generic,
3331 0x00000000);
3332 /* XXX : not implemented */
3333 spr_register(env, SPR_HID1, "HID1",
3334 SPR_NOACCESS, SPR_NOACCESS,
3335 &spr_read_generic, &spr_write_generic,
3336 0x00000000);
3337 /* Memory management */
3338 gen_low_BATs(env);
3339 gen_6xx_7xx_soft_tlb(env, 64, 2);
3340 init_excp_602(env);
3341 env->dcache_line_size = 32;
3342 env->icache_line_size = 32;
3343 /* Allocate hardware IRQ controller */
3344 ppc6xx_irq_init(env);
3345 }
3346
3347 /* PowerPC 603 */
3348 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3349 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
3350 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3351 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3352 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
3353 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
3354 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3355 POWERPC_FLAG_BE)
3356 #define check_pow_603 check_pow_hid0
3357
3358 static void init_proc_603 (CPUPPCState *env)
3359 {
3360 gen_spr_ne_601(env);
3361 gen_spr_603(env);
3362 /* Time base */
3363 gen_tbl(env);
3364 /* hardware implementation registers */
3365 /* XXX : not implemented */
3366 spr_register(env, SPR_HID0, "HID0",
3367 SPR_NOACCESS, SPR_NOACCESS,
3368 &spr_read_generic, &spr_write_generic,
3369 0x00000000);
3370 /* XXX : not implemented */
3371 spr_register(env, SPR_HID1, "HID1",
3372 SPR_NOACCESS, SPR_NOACCESS,
3373 &spr_read_generic, &spr_write_generic,
3374 0x00000000);
3375 /* Memory management */
3376 gen_low_BATs(env);
3377 gen_6xx_7xx_soft_tlb(env, 64, 2);
3378 init_excp_603(env);
3379 env->dcache_line_size = 32;
3380 env->icache_line_size = 32;
3381 /* Allocate hardware IRQ controller */
3382 ppc6xx_irq_init(env);
3383 }
3384
3385 /* PowerPC 603e */
3386 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3387 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3388 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3389 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3390 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
3391 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
3392 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3393 POWERPC_FLAG_BE)
3394 #define check_pow_603E check_pow_hid0
3395
3396 static void init_proc_603E (CPUPPCState *env)
3397 {
3398 gen_spr_ne_601(env);
3399 gen_spr_603(env);
3400 /* Time base */
3401 gen_tbl(env);
3402 /* hardware implementation registers */
3403 /* XXX : not implemented */
3404 spr_register(env, SPR_HID0, "HID0",
3405 SPR_NOACCESS, SPR_NOACCESS,
3406 &spr_read_generic, &spr_write_generic,
3407 0x00000000);
3408 /* XXX : not implemented */
3409 spr_register(env, SPR_HID1, "HID1",
3410 SPR_NOACCESS, SPR_NOACCESS,
3411 &spr_read_generic, &spr_write_generic,
3412 0x00000000);
3413 /* XXX : not implemented */
3414 spr_register(env, SPR_IABR, "IABR",
3415 SPR_NOACCESS, SPR_NOACCESS,
3416 &spr_read_generic, &spr_write_generic,
3417 0x00000000);
3418 /* Memory management */
3419 gen_low_BATs(env);
3420 gen_6xx_7xx_soft_tlb(env, 64, 2);
3421 init_excp_603(env);
3422 env->dcache_line_size = 32;
3423 env->icache_line_size = 32;
3424 /* Allocate hardware IRQ controller */
3425 ppc6xx_irq_init(env);
3426 }
3427
3428 /* PowerPC G2 */
3429 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3430 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3431 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3432 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3433 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3434 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3435 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3436 POWERPC_FLAG_BE)
3437 #define check_pow_G2 check_pow_hid0
3438
3439 static void init_proc_G2 (CPUPPCState *env)
3440 {
3441 gen_spr_ne_601(env);
3442 gen_spr_G2_755(env);
3443 gen_spr_G2(env);
3444 /* Time base */
3445 gen_tbl(env);
3446 /* Hardware implementation register */
3447 /* XXX : not implemented */
3448 spr_register(env, SPR_HID0, "HID0",
3449 SPR_NOACCESS, SPR_NOACCESS,
3450 &spr_read_generic, &spr_write_generic,
3451 0x00000000);
3452 /* XXX : not implemented */
3453 spr_register(env, SPR_HID1, "HID1",
3454 SPR_NOACCESS, SPR_NOACCESS,
3455 &spr_read_generic, &spr_write_generic,
3456 0x00000000);
3457 /* XXX : not implemented */
3458 spr_register(env, SPR_HID2, "HID2",
3459 SPR_NOACCESS, SPR_NOACCESS,
3460 &spr_read_generic, &spr_write_generic,
3461 0x00000000);
3462 /* Memory management */
3463 gen_low_BATs(env);
3464 gen_high_BATs(env);
3465 gen_6xx_7xx_soft_tlb(env, 64, 2);
3466 init_excp_G2(env);
3467 env->dcache_line_size = 32;
3468 env->icache_line_size = 32;
3469 /* Allocate hardware IRQ controller */
3470 ppc6xx_irq_init(env);
3471 }
3472
3473 /* PowerPC G2LE */
3474 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3475 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3476 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3477 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3478 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3479 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3480 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3481 POWERPC_FLAG_BE)
3482 #define check_pow_G2LE check_pow_hid0
3483
3484 static void init_proc_G2LE (CPUPPCState *env)
3485 {
3486 gen_spr_ne_601(env);
3487 gen_spr_G2_755(env);
3488 gen_spr_G2(env);
3489 /* Time base */
3490 gen_tbl(env);
3491 /* Hardware implementation register */
3492 /* XXX : not implemented */
3493 spr_register(env, SPR_HID0, "HID0",
3494 SPR_NOACCESS, SPR_NOACCESS,
3495 &spr_read_generic, &spr_write_generic,
3496 0x00000000);
3497 /* XXX : not implemented */
3498 spr_register(env, SPR_HID1, "HID1",
3499 SPR_NOACCESS, SPR_NOACCESS,
3500 &spr_read_generic, &spr_write_generic,
3501 0x00000000);
3502 /* XXX : not implemented */
3503 spr_register(env, SPR_HID2, "HID2",
3504 SPR_NOACCESS, SPR_NOACCESS,
3505 &spr_read_generic, &spr_write_generic,
3506 0x00000000);
3507 /* Memory management */
3508 gen_low_BATs(env);
3509 gen_high_BATs(env);
3510 gen_6xx_7xx_soft_tlb(env, 64, 2);
3511 init_excp_G2(env);
3512 env->dcache_line_size = 32;
3513 env->icache_line_size = 32;
3514 /* Allocate hardware IRQ controller */
3515 ppc6xx_irq_init(env);
3516 }
3517
3518 /* PowerPC 604 */
3519 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3520 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3521 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
3522 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3523 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
3524 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
3525 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3526 POWERPC_FLAG_PMM)
3527 #define check_pow_604 check_pow_nocheck
3528
3529 static void init_proc_604 (CPUPPCState *env)
3530 {
3531 gen_spr_ne_601(env);
3532 gen_spr_604(env);
3533 /* Time base */
3534 gen_tbl(env);
3535 /* Hardware implementation registers */
3536 /* XXX : not implemented */
3537 spr_register(env, SPR_HID0, "HID0",
3538 SPR_NOACCESS, SPR_NOACCESS,
3539 &spr_read_generic, &spr_write_generic,
3540 0x00000000);
3541 /* XXX : not implemented */
3542 spr_register(env, SPR_HID1, "HID1",
3543 SPR_NOACCESS, SPR_NOACCESS,
3544 &spr_read_generic, &spr_write_generic,
3545 0x00000000);
3546 /* Memory management */
3547 gen_low_BATs(env);
3548 init_excp_604(env);
3549 env->dcache_line_size = 32;
3550 env->icache_line_size = 32;
3551 /* Allocate hardware IRQ controller */
3552 ppc6xx_irq_init(env);
3553 }
3554
3555 /* PowerPC 740/750 (aka G3) */
3556 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3557 #define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
3558 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3559 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3560 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
3561 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
3562 #define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3563 POWERPC_FLAG_PMM)
3564 #define check_pow_7x0 check_pow_hid0
3565
3566 static void init_proc_7x0 (CPUPPCState *env)
3567 {
3568 gen_spr_ne_601(env);
3569 gen_spr_7xx(env);
3570 /* Time base */
3571 gen_tbl(env);
3572 /* Thermal management */
3573 gen_spr_thrm(env);
3574 /* Hardware implementation registers */
3575 /* XXX : not implemented */
3576 spr_register(env, SPR_HID0, "HID0",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 /* XXX : not implemented */
3581 spr_register(env, SPR_HID1, "HID1",
3582 SPR_NOACCESS, SPR_NOACCESS,
3583 &spr_read_generic, &spr_write_generic,
3584 0x00000000);
3585 /* Memory management */
3586 gen_low_BATs(env);
3587 init_excp_7x0(env);
3588 env->dcache_line_size = 32;
3589 env->icache_line_size = 32;
3590 /* Allocate hardware IRQ controller */
3591 ppc6xx_irq_init(env);
3592 }
3593
3594 /* PowerPC 750FX/GX */
3595 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3596 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
3597 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3598 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3599 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
3600 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
3601 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3602 POWERPC_FLAG_PMM)
3603 #define check_pow_750fx check_pow_hid0
3604
3605 static void init_proc_750fx (CPUPPCState *env)
3606 {
3607 gen_spr_ne_601(env);
3608 gen_spr_7xx(env);
3609 /* Time base */
3610 gen_tbl(env);
3611 /* Thermal management */
3612 gen_spr_thrm(env);
3613 /* Hardware implementation registers */
3614 /* XXX : not implemented */
3615 spr_register(env, SPR_HID0, "HID0",
3616 SPR_NOACCESS, SPR_NOACCESS,
3617 &spr_read_generic, &spr_write_generic,
3618 0x00000000);
3619 /* XXX : not implemented */
3620 spr_register(env, SPR_HID1, "HID1",
3621 SPR_NOACCESS, SPR_NOACCESS,
3622 &spr_read_generic, &spr_write_generic,
3623 0x00000000);
3624 /* XXX : not implemented */
3625 spr_register(env, SPR_750_HID2, "HID2",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_generic,
3628 0x00000000);
3629 /* Memory management */
3630 gen_low_BATs(env);
3631 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3632 gen_high_BATs(env);
3633 init_excp_750FX(env);
3634 env->dcache_line_size = 32;
3635 env->icache_line_size = 32;
3636 /* Allocate hardware IRQ controller */
3637 ppc6xx_irq_init(env);
3638 }
3639
3640 /* PowerPC 745/755 */
3641 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3642 #define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
3643 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3644 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3645 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
3646 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
3647 #define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3648 POWERPC_FLAG_PMM)
3649 #define check_pow_7x5 check_pow_hid0
3650
3651 static void init_proc_7x5 (CPUPPCState *env)
3652 {
3653 gen_spr_ne_601(env);
3654 gen_spr_G2_755(env);
3655 /* Time base */
3656 gen_tbl(env);
3657 /* L2 cache control */
3658 /* XXX : not implemented */
3659 spr_register(env, SPR_ICTC, "ICTC",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 /* XXX : not implemented */
3664 spr_register(env, SPR_L2PMCR, "L2PMCR",
3665 SPR_NOACCESS, SPR_NOACCESS,
3666 &spr_read_generic, &spr_write_generic,
3667 0x00000000);
3668 /* Hardware implementation registers */
3669 /* XXX : not implemented */
3670 spr_register(env, SPR_HID0, "HID0",
3671 SPR_NOACCESS, SPR_NOACCESS,
3672 &spr_read_generic, &spr_write_generic,
3673 0x00000000);
3674 /* XXX : not implemented */
3675 spr_register(env, SPR_HID1, "HID1",
3676 SPR_NOACCESS, SPR_NOACCESS,
3677 &spr_read_generic, &spr_write_generic,
3678 0x00000000);
3679 /* XXX : not implemented */
3680 spr_register(env, SPR_HID2, "HID2",
3681 SPR_NOACCESS, SPR_NOACCESS,
3682 &spr_read_generic, &spr_write_generic,
3683 0x00000000);
3684 /* Memory management */
3685 gen_low_BATs(env);
3686 gen_high_BATs(env);
3687 gen_6xx_7xx_soft_tlb(env, 64, 2);
3688 init_excp_7x5(env);
3689 env->dcache_line_size = 32;
3690 env->icache_line_size = 32;
3691 /* Allocate hardware IRQ controller */
3692 ppc6xx_irq_init(env);
3693 #if !defined(CONFIG_USER_ONLY)
3694 /* Hardware reset vector */
3695 env->hreset_vector = 0xFFFFFFFCUL;
3696 #endif
3697 }
3698
3699 /* PowerPC 7400 (aka G4) */
3700 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3701 PPC_EXTERN | PPC_MEM_TLBIA | \
3702 PPC_ALTIVEC)
3703 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3704 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3705 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3706 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3707 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3708 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3709 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3710 #define check_pow_7400 check_pow_hid0
3711
3712 static void init_proc_7400 (CPUPPCState *env)
3713 {
3714 gen_spr_ne_601(env);
3715 gen_spr_7xx(env);
3716 /* Time base */
3717 gen_tbl(env);
3718 /* 74xx specific SPR */
3719 gen_spr_74xx(env);
3720 /* Thermal management */
3721 gen_spr_thrm(env);
3722 /* Memory management */
3723 gen_low_BATs(env);
3724 init_excp_7400(env);
3725 env->dcache_line_size = 32;
3726 env->icache_line_size = 32;
3727 /* Allocate hardware IRQ controller */
3728 ppc6xx_irq_init(env);
3729 }
3730
3731 /* PowerPC 7410 (aka G4) */
3732 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3733 PPC_EXTERN | PPC_MEM_TLBIA | \
3734 PPC_ALTIVEC)
3735 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3736 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3737 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3738 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3739 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3740 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3741 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3742 #define check_pow_7410 check_pow_hid0
3743
3744 static void init_proc_7410 (CPUPPCState *env)
3745 {
3746 gen_spr_ne_601(env);
3747 gen_spr_7xx(env);
3748 /* Time base */
3749 gen_tbl(env);
3750 /* 74xx specific SPR */
3751 gen_spr_74xx(env);
3752 /* Thermal management */
3753 gen_spr_thrm(env);
3754 /* L2PMCR */
3755 /* XXX : not implemented */
3756 spr_register(env, SPR_L2PMCR, "L2PMCR",
3757 SPR_NOACCESS, SPR_NOACCESS,
3758 &spr_read_generic, &spr_write_generic,
3759 0x00000000);
3760 /* LDSTDB */
3761 /* XXX : not implemented */
3762 spr_register(env, SPR_LDSTDB, "LDSTDB",
3763 SPR_NOACCESS, SPR_NOACCESS,
3764 &spr_read_generic, &spr_write_generic,
3765 0x00000000);
3766 /* Memory management */
3767 gen_low_BATs(env);
3768 init_excp_7400(env);
3769 env->dcache_line_size = 32;
3770 env->icache_line_size = 32;
3771 /* Allocate hardware IRQ controller */
3772 ppc6xx_irq_init(env);
3773 }
3774
3775 /* PowerPC 7440 (aka G4) */
3776 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3777 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3778 PPC_ALTIVEC)
3779 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3780 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3781 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3782 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3783 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3784 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3785 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3786 #define check_pow_7440 check_pow_hid0
3787
3788 __attribute__ (( unused ))
3789 static void init_proc_7440 (CPUPPCState *env)
3790 {
3791 gen_spr_ne_601(env);
3792 gen_spr_7xx(env);
3793 /* Time base */
3794 gen_tbl(env);
3795 /* 74xx specific SPR */
3796 gen_spr_74xx(env);
3797 /* LDSTCR */
3798 /* XXX : not implemented */
3799 spr_register(env, SPR_LDSTCR, "LDSTCR",
3800 SPR_NOACCESS, SPR_NOACCESS,
3801 &spr_read_generic, &spr_write_generic,
3802 0x00000000);
3803 /* ICTRL */
3804 /* XXX : not implemented */
3805 spr_register(env, SPR_ICTRL, "ICTRL",
3806 SPR_NOACCESS, SPR_NOACCESS,
3807 &spr_read_generic, &spr_write_generic,
3808 0x00000000);
3809 /* MSSSR0 */
3810 /* XXX : not implemented */
3811 spr_register(env, SPR_MSSSR0, "MSSSR0",
3812 SPR_NOACCESS, SPR_NOACCESS,
3813 &spr_read_generic, &spr_write_generic,
3814 0x00000000);
3815 /* PMC */
3816 /* XXX : not implemented */
3817 spr_register(env, SPR_PMC5, "PMC5",
3818 SPR_NOACCESS, SPR_NOACCESS,
3819 &spr_read_generic, &spr_write_generic,
3820 0x00000000);
3821 /* XXX : not implemented */
3822 spr_register(env, SPR_UPMC5, "UPMC5",
3823 &spr_read_ureg, SPR_NOACCESS,
3824 &spr_read_ureg, SPR_NOACCESS,
3825 0x00000000);
3826 /* XXX : not implemented */
3827 spr_register(env, SPR_PMC6, "PMC6",
3828 SPR_NOACCESS, SPR_NOACCESS,
3829 &spr_read_generic, &spr_write_generic,
3830 0x00000000);
3831 /* XXX : not implemented */
3832 spr_register(env, SPR_UPMC6, "UPMC6",
3833 &spr_read_ureg, SPR_NOACCESS,
3834 &spr_read_ureg, SPR_NOACCESS,
3835 0x00000000);
3836 /* Memory management */
3837 gen_low_BATs(env);
3838 gen_74xx_soft_tlb(env, 128, 2);
3839 init_excp_7450(env);
3840 env->dcache_line_size = 32;
3841 env->icache_line_size = 32;
3842 /* Allocate hardware IRQ controller */
3843 ppc6xx_irq_init(env);
3844 }
3845
3846 /* PowerPC 7450 (aka G4) */
3847 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3848 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3849 PPC_ALTIVEC)
3850 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3851 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3852 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3853 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3854 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3855 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3856 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3857 #define check_pow_7450 check_pow_hid0
3858
3859 __attribute__ (( unused ))
3860 static void init_proc_7450 (CPUPPCState *env)
3861 {
3862 gen_spr_ne_601(env);
3863 gen_spr_7xx(env);
3864 /* Time base */
3865 gen_tbl(env);
3866 /* 74xx specific SPR */
3867 gen_spr_74xx(env);
3868 /* Level 3 cache control */
3869 gen_l3_ctrl(env);
3870 /* LDSTCR */
3871 /* XXX : not implemented */
3872 spr_register(env, SPR_LDSTCR, "LDSTCR",
3873 SPR_NOACCESS, SPR_NOACCESS,
3874 &spr_read_generic, &spr_write_generic,
3875 0x00000000);
3876 /* ICTRL */
3877 /* XXX : not implemented */
3878 spr_register(env, SPR_ICTRL, "ICTRL",
3879 SPR_NOACCESS, SPR_NOACCESS,
3880 &spr_read_generic, &spr_write_generic,
3881 0x00000000);
3882 /* MSSSR0 */
3883 /* XXX : not implemented */
3884 spr_register(env, SPR_MSSSR0, "MSSSR0",
3885 SPR_NOACCESS, SPR_NOACCESS,
3886 &spr_read_generic, &spr_write_generic,
3887 0x00000000);
3888 /* PMC */
3889 /* XXX : not implemented */
3890 spr_register(env, SPR_PMC5, "PMC5",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_UPMC5, "UPMC5",
3896 &spr_read_ureg, SPR_NOACCESS,
3897 &spr_read_ureg, SPR_NOACCESS,
3898 0x00000000);
3899 /* XXX : not implemented */
3900 spr_register(env, SPR_PMC6, "PMC6",
3901 SPR_NOACCESS, SPR_NOACCESS,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 /* XXX : not implemented */
3905 spr_register(env, SPR_UPMC6, "UPMC6",
3906 &spr_read_ureg, SPR_NOACCESS,
3907 &spr_read_ureg, SPR_NOACCESS,
3908 0x00000000);
3909 /* Memory management */
3910 gen_low_BATs(env);
3911 gen_74xx_soft_tlb(env, 128, 2);
3912 init_excp_7450(env);
3913 env->dcache_line_size = 32;
3914 env->icache_line_size = 32;
3915 /* Allocate hardware IRQ controller */
3916 ppc6xx_irq_init(env);
3917 }
3918
3919 /* PowerPC 7445 (aka G4) */
3920 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3921 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3922 PPC_ALTIVEC)
3923 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3924 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3925 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3926 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3927 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3928 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
3929 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
3930 #define check_pow_7445 check_pow_hid0
3931
3932 __attribute__ (( unused ))
3933 static void init_proc_7445 (CPUPPCState *env)
3934 {
3935 gen_spr_ne_601(env);
3936 gen_spr_7xx(env);
3937 /* Time base */
3938 gen_tbl(env);
3939 /* 74xx specific SPR */
3940 gen_spr_74xx(env);
3941 /* LDSTCR */
3942 /* XXX : not implemented */
3943 spr_register(env, SPR_LDSTCR, "LDSTCR",
3944 SPR_NOACCESS, SPR_NOACCESS,
3945 &spr_read_generic, &spr_write_generic,
3946 0x00000000);
3947 /* ICTRL */
3948 /* XXX : not implemented */
3949 spr_register(env, SPR_ICTRL, "ICTRL",
3950 SPR_NOACCESS, SPR_NOACCESS,
3951 &spr_read_generic, &spr_write_generic,
3952 0x00000000);
3953 /* MSSSR0 */
3954 /* XXX : not implemented */
3955 spr_register(env, SPR_MSSSR0, "MSSSR0",
3956 SPR_NOACCESS, SPR_NOACCESS,
3957 &spr_read_generic, &spr_write_generic,
3958 0x00000000);
3959 /* PMC */
3960 /* XXX : not implemented */
3961 spr_register(env, SPR_PMC5, "PMC5",
3962 SPR_NOACCESS, SPR_NOACCESS,
3963 &spr_read_generic, &spr_write_generic,
3964 0x00000000);
3965 /* XXX : not implemented */
3966 spr_register(env, SPR_UPMC5, "UPMC5",
3967 &spr_read_ureg, SPR_NOACCESS,
3968 &spr_read_ureg, SPR_NOACCESS,
3969 0x00000000);
3970 /* XXX : not implemented */
3971 spr_register(env, SPR_PMC6, "PMC6",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, &spr_write_generic,
3974 0x00000000);
3975 /* XXX : not implemented */
3976 spr_register(env, SPR_UPMC6, "UPMC6",
3977 &spr_read_ureg, SPR_NOACCESS,
3978 &spr_read_ureg, SPR_NOACCESS,
3979 0x00000000);
3980 /* SPRGs */
3981 spr_register(env, SPR_SPRG4, "SPRG4",
3982 SPR_NOACCESS, SPR_NOACCESS,
3983 &spr_read_generic, &spr_write_generic,
3984 0x00000000);
3985 spr_register(env, SPR_USPRG4, "USPRG4",
3986 &spr_read_ureg, SPR_NOACCESS,
3987 &spr_read_ureg, SPR_NOACCESS,
3988 0x00000000);
3989 spr_register(env, SPR_SPRG5, "SPRG5",
3990 SPR_NOACCESS, SPR_NOACCESS,
3991 &spr_read_generic, &spr_write_generic,
3992 0x00000000);
3993 spr_register(env, SPR_USPRG5, "USPRG5",
3994 &spr_read_ureg, SPR_NOACCESS,
3995 &spr_read_ureg, SPR_NOACCESS,
3996 0x00000000);
3997 spr_register(env, SPR_SPRG6, "SPRG6",
3998 SPR_NOACCESS, SPR_NOACCESS,
3999 &spr_read_generic, &spr_write_generic,
4000 0x00000000);
4001 spr_register(env, SPR_USPRG6, "USPRG6",
4002 &spr_read_ureg, SPR_NOACCESS,
4003 &spr_read_ureg, SPR_NOACCESS,
4004 0x00000000);
4005 spr_register(env, SPR_SPRG7, "SPRG7",
4006 SPR_NOACCESS, SPR_NOACCESS,
4007 &spr_read_generic, &spr_write_generic,
4008 0x00000000);
4009 spr_register(env, SPR_USPRG7, "USPRG7",
4010 &spr_read_ureg, SPR_NOACCESS,
4011 &spr_read_ureg, SPR_NOACCESS,
4012 0x00000000);
4013 /* Memory management */
4014 gen_low_BATs(env);
4015 gen_high_BATs(env);
4016 gen_74xx_soft_tlb(env, 128, 2);
4017 init_excp_7450(env);
4018 env->dcache_line_size = 32;
4019 env->icache_line_size = 32;
4020 /* Allocate hardware IRQ controller */
4021 ppc6xx_irq_init(env);
4022 }
4023
4024 /* PowerPC 7455 (aka G4) */
4025 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
4026 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
4027 PPC_ALTIVEC)
4028 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
4029 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
4030 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
4031 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
4032 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
4033 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4034 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4035 #define check_pow_7455 check_pow_hid0
4036
4037 __attribute__ (( unused ))
4038 static void init_proc_7455 (CPUPPCState *env)
4039 {
4040 gen_spr_ne_601(env);
4041 gen_spr_7xx(env);
4042 /* Time base */
4043 gen_tbl(env);
4044 /* 74xx specific SPR */
4045 gen_spr_74xx(env);
4046 /* Level 3 cache control */
4047 gen_l3_ctrl(env);
4048 /* LDSTCR */
4049 /* XXX : not implemented */
4050 spr_register(env, SPR_LDSTCR, "LDSTCR",
4051 SPR_NOACCESS, SPR_NOACCESS,
4052 &spr_read_generic, &spr_write_generic,
4053 0x00000000);
4054 /* ICTRL */
4055 /* XXX : not implemented */
4056 spr_register(env, SPR_ICTRL, "ICTRL",
4057 SPR_NOACCESS, SPR_NOACCESS,
4058 &spr_read_generic, &spr_write_generic,
4059 0x00000000);
4060 /* MSSSR0 */
4061 /* XXX : not implemented */
4062 spr_register(env, SPR_MSSSR0, "MSSSR0",
4063 SPR_NOACCESS, SPR_NOACCESS,
4064 &spr_read_generic, &spr_write_generic,
4065 0x00000000);
4066 /* PMC */
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_PMC5, "PMC5",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000);
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_UPMC5, "UPMC5",
4074 &spr_read_ureg, SPR_NOACCESS,
4075 &spr_read_ureg, SPR_NOACCESS,
4076 0x00000000);
4077 /* XXX : not implemented */
4078 spr_register(env, SPR_PMC6, "PMC6",
4079 SPR_NOACCESS, SPR_NOACCESS,
4080 &spr_read_generic, &spr_write_generic,
4081 0x00000000);
4082 /* XXX : not implemented */
4083 spr_register(env, SPR_UPMC6, "UPMC6",
4084 &spr_read_ureg, SPR_NOACCESS,
4085 &spr_read_ureg, SPR_NOACCESS,
4086 0x00000000);
4087 /* SPRGs */
4088 spr_register(env, SPR_SPRG4, "SPRG4",
4089 SPR_NOACCESS, SPR_NOACCESS,
4090 &spr_read_generic, &spr_write_generic,
4091 0x00000000);
4092 spr_register(env, SPR_USPRG4, "USPRG4",
4093 &spr_read_ureg, SPR_NOACCESS,
4094 &spr_read_ureg, SPR_NOACCESS,
4095 0x00000000);
4096 spr_register(env, SPR_SPRG5, "SPRG5",
4097 SPR_NOACCESS, SPR_NOACCESS,
4098 &spr_read_generic, &spr_write_generic,
4099 0x00000000);
4100 spr_register(env, SPR_USPRG5, "USPRG5",
4101 &spr_read_ureg, SPR_NOACCESS,
4102 &spr_read_ureg, SPR_NOACCESS,
4103 0x00000000);
4104 spr_register(env, SPR_SPRG6, "SPRG6",
4105 SPR_NOACCESS, SPR_NOACCESS,
4106 &spr_read_generic, &spr_write_generic,
4107 0x00000000);
4108 spr_register(env, SPR_USPRG6, "USPRG6",
4109 &spr_read_ureg, SPR_NOACCESS,
4110 &spr_read_ureg, SPR_NOACCESS,
4111 0x00000000);
4112 spr_register(env, SPR_SPRG7, "SPRG7",
4113 SPR_NOACCESS, SPR_NOACCESS,
4114 &spr_read_generic, &spr_write_generic,
4115 0x00000000);
4116 spr_register(env, SPR_USPRG7, "USPRG7",
4117 &spr_read_ureg, SPR_NOACCESS,
4118 &spr_read_ureg, SPR_NOACCESS,
4119 0x00000000);
4120 /* Memory management */
4121 gen_low_BATs(env);
4122 gen_high_BATs(env);
4123 gen_74xx_soft_tlb(env, 128, 2);
4124 init_excp_7450(env);
4125 env->dcache_line_size = 32;
4126 env->icache_line_size = 32;
4127 /* Allocate hardware IRQ controller */
4128 ppc6xx_irq_init(env);
4129 }
4130
4131 #if defined (TARGET_PPC64)
4132 #define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
4133 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
4134 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
4135 PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
4136 /* PowerPC 970 */
4137 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4138 PPC_64B | PPC_ALTIVEC | \
4139 PPC_SEGMENT_64B | PPC_SLBI)
4140 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
4141 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
4142 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
4143 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
4144 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
4145 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4146 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4147
4148 #if defined(CONFIG_USER_ONLY)
4149 #define POWERPC970_HID5_INIT 0x00000080
4150 #else
4151 #define POWERPC970_HID5_INIT 0x00000000
4152 #endif
4153
4154 static int check_pow_970 (CPUPPCState *env)
4155 {
4156 if (env->spr[SPR_HID0] & 0x00600000)
4157 return 1;
4158
4159 return 0;
4160 }
4161
4162 static void init_proc_970 (CPUPPCState *env)
4163 {
4164 gen_spr_ne_601(env);
4165 gen_spr_7xx(env);
4166 /* Time base */
4167 gen_tbl(env);
4168 /* Hardware implementation registers */
4169 /* XXX : not implemented */
4170 spr_register(env, SPR_HID0, "HID0",
4171 SPR_NOACCESS, SPR_NOACCESS,
4172 &spr_read_generic, &spr_write_clear,
4173 0x60000000);
4174 /* XXX : not implemented */
4175 spr_register(env, SPR_HID1, "HID1",
4176 SPR_NOACCESS, SPR_NOACCESS,
4177 &spr_read_generic, &spr_write_generic,
4178 0x00000000);
4179 /* XXX : not implemented */
4180 spr_register(env, SPR_750_HID2, "HID2",
4181 SPR_NOACCESS, SPR_NOACCESS,
4182 &spr_read_generic, &spr_write_generic,
4183 0x00000000);
4184 /* XXX : not implemented */
4185 spr_register(env, SPR_970_HID5, "HID5",
4186 SPR_NOACCESS, SPR_NOACCESS,
4187 &spr_read_generic, &spr_write_generic,
4188 POWERPC970_HID5_INIT);
4189 /* Memory management */
4190 /* XXX: not correct */
4191 gen_low_BATs(env);
4192 /* XXX : not implemented */
4193 spr_register(env, SPR_MMUCFG, "MMUCFG",
4194 SPR_NOACCESS, SPR_NOACCESS,
4195 &spr_read_generic, SPR_NOACCESS,
4196 0x00000000); /* TOFIX */
4197 /* XXX : not implemented */
4198 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4199 SPR_NOACCESS, SPR_NOACCESS,
4200 &spr_read_generic, &spr_write_generic,
4201 0x00000000); /* TOFIX */
4202 spr_register(env, SPR_HIOR, "SPR_HIOR",
4203 SPR_NOACCESS, SPR_NOACCESS,
4204 &spr_read_generic, &spr_write_generic,
4205 0xFFF00000); /* XXX: This is a hack */
4206 #if !defined(CONFIG_USER_ONLY)
4207 env->slb_nr = 32;
4208 #endif
4209 init_excp_970(env);
4210 env->dcache_line_size = 128;
4211 env->icache_line_size = 128;
4212 /* Allocate hardware IRQ controller */
4213 ppc970_irq_init(env);
4214 }
4215
4216 /* PowerPC 970FX (aka G5) */
4217 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4218 PPC_64B | PPC_ALTIVEC | \
4219 PPC_SEGMENT_64B | PPC_SLBI)
4220 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
4221 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
4222 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
4223 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
4224 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
4225 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4226 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4227
4228 static int check_pow_970FX (CPUPPCState *env)
4229 {
4230 if (env->spr[SPR_HID0] & 0x00600000)
4231 return 1;
4232
4233 return 0;
4234 }
4235
4236 static void init_proc_970FX (CPUPPCState *env)
4237 {
4238 gen_spr_ne_601(env);
4239 gen_spr_7xx(env);
4240 /* Time base */
4241 gen_tbl(env);
4242 /* Hardware implementation registers */
4243 /* XXX : not implemented */
4244 spr_register(env, SPR_HID0, "HID0",
4245 SPR_NOACCESS, SPR_NOACCESS,
4246 &spr_read_generic, &spr_write_clear,
4247 0x60000000);
4248 /* XXX : not implemented */
4249 spr_register(env, SPR_HID1, "HID1",
4250 SPR_NOACCESS, SPR_NOACCESS,
4251 &spr_read_generic, &spr_write_generic,
4252 0x00000000);
4253 /* XXX : not implemented */
4254 spr_register(env, SPR_750_HID2, "HID2",
4255 SPR_NOACCESS, SPR_NOACCESS,
4256 &spr_read_generic, &spr_write_generic,
4257 0x00000000);
4258 /* XXX : not implemented */
4259 spr_register(env, SPR_970_HID5, "HID5",
4260 SPR_NOACCESS, SPR_NOACCESS,
4261 &spr_read_generic, &spr_write_generic,
4262 POWERPC970_HID5_INIT);
4263 /* Memory management */
4264 /* XXX: not correct */
4265 gen_low_BATs(env);
4266 /* XXX : not implemented */
4267 spr_register(env, SPR_MMUCFG, "MMUCFG",
4268 SPR_NOACCESS, SPR_NOACCESS,
4269 &spr_read_generic, SPR_NOACCESS,
4270 0x00000000); /* TOFIX */
4271 /* XXX : not implemented */
4272 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4273 SPR_NOACCESS, SPR_NOACCESS,
4274 &spr_read_generic, &spr_write_generic,
4275 0x00000000); /* TOFIX */
4276 spr_register(env, SPR_HIOR, "SPR_HIOR",
4277 SPR_NOACCESS, SPR_NOACCESS,
4278 &spr_read_generic, &spr_write_generic,
4279 0xFFF00000); /* XXX: This is a hack */
4280 #if !defined(CONFIG_USER_ONLY)
4281 env->slb_nr = 32;
4282 #endif
4283 init_excp_970(env);
4284 env->dcache_line_size = 128;
4285 env->icache_line_size = 128;
4286 /* Allocate hardware IRQ controller */
4287 ppc970_irq_init(env);
4288 }
4289
4290 /* PowerPC 970 GX */
4291 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4292 PPC_64B | PPC_ALTIVEC | \
4293 PPC_SEGMENT_64B | PPC_SLBI)
4294 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
4295 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
4296 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
4297 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
4298 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
4299 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4300 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4301
4302 static int check_pow_970GX (CPUPPCState *env)
4303 {
4304 if (env->spr[SPR_HID0] & 0x00600000)
4305 return 1;
4306
4307 return 0;
4308 }
4309
4310 static void init_proc_970GX (CPUPPCState *env)
4311 {
4312 gen_spr_ne_601(env);
4313 gen_spr_7xx(env);
4314 /* Time base */
4315 gen_tbl(env);
4316 /* Hardware implementation registers */
4317 /* XXX : not implemented */
4318 spr_register(env, SPR_HID0, "HID0",
4319 SPR_NOACCESS, SPR_NOACCESS,
4320 &spr_read_generic, &spr_write_clear,
4321 0x60000000);
4322 /* XXX : not implemented */
4323 spr_register(env, SPR_HID1, "HID1",
4324 SPR_NOACCESS, SPR_NOACCESS,
4325 &spr_read_generic, &spr_write_generic,
4326 0x00000000);
4327 /* XXX : not implemented */
4328 spr_register(env, SPR_750_HID2, "HID2",
4329 SPR_NOACCESS, SPR_NOACCESS,
4330 &spr_read_generic, &spr_write_generic,
4331 0x00000000);
4332 /* XXX : not implemented */
4333 spr_register(env, SPR_970_HID5, "HID5",
4334 SPR_NOACCESS, SPR_NOACCESS,
4335 &spr_read_generic, &spr_write_generic,
4336 POWERPC970_HID5_INIT);
4337 /* Memory management */
4338 /* XXX: not correct */
4339 gen_low_BATs(env);
4340 /* XXX : not implemented */
4341 spr_register(env, SPR_MMUCFG, "MMUCFG",
4342 SPR_NOACCESS, SPR_NOACCESS,
4343 &spr_read_generic, SPR_NOACCESS,
4344 0x00000000); /* TOFIX */
4345 /* XXX : not implemented */
4346 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4347 SPR_NOACCESS, SPR_NOACCESS,
4348 &spr_read_generic, &spr_write_generic,
4349 0x00000000); /* TOFIX */
4350 spr_register(env, SPR_HIOR, "SPR_HIOR",
4351 SPR_NOACCESS, SPR_NOACCESS,
4352 &spr_read_generic, &spr_write_generic,
4353 0xFFF00000); /* XXX: This is a hack */
4354 #if !defined(CONFIG_USER_ONLY)
4355 env->slb_nr = 32;
4356 #endif
4357 init_excp_970(env);
4358 env->dcache_line_size = 128;
4359 env->icache_line_size = 128;
4360 /* Allocate hardware IRQ controller */
4361 ppc970_irq_init(env);
4362 }
4363
4364 /* PowerPC 970 MP */
4365 #define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
4366 PPC_64B | PPC_ALTIVEC | \
4367 PPC_SEGMENT_64B | PPC_SLBI)
4368 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
4369 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
4370 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
4371 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
4372 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
4373 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4374 POWERPC_FLAG_BE | POWERPC_FLAG_PMM)
4375
4376 static int check_pow_970MP (CPUPPCState *env)
4377 {
4378 if (env->spr[SPR_HID0] & 0x01C00000)
4379 return 1;
4380
4381 return 0;
4382 }
4383
4384 static void init_proc_970MP (CPUPPCState *env)
4385 {
4386 gen_spr_ne_601(env);
4387 gen_spr_7xx(env);
4388 /* Time base */
4389 gen_tbl(env);
4390 /* Hardware implementation registers */
4391 /* XXX : not implemented */
4392 spr_register(env, SPR_HID0, "HID0",
4393 SPR_NOACCESS, SPR_NOACCESS,
4394 &spr_read_generic, &spr_write_clear,
4395 0x60000000);
4396 /* XXX : not implemented */
4397 spr_register(env, SPR_HID1, "HID1",
4398 SPR_NOACCESS, SPR_NOACCESS,
4399 &spr_read_generic, &spr_write_generic,
4400 0x00000000);
4401 /* XXX : not implemented */
4402 spr_register(env, SPR_750_HID2, "HID2",
4403 SPR_NOACCESS, SPR_NOACCESS,
4404 &spr_read_generic, &spr_write_generic,
4405 0x00000000);
4406 /* XXX : not implemented */
4407 spr_register(env, SPR_970_HID5, "HID5",
4408 SPR_NOACCESS, SPR_NOACCESS,
4409 &spr_read_generic, &spr_write_generic,
4410 POWERPC970_HID5_INIT);
4411 /* Memory management */
4412 /* XXX: not correct */
4413 gen_low_BATs(env);
4414 /* XXX : not implemented */
4415 spr_register(env, SPR_MMUCFG, "MMUCFG",
4416 SPR_NOACCESS, SPR_NOACCESS,
4417 &spr_read_generic, SPR_NOACCESS,
4418 0x00000000); /* TOFIX */
4419 /* XXX : not implemented */
4420 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4421 SPR_NOACCESS, SPR_NOACCESS,
4422 &spr_read_generic, &spr_write_generic,
4423 0x00000000); /* TOFIX */
4424 spr_register(env, SPR_HIOR, "SPR_HIOR",
4425 SPR_NOACCESS, SPR_NOACCESS,
4426 &spr_read_generic, &spr_write_generic,
4427 0xFFF00000); /* XXX: This is a hack */
4428 #if !defined(CONFIG_USER_ONLY)
4429 env->slb_nr = 32;
4430 #endif
4431 init_excp_970(env);
4432 env->dcache_line_size = 128;
4433 env->icache_line_size = 128;
4434 /* Allocate hardware IRQ controller */
4435 ppc970_irq_init(env);
4436 }
4437
4438 /* PowerPC 620 */
4439 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
4440 PPC_64B | PPC_SLBI)
4441 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
4442 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
4443 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
4444 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
4445 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
4446 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE)
4447 #define check_pow_620 check_pow_nocheck /* Check this */
4448
4449 __attribute__ (( unused ))
4450 static void init_proc_620 (CPUPPCState *env)
4451 {
4452 gen_spr_ne_601(env);
4453 gen_spr_620(env);
4454 /* Time base */
4455 gen_tbl(env);
4456 /* Hardware implementation registers */
4457 /* XXX : not implemented */
4458 spr_register(env, SPR_HID0, "HID0",
4459 SPR_NOACCESS, SPR_NOACCESS,
4460 &spr_read_generic, &spr_write_generic,
4461 0x00000000);
4462 /* Memory management */
4463 gen_low_BATs(env);
4464 gen_high_BATs(env);
4465 init_excp_620(env);
4466 env->dcache_line_size = 64;
4467 env->icache_line_size = 64;
4468 /* Allocate hardware IRQ controller */
4469 ppc6xx_irq_init(env);
4470 }
4471 #endif /* defined (TARGET_PPC64) */
4472
4473 /* Default 32 bits PowerPC target will be 604 */
4474 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
4475 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
4476 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
4477 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
4478 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
4479 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
4480 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
4481 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
4482 #define check_pow_PPC32 check_pow_604
4483 #define init_proc_PPC32 init_proc_604
4484
4485 /* Default 64 bits PowerPC target will be 970 FX */
4486 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
4487 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
4488 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
4489 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
4490 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
4491 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
4492 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
4493 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
4494 #define check_pow_PPC64 check_pow_970FX
4495 #define init_proc_PPC64 init_proc_970FX
4496
4497 /* Default PowerPC target will be PowerPC 32 */
4498 #if defined (TARGET_PPC64) && 0 // XXX: TODO
4499 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
4500 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
4501 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
4502 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
4503 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
4504 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
4505 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
4506 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
4507 #define check_pow_DEFAULT check_pow_PPC64
4508 #define init_proc_DEFAULT init_proc_PPC64
4509 #else
4510 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
4511 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
4512 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
4513 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
4514 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
4515 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
4516 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
4517 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
4518 #define check_pow_DEFAULT check_pow_PPC32
4519 #define init_proc_DEFAULT init_proc_PPC32
4520 #endif
4521
4522 /*****************************************************************************/
4523 /* PVR definitions for most known PowerPC */
4524 enum {
4525 /* PowerPC 401 family */
4526 /* Generic PowerPC 401 */
4527 #define CPU_POWERPC_401 CPU_POWERPC_401G2
4528 /* PowerPC 401 cores */
4529 CPU_POWERPC_401A1 = 0x00210000,
4530 CPU_POWERPC_401B2 = 0x00220000,
4531 #if 0
4532 CPU_POWERPC_401B3 = xxx,
4533 #endif
4534 CPU_POWERPC_401C2 = 0x00230000,
4535 CPU_POWERPC_401D2 = 0x00240000,
4536 CPU_POWERPC_401E2 = 0x00250000,
4537 CPU_POWERPC_401F2 = 0x00260000,
4538 CPU_POWERPC_401G2 = 0x00270000,
4539 /* PowerPC 401 microcontrolers */
4540 #if 0
4541 CPU_POWERPC_401GF = xxx,
4542 #endif
4543 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
4544 /* IBM Processor for Network Resources */
4545 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
4546 #if 0
4547 CPU_POWERPC_XIPCHIP = xxx,
4548 #endif
4549 /* PowerPC 403 family */
4550 /* Generic PowerPC 403 */
4551 #define CPU_POWERPC_403 CPU_POWERPC_403GC
4552 /* PowerPC 403 microcontrollers */
4553 CPU_POWERPC_403GA = 0x00200011,
4554 CPU_POWERPC_403GB = 0x00200100,
4555 CPU_POWERPC_403GC = 0x00200200,
4556 CPU_POWERPC_403GCX = 0x00201400,
4557 #if 0
4558 CPU_POWERPC_403GP = xxx,
4559 #endif
4560 /* PowerPC 405 family */
4561 /* Generic PowerPC 405 */
4562 #define CPU_POWERPC_405 CPU_POWERPC_405D4
4563 /* PowerPC 405 cores */
4564 #if 0
4565 CPU_POWERPC_405A3 = xxx,
4566 #endif
4567 #if 0
4568 CPU_POWERPC_405A4 = xxx,
4569 #endif
4570 #if 0
4571 CPU_POWERPC_405B3 = xxx,
4572 #endif
4573 #if 0
4574 CPU_POWERPC_405B4 = xxx,
4575 #endif
4576 #if 0
4577 CPU_POWERPC_405C3 = xxx,
4578 #endif
4579 #if 0
4580 CPU_POWERPC_405C4 = xxx,
4581 #endif
4582 CPU_POWERPC_405D2 = 0x20010000,
4583 #if 0
4584 CPU_POWERPC_405D3 = xxx,
4585 #endif
4586 CPU_POWERPC_405D4 = 0x41810000,
4587 #if 0
4588 CPU_POWERPC_405D5 = xxx,
4589 #endif
4590 #if 0
4591 CPU_POWERPC_405E4 = xxx,
4592 #endif
4593 #if 0
4594 CPU_POWERPC_405F4 = xxx,
4595 #endif
4596 #if 0
4597 CPU_POWERPC_405F5 = xxx,
4598 #endif
4599 #if 0
4600 CPU_POWERPC_405F6 = xxx,
4601 #endif
4602 /* PowerPC 405 microcontrolers */
4603 /* XXX: missing 0x200108a0 */
4604 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4605 CPU_POWERPC_405CRa = 0x40110041,
4606 CPU_POWERPC_405CRb = 0x401100C5,
4607 CPU_POWERPC_405CRc = 0x40110145,
4608 CPU_POWERPC_405EP = 0x51210950,
4609 #if 0
4610 CPU_POWERPC_405EXr = xxx,
4611 #endif
4612 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4613 #if 0
4614 CPU_POWERPC_405FX = xxx,
4615 #endif
4616 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4617 CPU_POWERPC_405GPa = 0x40110000,
4618 CPU_POWERPC_405GPb = 0x40110040,
4619 CPU_POWERPC_405GPc = 0x40110082,
4620 CPU_POWERPC_405GPd = 0x401100C4,
4621 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4622 CPU_POWERPC_405GPR = 0x50910951,
4623 #if 0
4624 CPU_POWERPC_405H = xxx,
4625 #endif
4626 #if 0
4627 CPU_POWERPC_405L = xxx,
4628 #endif
4629 CPU_POWERPC_405LP = 0x41F10000,
4630 #if 0
4631 CPU_POWERPC_405PM = xxx,
4632 #endif
4633 #if 0
4634 CPU_POWERPC_405PS = xxx,
4635 #endif
4636 #if 0
4637 CPU_POWERPC_405S = xxx,
4638 #endif
4639 /* IBM network processors */
4640 CPU_POWERPC_NPE405H = 0x414100C0,
4641 CPU_POWERPC_NPE405H2 = 0x41410140,
4642 CPU_POWERPC_NPE405L = 0x416100C0,
4643 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4644 #if 0
4645 CPU_POWERPC_NPCxx1 = xxx,
4646 #endif
4647 #if 0
4648 CPU_POWERPC_NPR161 = xxx,
4649 #endif
4650 #if 0
4651 CPU_POWERPC_LC77700 = xxx,
4652 #endif
4653 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4654 #if 0
4655 CPU_POWERPC_STB01000 = xxx,
4656 #endif
4657 #if 0
4658 CPU_POWERPC_STB01010 = xxx,
4659 #endif
4660 #if 0
4661 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4662 #endif
4663 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4664 #if 0
4665 CPU_POWERPC_STB043 = xxx,
4666 #endif
4667 #if 0
4668 CPU_POWERPC_STB045 = xxx,
4669 #endif
4670 CPU_POWERPC_STB04 = 0x41810000,
4671 CPU_POWERPC_STB25 = 0x51510950,
4672 #if 0
4673 CPU_POWERPC_STB130 = xxx,
4674 #endif
4675 /* Xilinx cores */
4676 CPU_POWERPC_X2VP4 = 0x20010820,
4677 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4678 CPU_POWERPC_X2VP20 = 0x20010860,
4679 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4680 #if 0
4681 CPU_POWERPC_ZL10310 = xxx,
4682 #endif
4683 #if 0
4684 CPU_POWERPC_ZL10311 = xxx,
4685 #endif
4686 #if 0
4687 CPU_POWERPC_ZL10320 = xxx,
4688 #endif
4689 #if 0
4690 CPU_POWERPC_ZL10321 = xxx,
4691 #endif
4692 /* PowerPC 440 family */
4693 /* Generic PowerPC 440 */
4694 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
4695 /* PowerPC 440 cores */
4696 #if 0
4697 CPU_POWERPC_440A4 = xxx,
4698 #endif
4699 #if 0
4700 CPU_POWERPC_440A5 = xxx,
4701 #endif
4702 #if 0
4703 CPU_POWERPC_440B4 = xxx,
4704 #endif
4705 #if 0
4706 CPU_POWERPC_440F5 = xxx,
4707 #endif
4708 #if 0
4709 CPU_POWERPC_440G5 = xxx,
4710 #endif
4711 #if 0
4712 CPU_POWERPC_440H4 = xxx,
4713 #endif
4714 #if 0
4715 CPU_POWERPC_440H6 = xxx,
4716 #endif
4717 /* PowerPC 440 microcontrolers */
4718 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4719 CPU_POWERPC_440EPa = 0x42221850,
4720 CPU_POWERPC_440EPb = 0x422218D3,
4721 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4722 CPU_POWERPC_440GPb = 0x40120440,
4723 CPU_POWERPC_440GPc = 0x40120481,
4724 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4725 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4726 CPU_POWERPC_440GRX = 0x200008D0,
4727 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4728 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4729 CPU_POWERPC_440GXa = 0x51B21850,
4730 CPU_POWERPC_440GXb = 0x51B21851,
4731 CPU_POWERPC_440GXc = 0x51B21892,
4732 CPU_POWERPC_440GXf = 0x51B21894,
4733 #if 0
4734 CPU_POWERPC_440S = xxx,
4735 #endif
4736 CPU_POWERPC_440SP = 0x53221850,
4737 CPU_POWERPC_440SP2 = 0x53221891,
4738 CPU_POWERPC_440SPE = 0x53421890,
4739 /* PowerPC 460 family */
4740 #if 0
4741 /* Generic PowerPC 464 */
4742 #define CPU_POWERPC_464 CPU_POWERPC_464H90
4743 #endif
4744 /* PowerPC 464 microcontrolers */
4745 #if 0
4746 CPU_POWERPC_464H90 = xxx,
4747 #endif
4748 #if 0
4749 CPU_POWERPC_464H90FP = xxx,
4750 #endif
4751 /* Freescale embedded PowerPC cores */
4752 /* PowerPC MPC 5xx cores (aka RCPU) */
4753 CPU_POWERPC_5xx = 0x00020020,
4754 #define CPU_POWERPC_509 CPU_POWERPC_5xx
4755 #define CPU_POWERPC_533 CPU_POWERPC_5xx
4756 #define CPU_POWERPC_534 CPU_POWERPC_5xx
4757 #define CPU_POWERPC_555 CPU_POWERPC_5xx
4758 #define CPU_POWERPC_556 CPU_POWERPC_5xx
4759 #define CPU_POWERPC_560 CPU_POWERPC_5xx
4760 #define CPU_POWERPC_561 CPU_POWERPC_5xx
4761 #define CPU_POWERPC_562 CPU_POWERPC_5xx
4762 #define CPU_POWERPC_563 CPU_POWERPC_5xx
4763 #define CPU_POWERPC_564 CPU_POWERPC_5xx
4764 #define CPU_POWERPC_565 CPU_POWERPC_5xx
4765 #define CPU_POWERPC_566 CPU_POWERPC_5xx
4766 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4767 CPU_POWERPC_8xx = 0x00500000,
4768 #define CPU_POWERPC_821 CPU_POWERPC_8xx
4769 #define CPU_POWERPC_823 CPU_POWERPC_8xx
4770 #define CPU_POWERPC_850 CPU_POWERPC_8xx
4771 #define CPU_POWERPC_852T CPU_POWERPC_8xx
4772 #define CPU_POWERPC_855T CPU_POWERPC_8xx
4773 #define CPU_POWERPC_859 CPU_POWERPC_8xx
4774 #define CPU_POWERPC_860 CPU_POWERPC_8xx
4775 #define CPU_POWERPC_862 CPU_POWERPC_8xx
4776 #define CPU_POWERPC_866 CPU_POWERPC_8xx
4777 #define CPU_POWERPC_857 CPU_POWERPC_8xx
4778 #define CPU_POWERPC_870 CPU_POWERPC_8xx
4779 #define CPU_POWERPC_875 CPU_POWERPC_8xx
4780 #define CPU_POWERPC_880 CPU_POWERPC_8xx
4781 #define CPU_POWERPC_885 CPU_POWERPC_8xx
4782 /* G2 cores (aka PowerQUICC-II) */
4783 CPU_POWERPC_G2 = 0x00810011,
4784 CPU_POWERPC_G2H4 = 0x80811010,
4785 CPU_POWERPC_G2gp = 0x80821010,
4786 CPU_POWERPC_G2ls = 0x90810010,
4787 CPU_POWERPC_MPC603 = 0x00810100,
4788 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
4789 CPU_POWERPC_G2_HIP3 = 0x00810101,
4790 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
4791 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
4792 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
4793 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
4794 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
4795 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
4796 CPU_POWERPC_G2_HIP4 = 0x80811014,
4797 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
4798 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
4799 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
4800 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
4801 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
4802 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
4803 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
4804 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
4805 /* G2_LE core (aka PowerQUICC-II) */
4806 CPU_POWERPC_G2LE = 0x80820010,
4807 CPU_POWERPC_G2LEgp = 0x80822010,
4808 CPU_POWERPC_G2LEls = 0xA0822010,
4809 CPU_POWERPC_G2LEgp1 = 0x80822011,
4810 /* XXX: MPC 5121 ? */
4811 #define CPU_POWERPC_MPC5200 CPU_POWERPC_G2LEgp1
4812 CPU_POWERPC_G2LEgp3 = 0x80822013,
4813 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
4814 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
4815 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
4816 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
4817 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
4818 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
4819 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
4820 /* e200 family */
4821 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4822 #if 0
4823 CPU_POWERPC_e200z0 = xxx,
4824 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
4825 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
4826 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
4827 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
4828 #endif
4829 #if 0
4830 CPU_POWERPC_e200z1 = xxx,
4831 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
4832 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
4833 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
4834 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
4835 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
4836 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
4837 #endif
4838 #if 0 /* ? */
4839 CPU_POWERPC_e200z3 = 0x81120000,
4840 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
4841 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
4842 #endif
4843 CPU_POWERPC_e200z5 = 0x81000000,
4844 CPU_POWERPC_e200z6 = 0x81120000,
4845 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
4846 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
4847 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
4848 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
4849 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
4850 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
4851 /* e300 family */
4852 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4853 CPU_POWERPC_e300c1 = 0x00830000,
4854 #define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
4855 #define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
4856 #define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
4857 #define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
4858 #define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
4859 #define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
4860 #define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
4861 #define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
4862 CPU_POWERPC_e300c2 = 0x00840000,
4863 #define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
4864 #define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
4865 #define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
4866 #define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
4867 CPU_POWERPC_e300c3 = 0x00850000,
4868 #define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
4869 #define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
4870 #define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
4871 #define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
4872 #define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
4873 #define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
4874 CPU_POWERPC_e300c4 = 0x00860000,
4875 #define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
4876 #define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
4877 #define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
4878 #define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
4879 #define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
4880 #define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
4881 /* e500 family */
4882 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4883 CPU_POWERPC_e500_v10 = 0x80200010,
4884 #define CPU_POWERPC_MPC8540_v1 CPU_POWERPC_e500_v10
4885 CPU_POWERPC_e500_v20 = 0x80200020,
4886 #define CPU_POWERPC_MPC8540_v2 CPU_POWERPC_e500_v20
4887 #define CPU_POWERPC_MPC8541 CPU_POWERPC_e500_v20
4888 #define CPU_POWERPC_MPC8541E CPU_POWERPC_e500_v20
4889 #define CPU_POWERPC_MPC8555 CPU_POWERPC_e500_v20
4890 #define CPU_POWERPC_MPC8555E CPU_POWERPC_e500_v20
4891 #define CPU_POWERPC_MPC8560 CPU_POWERPC_e500_v20
4892 CPU_POWERPC_e500v2_v10 = 0x80210010,
4893 #define CPU_POWERPC_MPC8543 CPU_POWERPC_e500v2_v10
4894 #define CPU_POWERPC_MPC8543E CPU_POWERPC_e500v2_v10
4895 #define CPU_POWERPC_MPC8545 CPU_POWERPC_e500v2_v10
4896 #define CPU_POWERPC_MPC8545E CPU_POWERPC_e500v2_v10
4897 #define CPU_POWERPC_MPC8547E CPU_POWERPC_e500v2_v10
4898 #define CPU_POWERPC_MPC8548 CPU_POWERPC_e500v2_v10
4899 #define CPU_POWERPC_MPC8548E CPU_POWERPC_e500v2_v10
4900 CPU_POWERPC_e500v2_v20 = 0x80210020,
4901 CPU_POWERPC_e500v2_v21 = 0x80210021,
4902 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
4903 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
4904 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
4905 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
4906 CPU_POWERPC_e500v2_v22 = 0x80210022,
4907 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
4908 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
4909 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
4910 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
4911 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
4912 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
4913 CPU_POWERPC_e500v2_v30 = 0x80210030,
4914 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
4915 /* e600 family */
4916 CPU_POWERPC_e600 = 0x80040010,
4917 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
4918 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
4919 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
4920 /* PowerPC 6xx cores */
4921 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
4922 CPU_POWERPC_601_v0 = 0x00010001,
4923 CPU_POWERPC_601_v1 = 0x00010001,
4924 CPU_POWERPC_601_v2 = 0x00010002,
4925 CPU_POWERPC_602 = 0x00050100,
4926 CPU_POWERPC_603 = 0x00030100,
4927 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4928 CPU_POWERPC_603E_v11 = 0x00060101,
4929 CPU_POWERPC_603E_v12 = 0x00060102,
4930 CPU_POWERPC_603E_v13 = 0x00060103,
4931 CPU_POWERPC_603E_v14 = 0x00060104,
4932 CPU_POWERPC_603E_v22 = 0x00060202,
4933 CPU_POWERPC_603E_v3 = 0x00060300,
4934 CPU_POWERPC_603E_v4 = 0x00060400,
4935 CPU_POWERPC_603E_v41 = 0x00060401,
4936 CPU_POWERPC_603E7t = 0x00071201,
4937 CPU_POWERPC_603E7v = 0x00070100,
4938 CPU_POWERPC_603E7v1 = 0x00070101,
4939 CPU_POWERPC_603E7v2 = 0x00070201,
4940 CPU_POWERPC_603E7 = 0x00070200,
4941 CPU_POWERPC_603P = 0x00070000,
4942 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
4943 /* XXX: missing 0x00040303 (604) */
4944 CPU_POWERPC_604 = 0x00040103,
4945 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4946 /* XXX: missing 0x00091203 */
4947 /* XXX: missing 0x00092110 */
4948 /* XXX: missing 0x00092120 */
4949 CPU_POWERPC_604E_v10 = 0x00090100,
4950 CPU_POWERPC_604E_v22 = 0x00090202,
4951 CPU_POWERPC_604E_v24 = 0x00090204,
4952 /* XXX: missing 0x000a0100 */
4953 /* XXX: missing 0x00093102 */
4954 CPU_POWERPC_604R = 0x000a0101,
4955 #if 0
4956 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
4957 #endif
4958 /* PowerPC 740/750 cores (aka G3) */
4959 /* XXX: missing 0x00084202 */
4960 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4961 CPU_POWERPC_7x0_v20 = 0x00080200,
4962 CPU_POWERPC_7x0_v21 = 0x00080201,
4963 CPU_POWERPC_7x0_v22 = 0x00080202,
4964 CPU_POWERPC_7x0_v30 = 0x00080300,
4965 CPU_POWERPC_7x0_v31 = 0x00080301,
4966 CPU_POWERPC_740E = 0x00080100,
4967 CPU_POWERPC_7x0P = 0x10080000,
4968 /* XXX: missing 0x00087010 (CL ?) */
4969 CPU_POWERPC_750CL = 0x00087200,
4970 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4971 CPU_POWERPC_750CX_v21 = 0x00082201,
4972 CPU_POWERPC_750CX_v22 = 0x00082202,
4973 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4974 CPU_POWERPC_750CXE_v21 = 0x00082211,
4975 CPU_POWERPC_750CXE_v22 = 0x00082212,
4976 CPU_POWERPC_750CXE_v23 = 0x00082213,
4977 CPU_POWERPC_750CXE_v24 = 0x00082214,
4978 CPU_POWERPC_750CXE_v24b = 0x00083214,
4979 CPU_POWERPC_750CXE_v31 = 0x00083211,
4980 CPU_POWERPC_750CXE_v31b = 0x00083311,
4981 CPU_POWERPC_750CXR = 0x00083410,
4982 CPU_POWERPC_750E = 0x00080200,
4983 CPU_POWERPC_750FL = 0x700A0203,
4984 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4985 CPU_POWERPC_750FX_v10 = 0x70000100,
4986 CPU_POWERPC_750FX_v20 = 0x70000200,
4987 CPU_POWERPC_750FX_v21 = 0x70000201,
4988 CPU_POWERPC_750FX_v22 = 0x70000202,
4989 CPU_POWERPC_750FX_v23 = 0x70000203,
4990 CPU_POWERPC_750GL = 0x70020102,
4991 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4992 CPU_POWERPC_750GX_v10 = 0x70020100,
4993 CPU_POWERPC_750GX_v11 = 0x70020101,
4994 CPU_POWERPC_750GX_v12 = 0x70020102,
4995 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4996 CPU_POWERPC_750L_v22 = 0x00088202,
4997 CPU_POWERPC_750L_v30 = 0x00088300,
4998 CPU_POWERPC_750L_v32 = 0x00088302,
4999 /* PowerPC 745/755 cores */
5000 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
5001 CPU_POWERPC_7x5_v10 = 0x00083100,
5002 CPU_POWERPC_7x5_v11 = 0x00083101,
5003 CPU_POWERPC_7x5_v20 = 0x00083200,
5004 CPU_POWERPC_7x5_v21 = 0x00083201,
5005 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
5006 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
5007 CPU_POWERPC_7x5_v24 = 0x00083204,
5008 CPU_POWERPC_7x5_v25 = 0x00083205,
5009 CPU_POWERPC_7x5_v26 = 0x00083206,
5010 CPU_POWERPC_7x5_v27 = 0x00083207,
5011 CPU_POWERPC_7x5_v28 = 0x00083208,
5012 #if 0
5013 CPU_POWERPC_7x5P = xxx,
5014 #endif
5015 /* PowerPC 74xx cores (aka G4) */
5016 /* XXX: missing 0x000C1101 */
5017 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
5018 CPU_POWERPC_7400_v10 = 0x000C0100,
5019 CPU_POWERPC_7400_v11 = 0x000C0101,
5020 CPU_POWERPC_7400_v20 = 0x000C0200,
5021 CPU_POWERPC_7400_v22 = 0x000C0202,
5022 CPU_POWERPC_7400_v26 = 0x000C0206,
5023 CPU_POWERPC_7400_v27 = 0x000C0207,
5024 CPU_POWERPC_7400_v28 = 0x000C0208,
5025 CPU_POWERPC_7400_v29 = 0x000C0209,
5026 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
5027 CPU_POWERPC_7410_v10 = 0x800C1100,
5028 CPU_POWERPC_7410_v11 = 0x800C1101,
5029 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
5030 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
5031 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
5032 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
5033 CPU_POWERPC_7448_v10 = 0x80040100,
5034 CPU_POWERPC_7448_v11 = 0x80040101,
5035 CPU_POWERPC_7448_v20 = 0x80040200,
5036 CPU_POWERPC_7448_v21 = 0x80040201,
5037 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
5038 CPU_POWERPC_7450_v10 = 0x80000100,
5039 CPU_POWERPC_7450_v11 = 0x80000101,
5040 CPU_POWERPC_7450_v12 = 0x80000102,
5041 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
5042 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
5043 CPU_POWERPC_74x1 = 0x80000203,
5044 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
5045 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
5046 CPU_POWERPC_74x5_v10 = 0x80010100,
5047 /* XXX: missing 0x80010200 */
5048 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
5049 CPU_POWERPC_74x5_v32 = 0x80010302,
5050 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
5051 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
5052 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
5053 /* XXX: is 0x8002xxxx 7447 and 0x8003xxxx 7457 ? */
5054 /* XXX: missing 0x80030102 */
5055 /* XXX: missing 0x80020101 */
5056 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
5057 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
5058 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
5059 /* 64 bits PowerPC */
5060 #if defined(TARGET_PPC64)
5061 CPU_POWERPC_620 = 0x00140000,
5062 CPU_POWERPC_630 = 0x00400000,
5063 CPU_POWERPC_631 = 0x00410104,
5064 CPU_POWERPC_POWER4 = 0x00350000,
5065 CPU_POWERPC_POWER4P = 0x00380000,
5066 /* XXX: missing 0x003A0201 */
5067 CPU_POWERPC_POWER5 = 0x003A0203,
5068 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
5069 CPU_POWERPC_POWER5P = 0x003B0000,
5070 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
5071 CPU_POWERPC_POWER6 = 0x003E0000,
5072 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
5073 CPU_POWERPC_POWER6A = 0x0F000002,
5074 CPU_POWERPC_970 = 0x00390202,
5075 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
5076 CPU_POWERPC_970FX_v10 = 0x00391100,
5077 CPU_POWERPC_970FX_v20 = 0x003C0200,
5078 CPU_POWERPC_970FX_v21 = 0x003C0201,
5079 CPU_POWERPC_970FX_v30 = 0x003C0300,
5080 CPU_POWERPC_970FX_v31 = 0x003C0301,
5081 CPU_POWERPC_970GX = 0x00450000,
5082 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
5083 CPU_POWERPC_970MP_v10 = 0x00440100,
5084 CPU_POWERPC_970MP_v11 = 0x00440101,
5085 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
5086 CPU_POWERPC_CELL_v10 = 0x00700100,
5087 CPU_POWERPC_CELL_v20 = 0x00700400,
5088 CPU_POWERPC_CELL_v30 = 0x00700500,
5089 CPU_POWERPC_CELL_v31 = 0x00700501,
5090 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
5091 CPU_POWERPC_RS64 = 0x00330000,
5092 CPU_POWERPC_RS64II = 0x00340000,
5093 CPU_POWERPC_RS64III = 0x00360000,
5094 CPU_POWERPC_RS64IV = 0x00370000,
5095 #endif /* defined(TARGET_PPC64) */
5096 /* Original POWER */
5097 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
5098 * POWER2 (RIOS2) & RSC2 (P2SC) here
5099 */
5100 #if 0
5101 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
5102 #endif
5103 #if 0
5104 CPU_POWER2 = xxx, /* 0x40000 ? */
5105 #endif
5106 /* PA Semi core */
5107 CPU_POWERPC_PA6T = 0x00900000,
5108 };
5109
5110 /* System version register (used on MPC 8xxx) */
5111 enum {
5112 PPC_SVR_5200_v10 = 0x80110010,
5113 PPC_SVR_5200_v11 = 0x80110011,
5114 PPC_SVR_5200_v12 = 0x80110012,
5115 PPC_SVR_5200B_v20 = 0x80110020,
5116 PPC_SVR_5200B_v21 = 0x80110021,
5117 #if 0
5118 PPC_SVR_5533 = xxx,
5119 #endif
5120 #if 0
5121 PPC_SVR_5534 = xxx,
5122 #endif
5123 #if 0
5124 PPC_SVR_5553 = xxx,
5125 #endif
5126 #if 0
5127 PPC_SVR_5554 = xxx,
5128 #endif
5129 #if 0
5130 PPC_SVR_5561 = xxx,
5131 #endif
5132 #if 0
5133 PPC_SVR_5565 = xxx,
5134 #endif
5135 #if 0
5136 PPC_SVR_5566 = xxx,
5137 #endif
5138 #if 0
5139 PPC_SVR_5567 = xxx,
5140 #endif
5141 #if 0
5142 PPC_SVR_8313 = xxx,
5143 #endif
5144 #if 0
5145 PPC_SVR_8313E = xxx,
5146 #endif
5147 #if 0
5148 PPC_SVR_8314 = xxx,
5149 #endif
5150 #if 0
5151 PPC_SVR_8314E = xxx,
5152 #endif
5153 #if 0
5154 PPC_SVR_8315 = xxx,
5155 #endif
5156 #if 0
5157 PPC_SVR_8315E = xxx,
5158 #endif
5159 #if 0
5160 PPC_SVR_8321 = xxx,
5161 #endif
5162 #if 0
5163 PPC_SVR_8321E = xxx,
5164 #endif
5165 #if 0
5166 PPC_SVR_8323 = xxx,
5167 #endif
5168 #if 0
5169 PPC_SVR_8323E = xxx,
5170 #endif
5171 PPC_SVR_8343A = 0x80570030,
5172 PPC_SVR_8343EA = 0x80560030,
5173 PPC_SVR_8347AP = 0x80550030, /* PBGA package */
5174 PPC_SVR_8347AT = 0x80530030, /* TBGA package */
5175 PPC_SVR_8347EAP = 0x80540030, /* PBGA package */
5176 PPC_SVR_8347EAT = 0x80520030, /* TBGA package */
5177 PPC_SVR_8349 = 0x80510010,
5178 PPC_SVR_8349A = 0x80510030,
5179 PPC_SVR_8349E = 0x80500010,
5180 PPC_SVR_8349EA = 0x80500030,
5181 #if 0
5182 PPC_SVR_8358E = xxx,
5183 #endif
5184 #if 0
5185 PPC_SVR_8360E = xxx,
5186 #endif
5187 PPC_SVR_8377 = 0x80C70010,
5188 PPC_SVR_8377E = 0x80C60010,
5189 PPC_SVR_8378 = 0x80C50010,
5190 PPC_SVR_8378E = 0x80C40010,
5191 PPC_SVR_8379 = 0x80C30010,
5192 PPC_SVR_8379E = 0x80C00010,
5193 PPC_SVR_8533_v10 = 0x80340010,
5194 PPC_SVR_8533_v11 = 0x80340011,
5195 PPC_SVR_8533E_v10 = 0x803C0010,
5196 PPC_SVR_8533E_v11 = 0x803C0011,
5197 PPC_SVR_8540_v10 = 0x80300010,
5198 PPC_SVR_8540_v20 = 0x80300020,
5199 PPC_SVR_8540_v21 = 0x80300021,
5200 PPC_SVR_8541_v10 = 0x80720010,
5201 PPC_SVR_8541_v11 = 0x80720011,
5202 PPC_SVR_8541E_v10 = 0x807A0010,
5203 PPC_SVR_8541E_v11 = 0x807A0011,
5204 PPC_SVR_8543_v10 = 0x80320010,
5205 PPC_SVR_8543_v11 = 0x80320011,
5206 PPC_SVR_8543_v20 = 0x80320020,
5207 PPC_SVR_8543_v21 = 0x80320021,
5208 PPC_SVR_8543E_v10 = 0x803A0010,
5209 PPC_SVR_8543E_v11 = 0x803A0011,
5210 PPC_SVR_8543E_v20 = 0x803A0020,
5211 PPC_SVR_8543E_v21 = 0x803A0021,
5212 PPC_SVR_8544_v10 = 0x80340110,
5213 PPC_SVR_8544_v11 = 0x80340111,
5214 PPC_SVR_8544E_v10 = 0x803C0110,
5215 PPC_SVR_8544E_v11 = 0x803C0111,
5216 PPC_SVR_8545_v20 = 0x80310220,
5217 PPC_SVR_8545_v21 = 0x80310221,
5218 PPC_SVR_8545E_v20 = 0x80390220,
5219 PPC_SVR_8545E_v21 = 0x80390221,
5220 PPC_SVR_8547E_v20 = 0x80390120,
5221 PPC_SVR_8547E_v21 = 0x80390121,
5222 PPC_SCR_8548_v10 = 0x80310010,
5223 PPC_SCR_8548_v11 = 0x80310011,
5224 PPC_SCR_8548_v20 = 0x80310020,
5225 PPC_SCR_8548_v21 = 0x80310021,
5226 PPC_SVR_8548E_v10 = 0x80390010,
5227 PPC_SVR_8548E_v11 = 0x80390011,
5228 PPC_SVR_8548E_v20 = 0x80390020,
5229 PPC_SVR_8548E_v21 = 0x80390021,
5230 PPC_SVR_8555_v10 = 0x80710010,
5231 PPC_SVR_8555_v11 = 0x80710011,
5232 PPC_SVR_8555E_v10 = 0x80790010,
5233 PPC_SVR_8555E_v11 = 0x80790011,
5234 PPC_SVR_8560_v10 = 0x80700010,
5235 PPC_SVR_8560_v20 = 0x80700020,
5236 PPC_SVR_8560_v21 = 0x80700021,
5237 PPC_SVR_8567 = 0x80750111,
5238 PPC_SVR_8567E = 0x807D0111,
5239 PPC_SVR_8568 = 0x80750011,
5240 PPC_SVR_8568E = 0x807D0011,
5241 PPC_SVR_8572 = 0x80E00010,
5242 PPC_SVR_8572E = 0x80E80010,
5243 #if 0
5244 PPC_SVR_8610 = xxx,
5245 #endif
5246 PPC_SVR_8641 = 0x80900021,
5247 PPC_SVR_8641D = 0x80900121,
5248 };
5249
5250 /*****************************************************************************/
5251 /* PowerPC CPU definitions */
5252 #define POWERPC_DEF(_name, _pvr, _type) \
5253 { \
5254 .name = _name, \
5255 .pvr = _pvr, \
5256 .insns_flags = glue(POWERPC_INSNS_,_type), \
5257 .msr_mask = glue(POWERPC_MSRM_,_type), \
5258 .mmu_model = glue(POWERPC_MMU_,_type), \
5259 .excp_model = glue(POWERPC_EXCP_,_type), \
5260 .bus_model = glue(POWERPC_INPUT_,_type), \
5261 .bfd_mach = glue(POWERPC_BFDM_,_type), \
5262 .flags = glue(POWERPC_FLAG_,_type), \
5263 .init_proc = &glue(init_proc_,_type), \
5264 .check_pow = &glue(check_pow_,_type), \
5265 }
5266
5267 static const ppc_def_t ppc_defs[] = {
5268 /* Embedded PowerPC */
5269 /* PowerPC 401 family */
5270 /* Generic PowerPC 401 */
5271 POWERPC_DEF("401", CPU_POWERPC_401, 401),
5272 /* PowerPC 401 cores */
5273 /* PowerPC 401A1 */
5274 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
5275 /* PowerPC 401B2 */
5276 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
5277 #if defined (TODO)
5278 /* PowerPC 401B3 */
5279 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
5280 #endif
5281 /* PowerPC 401C2 */
5282 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
5283 /* PowerPC 401D2 */
5284 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
5285 /* PowerPC 401E2 */
5286 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
5287 /* PowerPC 401F2 */
5288 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
5289 /* PowerPC 401G2 */
5290 /* XXX: to be checked */
5291 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
5292 /* PowerPC 401 microcontrolers */
5293 #if defined (TODO)
5294 /* PowerPC 401GF */
5295 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
5296 #endif
5297 /* IOP480 (401 microcontroler) */
5298 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
5299 /* IBM Processor for Network Resources */
5300 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
5301 #if defined (TODO)
5302 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
5303 #endif
5304 /* PowerPC 403 family */
5305 /* Generic PowerPC 403 */
5306 POWERPC_DEF("403", CPU_POWERPC_403, 403),
5307 /* PowerPC 403 microcontrolers */
5308 /* PowerPC 403 GA */
5309 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
5310 /* PowerPC 403 GB */
5311 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
5312 /* PowerPC 403 GC */
5313 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
5314 /* PowerPC 403 GCX */
5315 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
5316 #if defined (TODO)
5317 /* PowerPC 403 GP */
5318 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
5319 #endif
5320 /* PowerPC 405 family */
5321 /* Generic PowerPC 405 */
5322 POWERPC_DEF("405", CPU_POWERPC_405, 405),
5323 /* PowerPC 405 cores */
5324 #if defined (TODO)
5325 /* PowerPC 405 A3 */
5326 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
5327 #endif
5328 #if defined (TODO)
5329 /* PowerPC 405 A4 */
5330 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
5331 #endif
5332 #if defined (TODO)
5333 /* PowerPC 405 B3 */
5334 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
5335 #endif
5336 #if defined (TODO)
5337 /* PowerPC 405 B4 */
5338 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
5339 #endif
5340 #if defined (TODO)
5341 /* PowerPC 405 C3 */
5342 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
5343 #endif
5344 #if defined (TODO)
5345 /* PowerPC 405 C4 */
5346 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
5347 #endif
5348 /* PowerPC 405 D2 */
5349 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
5350 #if defined (TODO)
5351 /* PowerPC 405 D3 */
5352 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
5353 #endif
5354 /* PowerPC 405 D4 */
5355 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
5356 #if defined (TODO)
5357 /* PowerPC 405 D5 */
5358 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
5359 #endif
5360 #if defined (TODO)
5361 /* PowerPC 405 E4 */
5362 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
5363 #endif
5364 #if defined (TODO)
5365 /* PowerPC 405 F4 */
5366 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
5367 #endif
5368 #if defined (TODO)
5369 /* PowerPC 405 F5 */
5370 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
5371 #endif
5372 #if defined (TODO)
5373 /* PowerPC 405 F6 */
5374 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
5375 #endif
5376 /* PowerPC 405 microcontrolers */
5377 /* PowerPC 405 CR */
5378 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
5379 /* PowerPC 405 CRa */
5380 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
5381 /* PowerPC 405 CRb */
5382 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
5383 /* PowerPC 405 CRc */
5384 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
5385 /* PowerPC 405 EP */
5386 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
5387 #if defined(TODO)
5388 /* PowerPC 405 EXr */
5389 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
5390 #endif
5391 /* PowerPC 405 EZ */
5392 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
5393 #if defined(TODO)
5394 /* PowerPC 405 FX */
5395 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
5396 #endif
5397 /* PowerPC 405 GP */
5398 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
5399 /* PowerPC 405 GPa */
5400 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
5401 /* PowerPC 405 GPb */
5402 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
5403 /* PowerPC 405 GPc */
5404 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
5405 /* PowerPC 405 GPd */
5406 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
5407 /* PowerPC 405 GPe */
5408 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
5409 /* PowerPC 405 GPR */
5410 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
5411 #if defined(TODO)
5412 /* PowerPC 405 H */
5413 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
5414 #endif
5415 #if defined(TODO)
5416 /* PowerPC 405 L */
5417 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
5418 #endif
5419 /* PowerPC 405 LP */
5420 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
5421 #if defined(TODO)
5422 /* PowerPC 405 PM */
5423 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
5424 #endif
5425 #if defined(TODO)
5426 /* PowerPC 405 PS */
5427 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
5428 #endif
5429 #if defined(TODO)
5430 /* PowerPC 405 S */
5431 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
5432 #endif
5433 /* Npe405 H */
5434 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
5435 /* Npe405 H2 */
5436 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
5437 /* Npe405 L */
5438 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
5439 /* Npe4GS3 */
5440 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
5441 #if defined (TODO)
5442 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
5443 #endif
5444 #if defined (TODO)
5445 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
5446 #endif
5447 #if defined (TODO)
5448 /* PowerPC LC77700 (Sanyo) */
5449 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
5450 #endif
5451 /* PowerPC 401/403/405 based set-top-box microcontrolers */
5452 #if defined (TODO)
5453 /* STB010000 */
5454 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
5455 #endif
5456 #if defined (TODO)
5457 /* STB01010 */
5458 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
5459 #endif
5460 #if defined (TODO)
5461 /* STB0210 */
5462 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
5463 #endif
5464 /* STB03xx */
5465 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
5466 #if defined (TODO)
5467 /* STB043x */
5468 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
5469 #endif
5470 #if defined (TODO)
5471 /* STB045x */
5472 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
5473 #endif
5474 /* STB04xx */
5475 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
5476 /* STB25xx */
5477 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
5478 #if defined (TODO)
5479 /* STB130 */
5480 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
5481 #endif
5482 /* Xilinx PowerPC 405 cores */
5483 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
5484 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
5485 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
5486 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
5487 #if defined (TODO)
5488 /* Zarlink ZL10310 */
5489 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
5490 #endif
5491 #if defined (TODO)
5492 /* Zarlink ZL10311 */
5493 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
5494 #endif
5495 #if defined (TODO)
5496 /* Zarlink ZL10320 */
5497 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
5498 #endif
5499 #if defined (TODO)
5500 /* Zarlink ZL10321 */
5501 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
5502 #endif
5503 /* PowerPC 440 family */
5504 /* Generic PowerPC 440 */
5505 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
5506 /* PowerPC 440 cores */
5507 #if defined (TODO)
5508 /* PowerPC 440 A4 */
5509 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
5510 #endif
5511 #if defined (TODO)
5512 /* PowerPC 440 A5 */
5513 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
5514 #endif
5515 #if defined (TODO)
5516 /* PowerPC 440 B4 */
5517 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
5518 #endif
5519 #if defined (TODO)
5520 /* PowerPC 440 G4 */
5521 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
5522 #endif
5523 #if defined (TODO)
5524 /* PowerPC 440 F5 */
5525 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
5526 #endif
5527 #if defined (TODO)
5528 /* PowerPC 440 G5 */
5529 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
5530 #endif
5531 #if defined (TODO)
5532 /* PowerPC 440H4 */
5533 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
5534 #endif
5535 #if defined (TODO)
5536 /* PowerPC 440H6 */
5537 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
5538 #endif
5539 /* PowerPC 440 microcontrolers */
5540 /* PowerPC 440 EP */
5541 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
5542 /* PowerPC 440 EPa */
5543 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
5544 /* PowerPC 440 EPb */
5545 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
5546 /* PowerPC 440 EPX */
5547 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
5548 /* PowerPC 440 GP */
5549 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
5550 /* PowerPC 440 GPb */
5551 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
5552 /* PowerPC 440 GPc */
5553 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
5554 /* PowerPC 440 GR */
5555 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
5556 /* PowerPC 440 GRa */
5557 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
5558 /* PowerPC 440 GRX */
5559 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
5560 /* PowerPC 440 GX */
5561 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
5562 /* PowerPC 440 GXa */
5563 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
5564 /* PowerPC 440 GXb */
5565 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
5566 /* PowerPC 440 GXc */
5567 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
5568 /* PowerPC 440 GXf */
5569 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
5570 #if defined(TODO)
5571 /* PowerPC 440 S */
5572 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
5573 #endif
5574 /* PowerPC 440 SP */
5575 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
5576 /* PowerPC 440 SP2 */
5577 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
5578 /* PowerPC 440 SPE */
5579 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
5580 /* PowerPC 460 family */
5581 #if defined (TODO)
5582 /* Generic PowerPC 464 */
5583 POWERPC_DEF("464", CPU_POWERPC_464, 460),
5584 #endif
5585 /* PowerPC 464 microcontrolers */
5586 #if defined (TODO)
5587 /* PowerPC 464H90 */
5588 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
5589 #endif
5590 #if defined (TODO)
5591 /* PowerPC 464H90F */
5592 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
5593 #endif
5594 /* Freescale embedded PowerPC cores */
5595 /* e200 family */
5596 #if defined (TODO)
5597 /* Generic PowerPC e200 core */
5598 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
5599 #endif
5600 #if defined (TODO)
5601 /* PowerPC e200z5 core */
5602 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
5603 #endif
5604 #if defined (TODO)
5605 /* PowerPC e200z6 core */
5606 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
5607 #endif
5608 /* e300 family */
5609 #if defined (TODO)
5610 /* Generic PowerPC e300 core */
5611 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
5612 #endif
5613 #if defined (TODO)
5614 /* PowerPC e300c1 core */
5615 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
5616 #endif
5617 #if defined (TODO)
5618 /* PowerPC e300c2 core */
5619 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
5620 #endif
5621 #if defined (TODO)
5622 /* PowerPC e300c3 core */
5623 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
5624 #endif
5625 /* e500 family */
5626 #if defined (TODO)
5627 /* PowerPC e500 core */
5628 POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
5629 #endif
5630 #if defined (TODO)
5631 /* PowerPC e500 v1.1 core */
5632 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, e500),
5633 #endif
5634 #if defined (TODO)
5635 /* PowerPC e500 v1.2 core */
5636 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, e500),
5637 #endif
5638 #if defined (TODO)
5639 /* PowerPC e500 v2.1 core */
5640 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, e500),
5641 #endif
5642 #if defined (TODO)
5643 /* PowerPC e500 v2.2 core */
5644 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, e500),
5645 #endif
5646 /* e600 family */
5647 #if defined (TODO)
5648 /* PowerPC e600 core */
5649 POWERPC_DEF("e600", CPU_POWERPC_e600, e600),
5650 #endif
5651 /* PowerPC MPC 5xx cores */
5652 #if defined (TODO)
5653 /* PowerPC MPC 5xx */
5654 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 5xx),
5655 #endif
5656 /* PowerPC MPC 8xx cores */
5657 #if defined (TODO)
5658 /* PowerPC MPC 8xx */
5659 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 8xx),
5660 #endif
5661 /* PowerPC MPC 8xxx cores */
5662 #if defined (TODO)
5663 /* PowerPC MPC 82xx HIP3 */
5664 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 82xx),
5665 #endif
5666 #if defined (TODO)
5667 /* PowerPC MPC 82xx HIP4 */
5668 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 82xx),
5669 #endif
5670 #if defined (TODO)
5671 /* PowerPC MPC 827x */
5672 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 827x),
5673 #endif
5674
5675 /* 32 bits "classic" PowerPC */
5676 /* PowerPC 6xx family */
5677 /* PowerPC 601 */
5678 POWERPC_DEF("601", CPU_POWERPC_601, 601),
5679 /* PowerPC 601v0 */
5680 POWERPC_DEF("601v0", CPU_POWERPC_601_v0, 601),
5681 /* PowerPC 601v1 */
5682 POWERPC_DEF("601v1", CPU_POWERPC_601_v1, 601),
5683 /* PowerPC 601v2 */
5684 POWERPC_DEF("601v2", CPU_POWERPC_601_v2, 601),
5685 /* PowerPC 602 */
5686 POWERPC_DEF("602", CPU_POWERPC_602, 602),
5687 /* PowerPC 603 */
5688 POWERPC_DEF("603", CPU_POWERPC_603, 603),
5689 /* Code name for PowerPC 603 */
5690 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
5691 /* PowerPC 603e */
5692 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
5693 /* Code name for PowerPC 603e */
5694 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
5695 /* PowerPC 603e v1.1 */
5696 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 603E),
5697 /* PowerPC 603e v1.2 */
5698 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 603E),
5699 /* PowerPC 603e v1.3 */
5700 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 603E),
5701 /* PowerPC 603e v1.4 */
5702 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 603E),
5703 /* PowerPC 603e v2.2 */
5704 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 603E),
5705 /* PowerPC 603e v3 */
5706 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 603E),
5707 /* PowerPC 603e v4 */
5708 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 603E),
5709 /* PowerPC 603e v4.1 */
5710 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 603E),
5711 /* PowerPC 603e */
5712 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
5713 /* PowerPC 603e7t */
5714 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
5715 /* PowerPC 603e7v */
5716 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
5717 /* Code name for PowerPC 603ev */
5718 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
5719 /* PowerPC 603e7v1 */
5720 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
5721 /* PowerPC 603e7v2 */
5722 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
5723 /* PowerPC 603p */
5724 /* to be checked */
5725 POWERPC_DEF("603p", CPU_POWERPC_603P, 603),
5726 /* PowerPC 603r */
5727 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
5728 /* Code name for PowerPC 603r */
5729 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
5730 /* PowerPC G2 core */
5731 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
5732 /* PowerPC G2 H4 */
5733 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
5734 /* PowerPC G2 GP */
5735 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
5736 /* PowerPC G2 LS */
5737 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
5738 /* PowerPC G2LE */
5739 /* Same as G2, with little-endian mode support */
5740 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
5741 /* PowerPC G2LE GP */
5742 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
5743 /* PowerPC G2LE LS */
5744 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
5745 /* PowerPC 604 */
5746 POWERPC_DEF("604", CPU_POWERPC_604, 604),
5747 /* PowerPC 604e */
5748 /* XXX: code names "Sirocco" "Mach 5" */
5749 POWERPC_DEF("604e", CPU_POWERPC_604E, 604),
5750 /* PowerPC 604e v1.0 */
5751 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 604),
5752 /* PowerPC 604e v2.2 */
5753 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 604),
5754 /* PowerPC 604e v2.4 */
5755 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 604),
5756 /* PowerPC 604r */
5757 POWERPC_DEF("604r", CPU_POWERPC_604R, 604),
5758 #if defined(TODO)
5759 /* PowerPC 604ev */
5760 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604),
5761 #endif
5762 /* PowerPC 7xx family */
5763 /* Generic PowerPC 740 (G3) */
5764 POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
5765 /* Generic PowerPC 750 (G3) */
5766 POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
5767 /* Code name for generic PowerPC 740/750 (G3) */
5768 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
5769 /* XXX: 750 codename "Typhoon" */
5770 /* PowerPC 740/750 is also known as G3 */
5771 POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
5772 /* PowerPC 740 v2.0 (G3) */
5773 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 7x0),
5774 /* PowerPC 750 v2.0 (G3) */
5775 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 7x0),
5776 /* PowerPC 740 v2.1 (G3) */
5777 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 7x0),
5778 /* PowerPC 750 v2.1 (G3) */
5779 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 7x0),
5780 /* PowerPC 740 v2.2 (G3) */
5781 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 7x0),
5782 /* PowerPC 750 v2.2 (G3) */
5783 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 7x0),
5784 /* PowerPC 740 v3.0 (G3) */
5785 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 7x0),
5786 /* PowerPC 750 v3.0 (G3) */
5787 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 7x0),
5788 /* PowerPC 740 v3.1 (G3) */
5789 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 7x0),
5790 /* PowerPC 750 v3.1 (G3) */
5791 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 7x0),
5792 /* PowerPC 740E (G3) */
5793 POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
5794 /* PowerPC 740P (G3) */
5795 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
5796 /* PowerPC 750P (G3) */
5797 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
5798 /* Code name for PowerPC 740P/750P (G3) */
5799 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
5800 /* PowerPC 750CL (G3 embedded) */
5801 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
5802 /* PowerPC 750CX (G3 embedded) */
5803 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
5804 /* PowerPC 750CX v2.1 (G3 embedded) */
5805 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 7x0),
5806 /* PowerPC 750CX v2.2 (G3 embedded) */
5807 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 7x0),
5808 /* PowerPC 750CXe (G3 embedded) */
5809 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
5810 /* PowerPC 750CXe v2.1 (G3 embedded) */
5811 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 7x0),
5812 /* PowerPC 750CXe v2.2 (G3 embedded) */
5813 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 7x0),
5814 /* PowerPC 750CXe v2.3 (G3 embedded) */
5815 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 7x0),
5816 /* PowerPC 750CXe v2.4 (G3 embedded) */
5817 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 7x0),
5818 /* PowerPC 750CXe v2.4b (G3 embedded) */
5819 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 7x0),
5820 /* PowerPC 750CXe v3.1 (G3 embedded) */
5821 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 7x0),
5822 /* PowerPC 750CXe v3.1b (G3 embedded) */
5823 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
5824 /* PowerPC 750CXr (G3 embedded) */
5825 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
5826 /* PowerPC 750E (G3) */
5827 POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
5828 /* PowerPC 750FL (G3 embedded) */
5829 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
5830 /* PowerPC 750FX (G3 embedded) */
5831 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
5832 /* PowerPC 750FX v1.0 (G3 embedded) */
5833 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 750fx),
5834 /* PowerPC 750FX v2.0 (G3 embedded) */
5835 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 750fx),
5836 /* PowerPC 750FX v2.1 (G3 embedded) */
5837 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 750fx),
5838 /* PowerPC 750FX v2.2 (G3 embedded) */
5839 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 750fx),
5840 /* PowerPC 750FX v2.3 (G3 embedded) */
5841 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 750fx),
5842 /* PowerPC 750GL (G3 embedded) */
5843 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
5844 /* PowerPC 750GX (G3 embedded) */
5845 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
5846 /* PowerPC 750GX v1.0 (G3 embedded) */
5847 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 750fx),
5848 /* PowerPC 750GX v1.1 (G3 embedded) */
5849 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 750fx),
5850 /* PowerPC 750GX v1.2 (G3 embedded) */
5851 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 750fx),
5852 /* PowerPC 750L (G3 embedded) */
5853 POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
5854 /* Code name for PowerPC 750L (G3 embedded) */
5855 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
5856 /* PowerPC 750L v2.2 (G3 embedded) */
5857 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 7x0),
5858 /* PowerPC 750L v3.0 (G3 embedded) */
5859 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 7x0),
5860 /* PowerPC 750L v3.2 (G3 embedded) */
5861 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 7x0),
5862 /* Generic PowerPC 745 */
5863 POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
5864 /* Generic PowerPC 755 */
5865 POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
5866 /* Code name for PowerPC 745/755 */
5867 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
5868 /* PowerPC 745 v1.0 */
5869 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 7x5),
5870 /* PowerPC 755 v1.0 */
5871 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 7x5),
5872 /* PowerPC 745 v1.1 */
5873 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 7x5),
5874 /* PowerPC 755 v1.1 */
5875 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 7x5),
5876 /* PowerPC 745 v2.0 */
5877 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 7x5),
5878 /* PowerPC 755 v2.0 */
5879 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 7x5),
5880 /* PowerPC 745 v2.1 */
5881 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 7x5),
5882 /* PowerPC 755 v2.1 */
5883 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 7x5),
5884 /* PowerPC 745 v2.2 */
5885 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 7x5),
5886 /* PowerPC 755 v2.2 */
5887 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 7x5),
5888 /* PowerPC 745 v2.3 */
5889 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 7x5),
5890 /* PowerPC 755 v2.3 */
5891 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 7x5),
5892 /* PowerPC 745 v2.4 */
5893 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 7x5),
5894 /* PowerPC 755 v2.4 */
5895 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 7x5),
5896 /* PowerPC 745 v2.5 */
5897 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 7x5),
5898 /* PowerPC 755 v2.5 */
5899 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 7x5),
5900 /* PowerPC 745 v2.6 */
5901 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 7x5),
5902 /* PowerPC 755 v2.6 */
5903 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 7x5),
5904 /* PowerPC 745 v2.7 */
5905 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 7x5),
5906 /* PowerPC 755 v2.7 */
5907 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 7x5),
5908 /* PowerPC 745 v2.8 */
5909 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 7x5),
5910 /* PowerPC 755 v2.8 */
5911 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 7x5),
5912 #if defined (TODO)
5913 /* PowerPC 745P (G3) */
5914 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
5915 /* PowerPC 755P (G3) */
5916 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
5917 #endif
5918 /* PowerPC 74xx family */
5919 /* PowerPC 7400 (G4) */
5920 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
5921 /* Code name for PowerPC 7400 */
5922 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
5923 /* PowerPC 74xx is also well known as G4 */
5924 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
5925 /* PowerPC 7400 v1.0 (G4) */
5926 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 7400),
5927 /* PowerPC 7400 v1.1 (G4) */
5928 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 7400),
5929 /* PowerPC 7400 v2.0 (G4) */
5930 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 7400),
5931 /* PowerPC 7400 v2.2 (G4) */
5932 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 7400),
5933 /* PowerPC 7400 v2.6 (G4) */
5934 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 7400),
5935 /* PowerPC 7400 v2.7 (G4) */
5936 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 7400),
5937 /* PowerPC 7400 v2.8 (G4) */
5938 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 7400),
5939 /* PowerPC 7400 v2.9 (G4) */
5940 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 7400),
5941 /* PowerPC 7410 (G4) */
5942 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
5943 /* Code name for PowerPC 7410 */
5944 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
5945 /* PowerPC 7410 v1.0 (G4) */
5946 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 7410),
5947 /* PowerPC 7410 v1.1 (G4) */
5948 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 7410),
5949 /* PowerPC 7410 v1.2 (G4) */
5950 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 7410),
5951 /* PowerPC 7410 v1.3 (G4) */
5952 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 7410),
5953 /* PowerPC 7410 v1.4 (G4) */
5954 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 7410),
5955 /* PowerPC 7448 (G4) */
5956 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
5957 /* PowerPC 7448 v1.0 (G4) */
5958 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 7400),
5959 /* PowerPC 7448 v1.1 (G4) */
5960 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 7400),
5961 /* PowerPC 7448 v2.0 (G4) */
5962 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 7400),
5963 /* PowerPC 7448 v2.1 (G4) */
5964 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 7400),
5965 /* PowerPC 7450 (G4) */
5966 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
5967 /* Code name for PowerPC 7450 */
5968 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
5969 /* PowerPC 7450 v1.0 (G4) */
5970 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 7450),
5971 /* PowerPC 7450 v1.1 (G4) */
5972 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 7450),
5973 /* PowerPC 7450 v1.2 (G4) */
5974 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 7450),
5975 /* PowerPC 7450 v2.0 (G4) */
5976 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 7450),
5977 /* PowerPC 7450 v2.1 (G4) */
5978 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 7450),
5979 /* PowerPC 7441 (G4) */
5980 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
5981 /* PowerPC 7451 (G4) */
5982 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
5983 /* PowerPC 7441g (G4) */
5984 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
5985 /* PowerPC 7451g (G4) */
5986 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
5987 /* PowerPC 7445 (G4) */
5988 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
5989 /* PowerPC 7455 (G4) */
5990 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
5991 /* Code name for PowerPC 7445/7455 */
5992 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
5993 /* PowerPC 7445 v1.0 (G4) */
5994 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 7445),
5995 /* PowerPC 7455 v1.0 (G4) */
5996 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 7455),
5997 /* PowerPC 7445 v2.1 (G4) */
5998 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 7445),
5999 /* PowerPC 7455 v2.1 (G4) */
6000 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 7455),
6001 /* PowerPC 7445 v3.2 (G4) */
6002 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 7445),
6003 /* PowerPC 7455 v3.2 (G4) */
6004 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 7455),
6005 /* PowerPC 7445 v3.3 (G4) */
6006 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 7445),
6007 /* PowerPC 7455 v3.3 (G4) */
6008 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 7455),
6009 /* PowerPC 7445 v3.4 (G4) */
6010 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 7445),
6011 /* PowerPC 7455 v3.4 (G4) */
6012 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 7455),
6013 /* PowerPC 7447 (G4) */
6014 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
6015 /* PowerPC 7457 (G4) */
6016 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
6017 /* Code name for PowerPC 7447/7457 */
6018 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
6019 /* PowerPC 7447 v1.0 (G4) */
6020 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 7445),
6021 /* PowerPC 7457 v1.0 (G4) */
6022 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 7455),
6023 /* Code name for PowerPC 7447A/7457A */
6024 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 7455),
6025 /* PowerPC 7447 v1.1 (G4) */
6026 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 7445),
6027 /* PowerPC 7457 v1.1 (G4) */
6028 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 7455),
6029 /* PowerPC 7447 v1.2 (G4) */
6030 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 7445),
6031 /* PowerPC 7457 v1.2 (G4) */
6032 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 7455),
6033 /* 64 bits PowerPC */
6034 #if defined (TARGET_PPC64)
6035 /* PowerPC 620 */
6036 /* XXX: code name "Trident" */
6037 POWERPC_DEF("620", CPU_POWERPC_620, 620),
6038 #if defined (TODO)
6039 /* PowerPC 630 (POWER3) */
6040 /* XXX: code names: "Boxer" "Dino" */
6041 POWERPC_DEF("630", CPU_POWERPC_630, 630),
6042 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
6043 #endif
6044 #if defined (TODO)
6045 /* PowerPC 631 (Power 3+) */
6046 POWERPC_DEF("631", CPU_POWERPC_631, 631),
6047 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
6048 #endif
6049 #if defined (TODO)
6050 /* POWER4 */
6051 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
6052 #endif
6053 #if defined (TODO)
6054 /* POWER4p */
6055 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
6056 #endif
6057 #if defined (TODO)
6058 /* POWER5 */
6059 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
6060 /* POWER5GR */
6061 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
6062 #endif
6063 #if defined (TODO)
6064 /* POWER5+ */
6065 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
6066 /* POWER5GS */
6067 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
6068 #endif
6069 #if defined (TODO)
6070 /* POWER6 */
6071 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
6072 /* POWER6 running in POWER5 mode */
6073 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
6074 /* POWER6A */
6075 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
6076 #endif
6077 /* PowerPC 970 */
6078 POWERPC_DEF("970", CPU_POWERPC_970, 970),
6079 /* PowerPC 970FX (G5) */
6080 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
6081 /* PowerPC 970FX v1.0 (G5) */
6082 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 970FX),
6083 /* PowerPC 970FX v2.0 (G5) */
6084 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 970FX),
6085 /* PowerPC 970FX v2.1 (G5) */
6086 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 970FX),
6087 /* PowerPC 970FX v3.0 (G5) */
6088 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 970FX),
6089 /* PowerPC 970FX v3.1 (G5) */
6090 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 970FX),
6091 /* PowerPC 970GX (G5) */
6092 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
6093 /* PowerPC 970MP */
6094 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
6095 /* PowerPC 970MP v1.0 */
6096 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 970MP),
6097 /* PowerPC 970MP v1.1 */
6098 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 970MP),
6099 #if defined (TODO)
6100 /* PowerPC Cell */
6101 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
6102 #endif
6103 #if defined (TODO)
6104 /* PowerPC Cell v1.0 */
6105 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 970),
6106 #endif
6107 #if defined (TODO)
6108 /* PowerPC Cell v2.0 */
6109 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 970),
6110 #endif
6111 #if defined (TODO)
6112 /* PowerPC Cell v3.0 */
6113 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 970),
6114 #endif
6115 #if defined (TODO)
6116 /* PowerPC Cell v3.1 */
6117 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 970),
6118 #endif
6119 #if defined (TODO)
6120 /* PowerPC Cell v3.2 */
6121 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 970),
6122 #endif
6123 #if defined (TODO)
6124 /* RS64 (Apache/A35) */
6125 /* This one seems to support the whole POWER2 instruction set
6126 * and the PowerPC 64 one.
6127 */
6128 /* What about A10 & A30 ? */
6129 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
6130 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
6131 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
6132 #endif
6133 #if defined (TODO)
6134 /* RS64-II (NorthStar/A50) */
6135 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
6136 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
6137 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
6138 #endif
6139 #if defined (TODO)
6140 /* RS64-III (Pulsar) */
6141 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
6142 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
6143 #endif
6144 #if defined (TODO)
6145 /* RS64-IV (IceStar/IStar/SStar) */
6146 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
6147 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
6148 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
6149 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
6150 #endif
6151 #endif /* defined (TARGET_PPC64) */
6152 /* POWER */
6153 #if defined (TODO)
6154 /* Original POWER */
6155 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
6156 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
6157 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
6158 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
6159 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
6160 #endif
6161 #if defined (TODO)
6162 /* POWER2 */
6163 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
6164 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
6165 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
6166 #endif
6167 /* PA semi cores */
6168 #if defined (TODO)
6169 /* PA PA6T */
6170 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
6171 #endif
6172 /* Generic PowerPCs */
6173 #if defined (TARGET_PPC64)
6174 #if defined (TODO)
6175 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
6176 #endif
6177 #endif
6178 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
6179 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
6180 /* Fallback */
6181 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
6182 };
6183
6184 /*****************************************************************************/
6185 /* Generic CPU instanciation routine */
6186 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
6187 {
6188 #if !defined(CONFIG_USER_ONLY)
6189 int i;
6190
6191 env->irq_inputs = NULL;
6192 /* Set all exception vectors to an invalid address */
6193 for (i = 0; i < POWERPC_EXCP_NB; i++)
6194 env->excp_vectors[i] = (target_ulong)(-1ULL);
6195 env->excp_prefix = 0x00000000;
6196 env->ivor_mask = 0x00000000;
6197 env->ivpr_mask = 0x00000000;
6198 /* Default MMU definitions */
6199 env->nb_BATs = 0;
6200 env->nb_tlb = 0;
6201 env->nb_ways = 0;
6202 #endif
6203 /* Register SPR common to all PowerPC implementations */
6204 gen_spr_generic(env);
6205 spr_register(env, SPR_PVR, "PVR",
6206 SPR_NOACCESS, SPR_NOACCESS,
6207 &spr_read_generic, SPR_NOACCESS,
6208 def->pvr);
6209 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6210 (*def->init_proc)(env);
6211 /* MSR bits & flags consistency checks */
6212 if (env->msr_mask & (1 << 25)) {
6213 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6214 case POWERPC_FLAG_SPE:
6215 case POWERPC_FLAG_VRE:
6216 break;
6217 default:
6218 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6219 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6220 exit(1);
6221 }
6222 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6223 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6224 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6225 exit(1);
6226 }
6227 if (env->msr_mask & (1 << 17)) {
6228 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6229 case POWERPC_FLAG_TGPR:
6230 case POWERPC_FLAG_CE:
6231 break;
6232 default:
6233 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6234 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6235 exit(1);
6236 }
6237 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6238 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6239 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6240 exit(1);
6241 }
6242 if (env->msr_mask & (1 << 10)) {
6243 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6244 POWERPC_FLAG_UBLE)) {
6245 case POWERPC_FLAG_SE:
6246 case POWERPC_FLAG_DWE:
6247 case POWERPC_FLAG_UBLE:
6248 break;
6249 default:
6250 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6251 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6252 "POWERPC_FLAG_UBLE\n");
6253 exit(1);
6254 }
6255 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6256 POWERPC_FLAG_UBLE)) {
6257 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6258 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6259 "POWERPC_FLAG_UBLE\n");
6260 exit(1);
6261 }
6262 if (env->msr_mask & (1 << 9)) {
6263 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6264 case POWERPC_FLAG_BE:
6265 case POWERPC_FLAG_DE:
6266 break;
6267 default:
6268 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6269 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6270 exit(1);
6271 }
6272 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6273 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6274 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6275 exit(1);
6276 }
6277 if (env->msr_mask & (1 << 2)) {
6278 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6279 case POWERPC_FLAG_PX:
6280 case POWERPC_FLAG_PMM:
6281 break;
6282 default:
6283 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6284 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6285 exit(1);
6286 }
6287 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6288 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6289 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6290 exit(1);
6291 }
6292 /* Allocate TLBs buffer when needed */
6293 #if !defined(CONFIG_USER_ONLY)
6294 if (env->nb_tlb != 0) {
6295 int nb_tlb = env->nb_tlb;
6296 if (env->id_tlbs != 0)
6297 nb_tlb *= 2;
6298 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
6299 /* Pre-compute some useful values */
6300 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6301 }
6302 if (env->irq_inputs == NULL) {
6303 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
6304 " Attempt Qemu to crash very soon !\n");
6305 }
6306 #endif
6307 if (env->check_pow == NULL) {
6308 fprintf(stderr, "WARNING: no power management check handler "
6309 "registered.\n"
6310 " Attempt Qemu to crash very soon !\n");
6311 }
6312 }
6313
6314 #if defined(PPC_DUMP_CPU)
6315 static void dump_ppc_sprs (CPUPPCState *env)
6316 {
6317 ppc_spr_t *spr;
6318 #if !defined(CONFIG_USER_ONLY)
6319 uint32_t sr, sw;
6320 #endif
6321 uint32_t ur, uw;
6322 int i, j, n;
6323
6324 printf("Special purpose registers:\n");
6325 for (i = 0; i < 32; i++) {
6326 for (j = 0; j < 32; j++) {
6327 n = (i << 5) | j;
6328 spr = &env->spr_cb[n];
6329 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
6330 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
6331 #if !defined(CONFIG_USER_ONLY)
6332 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
6333 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
6334 if (sw || sr || uw || ur) {
6335 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
6336 (i << 5) | j, (i << 5) | j, spr->name,
6337 sw ? 'w' : '-', sr ? 'r' : '-',
6338 uw ? 'w' : '-', ur ? 'r' : '-');
6339 }
6340 #else
6341 if (uw || ur) {
6342 printf("SPR: %4d (%03x) %-8s u%c%c\n",
6343 (i << 5) | j, (i << 5) | j, spr->name,
6344 uw ? 'w' : '-', ur ? 'r' : '-');
6345 }
6346 #endif
6347 }
6348 }
6349 fflush(stdout);
6350 fflush(stderr);
6351 }
6352 #endif
6353
6354 /*****************************************************************************/
6355 #include <stdlib.h>
6356 #include <string.h>
6357
6358 int fflush (FILE *stream);
6359
6360 /* Opcode types */
6361 enum {
6362 PPC_DIRECT = 0, /* Opcode routine */
6363 PPC_INDIRECT = 1, /* Indirect opcode table */
6364 };
6365
6366 static inline int is_indirect_opcode (void *handler)
6367 {
6368 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
6369 }
6370
6371 static inline opc_handler_t **ind_table(void *handler)
6372 {
6373 return (opc_handler_t **)((unsigned long)handler & ~3);
6374 }
6375
6376 /* Instruction table creation */
6377 /* Opcodes tables creation */
6378 static void fill_new_table (opc_handler_t **table, int len)
6379 {
6380 int i;
6381
6382 for (i = 0; i < len; i++)
6383 table[i] = &invalid_handler;
6384 }
6385
6386 static int create_new_table (opc_handler_t **table, unsigned char idx)
6387 {
6388 opc_handler_t **tmp;
6389
6390 tmp = malloc(0x20 * sizeof(opc_handler_t));
6391 if (tmp == NULL)
6392 return -1;
6393 fill_new_table(tmp, 0x20);
6394 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
6395
6396 return 0;
6397 }
6398
6399 static int insert_in_table (opc_handler_t **table, unsigned char idx,
6400 opc_handler_t *handler)
6401 {
6402 if (table[idx] != &invalid_handler)
6403 return -1;
6404 table[idx] = handler;
6405
6406 return 0;
6407 }
6408
6409 static int register_direct_insn (opc_handler_t **ppc_opcodes,
6410 unsigned char idx, opc_handler_t *handler)
6411 {
6412 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
6413 printf("*** ERROR: opcode %02x already assigned in main "
6414 "opcode table\n", idx);
6415 return -1;
6416 }
6417
6418 return 0;
6419 }
6420
6421 static int register_ind_in_table (opc_handler_t **table,
6422 unsigned char idx1, unsigned char idx2,
6423 opc_handler_t *handler)
6424 {
6425 if (table[idx1] == &invalid_handler) {
6426 if (create_new_table(table, idx1) < 0) {
6427 printf("*** ERROR: unable to create indirect table "
6428 "idx=%02x\n", idx1);
6429 return -1;
6430 }
6431 } else {
6432 if (!is_indirect_opcode(table[idx1])) {
6433 printf("*** ERROR: idx %02x already assigned to a direct "
6434 "opcode\n", idx1);
6435 return -1;
6436 }
6437 }
6438 if (handler != NULL &&
6439 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
6440 printf("*** ERROR: opcode %02x already assigned in "
6441 "opcode table %02x\n", idx2, idx1);
6442 return -1;
6443 }
6444
6445 return 0;
6446 }
6447
6448 static int register_ind_insn (opc_handler_t **ppc_opcodes,
6449 unsigned char idx1, unsigned char idx2,
6450 opc_handler_t *handler)
6451 {
6452 int ret;
6453
6454 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
6455
6456 return ret;
6457 }
6458
6459 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
6460 unsigned char idx1, unsigned char idx2,
6461 unsigned char idx3, opc_handler_t *handler)
6462 {
6463 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
6464 printf("*** ERROR: unable to join indirect table idx "
6465 "[%02x-%02x]\n", idx1, idx2);
6466 return -1;
6467 }
6468 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
6469 handler) < 0) {
6470 printf("*** ERROR: unable to insert opcode "
6471 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
6472 return -1;
6473 }
6474
6475 return 0;
6476 }
6477
6478 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
6479 {
6480 if (insn->opc2 != 0xFF) {
6481 if (insn->opc3 != 0xFF) {
6482 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
6483 insn->opc3, &insn->handler) < 0)
6484 return -1;
6485 } else {
6486 if (register_ind_insn(ppc_opcodes, insn->opc1,
6487 insn->opc2, &insn->handler) < 0)
6488 return -1;
6489 }
6490 } else {
6491 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
6492 return -1;
6493 }
6494
6495 return 0;
6496 }
6497
6498 static int test_opcode_table (opc_handler_t **table, int len)
6499 {
6500 int i, count, tmp;
6501
6502 for (i = 0, count = 0; i < len; i++) {
6503 /* Consistency fixup */
6504 if (table[i] == NULL)
6505 table[i] = &invalid_handler;
6506 if (table[i] != &invalid_handler) {
6507 if (is_indirect_opcode(table[i])) {
6508 tmp = test_opcode_table(ind_table(table[i]), 0x20);
6509 if (tmp == 0) {
6510 free(table[i]);
6511 table[i] = &invalid_handler;
6512 } else {
6513 count++;
6514 }
6515 } else {
6516 count++;
6517 }
6518 }
6519 }
6520
6521 return count;
6522 }
6523
6524 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
6525 {
6526 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
6527 printf("*** WARNING: no opcode defined !\n");
6528 }
6529
6530 /*****************************************************************************/
6531 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
6532 {
6533 opcode_t *opc, *start, *end;
6534
6535 fill_new_table(env->opcodes, 0x40);
6536 if (&opc_start < &opc_end) {
6537 start = &opc_start;
6538 end = &opc_end;
6539 } else {
6540 start = &opc_end;
6541 end = &opc_start;
6542 }
6543 for (opc = start + 1; opc != end; opc++) {
6544 if ((opc->handler.type & def->insns_flags) != 0) {
6545 if (register_insn(env->opcodes, opc) < 0) {
6546 printf("*** ERROR initializing PowerPC instruction "
6547 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
6548 opc->opc3);
6549 return -1;
6550 }
6551 }
6552 }
6553 fix_opcode_tables(env->opcodes);
6554 fflush(stdout);
6555 fflush(stderr);
6556
6557 return 0;
6558 }
6559
6560 #if defined(PPC_DUMP_CPU)
6561 static void dump_ppc_insns (CPUPPCState *env)
6562 {
6563 opc_handler_t **table, *handler;
6564 uint8_t opc1, opc2, opc3;
6565
6566 printf("Instructions set:\n");
6567 /* opc1 is 6 bits long */
6568 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
6569 table = env->opcodes;
6570 handler = table[opc1];
6571 if (is_indirect_opcode(handler)) {
6572 /* opc2 is 5 bits long */
6573 for (opc2 = 0; opc2 < 0x20; opc2++) {
6574 table = env->opcodes;
6575 handler = env->opcodes[opc1];
6576 table = ind_table(handler);
6577 handler = table[opc2];
6578 if (is_indirect_opcode(handler)) {
6579 table = ind_table(handler);
6580 /* opc3 is 5 bits long */
6581 for (opc3 = 0; opc3 < 0x20; opc3++) {
6582 handler = table[opc3];
6583 if (handler->handler != &gen_invalid) {
6584 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
6585 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
6586 handler->oname);
6587 }
6588 }
6589 } else {
6590 if (handler->handler != &gen_invalid) {
6591 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
6592 opc1, opc2, opc1, opc2, handler->oname);
6593 }
6594 }
6595 }
6596 } else {
6597 if (handler->handler != &gen_invalid) {
6598 printf("INSN: %02x -- -- (%02d ----) : %s\n",
6599 opc1, opc1, handler->oname);
6600 }
6601 }
6602 }
6603 }
6604 #endif
6605
6606 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
6607 {
6608 env->msr_mask = def->msr_mask;
6609 env->mmu_model = def->mmu_model;
6610 env->excp_model = def->excp_model;
6611 env->bus_model = def->bus_model;
6612 env->flags = def->flags;
6613 env->bfd_mach = def->bfd_mach;
6614 env->check_pow = def->check_pow;
6615 if (create_ppc_opcodes(env, def) < 0)
6616 return -1;
6617 init_ppc_proc(env, def);
6618 #if defined(PPC_DUMP_CPU)
6619 {
6620 const unsigned char *mmu_model, *excp_model, *bus_model;
6621 switch (env->mmu_model) {
6622 case POWERPC_MMU_32B:
6623 mmu_model = "PowerPC 32";
6624 break;
6625 case POWERPC_MMU_SOFT_6xx:
6626 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
6627 break;
6628 case POWERPC_MMU_SOFT_74xx:
6629 mmu_model = "PowerPC 74xx with software driven TLBs";
6630 break;
6631 case POWERPC_MMU_SOFT_4xx:
6632 mmu_model = "PowerPC 4xx with software driven TLBs";
6633 break;
6634 case POWERPC_MMU_SOFT_4xx_Z:
6635 mmu_model = "PowerPC 4xx with software driven TLBs "
6636 "and zones protections";
6637 break;
6638 case POWERPC_MMU_REAL_4xx:
6639 mmu_model = "PowerPC 4xx real mode only";
6640 break;
6641 case POWERPC_MMU_BOOKE:
6642 mmu_model = "PowerPC BookE";
6643 break;
6644 case POWERPC_MMU_BOOKE_FSL:
6645 mmu_model = "PowerPC BookE FSL";
6646 break;
6647 #if defined (TARGET_PPC64)
6648 case POWERPC_MMU_64B:
6649 mmu_model = "PowerPC 64";
6650 break;
6651 #endif
6652 default:
6653 mmu_model = "Unknown or invalid";
6654 break;
6655 }
6656 switch (env->excp_model) {
6657 case POWERPC_EXCP_STD:
6658 excp_model = "PowerPC";
6659 break;
6660 case POWERPC_EXCP_40x:
6661 excp_model = "PowerPC 40x";
6662 break;
6663 case POWERPC_EXCP_601:
6664 excp_model = "PowerPC 601";
6665 break;
6666 case POWERPC_EXCP_602:
6667 excp_model = "PowerPC 602";
6668 break;
6669 case POWERPC_EXCP_603:
6670 excp_model = "PowerPC 603";
6671 break;
6672 case POWERPC_EXCP_603E:
6673 excp_model = "PowerPC 603e";
6674 break;
6675 case POWERPC_EXCP_604:
6676 excp_model = "PowerPC 604";
6677 break;
6678 case POWERPC_EXCP_7x0:
6679 excp_model = "PowerPC 740/750";
6680 break;
6681 case POWERPC_EXCP_7x5:
6682 excp_model = "PowerPC 745/755";
6683 break;
6684 case POWERPC_EXCP_74xx:
6685 excp_model = "PowerPC 74xx";
6686 break;
6687 case POWERPC_EXCP_BOOKE:
6688 excp_model = "PowerPC BookE";
6689 break;
6690 #if defined (TARGET_PPC64)
6691 case POWERPC_EXCP_970:
6692 excp_model = "PowerPC 970";
6693 break;
6694 #endif
6695 default:
6696 excp_model = "Unknown or invalid";
6697 break;
6698 }
6699 switch (env->bus_model) {
6700 case PPC_FLAGS_INPUT_6xx:
6701 bus_model = "PowerPC 6xx";
6702 break;
6703 case PPC_FLAGS_INPUT_BookE:
6704 bus_model = "PowerPC BookE";
6705 break;
6706 case PPC_FLAGS_INPUT_405:
6707 bus_model = "PowerPC 405";
6708 break;
6709 case PPC_FLAGS_INPUT_401:
6710 bus_model = "PowerPC 401/403";
6711 break;
6712 #if defined (TARGET_PPC64)
6713 case PPC_FLAGS_INPUT_970:
6714 bus_model = "PowerPC 970";
6715 break;
6716 #endif
6717 default:
6718 bus_model = "Unknown or invalid";
6719 break;
6720 }
6721 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6722 " MMU model : %s\n",
6723 def->name, def->pvr, def->msr_mask, mmu_model);
6724 #if !defined(CONFIG_USER_ONLY)
6725 if (env->tlb != NULL) {
6726 printf(" %d %s TLB in %d ways\n",
6727 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6728 env->nb_ways);
6729 }
6730 #endif
6731 printf(" Exceptions model : %s\n"
6732 " Bus model : %s\n",
6733 excp_model, bus_model);
6734 printf(" MSR features :\n");
6735 if (env->flags & POWERPC_FLAG_SPE)
6736 printf(" signal processing engine enable"
6737 "\n");
6738 else if (env->flags & POWERPC_FLAG_VRE)
6739 printf(" vector processor enable\n");
6740 if (env->flags & POWERPC_FLAG_TGPR)
6741 printf(" temporary GPRs\n");
6742 else if (env->flags & POWERPC_FLAG_CE)
6743 printf(" critical input enable\n");
6744 if (env->flags & POWERPC_FLAG_SE)
6745 printf(" single-step trace mode\n");
6746 else if (env->flags & POWERPC_FLAG_DWE)
6747 printf(" debug wait enable\n");
6748 else if (env->flags & POWERPC_FLAG_UBLE)
6749 printf(" user BTB lock enable\n");
6750 if (env->flags & POWERPC_FLAG_BE)
6751 printf(" branch-step trace mode\n");
6752 else if (env->flags & POWERPC_FLAG_DE)
6753 printf(" debug interrupt enable\n");
6754 if (env->flags & POWERPC_FLAG_PX)
6755 printf(" inclusive protection\n");
6756 else if (env->flags & POWERPC_FLAG_PMM)
6757 printf(" performance monitor mark\n");
6758 if (env->flags == POWERPC_FLAG_NONE)
6759 printf(" none\n");
6760 }
6761 dump_ppc_insns(env);
6762 dump_ppc_sprs(env);
6763 fflush(stdout);
6764 #endif
6765
6766 return 0;
6767 }
6768
6769 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
6770 {
6771 const ppc_def_t *ret;
6772 uint32_t pvr_rev;
6773 int i, best, match, best_match, max;
6774
6775 ret = NULL;
6776 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6777 best = -1;
6778 pvr_rev = pvr & 0xFFFF;
6779 /* We want all specified bits to match */
6780 best_match = 32 - ctz32(pvr_rev);
6781 for (i = 0; i < max; i++) {
6782 /* We check that the 16 higher bits are the same to ensure the CPU
6783 * model will be the choosen one.
6784 */
6785 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
6786 /* We want as much as possible of the low-level 16 bits
6787 * to be the same but we allow inexact matches.
6788 */
6789 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
6790 /* We check '>=' instead of '>' because the PPC_defs table
6791 * is ordered by increasing revision.
6792 * Then, we will match the higher revision compatible
6793 * with the requested PVR
6794 */
6795 if (match >= best_match) {
6796 best = i;
6797 best_match = match;
6798 }
6799 }
6800 }
6801 if (best != -1)
6802 ret = &ppc_defs[best];
6803
6804 return ret;
6805 }
6806
6807 #include <ctype.h>
6808
6809 const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name)
6810 {
6811 const ppc_def_t *ret;
6812 const unsigned char *p;
6813 int i, max, len;
6814
6815 /* Check if the given name is a PVR */
6816 len = strlen(name);
6817 if (len == 10 && name[0] == '0' && name[1] == 'x') {
6818 p = name + 2;
6819 goto check_pvr;
6820 } else if (len == 8) {
6821 p = name;
6822 check_pvr:
6823 for (i = 0; i < 8; i++) {
6824 if (!isxdigit(*p++))
6825 break;
6826 }
6827 if (i == 8)
6828 return ppc_find_by_pvr(strtoul(name, NULL, 16));
6829 }
6830 ret = NULL;
6831 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6832 for (i = 0; i < max; i++) {
6833 if (strcasecmp(name, ppc_defs[i].name) == 0) {
6834 ret = &ppc_defs[i];
6835 break;
6836 }
6837 }
6838
6839 return ret;
6840 }
6841
6842 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
6843 {
6844 int i, max;
6845
6846 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
6847 for (i = 0; i < max; i++) {
6848 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
6849 ppc_defs[i].name, ppc_defs[i].pvr);
6850 }
6851 }
Stable branch of Qemu 0.9.1