9 static uint32_t cortexa8_cp15_c0_c1
[8] =
10 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
12 static uint32_t cortexa8_cp15_c0_c2
[8] =
13 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
15 static uint32_t mpcore_cp15_c0_c1
[8] =
16 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
18 static uint32_t mpcore_cp15_c0_c2
[8] =
19 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
21 static uint32_t arm1136_cp15_c0_c1
[8] =
22 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
24 static uint32_t arm1136_cp15_c0_c2
[8] =
25 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
27 static uint32_t cpu_arm_find_by_name(const char *name
);
29 static inline void set_feature(CPUARMState
*env
, int feature
)
31 env
->features
|= 1u << feature
;
34 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
36 env
->cp15
.c0_cpuid
= id
;
38 case ARM_CPUID_ARM926
:
39 set_feature(env
, ARM_FEATURE_VFP
);
40 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
41 env
->cp15
.c0_cachetype
= 0x1dd20d2;
42 env
->cp15
.c1_sys
= 0x00090078;
44 case ARM_CPUID_ARM946
:
45 set_feature(env
, ARM_FEATURE_MPU
);
46 env
->cp15
.c0_cachetype
= 0x0f004006;
47 env
->cp15
.c1_sys
= 0x00000078;
49 case ARM_CPUID_ARM1026
:
50 set_feature(env
, ARM_FEATURE_VFP
);
51 set_feature(env
, ARM_FEATURE_AUXCR
);
52 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
53 env
->cp15
.c0_cachetype
= 0x1dd20d2;
54 env
->cp15
.c1_sys
= 0x00090078;
56 case ARM_CPUID_ARM1136
:
57 set_feature(env
, ARM_FEATURE_V6
);
58 set_feature(env
, ARM_FEATURE_VFP
);
59 set_feature(env
, ARM_FEATURE_AUXCR
);
60 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
61 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
62 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
63 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
64 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
65 env
->cp15
.c0_cachetype
= 0x1dd20d2;
67 case ARM_CPUID_ARM11MPCORE
:
68 set_feature(env
, ARM_FEATURE_V6
);
69 set_feature(env
, ARM_FEATURE_V6K
);
70 set_feature(env
, ARM_FEATURE_VFP
);
71 set_feature(env
, ARM_FEATURE_AUXCR
);
72 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
73 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
74 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
75 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
76 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
77 env
->cp15
.c0_cachetype
= 0x1dd20d2;
79 case ARM_CPUID_CORTEXA8
:
80 set_feature(env
, ARM_FEATURE_V6
);
81 set_feature(env
, ARM_FEATURE_V6K
);
82 set_feature(env
, ARM_FEATURE_V7
);
83 set_feature(env
, ARM_FEATURE_AUXCR
);
84 set_feature(env
, ARM_FEATURE_THUMB2
);
85 set_feature(env
, ARM_FEATURE_VFP
);
86 set_feature(env
, ARM_FEATURE_VFP3
);
87 set_feature(env
, ARM_FEATURE_NEON
);
88 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
89 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
90 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
91 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
92 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
93 env
->cp15
.c0_cachetype
= 0x1dd20d2;
95 case ARM_CPUID_CORTEXM3
:
96 set_feature(env
, ARM_FEATURE_V6
);
97 set_feature(env
, ARM_FEATURE_THUMB2
);
98 set_feature(env
, ARM_FEATURE_V7
);
99 set_feature(env
, ARM_FEATURE_M
);
100 set_feature(env
, ARM_FEATURE_DIV
);
102 case ARM_CPUID_ANY
: /* For userspace emulation. */
103 set_feature(env
, ARM_FEATURE_V6
);
104 set_feature(env
, ARM_FEATURE_V6K
);
105 set_feature(env
, ARM_FEATURE_V7
);
106 set_feature(env
, ARM_FEATURE_THUMB2
);
107 set_feature(env
, ARM_FEATURE_VFP
);
108 set_feature(env
, ARM_FEATURE_VFP3
);
109 set_feature(env
, ARM_FEATURE_NEON
);
110 set_feature(env
, ARM_FEATURE_DIV
);
112 case ARM_CPUID_TI915T
:
113 case ARM_CPUID_TI925T
:
114 set_feature(env
, ARM_FEATURE_OMAPCP
);
115 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
116 env
->cp15
.c0_cachetype
= 0x5109149;
117 env
->cp15
.c1_sys
= 0x00000070;
118 env
->cp15
.c15_i_max
= 0x000;
119 env
->cp15
.c15_i_min
= 0xff0;
121 case ARM_CPUID_PXA250
:
122 case ARM_CPUID_PXA255
:
123 case ARM_CPUID_PXA260
:
124 case ARM_CPUID_PXA261
:
125 case ARM_CPUID_PXA262
:
126 set_feature(env
, ARM_FEATURE_XSCALE
);
127 /* JTAG_ID is ((id << 28) | 0x09265013) */
128 env
->cp15
.c0_cachetype
= 0xd172172;
129 env
->cp15
.c1_sys
= 0x00000078;
131 case ARM_CPUID_PXA270_A0
:
132 case ARM_CPUID_PXA270_A1
:
133 case ARM_CPUID_PXA270_B0
:
134 case ARM_CPUID_PXA270_B1
:
135 case ARM_CPUID_PXA270_C0
:
136 case ARM_CPUID_PXA270_C5
:
137 set_feature(env
, ARM_FEATURE_XSCALE
);
138 /* JTAG_ID is ((id << 28) | 0x09265013) */
139 set_feature(env
, ARM_FEATURE_IWMMXT
);
140 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
141 env
->cp15
.c0_cachetype
= 0xd172172;
142 env
->cp15
.c1_sys
= 0x00000078;
145 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
150 void cpu_reset(CPUARMState
*env
)
153 id
= env
->cp15
.c0_cpuid
;
154 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
156 cpu_reset_model_id(env
, id
);
157 #if defined (CONFIG_USER_ONLY)
158 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
159 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
161 /* SVC mode with interrupts disabled. */
162 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
163 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
166 env
->uncached_cpsr
&= ~CPSR_I
;
167 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
173 CPUARMState
*cpu_arm_init(const char *cpu_model
)
178 id
= cpu_arm_find_by_name(cpu_model
);
181 env
= qemu_mallocz(sizeof(CPUARMState
));
185 env
->cp15
.c0_cpuid
= id
;
195 static const struct arm_cpu_t arm_cpu_names
[] = {
196 { ARM_CPUID_ARM926
, "arm926"},
197 { ARM_CPUID_ARM946
, "arm946"},
198 { ARM_CPUID_ARM1026
, "arm1026"},
199 { ARM_CPUID_ARM1136
, "arm1136"},
200 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
201 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
202 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
203 { ARM_CPUID_TI925T
, "ti925t" },
204 { ARM_CPUID_PXA250
, "pxa250" },
205 { ARM_CPUID_PXA255
, "pxa255" },
206 { ARM_CPUID_PXA260
, "pxa260" },
207 { ARM_CPUID_PXA261
, "pxa261" },
208 { ARM_CPUID_PXA262
, "pxa262" },
209 { ARM_CPUID_PXA270
, "pxa270" },
210 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
211 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
212 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
213 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
214 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
215 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
216 { ARM_CPUID_ANY
, "any"},
220 void arm_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
224 (*cpu_fprintf
)(f
, "Available CPUs:\n");
225 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
226 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
230 /* return 0 if not found */
231 static uint32_t cpu_arm_find_by_name(const char *name
)
237 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
238 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
239 id
= arm_cpu_names
[i
].id
;
246 void cpu_arm_close(CPUARMState
*env
)
251 /* Polynomial multiplication is like integer multiplcation except the
252 partial products are XORed, not added. */
253 uint32_t helper_neon_mul_p8(uint32_t op1
, uint32_t op2
)
265 mask
|= (0xff << 16);
267 mask
|= (0xff << 24);
268 result
^= op2
& mask
;
269 op1
= (op1
>> 1) & 0x7f7f7f7f;
270 op2
= (op2
<< 1) & 0xfefefefe;
275 uint32_t cpsr_read(CPUARMState
*env
)
278 ZF
= (env
->NZF
== 0);
279 return env
->uncached_cpsr
| (env
->NZF
& 0x80000000) | (ZF
<< 30) |
280 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
281 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
282 | ((env
->condexec_bits
& 0xfc) << 8)
286 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
288 /* NOTE: N = 1 and Z = 1 cannot be stored currently */
289 if (mask
& CPSR_NZCV
) {
290 env
->NZF
= (val
& 0xc0000000) ^ 0x40000000;
291 env
->CF
= (val
>> 29) & 1;
292 env
->VF
= (val
<< 3) & 0x80000000;
295 env
->QF
= ((val
& CPSR_Q
) != 0);
297 env
->thumb
= ((val
& CPSR_T
) != 0);
298 if (mask
& CPSR_IT_0_1
) {
299 env
->condexec_bits
&= ~3;
300 env
->condexec_bits
|= (val
>> 25) & 3;
302 if (mask
& CPSR_IT_2_7
) {
303 env
->condexec_bits
&= 3;
304 env
->condexec_bits
|= (val
>> 8) & 0xfc;
306 if (mask
& CPSR_GE
) {
307 env
->GE
= (val
>> 16) & 0xf;
310 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
311 switch_mode(env
, val
& CPSR_M
);
313 mask
&= ~CACHED_CPSR_BITS
;
314 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
317 #if defined(CONFIG_USER_ONLY)
319 void do_interrupt (CPUState
*env
)
321 env
->exception_index
= -1;
324 /* Structure used to record exclusive memory locations. */
325 typedef struct mmon_state
{
326 struct mmon_state
*next
;
327 CPUARMState
*cpu_env
;
331 /* Chain of current locks. */
332 static mmon_state
* mmon_head
= NULL
;
334 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
335 int mmu_idx
, int is_softmmu
)
338 env
->exception_index
= EXCP_PREFETCH_ABORT
;
339 env
->cp15
.c6_insn
= address
;
341 env
->exception_index
= EXCP_DATA_ABORT
;
342 env
->cp15
.c6_data
= address
;
347 static void allocate_mmon_state(CPUState
*env
)
349 env
->mmon_entry
= malloc(sizeof (mmon_state
));
350 if (!env
->mmon_entry
)
352 memset (env
->mmon_entry
, 0, sizeof (mmon_state
));
353 env
->mmon_entry
->cpu_env
= env
;
354 mmon_head
= env
->mmon_entry
;
357 /* Flush any monitor locks for the specified address. */
358 static void flush_mmon(uint32_t addr
)
362 for (mon
= mmon_head
; mon
; mon
= mon
->next
)
364 if (mon
->addr
!= addr
)
372 /* Mark an address for exclusive access. */
373 void helper_mark_exclusive(CPUState
*env
, uint32_t addr
)
375 if (!env
->mmon_entry
)
376 allocate_mmon_state(env
);
377 /* Clear any previous locks. */
379 env
->mmon_entry
->addr
= addr
;
382 /* Test if an exclusive address is still exclusive. Returns zero
383 if the address is still exclusive. */
384 int helper_test_exclusive(CPUState
*env
, uint32_t addr
)
388 if (!env
->mmon_entry
)
390 if (env
->mmon_entry
->addr
== addr
)
398 void helper_clrex(CPUState
*env
)
400 if (!(env
->mmon_entry
&& env
->mmon_entry
->addr
))
402 flush_mmon(env
->mmon_entry
->addr
);
405 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
410 /* These should probably raise undefined insn exceptions. */
411 void helper_set_cp(CPUState
*env
, uint32_t insn
, uint32_t val
)
413 int op1
= (insn
>> 8) & 0xf;
414 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
418 uint32_t helper_get_cp(CPUState
*env
, uint32_t insn
)
420 int op1
= (insn
>> 8) & 0xf;
421 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
425 void helper_set_cp15(CPUState
*env
, uint32_t insn
, uint32_t val
)
427 cpu_abort(env
, "cp15 insn %08x\n", insn
);
430 uint32_t helper_get_cp15(CPUState
*env
, uint32_t insn
)
432 cpu_abort(env
, "cp15 insn %08x\n", insn
);
436 /* These should probably raise undefined insn exceptions. */
437 void helper_v7m_msr(CPUState
*env
, int reg
, uint32_t val
)
439 cpu_abort(env
, "v7m_mrs %d\n", reg
);
442 uint32_t helper_v7m_mrs(CPUState
*env
, int reg
)
444 cpu_abort(env
, "v7m_mrs %d\n", reg
);
448 void switch_mode(CPUState
*env
, int mode
)
450 if (mode
!= ARM_CPU_MODE_USR
)
451 cpu_abort(env
, "Tried to switch out of user mode\n");
454 void helper_set_r13_banked(CPUState
*env
, int mode
, uint32_t val
)
456 cpu_abort(env
, "banked r13 write\n");
459 uint32_t helper_get_r13_banked(CPUState
*env
, int mode
)
461 cpu_abort(env
, "banked r13 read\n");
467 extern int semihosting_enabled
;
469 /* Map CPU modes onto saved register banks. */
470 static inline int bank_number (int mode
)
473 case ARM_CPU_MODE_USR
:
474 case ARM_CPU_MODE_SYS
:
476 case ARM_CPU_MODE_SVC
:
478 case ARM_CPU_MODE_ABT
:
480 case ARM_CPU_MODE_UND
:
482 case ARM_CPU_MODE_IRQ
:
484 case ARM_CPU_MODE_FIQ
:
487 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
491 void switch_mode(CPUState
*env
, int mode
)
496 old_mode
= env
->uncached_cpsr
& CPSR_M
;
497 if (mode
== old_mode
)
500 if (old_mode
== ARM_CPU_MODE_FIQ
) {
501 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
502 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
503 } else if (mode
== ARM_CPU_MODE_FIQ
) {
504 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
505 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
508 i
= bank_number(old_mode
);
509 env
->banked_r13
[i
] = env
->regs
[13];
510 env
->banked_r14
[i
] = env
->regs
[14];
511 env
->banked_spsr
[i
] = env
->spsr
;
513 i
= bank_number(mode
);
514 env
->regs
[13] = env
->banked_r13
[i
];
515 env
->regs
[14] = env
->banked_r14
[i
];
516 env
->spsr
= env
->banked_spsr
[i
];
519 static void v7m_push(CPUARMState
*env
, uint32_t val
)
522 stl_phys(env
->regs
[13], val
);
525 static uint32_t v7m_pop(CPUARMState
*env
)
528 val
= ldl_phys(env
->regs
[13]);
533 /* Switch to V7M main or process stack pointer. */
534 static void switch_v7m_sp(CPUARMState
*env
, int process
)
537 if (env
->v7m
.current_sp
!= process
) {
538 tmp
= env
->v7m
.other_sp
;
539 env
->v7m
.other_sp
= env
->regs
[13];
541 env
->v7m
.current_sp
= process
;
545 static void do_v7m_exception_exit(CPUARMState
*env
)
550 type
= env
->regs
[15];
551 if (env
->v7m
.exception
!= 0)
552 armv7m_nvic_complete_irq(env
->v7m
.nvic
, env
->v7m
.exception
);
554 /* Switch to the target stack. */
555 switch_v7m_sp(env
, (type
& 4) != 0);
557 env
->regs
[0] = v7m_pop(env
);
558 env
->regs
[1] = v7m_pop(env
);
559 env
->regs
[2] = v7m_pop(env
);
560 env
->regs
[3] = v7m_pop(env
);
561 env
->regs
[12] = v7m_pop(env
);
562 env
->regs
[14] = v7m_pop(env
);
563 env
->regs
[15] = v7m_pop(env
);
565 xpsr_write(env
, xpsr
, 0xfffffdff);
566 /* Undo stack alignment. */
569 /* ??? The exception return type specifies Thread/Handler mode. However
570 this is also implied by the xPSR value. Not sure what to do
571 if there is a mismatch. */
572 /* ??? Likewise for mismatches between the CONTROL register and the stack
576 void do_interrupt_v7m(CPUARMState
*env
)
578 uint32_t xpsr
= xpsr_read(env
);
583 if (env
->v7m
.current_sp
)
585 if (env
->v7m
.exception
== 0)
588 /* For exceptions we just mark as pending on the NVIC, and let that
590 /* TODO: Need to escalate if the current priority is higher than the
591 one we're raising. */
592 switch (env
->exception_index
) {
594 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_USAGE
);
598 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_SVC
);
600 case EXCP_PREFETCH_ABORT
:
601 case EXCP_DATA_ABORT
:
602 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_MEM
);
605 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_DEBUG
);
608 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->v7m
.nvic
);
610 case EXCP_EXCEPTION_EXIT
:
611 do_v7m_exception_exit(env
);
614 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
615 return; /* Never happens. Keep compiler happy. */
618 /* Align stack pointer. */
619 /* ??? Should only do this if Configuration Control Register
620 STACKALIGN bit is set. */
621 if (env
->regs
[13] & 4) {
625 /* Switch to the hander mode. */
627 v7m_push(env
, env
->regs
[15]);
628 v7m_push(env
, env
->regs
[14]);
629 v7m_push(env
, env
->regs
[12]);
630 v7m_push(env
, env
->regs
[3]);
631 v7m_push(env
, env
->regs
[2]);
632 v7m_push(env
, env
->regs
[1]);
633 v7m_push(env
, env
->regs
[0]);
634 switch_v7m_sp(env
, 0);
635 env
->uncached_cpsr
&= ~CPSR_IT
;
637 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
638 env
->regs
[15] = addr
& 0xfffffffe;
639 env
->thumb
= addr
& 1;
642 /* Handle a CPU exception. */
643 void do_interrupt(CPUARMState
*env
)
651 do_interrupt_v7m(env
);
654 /* TODO: Vectored interrupt controller. */
655 switch (env
->exception_index
) {
657 new_mode
= ARM_CPU_MODE_UND
;
666 if (semihosting_enabled
) {
667 /* Check for semihosting interrupt. */
669 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
671 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
673 /* Only intercept calls from privileged modes, to provide some
674 semblance of security. */
675 if (((mask
== 0x123456 && !env
->thumb
)
676 || (mask
== 0xab && env
->thumb
))
677 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
678 env
->regs
[0] = do_arm_semihosting(env
);
682 new_mode
= ARM_CPU_MODE_SVC
;
685 /* The PC already points to the next instructon. */
689 /* See if this is a semihosting syscall. */
691 mask
= lduw_code(env
->regs
[15]) & 0xff;
693 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
695 env
->regs
[0] = do_arm_semihosting(env
);
699 /* Fall through to prefetch abort. */
700 case EXCP_PREFETCH_ABORT
:
701 new_mode
= ARM_CPU_MODE_ABT
;
703 mask
= CPSR_A
| CPSR_I
;
706 case EXCP_DATA_ABORT
:
707 new_mode
= ARM_CPU_MODE_ABT
;
709 mask
= CPSR_A
| CPSR_I
;
713 new_mode
= ARM_CPU_MODE_IRQ
;
715 /* Disable IRQ and imprecise data aborts. */
716 mask
= CPSR_A
| CPSR_I
;
720 new_mode
= ARM_CPU_MODE_FIQ
;
722 /* Disable FIQ, IRQ and imprecise data aborts. */
723 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
727 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
728 return; /* Never happens. Keep compiler happy. */
731 if (env
->cp15
.c1_sys
& (1 << 13)) {
734 switch_mode (env
, new_mode
);
735 env
->spsr
= cpsr_read(env
);
737 env
->condexec_bits
= 0;
738 /* Switch to the new mode, and switch to Arm mode. */
739 /* ??? Thumb interrupt handlers not implemented. */
740 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
741 env
->uncached_cpsr
|= mask
;
743 env
->regs
[14] = env
->regs
[15] + offset
;
744 env
->regs
[15] = addr
;
745 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
748 /* Check section/page access permissions.
749 Returns the page protection flags, or zero if the access is not
751 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
757 return PAGE_READ
| PAGE_WRITE
;
759 if (access_type
== 1)
766 if (access_type
== 1)
768 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
770 return is_user
? 0 : PAGE_READ
;
777 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
782 return PAGE_READ
| PAGE_WRITE
;
784 return PAGE_READ
| PAGE_WRITE
;
785 case 4: case 7: /* Reserved. */
788 return is_user
? 0 : prot_ro
;
796 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
797 int is_user
, uint32_t *phys_ptr
, int *prot
)
807 /* Pagetable walk. */
808 /* Lookup l1 descriptor. */
809 if (address
& env
->cp15
.c2_mask
)
810 table
= env
->cp15
.c2_base1
;
812 table
= env
->cp15
.c2_base0
;
813 table
= (table
& 0xffffc000) | ((address
>> 18) & 0x3ffc);
814 desc
= ldl_phys(table
);
816 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
818 /* Secton translation fault. */
822 if (domain
== 0 || domain
== 2) {
824 code
= 9; /* Section domain fault. */
826 code
= 11; /* Page domain fault. */
831 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
832 ap
= (desc
>> 10) & 3;
835 /* Lookup l2 entry. */
837 /* Coarse pagetable. */
838 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
840 /* Fine pagetable. */
841 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
843 desc
= ldl_phys(table
);
845 case 0: /* Page translation fault. */
848 case 1: /* 64k page. */
849 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
850 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
852 case 2: /* 4k page. */
853 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
854 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
856 case 3: /* 1k page. */
858 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
859 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
861 /* Page translation fault. */
866 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
868 ap
= (desc
>> 4) & 3;
871 /* Never happens, but compiler isn't smart enough to tell. */
876 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
878 /* Access permission fault. */
881 *phys_ptr
= phys_addr
;
884 return code
| (domain
<< 4);
887 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
888 int is_user
, uint32_t *phys_ptr
, int *prot
)
899 /* Pagetable walk. */
900 /* Lookup l1 descriptor. */
901 if (address
& env
->cp15
.c2_mask
)
902 table
= env
->cp15
.c2_base1
;
904 table
= env
->cp15
.c2_base0
;
905 table
= (table
& 0xffffc000) | ((address
>> 18) & 0x3ffc);
906 desc
= ldl_phys(table
);
909 /* Secton translation fault. */
913 } else if (type
== 2 && (desc
& (1 << 18))) {
917 /* Section or page. */
918 domain
= (desc
>> 4) & 0x1e;
920 domain
= (env
->cp15
.c3
>> domain
) & 3;
921 if (domain
== 0 || domain
== 2) {
923 code
= 9; /* Section domain fault. */
925 code
= 11; /* Page domain fault. */
929 if (desc
& (1 << 18)) {
931 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
934 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
936 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
937 xn
= desc
& (1 << 4);
940 /* Lookup l2 entry. */
941 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
942 desc
= ldl_phys(table
);
943 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
945 case 0: /* Page translation fault. */
948 case 1: /* 64k page. */
949 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
950 xn
= desc
& (1 << 15);
952 case 2: case 3: /* 4k page. */
953 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
957 /* Never happens, but compiler isn't smart enough to tell. */
962 if (xn
&& access_type
== 2)
965 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
967 /* Access permission fault. */
970 *phys_ptr
= phys_addr
;
973 return code
| (domain
<< 4);
976 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
977 int is_user
, uint32_t *phys_ptr
, int *prot
)
984 for (n
= 7; n
>= 0; n
--) {
985 base
= env
->cp15
.c6_region
[n
];
988 mask
= 1 << ((base
>> 1) & 0x1f);
989 /* Keep this shift separate from the above to avoid an
990 (undefined) << 32. */
991 mask
= (mask
<< 1) - 1;
992 if (((base
^ address
) & ~mask
) == 0)
998 if (access_type
== 2) {
999 mask
= env
->cp15
.c5_insn
;
1001 mask
= env
->cp15
.c5_data
;
1003 mask
= (mask
>> (n
* 4)) & 0xf;
1010 *prot
= PAGE_READ
| PAGE_WRITE
;
1015 *prot
|= PAGE_WRITE
;
1018 *prot
= PAGE_READ
| PAGE_WRITE
;
1029 /* Bad permission. */
1035 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1036 int access_type
, int is_user
,
1037 uint32_t *phys_ptr
, int *prot
)
1039 /* Fast Context Switch Extension. */
1040 if (address
< 0x02000000)
1041 address
+= env
->cp15
.c13_fcse
;
1043 if ((env
->cp15
.c1_sys
& 1) == 0) {
1044 /* MMU/MPU disabled. */
1045 *phys_ptr
= address
;
1046 *prot
= PAGE_READ
| PAGE_WRITE
;
1048 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1049 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1051 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1052 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1055 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1060 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1061 int access_type
, int mmu_idx
, int is_softmmu
)
1067 is_user
= mmu_idx
== MMU_USER_IDX
;
1068 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
);
1070 /* Map a single [sub]page. */
1071 phys_addr
&= ~(uint32_t)0x3ff;
1072 address
&= ~(uint32_t)0x3ff;
1073 return tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
,
1077 if (access_type
== 2) {
1078 env
->cp15
.c5_insn
= ret
;
1079 env
->cp15
.c6_insn
= address
;
1080 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1082 env
->cp15
.c5_data
= ret
;
1083 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1084 env
->cp15
.c5_data
|= (1 << 11);
1085 env
->cp15
.c6_data
= address
;
1086 env
->exception_index
= EXCP_DATA_ABORT
;
1091 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1097 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
);
1105 /* Not really implemented. Need to figure out a sane way of doing this.
1106 Maybe add generic watchpoint support and use that. */
1108 void helper_mark_exclusive(CPUState
*env
, uint32_t addr
)
1110 env
->mmon_addr
= addr
;
1113 int helper_test_exclusive(CPUState
*env
, uint32_t addr
)
1115 return (env
->mmon_addr
!= addr
);
1118 void helper_clrex(CPUState
*env
)
1120 env
->mmon_addr
= -1;
1123 void helper_set_cp(CPUState
*env
, uint32_t insn
, uint32_t val
)
1125 int cp_num
= (insn
>> 8) & 0xf;
1126 int cp_info
= (insn
>> 5) & 7;
1127 int src
= (insn
>> 16) & 0xf;
1128 int operand
= insn
& 0xf;
1130 if (env
->cp
[cp_num
].cp_write
)
1131 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1132 cp_info
, src
, operand
, val
);
1135 uint32_t helper_get_cp(CPUState
*env
, uint32_t insn
)
1137 int cp_num
= (insn
>> 8) & 0xf;
1138 int cp_info
= (insn
>> 5) & 7;
1139 int dest
= (insn
>> 16) & 0xf;
1140 int operand
= insn
& 0xf;
1142 if (env
->cp
[cp_num
].cp_read
)
1143 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1144 cp_info
, dest
, operand
);
1148 /* Return basic MPU access permission bits. */
1149 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1156 for (i
= 0; i
< 16; i
+= 2) {
1157 ret
|= (val
>> i
) & mask
;
1163 /* Pad basic MPU access permission bits to extended format. */
1164 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1171 for (i
= 0; i
< 16; i
+= 2) {
1172 ret
|= (val
& mask
) << i
;
1178 void helper_set_cp15(CPUState
*env
, uint32_t insn
, uint32_t val
)
1184 op1
= (insn
>> 21) & 7;
1185 op2
= (insn
>> 5) & 7;
1187 switch ((insn
>> 16) & 0xf) {
1189 if (((insn
>> 21) & 7) == 2) {
1190 /* ??? Select cache level. Ignore. */
1194 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1196 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1199 case 1: /* System configuration. */
1200 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1204 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1205 env
->cp15
.c1_sys
= val
;
1206 /* ??? Lots of these bits are not implemented. */
1207 /* This may enable/disable the MMU, so do a TLB flush. */
1210 case 1: /* Auxiliary cotrol register. */
1211 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1212 env
->cp15
.c1_xscaleauxcr
= val
;
1215 /* Not implemented. */
1218 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1220 env
->cp15
.c1_coproc
= val
;
1221 /* ??? Is this safe when called from within a TB? */
1228 case 2: /* MMU Page table control / MPU cache control. */
1229 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1232 env
->cp15
.c2_data
= val
;
1235 env
->cp15
.c2_insn
= val
;
1243 env
->cp15
.c2_base0
= val
;
1246 env
->cp15
.c2_base1
= val
;
1249 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1256 case 3: /* MMU Domain access control / MPU write buffer control. */
1258 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1260 case 4: /* Reserved. */
1262 case 5: /* MMU Fault status / MPU access permission. */
1263 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1267 if (arm_feature(env
, ARM_FEATURE_MPU
))
1268 val
= extended_mpu_ap_bits(val
);
1269 env
->cp15
.c5_data
= val
;
1272 if (arm_feature(env
, ARM_FEATURE_MPU
))
1273 val
= extended_mpu_ap_bits(val
);
1274 env
->cp15
.c5_insn
= val
;
1277 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1279 env
->cp15
.c5_data
= val
;
1282 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1284 env
->cp15
.c5_insn
= val
;
1290 case 6: /* MMU Fault address / MPU base/size. */
1291 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1294 env
->cp15
.c6_region
[crm
] = val
;
1296 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1300 env
->cp15
.c6_data
= val
;
1302 case 1: /* ??? This is WFAR on armv6 */
1304 env
->cp15
.c6_insn
= val
;
1311 case 7: /* Cache control. */
1312 env
->cp15
.c15_i_max
= 0x000;
1313 env
->cp15
.c15_i_min
= 0xff0;
1314 /* No cache, so nothing to do. */
1315 /* ??? MPCore has VA to PA translation functions. */
1317 case 8: /* MMU TLB control. */
1319 case 0: /* Invalidate all. */
1322 case 1: /* Invalidate single TLB entry. */
1324 /* ??? This is wrong for large pages and sections. */
1325 /* As an ugly hack to make linux work we always flush a 4K
1328 tlb_flush_page(env
, val
);
1329 tlb_flush_page(env
, val
+ 0x400);
1330 tlb_flush_page(env
, val
+ 0x800);
1331 tlb_flush_page(env
, val
+ 0xc00);
1336 case 2: /* Invalidate on ASID. */
1337 tlb_flush(env
, val
== 0);
1339 case 3: /* Invalidate single entry on MVA. */
1340 /* ??? This is like case 1, but ignores ASID. */
1348 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1351 case 0: /* Cache lockdown. */
1353 case 0: /* L1 cache. */
1356 env
->cp15
.c9_data
= val
;
1359 env
->cp15
.c9_insn
= val
;
1365 case 1: /* L2 cache. */
1366 /* Ignore writes to L2 lockdown/auxiliary registers. */
1372 case 1: /* TCM memory region registers. */
1373 /* Not implemented. */
1379 case 10: /* MMU TLB lockdown. */
1380 /* ??? TLB lockdown not implemented. */
1382 case 12: /* Reserved. */
1384 case 13: /* Process ID. */
1387 /* Unlike real hardware the qemu TLB uses virtual addresses,
1388 not modified virtual addresses, so this causes a TLB flush.
1390 if (env
->cp15
.c13_fcse
!= val
)
1392 env
->cp15
.c13_fcse
= val
;
1395 /* This changes the ASID, so do a TLB flush. */
1396 if (env
->cp15
.c13_context
!= val
1397 && !arm_feature(env
, ARM_FEATURE_MPU
))
1399 env
->cp15
.c13_context
= val
;
1402 env
->cp15
.c13_tls1
= val
;
1405 env
->cp15
.c13_tls2
= val
;
1408 env
->cp15
.c13_tls3
= val
;
1414 case 14: /* Reserved. */
1416 case 15: /* Implementation specific. */
1417 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1418 if (op2
== 0 && crm
== 1) {
1419 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1420 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1422 env
->cp15
.c15_cpar
= val
& 0x3fff;
1428 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1432 case 1: /* Set TI925T configuration. */
1433 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1434 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1435 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1437 case 2: /* Set I_max. */
1438 env
->cp15
.c15_i_max
= val
;
1440 case 3: /* Set I_min. */
1441 env
->cp15
.c15_i_min
= val
;
1443 case 4: /* Set thread-ID. */
1444 env
->cp15
.c15_threadid
= val
& 0xffff;
1446 case 8: /* Wait-for-interrupt (deprecated). */
1447 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1457 /* ??? For debugging only. Should raise illegal instruction exception. */
1458 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1459 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1462 uint32_t helper_get_cp15(CPUState
*env
, uint32_t insn
)
1468 op1
= (insn
>> 21) & 7;
1469 op2
= (insn
>> 5) & 7;
1471 switch ((insn
>> 16) & 0xf) {
1472 case 0: /* ID codes. */
1478 case 0: /* Device ID. */
1479 return env
->cp15
.c0_cpuid
;
1480 case 1: /* Cache Type. */
1481 return env
->cp15
.c0_cachetype
;
1482 case 2: /* TCM status. */
1484 case 3: /* TLB type register. */
1485 return 0; /* No lockable TLB entries. */
1486 case 5: /* CPU ID */
1487 return env
->cpu_index
;
1492 if (!arm_feature(env
, ARM_FEATURE_V6
))
1494 return env
->cp15
.c0_c1
[op2
];
1496 if (!arm_feature(env
, ARM_FEATURE_V6
))
1498 return env
->cp15
.c0_c2
[op2
];
1499 case 3: case 4: case 5: case 6: case 7:
1505 /* These registers aren't documented on arm11 cores. However
1506 Linux looks at them anyway. */
1507 if (!arm_feature(env
, ARM_FEATURE_V6
))
1511 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1517 case 1: /* System configuration. */
1518 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1521 case 0: /* Control register. */
1522 return env
->cp15
.c1_sys
;
1523 case 1: /* Auxiliary control register. */
1524 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1525 return env
->cp15
.c1_xscaleauxcr
;
1526 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1528 switch (ARM_CPUID(env
)) {
1529 case ARM_CPUID_ARM1026
:
1531 case ARM_CPUID_ARM1136
:
1533 case ARM_CPUID_ARM11MPCORE
:
1535 case ARM_CPUID_CORTEXA8
:
1540 case 2: /* Coprocessor access register. */
1541 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1543 return env
->cp15
.c1_coproc
;
1547 case 2: /* MMU Page table control / MPU cache control. */
1548 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1551 return env
->cp15
.c2_data
;
1554 return env
->cp15
.c2_insn
;
1562 return env
->cp15
.c2_base0
;
1564 return env
->cp15
.c2_base1
;
1570 mask
= env
->cp15
.c2_mask
;
1581 case 3: /* MMU Domain access control / MPU write buffer control. */
1582 return env
->cp15
.c3
;
1583 case 4: /* Reserved. */
1585 case 5: /* MMU Fault status / MPU access permission. */
1586 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1590 if (arm_feature(env
, ARM_FEATURE_MPU
))
1591 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1592 return env
->cp15
.c5_data
;
1594 if (arm_feature(env
, ARM_FEATURE_MPU
))
1595 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1596 return env
->cp15
.c5_insn
;
1598 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1600 return env
->cp15
.c5_data
;
1602 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1604 return env
->cp15
.c5_insn
;
1608 case 6: /* MMU Fault address. */
1609 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1612 return env
->cp15
.c6_region
[crm
];
1614 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1618 return env
->cp15
.c6_data
;
1620 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1621 /* Watchpoint Fault Adrress. */
1622 return 0; /* Not implemented. */
1624 /* Instruction Fault Adrress. */
1625 /* Arm9 doesn't have an IFAR, but implementing it anyway
1626 shouldn't do any harm. */
1627 return env
->cp15
.c6_insn
;
1630 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1631 /* Instruction Fault Adrress. */
1632 return env
->cp15
.c6_insn
;
1640 case 7: /* Cache control. */
1641 /* ??? This is for test, clean and invaidate operations that set the
1642 Z flag. We can't represent N = Z = 1, so it also clears
1643 the N flag. Oh well. */
1646 case 8: /* MMU TLB control. */
1648 case 9: /* Cache lockdown. */
1650 case 0: /* L1 cache. */
1651 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1655 return env
->cp15
.c9_data
;
1657 return env
->cp15
.c9_insn
;
1661 case 1: /* L2 cache */
1664 /* L2 Lockdown and Auxiliary control. */
1669 case 10: /* MMU TLB lockdown. */
1670 /* ??? TLB lockdown not implemented. */
1672 case 11: /* TCM DMA control. */
1673 case 12: /* Reserved. */
1675 case 13: /* Process ID. */
1678 return env
->cp15
.c13_fcse
;
1680 return env
->cp15
.c13_context
;
1682 return env
->cp15
.c13_tls1
;
1684 return env
->cp15
.c13_tls2
;
1686 return env
->cp15
.c13_tls3
;
1690 case 14: /* Reserved. */
1692 case 15: /* Implementation specific. */
1693 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1694 if (op2
== 0 && crm
== 1)
1695 return env
->cp15
.c15_cpar
;
1699 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1703 case 1: /* Read TI925T configuration. */
1704 return env
->cp15
.c15_ticonfig
;
1705 case 2: /* Read I_max. */
1706 return env
->cp15
.c15_i_max
;
1707 case 3: /* Read I_min. */
1708 return env
->cp15
.c15_i_min
;
1709 case 4: /* Read thread-ID. */
1710 return env
->cp15
.c15_threadid
;
1711 case 8: /* TI925T_status */
1719 /* ??? For debugging only. Should raise illegal instruction exception. */
1720 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1721 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1725 void helper_set_r13_banked(CPUState
*env
, int mode
, uint32_t val
)
1727 env
->banked_r13
[bank_number(mode
)] = val
;
1730 uint32_t helper_get_r13_banked(CPUState
*env
, int mode
)
1732 return env
->banked_r13
[bank_number(mode
)];
1735 uint32_t helper_v7m_mrs(CPUState
*env
, int reg
)
1739 return xpsr_read(env
) & 0xf8000000;
1741 return xpsr_read(env
) & 0xf80001ff;
1743 return xpsr_read(env
) & 0xff00fc00;
1745 return xpsr_read(env
) & 0xff00fdff;
1747 return xpsr_read(env
) & 0x000001ff;
1749 return xpsr_read(env
) & 0x0700fc00;
1751 return xpsr_read(env
) & 0x0700edff;
1753 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1755 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1756 case 16: /* PRIMASK */
1757 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1758 case 17: /* FAULTMASK */
1759 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1760 case 18: /* BASEPRI */
1761 case 19: /* BASEPRI_MAX */
1762 return env
->v7m
.basepri
;
1763 case 20: /* CONTROL */
1764 return env
->v7m
.control
;
1766 /* ??? For debugging only. */
1767 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1772 void helper_v7m_msr(CPUState
*env
, int reg
, uint32_t val
)
1776 xpsr_write(env
, val
, 0xf8000000);
1779 xpsr_write(env
, val
, 0xf8000000);
1782 xpsr_write(env
, val
, 0xfe00fc00);
1785 xpsr_write(env
, val
, 0xfe00fc00);
1788 /* IPSR bits are readonly. */
1791 xpsr_write(env
, val
, 0x0600fc00);
1794 xpsr_write(env
, val
, 0x0600fc00);
1797 if (env
->v7m
.current_sp
)
1798 env
->v7m
.other_sp
= val
;
1800 env
->regs
[13] = val
;
1803 if (env
->v7m
.current_sp
)
1804 env
->regs
[13] = val
;
1806 env
->v7m
.other_sp
= val
;
1808 case 16: /* PRIMASK */
1810 env
->uncached_cpsr
|= CPSR_I
;
1812 env
->uncached_cpsr
&= ~CPSR_I
;
1814 case 17: /* FAULTMASK */
1816 env
->uncached_cpsr
|= CPSR_F
;
1818 env
->uncached_cpsr
&= ~CPSR_F
;
1820 case 18: /* BASEPRI */
1821 env
->v7m
.basepri
= val
& 0xff;
1823 case 19: /* BASEPRI_MAX */
1825 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1826 env
->v7m
.basepri
= val
;
1828 case 20: /* CONTROL */
1829 env
->v7m
.control
= val
& 3;
1830 switch_v7m_sp(env
, (val
& 2) != 0);
1833 /* ??? For debugging only. */
1834 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
1839 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
1840 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
1843 if (cpnum
< 0 || cpnum
> 14) {
1844 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
1848 env
->cp
[cpnum
].cp_read
= cp_read
;
1849 env
->cp
[cpnum
].cp_write
= cp_write
;
1850 env
->cp
[cpnum
].opaque
= opaque
;