target-mips/op.c

   1 /*
   2  *  MIPS emulation micro-operations for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *  Copyright (c) 2006 Marius Groeger (FPU operations)
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include "config.h"
  23 #include "exec.h"
  24
  25 #ifndef CALL_FROM_TB0
  26 #define CALL_FROM_TB0(func) func()
  27 #endif
  28 #ifndef CALL_FROM_TB1
  29 #define CALL_FROM_TB1(func, arg0) func(arg0)
  30 #endif
  31 #ifndef CALL_FROM_TB1_CONST16
  32 #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
  33 #endif
  34 #ifndef CALL_FROM_TB2
  35 #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
  36 #endif
  37 #ifndef CALL_FROM_TB2_CONST16
  38 #define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
  39         CALL_FROM_TB2(func, arg0, arg1)
  40 #endif
  41 #ifndef CALL_FROM_TB3
  42 #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
  43 #endif
  44 #ifndef CALL_FROM_TB4
  45 #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
  46         func(arg0, arg1, arg2, arg3)
  47 #endif
  48
  49 #define REG 1
  50 #include "op_template.c"
  51 #undef REG
  52 #define REG 2
  53 #include "op_template.c"
  54 #undef REG
  55 #define REG 3
  56 #include "op_template.c"
  57 #undef REG
  58 #define REG 4
  59 #include "op_template.c"
  60 #undef REG
  61 #define REG 5
  62 #include "op_template.c"
  63 #undef REG
  64 #define REG 6
  65 #include "op_template.c"
  66 #undef REG
  67 #define REG 7
  68 #include "op_template.c"
  69 #undef REG
  70 #define REG 8
  71 #include "op_template.c"
  72 #undef REG
  73 #define REG 9
  74 #include "op_template.c"
  75 #undef REG
  76 #define REG 10
  77 #include "op_template.c"
  78 #undef REG
  79 #define REG 11
  80 #include "op_template.c"
  81 #undef REG
  82 #define REG 12
  83 #include "op_template.c"
  84 #undef REG
  85 #define REG 13
  86 #include "op_template.c"
  87 #undef REG
  88 #define REG 14
  89 #include "op_template.c"
  90 #undef REG
  91 #define REG 15
  92 #include "op_template.c"
  93 #undef REG
  94 #define REG 16
  95 #include "op_template.c"
  96 #undef REG
  97 #define REG 17
  98 #include "op_template.c"
  99 #undef REG
 100 #define REG 18
 101 #include "op_template.c"
 102 #undef REG
 103 #define REG 19
 104 #include "op_template.c"
 105 #undef REG
 106 #define REG 20
 107 #include "op_template.c"
 108 #undef REG
 109 #define REG 21
 110 #include "op_template.c"
 111 #undef REG
 112 #define REG 22
 113 #include "op_template.c"
 114 #undef REG
 115 #define REG 23
 116 #include "op_template.c"
 117 #undef REG
 118 #define REG 24
 119 #include "op_template.c"
 120 #undef REG
 121 #define REG 25
 122 #include "op_template.c"
 123 #undef REG
 124 #define REG 26
 125 #include "op_template.c"
 126 #undef REG
 127 #define REG 27
 128 #include "op_template.c"
 129 #undef REG
 130 #define REG 28
 131 #include "op_template.c"
 132 #undef REG
 133 #define REG 29
 134 #include "op_template.c"
 135 #undef REG
 136 #define REG 30
 137 #include "op_template.c"
 138 #undef REG
 139 #define REG 31
 140 #include "op_template.c"
 141 #undef REG
 142
 143 #define TN
 144 #include "op_template.c"
 145 #undef TN
 146
 147 #define FREG 0
 148 #include "fop_template.c"
 149 #undef FREG
 150 #define FREG 1
 151 #include "fop_template.c"
 152 #undef FREG
 153 #define FREG 2
 154 #include "fop_template.c"
 155 #undef FREG
 156 #define FREG 3
 157 #include "fop_template.c"
 158 #undef FREG
 159 #define FREG 4
 160 #include "fop_template.c"
 161 #undef FREG
 162 #define FREG 5
 163 #include "fop_template.c"
 164 #undef FREG
 165 #define FREG 6
 166 #include "fop_template.c"
 167 #undef FREG
 168 #define FREG 7
 169 #include "fop_template.c"
 170 #undef FREG
 171 #define FREG 8
 172 #include "fop_template.c"
 173 #undef FREG
 174 #define FREG 9
 175 #include "fop_template.c"
 176 #undef FREG
 177 #define FREG 10
 178 #include "fop_template.c"
 179 #undef FREG
 180 #define FREG 11
 181 #include "fop_template.c"
 182 #undef FREG
 183 #define FREG 12
 184 #include "fop_template.c"
 185 #undef FREG
 186 #define FREG 13
 187 #include "fop_template.c"
 188 #undef FREG
 189 #define FREG 14
 190 #include "fop_template.c"
 191 #undef FREG
 192 #define FREG 15
 193 #include "fop_template.c"
 194 #undef FREG
 195 #define FREG 16
 196 #include "fop_template.c"
 197 #undef FREG
 198 #define FREG 17
 199 #include "fop_template.c"
 200 #undef FREG
 201 #define FREG 18
 202 #include "fop_template.c"
 203 #undef FREG
 204 #define FREG 19
 205 #include "fop_template.c"
 206 #undef FREG
 207 #define FREG 20
 208 #include "fop_template.c"
 209 #undef FREG
 210 #define FREG 21
 211 #include "fop_template.c"
 212 #undef FREG
 213 #define FREG 22
 214 #include "fop_template.c"
 215 #undef FREG
 216 #define FREG 23
 217 #include "fop_template.c"
 218 #undef FREG
 219 #define FREG 24
 220 #include "fop_template.c"
 221 #undef FREG
 222 #define FREG 25
 223 #include "fop_template.c"
 224 #undef FREG
 225 #define FREG 26
 226 #include "fop_template.c"
 227 #undef FREG
 228 #define FREG 27
 229 #include "fop_template.c"
 230 #undef FREG
 231 #define FREG 28
 232 #include "fop_template.c"
 233 #undef FREG
 234 #define FREG 29
 235 #include "fop_template.c"
 236 #undef FREG
 237 #define FREG 30
 238 #include "fop_template.c"
 239 #undef FREG
 240 #define FREG 31
 241 #include "fop_template.c"
 242 #undef FREG
 243
 244 #define FTN
 245 #include "fop_template.c"
 246 #undef FTN
 247
 248 void op_dup_T0 (void)
 249 {
 250     T2 = T0;
 251     RETURN();
 252 }
 253
 254 void op_load_HI (void)
 255 {
 256     T0 = env->HI;
 257     RETURN();
 258 }
 259
 260 void op_store_HI (void)
 261 {
 262     env->HI = T0;
 263     RETURN();
 264 }
 265
 266 void op_load_LO (void)
 267 {
 268     T0 = env->LO;
 269     RETURN();
 270 }
 271
 272 void op_store_LO (void)
 273 {
 274     env->LO = T0;
 275     RETURN();
 276 }
 277
 278 /* Load and store */
 279 #define MEMSUFFIX _raw
 280 #include "op_mem.c"
 281 #undef MEMSUFFIX
 282 #if !defined(CONFIG_USER_ONLY)
 283 #define MEMSUFFIX _user
 284 #include "op_mem.c"
 285 #undef MEMSUFFIX
 286
 287 #define MEMSUFFIX _kernel
 288 #include "op_mem.c"
 289 #undef MEMSUFFIX
 290 #endif
 291
 292 /* Addresses computation */
 293 void op_addr_add (void)
 294 {
 295 /* For compatibility with 32-bit code, data reference in user mode
 296    with Status_UX = 0 should be casted to 32-bit and sign extended.
 297    See the MIPS64 PRA manual, section 4.10. */
 298 #ifdef TARGET_MIPS64
 299     if ((env->CP0_Status & (1 << CP0St_UM)) &&
 300         !(env->CP0_Status & (1 << CP0St_UX)))
 301         T0 = (int64_t)(int32_t)(T0 + T1);
 302     else
 303 #endif
 304         T0 += T1;
 305     RETURN();
 306 }
 307
 308 /* Arithmetic */
 309 void op_add (void)
 310 {
 311     T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
 312     RETURN();
 313 }
 314
 315 void op_addo (void)
 316 {
 317     target_ulong tmp;
 318
 319     tmp = (int32_t)T0;
 320     T0 = (int32_t)T0 + (int32_t)T1;
 321     if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
 322         /* operands of same sign, result different sign */
 323         CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
 324     }
 325     T0 = (int32_t)T0;
 326     RETURN();
 327 }
 328
 329 void op_sub (void)
 330 {
 331     T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
 332     RETURN();
 333 }
 334
 335 void op_subo (void)
 336 {
 337     target_ulong tmp;
 338
 339     tmp = (int32_t)T0;
 340     T0 = (int32_t)T0 - (int32_t)T1;
 341     if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
 342         /* operands of different sign, first operand and result different sign */
 343         CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
 344     }
 345     T0 = (int32_t)T0;
 346     RETURN();
 347 }
 348
 349 void op_mul (void)
 350 {
 351     T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
 352     RETURN();
 353 }
 354
 355 #if HOST_LONG_BITS < 64
 356 void op_div (void)
 357 {
 358     CALL_FROM_TB0(do_div);
 359     RETURN();
 360 }
 361 #else
 362 void op_div (void)
 363 {
 364     if (T1 != 0) {
 365         env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
 366         env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
 367     }
 368     RETURN();
 369 }
 370 #endif
 371
 372 void op_divu (void)
 373 {
 374     if (T1 != 0) {
 375         env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
 376         env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
 377     }
 378     RETURN();
 379 }
 380
 381 #ifdef TARGET_MIPS64
 382 /* Arithmetic */
 383 void op_dadd (void)
 384 {
 385     T0 += T1;
 386     RETURN();
 387 }
 388
 389 void op_daddo (void)
 390 {
 391     target_long tmp;
 392
 393     tmp = T0;
 394     T0 += T1;
 395     if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
 396         /* operands of same sign, result different sign */
 397         CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
 398     }
 399     RETURN();
 400 }
 401
 402 void op_dsub (void)
 403 {
 404     T0 -= T1;
 405     RETURN();
 406 }
 407
 408 void op_dsubo (void)
 409 {
 410     target_long tmp;
 411
 412     tmp = T0;
 413     T0 = (int64_t)T0 - (int64_t)T1;
 414     if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
 415         /* operands of different sign, first operand and result different sign */
 416         CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
 417     }
 418     RETURN();
 419 }
 420
 421 void op_dmul (void)
 422 {
 423     T0 = (int64_t)T0 * (int64_t)T1;
 424     RETURN();
 425 }
 426
 427 /* Those might call libgcc functions.  */
 428 void op_ddiv (void)
 429 {
 430     do_ddiv();
 431     RETURN();
 432 }
 433
 434 #if TARGET_LONG_BITS > HOST_LONG_BITS
 435 void op_ddivu (void)
 436 {
 437     do_ddivu();
 438     RETURN();
 439 }
 440 #else
 441 void op_ddivu (void)
 442 {
 443     if (T1 != 0) {
 444         env->LO = T0 / T1;
 445         env->HI = T0 % T1;
 446     }
 447     RETURN();
 448 }
 449 #endif
 450 #endif /* TARGET_MIPS64 */
 451
 452 /* Logical */
 453 void op_and (void)
 454 {
 455     T0 &= T1;
 456     RETURN();
 457 }
 458
 459 void op_nor (void)
 460 {
 461     T0 = ~(T0 | T1);
 462     RETURN();
 463 }
 464
 465 void op_or (void)
 466 {
 467     T0 |= T1;
 468     RETURN();
 469 }
 470
 471 void op_xor (void)
 472 {
 473     T0 ^= T1;
 474     RETURN();
 475 }
 476
 477 void op_sll (void)
 478 {
 479     T0 = (int32_t)((uint32_t)T0 << T1);
 480     RETURN();
 481 }
 482
 483 void op_sra (void)
 484 {
 485     T0 = (int32_t)((int32_t)T0 >> T1);
 486     RETURN();
 487 }
 488
 489 void op_srl (void)
 490 {
 491     T0 = (int32_t)((uint32_t)T0 >> T1);
 492     RETURN();
 493 }
 494
 495 void op_rotr (void)
 496 {
 497     target_ulong tmp;
 498
 499     if (T1) {
 500        tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
 501        T0 = (int32_t)((uint32_t)T0 >> T1) | tmp;
 502     }
 503     RETURN();
 504 }
 505
 506 void op_sllv (void)
 507 {
 508     T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
 509     RETURN();
 510 }
 511
 512 void op_srav (void)
 513 {
 514     T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
 515     RETURN();
 516 }
 517
 518 void op_srlv (void)
 519 {
 520     T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
 521     RETURN();
 522 }
 523
 524 void op_rotrv (void)
 525 {
 526     target_ulong tmp;
 527
 528     T0 &= 0x1F;
 529     if (T0) {
 530        tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
 531        T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
 532     } else
 533        T0 = T1;
 534     RETURN();
 535 }
 536
 537 void op_clo (void)
 538 {
 539     int n;
 540
 541     if (T0 == ~((target_ulong)0)) {
 542         T0 = 32;
 543     } else {
 544         for (n = 0; n < 32; n++) {
 545             if (!(T0 & (1 << 31)))
 546                 break;
 547             T0 = T0 << 1;
 548         }
 549         T0 = n;
 550     }
 551     RETURN();
 552 }
 553
 554 void op_clz (void)
 555 {
 556     int n;
 557
 558     if (T0 == 0) {
 559         T0 = 32;
 560     } else {
 561         for (n = 0; n < 32; n++) {
 562             if (T0 & (1 << 31))
 563                 break;
 564             T0 = T0 << 1;
 565         }
 566         T0 = n;
 567     }
 568     RETURN();
 569 }
 570
 571 #ifdef TARGET_MIPS64
 572
 573 #if TARGET_LONG_BITS > HOST_LONG_BITS
 574 /* Those might call libgcc functions.  */
 575 void op_dsll (void)
 576 {
 577     CALL_FROM_TB0(do_dsll);
 578     RETURN();
 579 }
 580
 581 void op_dsll32 (void)
 582 {
 583     CALL_FROM_TB0(do_dsll32);
 584     RETURN();
 585 }
 586
 587 void op_dsra (void)
 588 {
 589     CALL_FROM_TB0(do_dsra);
 590     RETURN();
 591 }
 592
 593 void op_dsra32 (void)
 594 {
 595     CALL_FROM_TB0(do_dsra32);
 596     RETURN();
 597 }
 598
 599 void op_dsrl (void)
 600 {
 601     CALL_FROM_TB0(do_dsrl);
 602     RETURN();
 603 }
 604
 605 void op_dsrl32 (void)
 606 {
 607     CALL_FROM_TB0(do_dsrl32);
 608     RETURN();
 609 }
 610
 611 void op_drotr (void)
 612 {
 613     CALL_FROM_TB0(do_drotr);
 614     RETURN();
 615 }
 616
 617 void op_drotr32 (void)
 618 {
 619     CALL_FROM_TB0(do_drotr32);
 620     RETURN();
 621 }
 622
 623 void op_dsllv (void)
 624 {
 625     CALL_FROM_TB0(do_dsllv);
 626     RETURN();
 627 }
 628
 629 void op_dsrav (void)
 630 {
 631     CALL_FROM_TB0(do_dsrav);
 632     RETURN();
 633 }
 634
 635 void op_dsrlv (void)
 636 {
 637     CALL_FROM_TB0(do_dsrlv);
 638     RETURN();
 639 }
 640
 641 void op_drotrv (void)
 642 {
 643     CALL_FROM_TB0(do_drotrv);
 644     RETURN();
 645 }
 646
 647 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
 648
 649 void op_dsll (void)
 650 {
 651     T0 = T0 << T1;
 652     RETURN();
 653 }
 654
 655 void op_dsll32 (void)
 656 {
 657     T0 = T0 << (T1 + 32);
 658     RETURN();
 659 }
 660
 661 void op_dsra (void)
 662 {
 663     T0 = (int64_t)T0 >> T1;
 664     RETURN();
 665 }
 666
 667 void op_dsra32 (void)
 668 {
 669     T0 = (int64_t)T0 >> (T1 + 32);
 670     RETURN();
 671 }
 672
 673 void op_dsrl (void)
 674 {
 675     T0 = T0 >> T1;
 676     RETURN();
 677 }
 678
 679 void op_dsrl32 (void)
 680 {
 681     T0 = T0 >> (T1 + 32);
 682     RETURN();
 683 }
 684
 685 void op_drotr (void)
 686 {
 687     target_ulong tmp;
 688
 689     if (T1) {
 690        tmp = T0 << (0x40 - T1);
 691        T0 = (T0 >> T1) | tmp;
 692     }
 693     RETURN();
 694 }
 695
 696 void op_drotr32 (void)
 697 {
 698     target_ulong tmp;
 699
 700     if (T1) {
 701        tmp = T0 << (0x40 - (32 + T1));
 702        T0 = (T0 >> (32 + T1)) | tmp;
 703     }
 704     RETURN();
 705 }
 706
 707 void op_dsllv (void)
 708 {
 709     T0 = T1 << (T0 & 0x3F);
 710     RETURN();
 711 }
 712
 713 void op_dsrav (void)
 714 {
 715     T0 = (int64_t)T1 >> (T0 & 0x3F);
 716     RETURN();
 717 }
 718
 719 void op_dsrlv (void)
 720 {
 721     T0 = T1 >> (T0 & 0x3F);
 722     RETURN();
 723 }
 724
 725 void op_drotrv (void)
 726 {
 727     target_ulong tmp;
 728
 729     T0 &= 0x3F;
 730     if (T0) {
 731        tmp = T1 << (0x40 - T0);
 732        T0 = (T1 >> T0) | tmp;
 733     } else
 734        T0 = T1;
 735     RETURN();
 736 }
 737 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 738
 739 void op_dclo (void)
 740 {
 741     int n;
 742
 743     if (T0 == ~((target_ulong)0)) {
 744         T0 = 64;
 745     } else {
 746         for (n = 0; n < 64; n++) {
 747             if (!(T0 & (1ULL << 63)))
 748                 break;
 749             T0 = T0 << 1;
 750         }
 751         T0 = n;
 752     }
 753     RETURN();
 754 }
 755
 756 void op_dclz (void)
 757 {
 758     int n;
 759
 760     if (T0 == 0) {
 761         T0 = 64;
 762     } else {
 763         for (n = 0; n < 64; n++) {
 764             if (T0 & (1ULL << 63))
 765                 break;
 766             T0 = T0 << 1;
 767         }
 768         T0 = n;
 769     }
 770     RETURN();
 771 }
 772 #endif
 773
 774 /* 64 bits arithmetic */
 775 #if TARGET_LONG_BITS > HOST_LONG_BITS
 776 void op_mult (void)
 777 {
 778     CALL_FROM_TB0(do_mult);
 779     RETURN();
 780 }
 781
 782 void op_multu (void)
 783 {
 784     CALL_FROM_TB0(do_multu);
 785     RETURN();
 786 }
 787
 788 void op_madd (void)
 789 {
 790     CALL_FROM_TB0(do_madd);
 791     RETURN();
 792 }
 793
 794 void op_maddu (void)
 795 {
 796     CALL_FROM_TB0(do_maddu);
 797     RETURN();
 798 }
 799
 800 void op_msub (void)
 801 {
 802     CALL_FROM_TB0(do_msub);
 803     RETURN();
 804 }
 805
 806 void op_msubu (void)
 807 {
 808     CALL_FROM_TB0(do_msubu);
 809     RETURN();
 810 }
 811
 812 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
 813
 814 static inline uint64_t get_HILO (void)
 815 {
 816     return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
 817 }
 818
 819 static inline void set_HILO (uint64_t HILO)
 820 {
 821     env->LO = (int32_t)(HILO & 0xFFFFFFFF);
 822     env->HI = (int32_t)(HILO >> 32);
 823 }
 824
 825 void op_mult (void)
 826 {
 827     set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 828     RETURN();
 829 }
 830
 831 void op_multu (void)
 832 {
 833     set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 834     RETURN();
 835 }
 836
 837 void op_madd (void)
 838 {
 839     int64_t tmp;
 840
 841     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 842     set_HILO((int64_t)get_HILO() + tmp);
 843     RETURN();
 844 }
 845
 846 void op_maddu (void)
 847 {
 848     uint64_t tmp;
 849
 850     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 851     set_HILO(get_HILO() + tmp);
 852     RETURN();
 853 }
 854
 855 void op_msub (void)
 856 {
 857     int64_t tmp;
 858
 859     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 860     set_HILO((int64_t)get_HILO() - tmp);
 861     RETURN();
 862 }
 863
 864 void op_msubu (void)
 865 {
 866     uint64_t tmp;
 867
 868     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 869     set_HILO(get_HILO() - tmp);
 870     RETURN();
 871 }
 872 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 873
 874 #ifdef TARGET_MIPS64
 875 void op_dmult (void)
 876 {
 877     CALL_FROM_TB4(muls64, &(env->HI), &(env->LO), T0, T1);
 878     RETURN();
 879 }
 880
 881 void op_dmultu (void)
 882 {
 883     CALL_FROM_TB4(mulu64, &(env->HI), &(env->LO), T0, T1);
 884     RETURN();
 885 }
 886 #endif
 887
 888 /* Conditional moves */
 889 void op_movn (void)
 890 {
 891     if (T1 != 0)
 892         env->gpr[PARAM1] = T0;
 893     RETURN();
 894 }
 895
 896 void op_movz (void)
 897 {
 898     if (T1 == 0)
 899         env->gpr[PARAM1] = T0;
 900     RETURN();
 901 }
 902
 903 void op_movf (void)
 904 {
 905     if (!(env->fcr31 & PARAM1))
 906         T0 = T1;
 907     RETURN();
 908 }
 909
 910 void op_movt (void)
 911 {
 912     if (env->fcr31 & PARAM1)
 913         T0 = T1;
 914     RETURN();
 915 }
 916
 917 /* Tests */
 918 #define OP_COND(name, cond) \
 919 void glue(op_, name) (void) \
 920 {                           \
 921     if (cond) {             \
 922         T0 = 1;             \
 923     } else {                \
 924         T0 = 0;             \
 925     }                       \
 926     RETURN();               \
 927 }
 928
 929 OP_COND(eq, T0 == T1);
 930 OP_COND(ne, T0 != T1);
 931 OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
 932 OP_COND(geu, T0 >= T1);
 933 OP_COND(lt, (int32_t)T0 < (int32_t)T1);
 934 OP_COND(ltu, T0 < T1);
 935 OP_COND(gez, (int32_t)T0 >= 0);
 936 OP_COND(gtz, (int32_t)T0 > 0);
 937 OP_COND(lez, (int32_t)T0 <= 0);
 938 OP_COND(ltz, (int32_t)T0 < 0);
 939
 940 /* Branches */
 941 void OPPROTO op_goto_tb0(void)
 942 {
 943     GOTO_TB(op_goto_tb0, PARAM1, 0);
 944     RETURN();
 945 }
 946
 947 void OPPROTO op_goto_tb1(void)
 948 {
 949     GOTO_TB(op_goto_tb1, PARAM1, 1);
 950     RETURN();
 951 }
 952
 953 /* Branch to register */
 954 void op_save_breg_target (void)
 955 {
 956     env->btarget = T2;
 957     RETURN();
 958 }
 959
 960 void op_restore_breg_target (void)
 961 {
 962     T2 = env->btarget;
 963     RETURN();
 964 }
 965
 966 void op_breg (void)
 967 {
 968     env->PC = T2;
 969     RETURN();
 970 }
 971
 972 void op_save_btarget (void)
 973 {
 974     env->btarget = PARAM1;
 975     RETURN();
 976 }
 977
 978 /* Conditional branch */
 979 void op_set_bcond (void)
 980 {
 981     T2 = T0;
 982     RETURN();
 983 }
 984
 985 void op_save_bcond (void)
 986 {
 987     env->bcond = T2;
 988     RETURN();
 989 }
 990
 991 void op_restore_bcond (void)
 992 {
 993     T2 = env->bcond;
 994     RETURN();
 995 }
 996
 997 void op_jnz_T2 (void)
 998 {
 999     if (T2)
1000         GOTO_LABEL_PARAM(1);
1001     RETURN();
1002 }
1003
1004 /* CP0 functions */
1005 void op_mfc0_index (void)
1006 {
1007     T0 = env->CP0_Index;
1008     RETURN();
1009 }
1010
1011 void op_mfc0_random (void)
1012 {
1013     CALL_FROM_TB0(do_mfc0_random);
1014     RETURN();
1015 }
1016
1017 void op_mfc0_entrylo0 (void)
1018 {
1019     T0 = (int32_t)env->CP0_EntryLo0;
1020     RETURN();
1021 }
1022
1023 void op_mfc0_entrylo1 (void)
1024 {
1025     T0 = (int32_t)env->CP0_EntryLo1;
1026     RETURN();
1027 }
1028
1029 void op_mfc0_context (void)
1030 {
1031     T0 = (int32_t)env->CP0_Context;
1032     RETURN();
1033 }
1034
1035 void op_mfc0_pagemask (void)
1036 {
1037     T0 = env->CP0_PageMask;
1038     RETURN();
1039 }
1040
1041 void op_mfc0_pagegrain (void)
1042 {
1043     T0 = env->CP0_PageGrain;
1044     RETURN();
1045 }
1046
1047 void op_mfc0_wired (void)
1048 {
1049     T0 = env->CP0_Wired;
1050     RETURN();
1051 }
1052
1053 void op_mfc0_hwrena (void)
1054 {
1055     T0 = env->CP0_HWREna;
1056     RETURN();
1057 }
1058
1059 void op_mfc0_badvaddr (void)
1060 {
1061     T0 = (int32_t)env->CP0_BadVAddr;
1062     RETURN();
1063 }
1064
1065 void op_mfc0_count (void)
1066 {
1067     CALL_FROM_TB0(do_mfc0_count);
1068     RETURN();
1069 }
1070
1071 void op_mfc0_entryhi (void)
1072 {
1073     T0 = (int32_t)env->CP0_EntryHi;
1074     RETURN();
1075 }
1076
1077 void op_mfc0_compare (void)
1078 {
1079     T0 = env->CP0_Compare;
1080     RETURN();
1081 }
1082
1083 void op_mfc0_status (void)
1084 {
1085     T0 = env->CP0_Status;
1086     RETURN();
1087 }
1088
1089 void op_mfc0_intctl (void)
1090 {
1091     T0 = env->CP0_IntCtl;
1092     RETURN();
1093 }
1094
1095 void op_mfc0_srsctl (void)
1096 {
1097     T0 = env->CP0_SRSCtl;
1098     RETURN();
1099 }
1100
1101 void op_mfc0_srsmap (void)
1102 {
1103     T0 = env->CP0_SRSMap;
1104     RETURN();
1105 }
1106
1107 void op_mfc0_cause (void)
1108 {
1109     T0 = env->CP0_Cause;
1110     RETURN();
1111 }
1112
1113 void op_mfc0_epc (void)
1114 {
1115     T0 = (int32_t)env->CP0_EPC;
1116     RETURN();
1117 }
1118
1119 void op_mfc0_prid (void)
1120 {
1121     T0 = env->CP0_PRid;
1122     RETURN();
1123 }
1124
1125 void op_mfc0_ebase (void)
1126 {
1127     T0 = env->CP0_EBase;
1128     RETURN();
1129 }
1130
1131 void op_mfc0_config0 (void)
1132 {
1133     T0 = env->CP0_Config0;
1134     RETURN();
1135 }
1136
1137 void op_mfc0_config1 (void)
1138 {
1139     T0 = env->CP0_Config1;
1140     RETURN();
1141 }
1142
1143 void op_mfc0_config2 (void)
1144 {
1145     T0 = env->CP0_Config2;
1146     RETURN();
1147 }
1148
1149 void op_mfc0_config3 (void)
1150 {
1151     T0 = env->CP0_Config3;
1152     RETURN();
1153 }
1154
1155 void op_mfc0_config6 (void)
1156 {
1157     T0 = env->CP0_Config6;
1158     RETURN();
1159 }
1160
1161 void op_mfc0_config7 (void)
1162 {
1163     T0 = env->CP0_Config7;
1164     RETURN();
1165 }
1166
1167 void op_mfc0_lladdr (void)
1168 {
1169     T0 = (int32_t)env->CP0_LLAddr >> 4;
1170     RETURN();
1171 }
1172
1173 void op_mfc0_watchlo0 (void)
1174 {
1175     T0 = (int32_t)env->CP0_WatchLo;
1176     RETURN();
1177 }
1178
1179 void op_mfc0_watchhi0 (void)
1180 {
1181     T0 = env->CP0_WatchHi;
1182     RETURN();
1183 }
1184
1185 void op_mfc0_xcontext (void)
1186 {
1187     T0 = (int32_t)env->CP0_XContext;
1188     RETURN();
1189 }
1190
1191 void op_mfc0_framemask (void)
1192 {
1193     T0 = env->CP0_Framemask;
1194     RETURN();
1195 }
1196
1197 void op_mfc0_debug (void)
1198 {
1199     T0 = env->CP0_Debug;
1200     if (env->hflags & MIPS_HFLAG_DM)
1201         T0 |= 1 << CP0DB_DM;
1202     RETURN();
1203 }
1204
1205 void op_mfc0_depc (void)
1206 {
1207     T0 = (int32_t)env->CP0_DEPC;
1208     RETURN();
1209 }
1210
1211 void op_mfc0_performance0 (void)
1212 {
1213     T0 = env->CP0_Performance0;
1214     RETURN();
1215 }
1216
1217 void op_mfc0_taglo (void)
1218 {
1219     T0 = env->CP0_TagLo;
1220     RETURN();
1221 }
1222
1223 void op_mfc0_datalo (void)
1224 {
1225     T0 = env->CP0_DataLo;
1226     RETURN();
1227 }
1228
1229 void op_mfc0_taghi (void)
1230 {
1231     T0 = env->CP0_TagHi;
1232     RETURN();
1233 }
1234
1235 void op_mfc0_datahi (void)
1236 {
1237     T0 = env->CP0_DataHi;
1238     RETURN();
1239 }
1240
1241 void op_mfc0_errorepc (void)
1242 {
1243     T0 = (int32_t)env->CP0_ErrorEPC;
1244     RETURN();
1245 }
1246
1247 void op_mfc0_desave (void)
1248 {
1249     T0 = env->CP0_DESAVE;
1250     RETURN();
1251 }
1252
1253 void op_mtc0_index (void)
1254 {
1255     env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 % env->nb_tlb);
1256     RETURN();
1257 }
1258
1259 void op_mtc0_entrylo0 (void)
1260 {
1261     /* Large physaddr not implemented */
1262     /* 1k pages not implemented */
1263     env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1264     RETURN();
1265 }
1266
1267 void op_mtc0_entrylo1 (void)
1268 {
1269     /* Large physaddr not implemented */
1270     /* 1k pages not implemented */
1271     env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1272     RETURN();
1273 }
1274
1275 void op_mtc0_context (void)
1276 {
1277     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1278     RETURN();
1279 }
1280
1281 void op_mtc0_pagemask (void)
1282 {
1283     /* 1k pages not implemented */
1284     env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1285     RETURN();
1286 }
1287
1288 void op_mtc0_pagegrain (void)
1289 {
1290     /* SmartMIPS not implemented */
1291     /* Large physaddr not implemented */
1292     /* 1k pages not implemented */
1293     env->CP0_PageGrain = 0;
1294     RETURN();
1295 }
1296
1297 void op_mtc0_wired (void)
1298 {
1299     env->CP0_Wired = T0 % env->nb_tlb;
1300     RETURN();
1301 }
1302
1303 void op_mtc0_hwrena (void)
1304 {
1305     env->CP0_HWREna = T0 & 0x0000000F;
1306     RETURN();
1307 }
1308
1309 void op_mtc0_count (void)
1310 {
1311     CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1312     RETURN();
1313 }
1314
1315 void op_mtc0_entryhi (void)
1316 {
1317     target_ulong old, val;
1318
1319     /* 1k pages not implemented */
1320     val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1321 #ifdef TARGET_MIPS64
1322     val = T0 & 0xC00000FFFFFFFFFFULL;
1323 #endif
1324     old = env->CP0_EntryHi;
1325     env->CP0_EntryHi = val;
1326     /* If the ASID changes, flush qemu's TLB.  */
1327     if ((old & 0xFF) != (val & 0xFF))
1328         CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1329     RETURN();
1330 }
1331
1332 void op_mtc0_compare (void)
1333 {
1334     CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1335     RETURN();
1336 }
1337
1338 void op_mtc0_status (void)
1339 {
1340     uint32_t val, old;
1341     uint32_t mask = env->Status_rw_bitmask;
1342
1343     /* No reverse endianness, no MDMX/DSP, no 64bit ops
1344        implemented. */
1345     val = T0 & mask;
1346     old = env->CP0_Status;
1347     if (!(val & (1 << CP0St_EXL)) &&
1348         !(val & (1 << CP0St_ERL)) &&
1349         !(env->hflags & MIPS_HFLAG_DM) &&
1350         (val & (1 << CP0St_UM)))
1351         env->hflags |= MIPS_HFLAG_UM;
1352     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1353     if (loglevel & CPU_LOG_EXEC)
1354         CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1355     CALL_FROM_TB1(cpu_mips_update_irq, env);
1356     RETURN();
1357 }
1358
1359 void op_mtc0_intctl (void)
1360 {
1361     /* vectored interrupts not implemented, timer on int 7,
1362        no performance counters. */
1363     env->CP0_IntCtl |= T0 & 0x000002e0;
1364     RETURN();
1365 }
1366
1367 void op_mtc0_srsctl (void)
1368 {
1369     /* shadow registers not implemented */
1370     env->CP0_SRSCtl = 0;
1371     RETURN();
1372 }
1373
1374 void op_mtc0_srsmap (void)
1375 {
1376     /* shadow registers not implemented */
1377     env->CP0_SRSMap = 0;
1378     RETURN();
1379 }
1380
1381 void op_mtc0_cause (void)
1382 {
1383     uint32_t mask = 0x00C00300;
1384
1385     if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1386         mask |= 1 << CP0Ca_DC;
1387
1388     env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
1389
1390     /* Handle the software interrupt as an hardware one, as they
1391        are very similar */
1392     if (T0 & CP0Ca_IP_mask) {
1393         CALL_FROM_TB1(cpu_mips_update_irq, env);
1394     }
1395     RETURN();
1396 }
1397
1398 void op_mtc0_epc (void)
1399 {
1400     env->CP0_EPC = T0;
1401     RETURN();
1402 }
1403
1404 void op_mtc0_ebase (void)
1405 {
1406     /* vectored interrupts not implemented */
1407     /* Multi-CPU not implemented */
1408     env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1409     RETURN();
1410 }
1411
1412 void op_mtc0_config0 (void)
1413 {
1414     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000001);
1415     RETURN();
1416 }
1417
1418 void op_mtc0_config2 (void)
1419 {
1420     /* tertiary/secondary caches not implemented */
1421     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1422     RETURN();
1423 }
1424
1425 void op_mtc0_watchlo0 (void)
1426 {
1427     /* Watch exceptions for instructions, data loads, data stores
1428        not implemented. */
1429     env->CP0_WatchLo = (T0 & ~0x7);
1430     RETURN();
1431 }
1432
1433 void op_mtc0_watchhi0 (void)
1434 {
1435     env->CP0_WatchHi = (T0 & 0x40FF0FF8);
1436     env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7);
1437     RETURN();
1438 }
1439
1440 void op_mtc0_framemask (void)
1441 {
1442     env->CP0_Framemask = T0; /* XXX */
1443     RETURN();
1444 }
1445
1446 void op_mtc0_debug (void)
1447 {
1448     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1449     if (T0 & (1 << CP0DB_DM))
1450         env->hflags |= MIPS_HFLAG_DM;
1451     else
1452         env->hflags &= ~MIPS_HFLAG_DM;
1453     RETURN();
1454 }
1455
1456 void op_mtc0_depc (void)
1457 {
1458     env->CP0_DEPC = T0;
1459     RETURN();
1460 }
1461
1462 void op_mtc0_performance0 (void)
1463 {
1464     env->CP0_Performance0 = T0; /* XXX */
1465     RETURN();
1466 }
1467
1468 void op_mtc0_taglo (void)
1469 {
1470     env->CP0_TagLo = T0 & 0xFFFFFCF6;
1471     RETURN();
1472 }
1473
1474 void op_mtc0_datalo (void)
1475 {
1476     env->CP0_DataLo = T0; /* XXX */
1477     RETURN();
1478 }
1479
1480 void op_mtc0_taghi (void)
1481 {
1482     env->CP0_TagHi = T0; /* XXX */
1483     RETURN();
1484 }
1485
1486 void op_mtc0_datahi (void)
1487 {
1488     env->CP0_DataHi = T0; /* XXX */
1489     RETURN();
1490 }
1491
1492 void op_mtc0_errorepc (void)
1493 {
1494     env->CP0_ErrorEPC = T0;
1495     RETURN();
1496 }
1497
1498 void op_mtc0_desave (void)
1499 {
1500     env->CP0_DESAVE = T0;
1501     RETURN();
1502 }
1503
1504 #ifdef TARGET_MIPS64
1505 void op_mtc0_xcontext (void)
1506 {
1507     env->CP0_XContext = (env->CP0_XContext & 0x1ffffffffULL) | (T0 & ~0x1ffffffffULL);
1508     RETURN();
1509 }
1510
1511 void op_dmfc0_entrylo0 (void)
1512 {
1513     T0 = env->CP0_EntryLo0;
1514     RETURN();
1515 }
1516
1517 void op_dmfc0_entrylo1 (void)
1518 {
1519     T0 = env->CP0_EntryLo1;
1520     RETURN();
1521 }
1522
1523 void op_dmfc0_context (void)
1524 {
1525     T0 = env->CP0_Context;
1526     RETURN();
1527 }
1528
1529 void op_dmfc0_badvaddr (void)
1530 {
1531     T0 = env->CP0_BadVAddr;
1532     RETURN();
1533 }
1534
1535 void op_dmfc0_entryhi (void)
1536 {
1537     T0 = env->CP0_EntryHi;
1538     RETURN();
1539 }
1540
1541 void op_dmfc0_epc (void)
1542 {
1543     T0 = env->CP0_EPC;
1544     RETURN();
1545 }
1546
1547 void op_dmfc0_lladdr (void)
1548 {
1549     T0 = env->CP0_LLAddr >> 4;
1550     RETURN();
1551 }
1552
1553 void op_dmfc0_watchlo0 (void)
1554 {
1555     T0 = env->CP0_WatchLo;
1556     RETURN();
1557 }
1558
1559 void op_dmfc0_xcontext (void)
1560 {
1561     T0 = env->CP0_XContext;
1562     RETURN();
1563 }
1564
1565 void op_dmfc0_depc (void)
1566 {
1567     T0 = env->CP0_DEPC;
1568     RETURN();
1569 }
1570
1571 void op_dmfc0_errorepc (void)
1572 {
1573     T0 = env->CP0_ErrorEPC;
1574     RETURN();
1575 }
1576 #endif /* TARGET_MIPS64 */
1577
1578 /* CP1 functions */
1579 #if 0
1580 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1581 #else
1582 # define DEBUG_FPU_STATE() do { } while(0)
1583 #endif
1584
1585 void op_cp0_enabled(void)
1586 {
1587     if (!(env->CP0_Status & (1 << CP0St_CU0)) &&
1588         (env->hflags & MIPS_HFLAG_UM)) {
1589         CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
1590     }
1591     RETURN();
1592 }
1593
1594 void op_cp1_enabled(void)
1595 {
1596     if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1597         CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
1598     }
1599     RETURN();
1600 }
1601
1602 /* convert MIPS rounding mode in FCR31 to IEEE library */
1603 unsigned int ieee_rm[] = {
1604     float_round_nearest_even,
1605     float_round_to_zero,
1606     float_round_up,
1607     float_round_down
1608 };
1609
1610 #define RESTORE_ROUNDING_MODE \
1611     set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1612
1613 inline char ieee_ex_to_mips(char xcpt)
1614 {
1615     return (xcpt & float_flag_inexact) >> 5 |
1616            (xcpt & float_flag_underflow) >> 3 |
1617            (xcpt & float_flag_overflow) >> 1 |
1618            (xcpt & float_flag_divbyzero) << 1 |
1619            (xcpt & float_flag_invalid) << 4;
1620 }
1621
1622 inline char mips_ex_to_ieee(char xcpt)
1623 {
1624     return (xcpt & FP_INEXACT) << 5 |
1625            (xcpt & FP_UNDERFLOW) << 3 |
1626            (xcpt & FP_OVERFLOW) << 1 |
1627            (xcpt & FP_DIV0) >> 1 |
1628            (xcpt & FP_INVALID) >> 4;
1629 }
1630
1631 inline void update_fcr31(void)
1632 {
1633     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fp_status));
1634
1635     SET_FP_CAUSE(env->fcr31, tmp);
1636     if (GET_FP_ENABLE(env->fcr31) & tmp)
1637         CALL_FROM_TB1(do_raise_exception, EXCP_FPE);
1638     else
1639         UPDATE_FP_FLAGS(env->fcr31, tmp);
1640 }
1641
1642
1643 void op_cfc1 (void)
1644 {
1645     switch (T1) {
1646     case 0:
1647         T0 = (int32_t)env->fcr0;
1648         break;
1649     case 25:
1650         T0 = ((env->fcr31 >> 24) & 0xfe) | ((env->fcr31 >> 23) & 0x1);
1651         break;
1652     case 26:
1653         T0 = env->fcr31 & 0x0003f07c;
1654         break;
1655     case 28:
1656         T0 = (env->fcr31 & 0x00000f83) | ((env->fcr31 >> 22) & 0x4);
1657         break;
1658     default:
1659         T0 = (int32_t)env->fcr31;
1660         break;
1661     }
1662     DEBUG_FPU_STATE();
1663     RETURN();
1664 }
1665
1666 void op_ctc1 (void)
1667 {
1668     switch(T1) {
1669     case 25:
1670         if (T0 & 0xffffff00)
1671             goto leave;
1672         env->fcr31 = (env->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
1673                      ((T0 & 0x1) << 23);
1674         break;
1675     case 26:
1676         if (T0 & 0x007c0000)
1677             goto leave;
1678         env->fcr31 = (env->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
1679         break;
1680     case 28:
1681         if (T0 & 0x007c0000)
1682             goto leave;
1683         env->fcr31 = (env->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
1684                      ((T0 & 0x4) << 22);
1685         break;
1686     case 31:
1687         if (T0 & 0x007c0000)
1688             goto leave;
1689         env->fcr31 = T0;
1690         break;
1691     default:
1692         goto leave;
1693     }
1694     /* set rounding mode */
1695     RESTORE_ROUNDING_MODE;
1696     set_float_exception_flags(0, &env->fp_status);
1697     if ((GET_FP_ENABLE(env->fcr31) | 0x20) & GET_FP_CAUSE(env->fcr31))
1698         CALL_FROM_TB1(do_raise_exception, EXCP_FPE);
1699  leave:
1700     DEBUG_FPU_STATE();
1701     RETURN();
1702 }
1703
1704 void op_mfc1 (void)
1705 {
1706     T0 = WT0;
1707     DEBUG_FPU_STATE();
1708     RETURN();
1709 }
1710
1711 void op_mtc1 (void)
1712 {
1713     WT0 = T0;
1714     DEBUG_FPU_STATE();
1715     RETURN();
1716 }
1717
1718 void op_dmfc1 (void)
1719 {
1720     T0 = DT0;
1721     DEBUG_FPU_STATE();
1722     RETURN();
1723 }
1724
1725 void op_dmtc1 (void)
1726 {
1727     DT0 = T0;
1728     DEBUG_FPU_STATE();
1729     RETURN();
1730 }
1731
1732 void op_mfhc1 (void)
1733 {
1734     T0 = WTH0;
1735     DEBUG_FPU_STATE();
1736     RETURN();
1737 }
1738
1739 void op_mthc1 (void)
1740 {
1741     WTH0 = T0;
1742     DEBUG_FPU_STATE();
1743     RETURN();
1744 }
1745
1746 /* Float support.
1747    Single precition routines have a "s" suffix, double precision a
1748    "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
1749    paired single lowwer "pl", paired single upper "pu".  */
1750
1751 #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1752
1753 FLOAT_OP(cvtd, s)
1754 {
1755     set_float_exception_flags(0, &env->fp_status);
1756     FDT2 = float32_to_float64(FST0, &env->fp_status);
1757     update_fcr31();
1758     DEBUG_FPU_STATE();
1759     RETURN();
1760 }
1761 FLOAT_OP(cvtd, w)
1762 {
1763     set_float_exception_flags(0, &env->fp_status);
1764     FDT2 = int32_to_float64(WT0, &env->fp_status);
1765     update_fcr31();
1766     DEBUG_FPU_STATE();
1767     RETURN();
1768 }
1769 FLOAT_OP(cvtd, l)
1770 {
1771     set_float_exception_flags(0, &env->fp_status);
1772     FDT2 = int64_to_float64(DT0, &env->fp_status);
1773     update_fcr31();
1774     DEBUG_FPU_STATE();
1775     RETURN();
1776 }
1777 FLOAT_OP(cvtl, d)
1778 {
1779     set_float_exception_flags(0, &env->fp_status);
1780     DT2 = float64_to_int64(FDT0, &env->fp_status);
1781     update_fcr31();
1782     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1783         DT2 = 0x7fffffffffffffffULL;
1784     DEBUG_FPU_STATE();
1785     RETURN();
1786 }
1787 FLOAT_OP(cvtl, s)
1788 {
1789     set_float_exception_flags(0, &env->fp_status);
1790     DT2 = float32_to_int64(FST0, &env->fp_status);
1791     update_fcr31();
1792     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1793         DT2 = 0x7fffffffffffffffULL;
1794     DEBUG_FPU_STATE();
1795     RETURN();
1796 }
1797 FLOAT_OP(cvtps, s)
1798 {
1799     WT2 = WT0;
1800     WTH2 = WT1;
1801     DEBUG_FPU_STATE();
1802     RETURN();
1803 }
1804 FLOAT_OP(cvtps, pw)
1805 {
1806     set_float_exception_flags(0, &env->fp_status);
1807     FST2 = int32_to_float32(WT0, &env->fp_status);
1808     FSTH2 = int32_to_float32(WTH0, &env->fp_status);
1809     update_fcr31();
1810     DEBUG_FPU_STATE();
1811     RETURN();
1812 }
1813 FLOAT_OP(cvtpw, ps)
1814 {
1815     set_float_exception_flags(0, &env->fp_status);
1816     WT2 = float32_to_int32(FST0, &env->fp_status);
1817     WTH2 = float32_to_int32(FSTH0, &env->fp_status);
1818     update_fcr31();
1819     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1820         WT2 = 0x7fffffff;
1821     DEBUG_FPU_STATE();
1822     RETURN();
1823 }
1824 FLOAT_OP(cvts, d)
1825 {
1826     set_float_exception_flags(0, &env->fp_status);
1827     FST2 = float64_to_float32(FDT0, &env->fp_status);
1828     update_fcr31();
1829     DEBUG_FPU_STATE();
1830     RETURN();
1831 }
1832 FLOAT_OP(cvts, w)
1833 {
1834     set_float_exception_flags(0, &env->fp_status);
1835     FST2 = int32_to_float32(WT0, &env->fp_status);
1836     update_fcr31();
1837     DEBUG_FPU_STATE();
1838     RETURN();
1839 }
1840 FLOAT_OP(cvts, l)
1841 {
1842     set_float_exception_flags(0, &env->fp_status);
1843     FST2 = int64_to_float32(DT0, &env->fp_status);
1844     update_fcr31();
1845     DEBUG_FPU_STATE();
1846     RETURN();
1847 }
1848 FLOAT_OP(cvts, pl)
1849 {
1850     set_float_exception_flags(0, &env->fp_status);
1851     WT2 = WT0;
1852     update_fcr31();
1853     DEBUG_FPU_STATE();
1854     RETURN();
1855 }
1856 FLOAT_OP(cvts, pu)
1857 {
1858     set_float_exception_flags(0, &env->fp_status);
1859     WT2 = WTH0;
1860     update_fcr31();
1861     DEBUG_FPU_STATE();
1862     RETURN();
1863 }
1864 FLOAT_OP(cvtw, s)
1865 {
1866     set_float_exception_flags(0, &env->fp_status);
1867     WT2 = float32_to_int32(FST0, &env->fp_status);
1868     update_fcr31();
1869     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1870         WT2 = 0x7fffffff;
1871     DEBUG_FPU_STATE();
1872     RETURN();
1873 }
1874 FLOAT_OP(cvtw, d)
1875 {
1876     set_float_exception_flags(0, &env->fp_status);
1877     WT2 = float64_to_int32(FDT0, &env->fp_status);
1878     update_fcr31();
1879     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1880         WT2 = 0x7fffffff;
1881     DEBUG_FPU_STATE();
1882     RETURN();
1883 }
1884
1885 FLOAT_OP(pll, ps)
1886 {
1887     DT2 = ((uint64_t)WT0 << 32) | WT1;
1888     DEBUG_FPU_STATE();
1889     RETURN();
1890 }
1891 FLOAT_OP(plu, ps)
1892 {
1893     DT2 = ((uint64_t)WT0 << 32) | WTH1;
1894     DEBUG_FPU_STATE();
1895     RETURN();
1896 }
1897 FLOAT_OP(pul, ps)
1898 {
1899     DT2 = ((uint64_t)WTH0 << 32) | WT1;
1900     DEBUG_FPU_STATE();
1901     RETURN();
1902 }
1903 FLOAT_OP(puu, ps)
1904 {
1905     DT2 = ((uint64_t)WTH0 << 32) | WTH1;
1906     DEBUG_FPU_STATE();
1907     RETURN();
1908 }
1909
1910 FLOAT_OP(roundl, d)
1911 {
1912     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1913     DT2 = float64_round_to_int(FDT0, &env->fp_status);
1914     RESTORE_ROUNDING_MODE;
1915     update_fcr31();
1916     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1917         DT2 = 0x7fffffffffffffffULL;
1918     DEBUG_FPU_STATE();
1919     RETURN();
1920 }
1921 FLOAT_OP(roundl, s)
1922 {
1923     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1924     DT2 = float32_round_to_int(FST0, &env->fp_status);
1925     RESTORE_ROUNDING_MODE;
1926     update_fcr31();
1927     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1928         DT2 = 0x7fffffffffffffffULL;
1929     DEBUG_FPU_STATE();
1930     RETURN();
1931 }
1932 FLOAT_OP(roundw, d)
1933 {
1934     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1935     WT2 = float64_round_to_int(FDT0, &env->fp_status);
1936     RESTORE_ROUNDING_MODE;
1937     update_fcr31();
1938     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1939         WT2 = 0x7fffffff;
1940     DEBUG_FPU_STATE();
1941     RETURN();
1942 }
1943 FLOAT_OP(roundw, s)
1944 {
1945     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1946     WT2 = float32_round_to_int(FST0, &env->fp_status);
1947     RESTORE_ROUNDING_MODE;
1948     update_fcr31();
1949     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1950         WT2 = 0x7fffffff;
1951     DEBUG_FPU_STATE();
1952     RETURN();
1953 }
1954
1955 FLOAT_OP(truncl, d)
1956 {
1957     DT2 = float64_to_int64_round_to_zero(FDT0, &env->fp_status);
1958     update_fcr31();
1959     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1960         DT2 = 0x7fffffffffffffffULL;
1961     DEBUG_FPU_STATE();
1962     RETURN();
1963 }
1964 FLOAT_OP(truncl, s)
1965 {
1966     DT2 = float32_to_int64_round_to_zero(FST0, &env->fp_status);
1967     update_fcr31();
1968     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1969         DT2 = 0x7fffffffffffffffULL;
1970     DEBUG_FPU_STATE();
1971     RETURN();
1972 }
1973 FLOAT_OP(truncw, d)
1974 {
1975     WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
1976     update_fcr31();
1977     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1978         WT2 = 0x7fffffff;
1979     DEBUG_FPU_STATE();
1980     RETURN();
1981 }
1982 FLOAT_OP(truncw, s)
1983 {
1984     WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
1985     update_fcr31();
1986     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1987         WT2 = 0x7fffffff;
1988     DEBUG_FPU_STATE();
1989     RETURN();
1990 }
1991
1992 FLOAT_OP(ceill, d)
1993 {
1994     set_float_rounding_mode(float_round_up, &env->fp_status);
1995     DT2 = float64_round_to_int(FDT0, &env->fp_status);
1996     RESTORE_ROUNDING_MODE;
1997     update_fcr31();
1998     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
1999         DT2 = 0x7fffffffffffffffULL;
2000     DEBUG_FPU_STATE();
2001     RETURN();
2002 }
2003 FLOAT_OP(ceill, s)
2004 {
2005     set_float_rounding_mode(float_round_up, &env->fp_status);
2006     DT2 = float32_round_to_int(FST0, &env->fp_status);
2007     RESTORE_ROUNDING_MODE;
2008     update_fcr31();
2009     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
2010         DT2 = 0x7fffffffffffffffULL;
2011     DEBUG_FPU_STATE();
2012     RETURN();
2013 }
2014 FLOAT_OP(ceilw, d)
2015 {
2016     set_float_rounding_mode(float_round_up, &env->fp_status);
2017     WT2 = float64_round_to_int(FDT0, &env->fp_status);
2018     RESTORE_ROUNDING_MODE;
2019     update_fcr31();
2020     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
2021         WT2 = 0x7fffffff;
2022     DEBUG_FPU_STATE();
2023     RETURN();
2024 }
2025 FLOAT_OP(ceilw, s)
2026 {
2027     set_float_rounding_mode(float_round_up, &env->fp_status);
2028     WT2 = float32_round_to_int(FST0, &env->fp_status);
2029     RESTORE_ROUNDING_MODE;
2030     update_fcr31();
2031     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
2032         WT2 = 0x7fffffff;
2033     DEBUG_FPU_STATE();
2034     RETURN();
2035 }
2036
2037 FLOAT_OP(floorl, d)
2038 {
2039     set_float_rounding_mode(float_round_down, &env->fp_status);
2040     DT2 = float64_round_to_int(FDT0, &env->fp_status);
2041     RESTORE_ROUNDING_MODE;
2042     update_fcr31();
2043     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
2044         DT2 = 0x7fffffffffffffffULL;
2045     DEBUG_FPU_STATE();
2046     RETURN();
2047 }
2048 FLOAT_OP(floorl, s)
2049 {
2050     set_float_rounding_mode(float_round_down, &env->fp_status);
2051     DT2 = float32_round_to_int(FST0, &env->fp_status);
2052     RESTORE_ROUNDING_MODE;
2053     update_fcr31();
2054     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
2055         DT2 = 0x7fffffffffffffffULL;
2056     DEBUG_FPU_STATE();
2057     RETURN();
2058 }
2059 FLOAT_OP(floorw, d)
2060 {
2061     set_float_rounding_mode(float_round_down, &env->fp_status);
2062     WT2 = float64_round_to_int(FDT0, &env->fp_status);
2063     RESTORE_ROUNDING_MODE;
2064     update_fcr31();
2065     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
2066         WT2 = 0x7fffffff;
2067     DEBUG_FPU_STATE();
2068     RETURN();
2069 }
2070 FLOAT_OP(floorw, s)
2071 {
2072     set_float_rounding_mode(float_round_down, &env->fp_status);
2073     WT2 = float32_round_to_int(FST0, &env->fp_status);
2074     RESTORE_ROUNDING_MODE;
2075     update_fcr31();
2076     if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID))
2077         WT2 = 0x7fffffff;
2078     DEBUG_FPU_STATE();
2079     RETURN();
2080 }
2081
2082 FLOAT_OP(movf, d)
2083 {
2084     if (!(env->fcr31 & PARAM1))
2085         DT2 = DT0;
2086     DEBUG_FPU_STATE();
2087     RETURN();
2088 }
2089 FLOAT_OP(movf, s)
2090 {
2091     if (!(env->fcr31 & PARAM1))
2092         WT2 = WT0;
2093     DEBUG_FPU_STATE();
2094     RETURN();
2095 }
2096 FLOAT_OP(movf, ps)
2097 {
2098     if (!(env->fcr31 & PARAM1)) {
2099         WT2 = WT0;
2100         WTH2 = WTH0;
2101     }
2102     DEBUG_FPU_STATE();
2103     RETURN();
2104 }
2105 FLOAT_OP(movt, d)
2106 {
2107     if (env->fcr31 & PARAM1)
2108         DT2 = DT0;
2109     DEBUG_FPU_STATE();
2110     RETURN();
2111 }
2112 FLOAT_OP(movt, s)
2113 {
2114     if (env->fcr31 & PARAM1)
2115         WT2 = WT0;
2116     DEBUG_FPU_STATE();
2117     RETURN();
2118 }
2119 FLOAT_OP(movt, ps)
2120 {
2121     if (env->fcr31 & PARAM1) {
2122         WT2 = WT0;
2123         WTH2 = WTH0;
2124     }
2125     DEBUG_FPU_STATE();
2126     RETURN();
2127 }
2128 FLOAT_OP(movz, d)
2129 {
2130     if (!T0)
2131         DT2 = DT0;
2132     DEBUG_FPU_STATE();
2133     RETURN();
2134 }
2135 FLOAT_OP(movz, s)
2136 {
2137     if (!T0)
2138         WT2 = WT0;
2139     DEBUG_FPU_STATE();
2140     RETURN();
2141 }
2142 FLOAT_OP(movz, ps)
2143 {
2144     if (!T0) {
2145         WT2 = WT0;
2146         WTH2 = WTH0;
2147     }
2148     DEBUG_FPU_STATE();
2149     RETURN();
2150 }
2151 FLOAT_OP(movn, d)
2152 {
2153     if (T0)
2154         DT2 = DT0;
2155     DEBUG_FPU_STATE();
2156     RETURN();
2157 }
2158 FLOAT_OP(movn, s)
2159 {
2160     if (T0)
2161         WT2 = WT0;
2162     DEBUG_FPU_STATE();
2163     RETURN();
2164 }
2165 FLOAT_OP(movn, ps)
2166 {
2167     if (T0) {
2168         WT2 = WT0;
2169         WTH2 = WTH0;
2170     }
2171     DEBUG_FPU_STATE();
2172     RETURN();
2173 }
2174
2175 /* binary operations */
2176 #define FLOAT_BINOP(name) \
2177 FLOAT_OP(name, d)         \
2178 {                         \
2179     set_float_exception_flags(0, &env->fp_status);            \
2180     FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status);    \
2181     update_fcr31();       \
2182     DEBUG_FPU_STATE();    \
2183     RETURN();             \
2184 }                         \
2185 FLOAT_OP(name, s)         \
2186 {                         \
2187     set_float_exception_flags(0, &env->fp_status);            \
2188     FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
2189     update_fcr31();       \
2190     DEBUG_FPU_STATE();    \
2191     RETURN();             \
2192 }                         \
2193 FLOAT_OP(name, ps)        \
2194 {                         \
2195     set_float_exception_flags(0, &env->fp_status);            \
2196     FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
2197     FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fp_status); \
2198     update_fcr31();       \
2199     DEBUG_FPU_STATE();    \
2200     RETURN();             \
2201 }
2202 FLOAT_BINOP(add)
2203 FLOAT_BINOP(sub)
2204 FLOAT_BINOP(mul)
2205 FLOAT_BINOP(div)
2206 #undef FLOAT_BINOP
2207
2208 FLOAT_OP(addr, ps)
2209 {
2210     set_float_exception_flags(0, &env->fp_status);
2211     FST2 = float32_add (FST0, FSTH0, &env->fp_status);
2212     FSTH2 = float32_add (FST1, FSTH1, &env->fp_status);
2213     update_fcr31();
2214     DEBUG_FPU_STATE();
2215     RETURN();
2216 }
2217
2218 /* ternary operations */
2219 #define FLOAT_TERNOP(name1, name2) \
2220 FLOAT_OP(name1 ## name2, d)        \
2221 {                                  \
2222     FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status);    \
2223     FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status);    \
2224     DEBUG_FPU_STATE();             \
2225     RETURN();                      \
2226 }                                  \
2227 FLOAT_OP(name1 ## name2, s)        \
2228 {                                  \
2229     FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2230     FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2231     DEBUG_FPU_STATE();             \
2232     RETURN();                      \
2233 }                                  \
2234 FLOAT_OP(name1 ## name2, ps)       \
2235 {                                  \
2236     FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2237     FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \
2238     FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2239     FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \
2240     DEBUG_FPU_STATE();             \
2241     RETURN();                      \
2242 }
2243 FLOAT_TERNOP(mul, add)
2244 FLOAT_TERNOP(mul, sub)
2245 #undef FLOAT_TERNOP
2246
2247 /* negated ternary operations */
2248 #define FLOAT_NTERNOP(name1, name2) \
2249 FLOAT_OP(n ## name1 ## name2, d)    \
2250 {                                   \
2251     FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status);    \
2252     FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status);    \
2253     FDT2 ^= 1ULL << 63;             \
2254     DEBUG_FPU_STATE();              \
2255     RETURN();                       \
2256 }                                   \
2257 FLOAT_OP(n ## name1 ## name2, s)    \
2258 {                                   \
2259     FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2260     FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2261     FST2 ^= 1 << 31;                \
2262     DEBUG_FPU_STATE();              \
2263     RETURN();                       \
2264 }                                   \
2265 FLOAT_OP(n ## name1 ## name2, ps)   \
2266 {                                   \
2267     FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2268     FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \
2269     FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2270     FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \
2271     FST2 ^= 1 << 31;                \
2272     FSTH2 ^= 1 << 31;               \
2273     DEBUG_FPU_STATE();              \
2274     RETURN();                       \
2275 }
2276 FLOAT_NTERNOP(mul, add)
2277 FLOAT_NTERNOP(mul, sub)
2278 #undef FLOAT_NTERNOP
2279
2280 /* unary operations, modifying fp status  */
2281 #define FLOAT_UNOP(name)  \
2282 FLOAT_OP(name, d)         \
2283 {                         \
2284     FDT2 = float64_ ## name(FDT0, &env->fp_status);   \
2285     DEBUG_FPU_STATE();    \
2286     RETURN();                      \
2287 }                         \
2288 FLOAT_OP(name, s)         \
2289 {                         \
2290     FST2 = float32_ ## name(FST0, &env->fp_status);   \
2291     DEBUG_FPU_STATE();    \
2292     RETURN();                      \
2293 }                         \
2294 FLOAT_OP(name, ps)        \
2295 {                         \
2296     FST2 = float32_ ## name(FST0, &env->fp_status);   \
2297     FSTH2 = float32_ ## name(FSTH0, &env->fp_status); \
2298     DEBUG_FPU_STATE();    \
2299     RETURN();                      \
2300 }
2301 FLOAT_UNOP(sqrt)
2302 #undef FLOAT_UNOP
2303
2304 /* unary operations, not modifying fp status  */
2305 #define FLOAT_UNOP(name)  \
2306 FLOAT_OP(name, d)         \
2307 {                         \
2308     FDT2 = float64_ ## name(FDT0);   \
2309     DEBUG_FPU_STATE();    \
2310     RETURN();             \
2311 }                         \
2312 FLOAT_OP(name, s)         \
2313 {                         \
2314     FST2 = float32_ ## name(FST0);   \
2315     DEBUG_FPU_STATE();    \
2316     RETURN();             \
2317 }                         \
2318 FLOAT_OP(name, ps)        \
2319 {                         \
2320     FST2 = float32_ ## name(FST0);   \
2321     FSTH2 = float32_ ## name(FSTH0); \
2322     DEBUG_FPU_STATE();    \
2323     RETURN();             \
2324 }
2325 FLOAT_UNOP(abs)
2326 FLOAT_UNOP(chs)
2327 #undef FLOAT_UNOP
2328
2329 FLOAT_OP(mov, d)
2330 {
2331     FDT2 = FDT0;
2332     DEBUG_FPU_STATE();
2333     RETURN();
2334 }
2335 FLOAT_OP(mov, s)
2336 {
2337     FST2 = FST0;
2338     DEBUG_FPU_STATE();
2339     RETURN();
2340 }
2341 FLOAT_OP(mov, ps)
2342 {
2343     FST2 = FST0;
2344     FSTH2 = FSTH0;
2345     DEBUG_FPU_STATE();
2346     RETURN();
2347 }
2348 FLOAT_OP(alnv, ps)
2349 {
2350     switch (T0 & 0x7) {
2351     case 0:
2352         FST2 = FST0;
2353         FSTH2 = FSTH0;
2354         break;
2355     case 4:
2356 #ifdef TARGET_WORDS_BIGENDIAN
2357         FSTH2 = FST0;
2358         FST2 = FSTH1;
2359 #else
2360         FSTH2 = FST1;
2361         FST2 = FSTH0;
2362 #endif
2363         break;
2364     default: /* unpredictable */
2365         break;
2366     }
2367     DEBUG_FPU_STATE();
2368     RETURN();
2369 }
2370
2371 #ifdef CONFIG_SOFTFLOAT
2372 #define clear_invalid() do {                                \
2373     int flags = get_float_exception_flags(&env->fp_status); \
2374     flags &= ~float_flag_invalid;                           \
2375     set_float_exception_flags(flags, &env->fp_status);      \
2376 } while(0)
2377 #else
2378 #define clear_invalid() do { } while(0)
2379 #endif
2380
2381 extern void dump_fpu_s(CPUState *env);
2382
2383 #define FOP_COND_D(op, cond)                   \
2384 void op_cmp_d_ ## op (void)                    \
2385 {                                              \
2386     int c = cond;                              \
2387     update_fcr31();                            \
2388     if (c)                                     \
2389         SET_FP_COND(PARAM1, env);              \
2390     else                                       \
2391         CLEAR_FP_COND(PARAM1, env);            \
2392     DEBUG_FPU_STATE();                         \
2393     RETURN();                                  \
2394 }                                              \
2395 void op_cmpabs_d_ ## op (void)                 \
2396 {                                              \
2397     int c;                                     \
2398     FDT0 &= ~(1ULL << 63);                     \
2399     FDT1 &= ~(1ULL << 63);                     \
2400     c = cond;                                  \
2401     update_fcr31();                            \
2402     if (c)                                     \
2403         SET_FP_COND(PARAM1, env);              \
2404     else                                       \
2405         CLEAR_FP_COND(PARAM1, env);            \
2406     DEBUG_FPU_STATE();                         \
2407     RETURN();                                  \
2408 }
2409
2410 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2411 {
2412     if (float64_is_signaling_nan(a) ||
2413         float64_is_signaling_nan(b) ||
2414         (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2415         float_raise(float_flag_invalid, status);
2416         return 1;
2417     } else if (float64_is_nan(a) || float64_is_nan(b)) {
2418         return 1;
2419     } else {
2420         return 0;
2421     }
2422 }
2423
2424 /* NOTE: the comma operator will make "cond" to eval to false,
2425  * but float*_is_unordered() is still called. */
2426 FOP_COND_D(f,   (float64_is_unordered(0, FDT1, FDT0, &env->fp_status), 0))
2427 FOP_COND_D(un,  float64_is_unordered(0, FDT1, FDT0, &env->fp_status))
2428 FOP_COND_D(eq,  !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
2429 FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fp_status)  || float64_eq(FDT0, FDT1, &env->fp_status))
2430 FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
2431 FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fp_status)  || float64_lt(FDT0, FDT1, &env->fp_status))
2432 FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
2433 FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fp_status)  || float64_le(FDT0, FDT1, &env->fp_status))
2434 /* NOTE: the comma operator will make "cond" to eval to false,
2435  * but float*_is_unordered() is still called. */
2436 FOP_COND_D(sf,  (float64_is_unordered(1, FDT1, FDT0, &env->fp_status), 0))
2437 FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fp_status))
2438 FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_eq(FDT0, FDT1, &env->fp_status))
2439 FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fp_status)  || float64_eq(FDT0, FDT1, &env->fp_status))
2440 FOP_COND_D(lt,  !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_lt(FDT0, FDT1, &env->fp_status))
2441 FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fp_status)  || float64_lt(FDT0, FDT1, &env->fp_status))
2442 FOP_COND_D(le,  !float64_is_unordered(1, FDT1, FDT0, &env->fp_status) && float64_le(FDT0, FDT1, &env->fp_status))
2443 FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fp_status)  || float64_le(FDT0, FDT1, &env->fp_status))
2444
2445 #define FOP_COND_S(op, cond)                   \
2446 void op_cmp_s_ ## op (void)                    \
2447 {                                              \
2448     int c = cond;                              \
2449     update_fcr31();                            \
2450     if (c)                                     \
2451         SET_FP_COND(PARAM1, env);              \
2452     else                                       \
2453         CLEAR_FP_COND(PARAM1, env);            \
2454     DEBUG_FPU_STATE();                         \
2455     RETURN();                                  \
2456 }                                              \
2457 void op_cmpabs_s_ ## op (void)                 \
2458 {                                              \
2459     int c;                                     \
2460     FST0 &= ~(1 << 31);                        \
2461     FST1 &= ~(1 << 31);                        \
2462     c = cond;                                  \
2463     update_fcr31();                            \
2464     if (c)                                     \
2465         SET_FP_COND(PARAM1, env);              \
2466     else                                       \
2467         CLEAR_FP_COND(PARAM1, env);            \
2468     DEBUG_FPU_STATE();                         \
2469     RETURN();                                  \
2470 }
2471
2472 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2473 {
2474     extern flag float32_is_nan(float32 a);
2475     if (float32_is_signaling_nan(a) ||
2476         float32_is_signaling_nan(b) ||
2477         (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2478         float_raise(float_flag_invalid, status);
2479         return 1;
2480     } else if (float32_is_nan(a) || float32_is_nan(b)) {
2481         return 1;
2482     } else {
2483         return 0;
2484     }
2485 }
2486
2487 /* NOTE: the comma operator will make "cond" to eval to false,
2488  * but float*_is_unordered() is still called. */
2489 FOP_COND_S(f,   (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0))
2490 FOP_COND_S(un,  float32_is_unordered(0, FST1, FST0, &env->fp_status))
2491 FOP_COND_S(eq,  !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
2492 FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status)  || float32_eq(FST0, FST1, &env->fp_status))
2493 FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
2494 FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status)  || float32_lt(FST0, FST1, &env->fp_status))
2495 FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
2496 FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status)  || float32_le(FST0, FST1, &env->fp_status))
2497 /* NOTE: the comma operator will make "cond" to eval to false,
2498  * but float*_is_unordered() is still called. */
2499 FOP_COND_S(sf,  (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0))
2500 FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status))
2501 FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_eq(FST0, FST1, &env->fp_status))
2502 FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status)  || float32_eq(FST0, FST1, &env->fp_status))
2503 FOP_COND_S(lt,  !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_lt(FST0, FST1, &env->fp_status))
2504 FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status)  || float32_lt(FST0, FST1, &env->fp_status))
2505 FOP_COND_S(le,  !float32_is_unordered(1, FST1, FST0, &env->fp_status) && float32_le(FST0, FST1, &env->fp_status))
2506 FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status)  || float32_le(FST0, FST1, &env->fp_status))
2507
2508 #define FOP_COND_PS(op, condl, condh)          \
2509 void op_cmp_ps_ ## op (void)                   \
2510 {                                              \
2511     int cl = condl;                            \
2512     int ch = condh;                            \
2513     update_fcr31();                            \
2514     if (cl)                                    \
2515         SET_FP_COND(PARAM1, env);              \
2516     else                                       \
2517         CLEAR_FP_COND(PARAM1, env);            \
2518     if (ch)                                    \
2519         SET_FP_COND(PARAM1 + 1, env);          \
2520     else                                       \
2521         CLEAR_FP_COND(PARAM1 + 1, env);        \
2522     DEBUG_FPU_STATE();                         \
2523     RETURN();                                  \
2524 }                                              \
2525 void op_cmpabs_ps_ ## op (void)                \
2526 {                                              \
2527     int cl, ch;                                \
2528     FST0 &= ~(1 << 31);                        \
2529     FSTH0 &= ~(1 << 31);                       \
2530     FST1 &= ~(1 << 31);                        \
2531     FSTH1 &= ~(1 << 31);                       \
2532     cl = condl;                                \
2533     ch = condh;                                \
2534     update_fcr31();                            \
2535     if (cl)                                    \
2536         SET_FP_COND(PARAM1, env);              \
2537     else                                       \
2538         CLEAR_FP_COND(PARAM1, env);            \
2539     if (ch)                                    \
2540         SET_FP_COND(PARAM1 + 1, env);          \
2541     else                                       \
2542         CLEAR_FP_COND(PARAM1 + 1, env);        \
2543     DEBUG_FPU_STATE();                         \
2544     RETURN();                                  \
2545 }
2546
2547 /* NOTE: the comma operator will make "cond" to eval to false,
2548  * but float*_is_unordered() is still called. */
2549 FOP_COND_PS(f,   (float32_is_unordered(0, FST1, FST0, &env->fp_status), 0),
2550                  (float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status), 0))
2551 FOP_COND_PS(un,  float32_is_unordered(0, FST1, FST0, &env->fp_status),
2552                  float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status))
2553 FOP_COND_PS(eq,  !float32_is_unordered(0, FST1, FST0, &env->fp_status)   && float32_eq(FST0, FST1, &env->fp_status),
2554                  !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status))
2555 FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fp_status)    || float32_eq(FST0, FST1, &env->fp_status),
2556                  float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status)  || float32_eq(FSTH0, FSTH1, &env->fp_status))
2557 FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fp_status)   && float32_lt(FST0, FST1, &env->fp_status),
2558                  !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status))
2559 FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fp_status)    || float32_lt(FST0, FST1, &env->fp_status),
2560                  float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status)  || float32_lt(FSTH0, FSTH1, &env->fp_status))
2561 FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fp_status)   && float32_le(FST0, FST1, &env->fp_status),
2562                  !float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status))
2563 FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fp_status)    || float32_le(FST0, FST1, &env->fp_status),
2564                  float32_is_unordered(0, FSTH1, FSTH0, &env->fp_status)  || float32_le(FSTH0, FSTH1, &env->fp_status))
2565 /* NOTE: the comma operator will make "cond" to eval to false,
2566  * but float*_is_unordered() is still called. */
2567 FOP_COND_PS(sf,  (float32_is_unordered(1, FST1, FST0, &env->fp_status), 0),
2568                  (float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status), 0))
2569 FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fp_status),
2570                  float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status))
2571 FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fp_status)   && float32_eq(FST0, FST1, &env->fp_status),
2572                  !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_eq(FSTH0, FSTH1, &env->fp_status))
2573 FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fp_status)    || float32_eq(FST0, FST1, &env->fp_status),
2574                  float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status)  || float32_eq(FSTH0, FSTH1, &env->fp_status))
2575 FOP_COND_PS(lt,  !float32_is_unordered(1, FST1, FST0, &env->fp_status)   && float32_lt(FST0, FST1, &env->fp_status),
2576                  !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_lt(FSTH0, FSTH1, &env->fp_status))
2577 FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fp_status)    || float32_lt(FST0, FST1, &env->fp_status),
2578                  float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status)  || float32_lt(FSTH0, FSTH1, &env->fp_status))
2579 FOP_COND_PS(le,  !float32_is_unordered(1, FST1, FST0, &env->fp_status)   && float32_le(FST0, FST1, &env->fp_status),
2580                  !float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status) && float32_le(FSTH0, FSTH1, &env->fp_status))
2581 FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fp_status)    || float32_le(FST0, FST1, &env->fp_status),
2582                  float32_is_unordered(1, FSTH1, FSTH0, &env->fp_status)  || float32_le(FSTH0, FSTH1, &env->fp_status))
2583
2584 void op_bc1f (void)
2585 {
2586     T0 = !IS_FP_COND_SET(PARAM1, env);
2587     DEBUG_FPU_STATE();
2588     RETURN();
2589 }
2590 void op_bc1fany2 (void)
2591 {
2592     T0 = (!IS_FP_COND_SET(PARAM1, env) ||
2593           !IS_FP_COND_SET(PARAM1 + 1, env));
2594     DEBUG_FPU_STATE();
2595     RETURN();
2596 }
2597 void op_bc1fany4 (void)
2598 {
2599     T0 = (!IS_FP_COND_SET(PARAM1, env) ||
2600           !IS_FP_COND_SET(PARAM1 + 1, env) ||
2601           !IS_FP_COND_SET(PARAM1 + 2, env) ||
2602           !IS_FP_COND_SET(PARAM1 + 3, env));
2603     DEBUG_FPU_STATE();
2604     RETURN();
2605 }
2606
2607 void op_bc1t (void)
2608 {
2609     T0 = IS_FP_COND_SET(PARAM1, env);
2610     DEBUG_FPU_STATE();
2611     RETURN();
2612 }
2613 void op_bc1tany2 (void)
2614 {
2615     T0 = (IS_FP_COND_SET(PARAM1, env) ||
2616           IS_FP_COND_SET(PARAM1 + 1, env));
2617     DEBUG_FPU_STATE();
2618     RETURN();
2619 }
2620 void op_bc1tany4 (void)
2621 {
2622     T0 = (IS_FP_COND_SET(PARAM1, env) ||
2623           IS_FP_COND_SET(PARAM1 + 1, env) ||
2624           IS_FP_COND_SET(PARAM1 + 2, env) ||
2625           IS_FP_COND_SET(PARAM1 + 3, env));
2626     DEBUG_FPU_STATE();
2627     RETURN();
2628 }
2629
2630 void op_tlbwi (void)
2631 {
2632     CALL_FROM_TB0(env->do_tlbwi);
2633     RETURN();
2634 }
2635
2636 void op_tlbwr (void)
2637 {
2638     CALL_FROM_TB0(env->do_tlbwr);
2639     RETURN();
2640 }
2641
2642 void op_tlbp (void)
2643 {
2644     CALL_FROM_TB0(env->do_tlbp);
2645     RETURN();
2646 }
2647
2648 void op_tlbr (void)
2649 {
2650     CALL_FROM_TB0(env->do_tlbr);
2651     RETURN();
2652 }
2653
2654 /* Specials */
2655 #if defined (CONFIG_USER_ONLY)
2656 void op_tls_value (void)
2657 {
2658     T0 = env->tls_value;
2659 }
2660 #endif
2661
2662 void op_pmon (void)
2663 {
2664     CALL_FROM_TB1(do_pmon, PARAM1);
2665     RETURN();
2666 }
2667
2668 void op_di (void)
2669 {
2670     T0 = env->CP0_Status;
2671     env->CP0_Status = T0 & ~(1 << CP0St_IE);
2672     CALL_FROM_TB1(cpu_mips_update_irq, env);
2673     RETURN();
2674 }
2675
2676 void op_ei (void)
2677 {
2678     T0 = env->CP0_Status;
2679     env->CP0_Status = T0 | (1 << CP0St_IE);
2680     CALL_FROM_TB1(cpu_mips_update_irq, env);
2681     RETURN();
2682 }
2683
2684 void op_trap (void)
2685 {
2686     if (T0) {
2687         CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
2688     }
2689     RETURN();
2690 }
2691
2692 void op_debug (void)
2693 {
2694     CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2695     RETURN();
2696 }
2697
2698 void op_set_lladdr (void)
2699 {
2700     env->CP0_LLAddr = T2;
2701     RETURN();
2702 }
2703
2704 void debug_pre_eret (void);
2705 void debug_post_eret (void);
2706 void op_eret (void)
2707 {
2708     if (loglevel & CPU_LOG_EXEC)
2709         CALL_FROM_TB0(debug_pre_eret);
2710     if (env->CP0_Status & (1 << CP0St_ERL)) {
2711         env->PC = env->CP0_ErrorEPC;
2712         env->CP0_Status &= ~(1 << CP0St_ERL);
2713     } else {
2714         env->PC = env->CP0_EPC;
2715         env->CP0_Status &= ~(1 << CP0St_EXL);
2716     }
2717     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2718         !(env->CP0_Status & (1 << CP0St_ERL)) &&
2719         !(env->hflags & MIPS_HFLAG_DM) &&
2720         (env->CP0_Status & (1 << CP0St_UM)))
2721         env->hflags |= MIPS_HFLAG_UM;
2722     if (loglevel & CPU_LOG_EXEC)
2723         CALL_FROM_TB0(debug_post_eret);
2724     env->CP0_LLAddr = 1;
2725     RETURN();
2726 }
2727
2728 void op_deret (void)
2729 {
2730     if (loglevel & CPU_LOG_EXEC)
2731         CALL_FROM_TB0(debug_pre_eret);
2732     env->PC = env->CP0_DEPC;
2733     env->hflags |= MIPS_HFLAG_DM;
2734     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2735         !(env->CP0_Status & (1 << CP0St_ERL)) &&
2736         !(env->hflags & MIPS_HFLAG_DM) &&
2737         (env->CP0_Status & (1 << CP0St_UM)))
2738         env->hflags |= MIPS_HFLAG_UM;
2739     if (loglevel & CPU_LOG_EXEC)
2740         CALL_FROM_TB0(debug_post_eret);
2741     env->CP0_LLAddr = 1;
2742     RETURN();
2743 }
2744
2745 void op_rdhwr_cpunum(void)
2746 {
2747     if (!(env->hflags & MIPS_HFLAG_UM) ||
2748         (env->CP0_HWREna & (1 << 0)) ||
2749         (env->CP0_Status & (1 << CP0St_CU0)))
2750         T0 = env->CP0_EBase & 0x3ff;
2751     else
2752         CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2753     RETURN();
2754 }
2755
2756 void op_rdhwr_synci_step(void)
2757 {
2758     if (!(env->hflags & MIPS_HFLAG_UM) ||
2759         (env->CP0_HWREna & (1 << 1)) ||
2760         (env->CP0_Status & (1 << CP0St_CU0)))
2761         T0 = env->SYNCI_Step;
2762     else
2763         CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2764     RETURN();
2765 }
2766
2767 void op_rdhwr_cc(void)
2768 {
2769     if (!(env->hflags & MIPS_HFLAG_UM) ||
2770         (env->CP0_HWREna & (1 << 2)) ||
2771         (env->CP0_Status & (1 << CP0St_CU0)))
2772         T0 = env->CP0_Count;
2773     else
2774         CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2775     RETURN();
2776 }
2777
2778 void op_rdhwr_ccres(void)
2779 {
2780     if (!(env->hflags & MIPS_HFLAG_UM) ||
2781         (env->CP0_HWREna & (1 << 3)) ||
2782         (env->CP0_Status & (1 << CP0St_CU0)))
2783         T0 = env->CCRes;
2784     else
2785         CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2786     RETURN();
2787 }
2788
2789 void op_save_state (void)
2790 {
2791     env->hflags = PARAM1;
2792     RETURN();
2793 }
2794
2795 void op_save_pc (void)
2796 {
2797     env->PC = PARAM1;
2798     RETURN();
2799 }
2800
2801 void op_save_fp_status (void)
2802 {
2803     union fps {
2804         uint32_t i;
2805         float_status f;
2806     } fps;
2807     fps.i = PARAM1;
2808     env->fp_status = fps.f;
2809     RETURN();
2810 }
2811
2812 void op_interrupt_restart (void)
2813 {
2814     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2815         !(env->CP0_Status & (1 << CP0St_ERL)) &&
2816         !(env->hflags & MIPS_HFLAG_DM) &&
2817         (env->CP0_Status & (1 << CP0St_IE)) &&
2818         (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
2819         env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
2820         CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT);
2821     }
2822     RETURN();
2823 }
2824
2825 void op_raise_exception (void)
2826 {
2827     CALL_FROM_TB1(do_raise_exception, PARAM1);
2828     RETURN();
2829 }
2830
2831 void op_raise_exception_err (void)
2832 {
2833     CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
2834     RETURN();
2835 }
2836
2837 void op_exit_tb (void)
2838 {
2839     EXIT_TB();
2840     RETURN();
2841 }
2842
2843 void op_wait (void)
2844 {
2845     env->halted = 1;
2846     CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
2847     RETURN();
2848 }
2849
2850 /* Bitfield operations. */
2851 void op_ext(void)
2852 {
2853     unsigned int pos = PARAM1;
2854     unsigned int size = PARAM2;
2855
2856     T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2857     RETURN();
2858 }
2859
2860 void op_ins(void)
2861 {
2862     unsigned int pos = PARAM1;
2863     unsigned int size = PARAM2;
2864     target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2865
2866     T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
2867     RETURN();
2868 }
2869
2870 void op_wsbh(void)
2871 {
2872     T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
2873     RETURN();
2874 }
2875
2876 #ifdef TARGET_MIPS64
2877 void op_dext(void)
2878 {
2879     unsigned int pos = PARAM1;
2880     unsigned int size = PARAM2;
2881
2882     T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2883     RETURN();
2884 }
2885
2886 void op_dins(void)
2887 {
2888     unsigned int pos = PARAM1;
2889     unsigned int size = PARAM2;
2890     target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2891
2892     T0 = (T0 & ~mask) | ((T1 << pos) & mask);
2893     RETURN();
2894 }
2895
2896 void op_dsbh(void)
2897 {
2898     T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
2899     RETURN();
2900 }
2901
2902 void op_dshd(void)
2903 {
2904     T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
2905     RETURN();
2906 }
2907 #endif
2908
2909 void op_seb(void)
2910 {
2911     T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
2912     RETURN();
2913 }
2914
2915 void op_seh(void)
2916 {
2917     T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
2918     RETURN();
2919 }