2 * QEMU 16450 UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-char.h"
29 //#define DEBUG_SERIAL
31 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
33 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
34 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
35 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
36 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
38 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
39 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
41 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
42 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
43 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
44 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
47 * These are the definitions for the Modem Control Register
49 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
50 #define UART_MCR_OUT2 0x08 /* Out2 complement */
51 #define UART_MCR_OUT1 0x04 /* Out1 complement */
52 #define UART_MCR_RTS 0x02 /* RTS complement */
53 #define UART_MCR_DTR 0x01 /* DTR complement */
56 * These are the definitions for the Modem Status Register
58 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
59 #define UART_MSR_RI 0x40 /* Ring Indicator */
60 #define UART_MSR_DSR 0x20 /* Data Set Ready */
61 #define UART_MSR_CTS 0x10 /* Clear to Send */
62 #define UART_MSR_DDCD 0x08 /* Delta DCD */
63 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
64 #define UART_MSR_DDSR 0x02 /* Delta DSR */
65 #define UART_MSR_DCTS 0x01 /* Delta CTS */
66 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
68 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
69 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
70 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
71 #define UART_LSR_FE 0x08 /* Frame error indicator */
72 #define UART_LSR_PE 0x04 /* Parity error indicator */
73 #define UART_LSR_OE 0x02 /* Overrun error indicator */
74 #define UART_LSR_DR 0x01 /* Receiver data ready */
78 uint8_t rbr
; /* receive register */
80 uint8_t iir
; /* read only */
83 uint8_t lsr
; /* read only */
84 uint8_t msr
; /* read only */
86 /* NOTE: this hidden state is necessary for tx irq generation as
87 it can be reset while reading iir */
91 int last_break_enable
;
92 target_phys_addr_t base
;
96 static void serial_update_irq(SerialState
*s
)
98 if ((s
->lsr
& UART_LSR_DR
) && (s
->ier
& UART_IER_RDI
)) {
99 s
->iir
= UART_IIR_RDI
;
100 } else if (s
->thr_ipending
&& (s
->ier
& UART_IER_THRI
)) {
101 s
->iir
= UART_IIR_THRI
;
103 s
->iir
= UART_IIR_NO_INT
;
105 if (s
->iir
!= UART_IIR_NO_INT
) {
106 qemu_irq_raise(s
->irq
);
108 qemu_irq_lower(s
->irq
);
112 static void serial_update_parameters(SerialState
*s
)
114 int speed
, parity
, data_bits
, stop_bits
;
115 QEMUSerialSetParams ssp
;
129 data_bits
= (s
->lcr
& 0x03) + 5;
132 speed
= 115200 / s
->divider
;
135 ssp
.data_bits
= data_bits
;
136 ssp
.stop_bits
= stop_bits
;
137 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
139 printf("speed=%d parity=%c data=%d stop=%d\n",
140 speed
, parity
, data_bits
, stop_bits
);
144 static void serial_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
146 SerialState
*s
= opaque
;
151 printf("serial: write addr=0x%02x val=0x%02x\n", addr
, val
);
156 if (s
->lcr
& UART_LCR_DLAB
) {
157 s
->divider
= (s
->divider
& 0xff00) | val
;
158 serial_update_parameters(s
);
161 s
->lsr
&= ~UART_LSR_THRE
;
162 serial_update_irq(s
);
164 qemu_chr_write(s
->chr
, &ch
, 1);
166 s
->lsr
|= UART_LSR_THRE
;
167 s
->lsr
|= UART_LSR_TEMT
;
168 serial_update_irq(s
);
172 if (s
->lcr
& UART_LCR_DLAB
) {
173 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
174 serial_update_parameters(s
);
177 if (s
->lsr
& UART_LSR_THRE
) {
180 serial_update_irq(s
);
189 serial_update_parameters(s
);
190 break_enable
= (val
>> 6) & 1;
191 if (break_enable
!= s
->last_break_enable
) {
192 s
->last_break_enable
= break_enable
;
193 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
211 static uint32_t serial_ioport_read(void *opaque
, uint32_t addr
)
213 SerialState
*s
= opaque
;
220 if (s
->lcr
& UART_LCR_DLAB
) {
221 ret
= s
->divider
& 0xff;
224 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
225 serial_update_irq(s
);
226 qemu_chr_accept_input(s
->chr
);
230 if (s
->lcr
& UART_LCR_DLAB
) {
231 ret
= (s
->divider
>> 8) & 0xff;
238 /* reset THR pending bit */
239 if ((ret
& 0x7) == UART_IIR_THRI
)
241 serial_update_irq(s
);
253 if (s
->mcr
& UART_MCR_LOOP
) {
254 /* in loopback, the modem output pins are connected to the
256 ret
= (s
->mcr
& 0x0c) << 4;
257 ret
|= (s
->mcr
& 0x02) << 3;
258 ret
|= (s
->mcr
& 0x01) << 5;
268 printf("serial: read addr=0x%02x val=0x%02x\n", addr
, ret
);
273 static int serial_can_receive(SerialState
*s
)
275 return !(s
->lsr
& UART_LSR_DR
);
278 static void serial_receive_byte(SerialState
*s
, int ch
)
281 s
->lsr
|= UART_LSR_DR
;
282 serial_update_irq(s
);
285 static void serial_receive_break(SerialState
*s
)
288 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
289 serial_update_irq(s
);
292 static int serial_can_receive1(void *opaque
)
294 SerialState
*s
= opaque
;
295 return serial_can_receive(s
);
298 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
300 SerialState
*s
= opaque
;
301 serial_receive_byte(s
, buf
[0]);
304 static void serial_event(void *opaque
, int event
)
306 SerialState
*s
= opaque
;
307 if (event
== CHR_EVENT_BREAK
)
308 serial_receive_break(s
);
311 static void serial_save(QEMUFile
*f
, void *opaque
)
313 SerialState
*s
= opaque
;
315 qemu_put_be16s(f
,&s
->divider
);
316 qemu_put_8s(f
,&s
->rbr
);
317 qemu_put_8s(f
,&s
->ier
);
318 qemu_put_8s(f
,&s
->iir
);
319 qemu_put_8s(f
,&s
->lcr
);
320 qemu_put_8s(f
,&s
->mcr
);
321 qemu_put_8s(f
,&s
->lsr
);
322 qemu_put_8s(f
,&s
->msr
);
323 qemu_put_8s(f
,&s
->scr
);
326 static int serial_load(QEMUFile
*f
, void *opaque
, int version_id
)
328 SerialState
*s
= opaque
;
334 qemu_get_be16s(f
, &s
->divider
);
336 s
->divider
= qemu_get_byte(f
);
337 qemu_get_8s(f
,&s
->rbr
);
338 qemu_get_8s(f
,&s
->ier
);
339 qemu_get_8s(f
,&s
->iir
);
340 qemu_get_8s(f
,&s
->lcr
);
341 qemu_get_8s(f
,&s
->mcr
);
342 qemu_get_8s(f
,&s
->lsr
);
343 qemu_get_8s(f
,&s
->msr
);
344 qemu_get_8s(f
,&s
->scr
);
349 /* If fd is zero, it means that the serial device uses the console */
350 SerialState
*serial_init(int base
, qemu_irq irq
, CharDriverState
*chr
)
354 s
= qemu_mallocz(sizeof(SerialState
));
358 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
359 s
->iir
= UART_IIR_NO_INT
;
360 s
->msr
= UART_MSR_DCD
| UART_MSR_DSR
| UART_MSR_CTS
;
362 register_savevm("serial", base
, 2, serial_save
, serial_load
, s
);
364 register_ioport_write(base
, 8, 1, serial_ioport_write
, s
);
365 register_ioport_read(base
, 8, 1, serial_ioport_read
, s
);
367 qemu_chr_add_handlers(chr
, serial_can_receive1
, serial_receive1
,
372 /* Memory mapped interface */
373 uint32_t serial_mm_readb (void *opaque
, target_phys_addr_t addr
)
375 SerialState
*s
= opaque
;
377 return serial_ioport_read(s
, (addr
- s
->base
) >> s
->it_shift
) & 0xFF;
380 void serial_mm_writeb (void *opaque
,
381 target_phys_addr_t addr
, uint32_t value
)
383 SerialState
*s
= opaque
;
385 serial_ioport_write(s
, (addr
- s
->base
) >> s
->it_shift
, value
& 0xFF);
388 uint32_t serial_mm_readw (void *opaque
, target_phys_addr_t addr
)
390 SerialState
*s
= opaque
;
393 val
= serial_ioport_read(s
, (addr
- s
->base
) >> s
->it_shift
) & 0xFFFF;
394 #ifdef TARGET_WORDS_BIGENDIAN
400 void serial_mm_writew (void *opaque
,
401 target_phys_addr_t addr
, uint32_t value
)
403 SerialState
*s
= opaque
;
404 #ifdef TARGET_WORDS_BIGENDIAN
405 value
= bswap16(value
);
407 serial_ioport_write(s
, (addr
- s
->base
) >> s
->it_shift
, value
& 0xFFFF);
410 uint32_t serial_mm_readl (void *opaque
, target_phys_addr_t addr
)
412 SerialState
*s
= opaque
;
415 val
= serial_ioport_read(s
, (addr
- s
->base
) >> s
->it_shift
);
416 #ifdef TARGET_WORDS_BIGENDIAN
422 void serial_mm_writel (void *opaque
,
423 target_phys_addr_t addr
, uint32_t value
)
425 SerialState
*s
= opaque
;
426 #ifdef TARGET_WORDS_BIGENDIAN
427 value
= bswap32(value
);
429 serial_ioport_write(s
, (addr
- s
->base
) >> s
->it_shift
, value
);
432 static CPUReadMemoryFunc
*serial_mm_read
[] = {
438 static CPUWriteMemoryFunc
*serial_mm_write
[] = {
444 SerialState
*serial_mm_init (target_phys_addr_t base
, int it_shift
,
445 qemu_irq irq
, CharDriverState
*chr
,
451 s
= qemu_mallocz(sizeof(SerialState
));
455 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
456 s
->iir
= UART_IIR_NO_INT
;
457 s
->msr
= UART_MSR_DCD
| UART_MSR_DSR
| UART_MSR_CTS
;
459 s
->it_shift
= it_shift
;
461 register_savevm("serial", base
, 2, serial_save
, serial_load
, s
);
464 s_io_memory
= cpu_register_io_memory(0, serial_mm_read
,
466 cpu_register_physical_memory(base
, 8 << it_shift
, s_io_memory
);
469 qemu_chr_add_handlers(chr
, serial_can_receive1
, serial_receive1
,