2 * QEMU ETRAX System Emulator
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu-timer.h"
29 void etrax_ack_irq(CPUState
*env
, uint32_t mask
);
31 #define R_TIME 0xb001e038
32 #define RW_TMR0_DIV 0xb001e000
33 #define R_TMR0_DATA 0xb001e004
34 #define RW_TMR0_CTRL 0xb001e008
35 #define RW_TMR1_DIV 0xb001e010
36 #define R_TMR1_DATA 0xb001e014
37 #define RW_TMR1_CTRL 0xb001e018
39 #define RW_INTR_MASK 0xb001e048
40 #define RW_ACK_INTR 0xb001e04c
41 #define R_INTR 0xb001e050
42 #define R_MASKED_INTR 0xb001e054
45 uint32_t rw_intr_mask
;
59 static struct fs_timer_t timer0
;
61 /* diff two timevals. Return a single int in us. */
62 int diff_timeval_us(struct timeval
*a
, struct timeval
*b
)
66 /* assume these values are signed. */
67 diff
= (a
->tv_sec
- b
->tv_sec
) * 1000 * 1000;
68 diff
+= (a
->tv_usec
- b
->tv_usec
);
72 static uint32_t timer_readb (void *opaque
, target_phys_addr_t addr
)
74 CPUState
*env
= opaque
;
76 printf ("%s %x pc=%x\n", __func__
, addr
, env
->pc
);
79 static uint32_t timer_readw (void *opaque
, target_phys_addr_t addr
)
81 CPUState
*env
= opaque
;
83 printf ("%s %x pc=%x\n", __func__
, addr
, env
->pc
);
87 static uint32_t timer_readl (void *opaque
, target_phys_addr_t addr
)
89 CPUState
*env
= opaque
;
96 printf ("R_TMR1_DATA\n");
100 static struct timeval last
;
102 gettimeofday(&now
, NULL
);
103 if (!(last
.tv_sec
== 0 && last
.tv_usec
== 0)) {
104 r
= diff_timeval_us(&now
, &last
);
105 r
*= 1000; /* convert to ns. */
106 r
++; /* make sure we increase for each call. */
116 r
= r_intr
& rw_intr_mask
;
119 printf ("%s %x p=%x\n", __func__
, addr
, env
->pc
);
126 timer_writeb (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
128 CPUState
*env
= opaque
;
129 printf ("%s %x %x pc=%x\n", __func__
, addr
, value
, env
->pc
);
132 timer_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
134 CPUState
*env
= opaque
;
135 printf ("%s %x %x pc=%x\n", __func__
, addr
, value
, env
->pc
);
138 static void write_ctrl(struct fs_timer_t
*t
, uint32_t v
)
152 printf ("extern or disabled timer clock?\n");
154 case 4: freq_hz
= 29493000; break;
155 case 5: freq_hz
= 32000000; break;
156 case 6: freq_hz
= 32768000; break;
157 case 7: freq_hz
= 100000000; break;
163 printf ("freq_hz=%d limit=%d\n", freq_hz
, t
->limit
);
168 ptimer_set_period(timer0
.ptimer
, freq_hz
/ t
->scale
);
171 printf ("op=%d\n", op
);
175 printf ("limit=%d %d\n", t
->limit
, t
->limit
/t
->scale
);
176 ptimer_set_limit(t
->ptimer
, t
->limit
/ t
->scale
, 1);
179 ptimer_stop(t
->ptimer
);
182 ptimer_run(t
->ptimer
, 0);
190 static void timer_ack_irq(void)
192 if (!(r_intr
& timer0
.mask
& rw_intr_mask
)) {
193 qemu_irq_lower(timer0
.irq
[0]);
194 etrax_ack_irq(timer0
.env
, 1 << 0x1b);
199 timer_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
201 CPUState
*env
= opaque
;
202 printf ("%s %x %x pc=%x\n",
203 __func__
, addr
, value
, env
->pc
);
207 printf ("RW_TMR0_DIV=%x\n", value
);
208 timer0
.limit
= value
;
211 printf ("RW_TMR0_CTRL=%x\n", value
);
212 write_ctrl(&timer0
, value
);
215 printf ("RW_TMR1_DIV=%x\n", value
);
218 printf ("RW_TMR1_CTRL=%x\n", value
);
221 printf ("RW_INTR_MASK=%x\n", value
);
222 rw_intr_mask
= value
;
229 printf ("%s %x %x pc=%x\n",
230 __func__
, addr
, value
, env
->pc
);
235 static CPUReadMemoryFunc
*timer_read
[] = {
241 static CPUWriteMemoryFunc
*timer_write
[] = {
247 static void timer_irq(void *opaque
)
249 struct fs_timer_t
*t
= opaque
;
252 if (t
->mask
& rw_intr_mask
) {
253 qemu_irq_raise(t
->irq
[0]);
257 void etraxfs_timer_init(CPUState
*env
, qemu_irq
*irqs
)
261 timer0
.bh
= qemu_bh_new(timer_irq
, &timer0
);
262 timer0
.ptimer
= ptimer_init(timer0
.bh
);
263 timer0
.irq
= irqs
+ 0x1b;
267 timer_regs
= cpu_register_io_memory(0, timer_read
, timer_write
, env
);
268 cpu_register_physical_memory (0xb001e000, 0x5c, timer_regs
);