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Remove old leftovers
[qemu/qemu_0_9_1_stable.git] / vl.h
blobb05ea119a139d3db69742a7f6d648c072070dd82
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef MIN
97 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
98 #endif
99 #ifndef MAX
100 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
101 #endif
102
103 /* cutils.c */
104 void pstrcpy(char *buf, int buf_size, const char *str);
105 char *pstrcat(char *buf, int buf_size, const char *s);
106 int strstart(const char *str, const char *val, const char **ptr);
107 int stristart(const char *str, const char *val, const char **ptr);
108
109 /* vl.c */
110 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
111
112 void hw_error(const char *fmt, ...);
113
114 extern const char *bios_dir;
115
116 extern int vm_running;
117 extern const char *qemu_name;
118
119 typedef struct vm_change_state_entry VMChangeStateEntry;
120 typedef void VMChangeStateHandler(void *opaque, int running);
121 typedef void VMStopHandler(void *opaque, int reason);
122
123 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
124 void *opaque);
125 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
126
127 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
128 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
129
130 void vm_start(void);
131 void vm_stop(int reason);
132
133 typedef void QEMUResetHandler(void *opaque);
134
135 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
136 void qemu_system_reset_request(void);
137 void qemu_system_shutdown_request(void);
138 void qemu_system_powerdown_request(void);
139 #if !defined(TARGET_SPARC)
140 // Please implement a power failure function to signal the OS
141 #define qemu_system_powerdown() do{}while(0)
142 #else
143 void qemu_system_powerdown(void);
144 #endif
145
146 void main_loop_wait(int timeout);
147
148 extern int ram_size;
149 extern int bios_size;
150 extern int rtc_utc;
151 extern int cirrus_vga_enabled;
152 extern int vmsvga_enabled;
153 extern int graphic_width;
154 extern int graphic_height;
155 extern int graphic_depth;
156 extern const char *keyboard_layout;
157 extern int kqemu_allowed;
158 extern int win2k_install_hack;
159 extern int alt_grab;
160 extern int usb_enabled;
161 extern int smp_cpus;
162 extern int cursor_hide;
163 extern int graphic_rotate;
164 extern int no_quit;
165 extern int semihosting_enabled;
166 extern int autostart;
167 extern int old_param;
168 extern const char *bootp_filename;
169
170 #define MAX_OPTION_ROMS 16
171 extern const char *option_rom[MAX_OPTION_ROMS];
172 extern int nb_option_roms;
173
174 #ifdef TARGET_SPARC
175 #define MAX_PROM_ENVS 128
176 extern const char *prom_envs[MAX_PROM_ENVS];
177 extern unsigned int nb_prom_envs;
178 #endif
179
180 /* XXX: make it dynamic */
181 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
182 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
183 #define BIOS_SIZE ((512 + 32) * 1024)
184 #elif defined(TARGET_MIPS)
185 #define BIOS_SIZE (4 * 1024 * 1024)
186 #endif
187
188 /* keyboard/mouse support */
189
190 #define MOUSE_EVENT_LBUTTON 0x01
191 #define MOUSE_EVENT_RBUTTON 0x02
192 #define MOUSE_EVENT_MBUTTON 0x04
193
194 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
195 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
196
197 typedef struct QEMUPutMouseEntry {
198 QEMUPutMouseEvent *qemu_put_mouse_event;
199 void *qemu_put_mouse_event_opaque;
200 int qemu_put_mouse_event_absolute;
201 char *qemu_put_mouse_event_name;
202
203 /* used internally by qemu for handling mice */
204 struct QEMUPutMouseEntry *next;
205 } QEMUPutMouseEntry;
206
207 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
208 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
209 void *opaque, int absolute,
210 const char *name);
211 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
212
213 void kbd_put_keycode(int keycode);
214 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
215 int kbd_mouse_is_absolute(void);
216
217 void do_info_mice(void);
218 void do_mouse_set(int index);
219
220 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
221 constants) */
222 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
223 #define QEMU_KEY_BACKSPACE 0x007f
224 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
225 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
226 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
227 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
228 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
229 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
230 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
231 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
232 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
233
234 #define QEMU_KEY_CTRL_UP 0xe400
235 #define QEMU_KEY_CTRL_DOWN 0xe401
236 #define QEMU_KEY_CTRL_LEFT 0xe402
237 #define QEMU_KEY_CTRL_RIGHT 0xe403
238 #define QEMU_KEY_CTRL_HOME 0xe404
239 #define QEMU_KEY_CTRL_END 0xe405
240 #define QEMU_KEY_CTRL_PAGEUP 0xe406
241 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
242
243 void kbd_put_keysym(int keysym);
244
245 /* async I/O support */
246
247 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
248 typedef int IOCanRWHandler(void *opaque);
249 typedef void IOHandler(void *opaque);
250
251 int qemu_set_fd_handler2(int fd,
252 IOCanRWHandler *fd_read_poll,
253 IOHandler *fd_read,
254 IOHandler *fd_write,
255 void *opaque);
256 int qemu_set_fd_handler(int fd,
257 IOHandler *fd_read,
258 IOHandler *fd_write,
259 void *opaque);
260
261 /* Polling handling */
262
263 /* return TRUE if no sleep should be done afterwards */
264 typedef int PollingFunc(void *opaque);
265
266 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
267 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
268
269 #ifdef _WIN32
270 /* Wait objects handling */
271 typedef void WaitObjectFunc(void *opaque);
272
273 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
274 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
275 #endif
276
277 typedef struct QEMUBH QEMUBH;
278
279 /* character device */
280
281 #define CHR_EVENT_BREAK 0 /* serial break char */
282 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
283 #define CHR_EVENT_RESET 2 /* new connection established */
284
285
286 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
287 typedef struct {
288 int speed;
289 int parity;
290 int data_bits;
291 int stop_bits;
292 } QEMUSerialSetParams;
293
294 #define CHR_IOCTL_SERIAL_SET_BREAK 2
295
296 #define CHR_IOCTL_PP_READ_DATA 3
297 #define CHR_IOCTL_PP_WRITE_DATA 4
298 #define CHR_IOCTL_PP_READ_CONTROL 5
299 #define CHR_IOCTL_PP_WRITE_CONTROL 6
300 #define CHR_IOCTL_PP_READ_STATUS 7
301 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
302 #define CHR_IOCTL_PP_EPP_READ 9
303 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
304 #define CHR_IOCTL_PP_EPP_WRITE 11
305
306 typedef void IOEventHandler(void *opaque, int event);
307
308 typedef struct CharDriverState {
309 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
310 void (*chr_update_read_handler)(struct CharDriverState *s);
311 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
312 IOEventHandler *chr_event;
313 IOCanRWHandler *chr_can_read;
314 IOReadHandler *chr_read;
315 void *handler_opaque;
316 void (*chr_send_event)(struct CharDriverState *chr, int event);
317 void (*chr_close)(struct CharDriverState *chr);
318 void *opaque;
319 int focus;
320 QEMUBH *bh;
321 } CharDriverState;
322
323 CharDriverState *qemu_chr_open(const char *filename);
324 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
325 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
326 void qemu_chr_send_event(CharDriverState *s, int event);
327 void qemu_chr_add_handlers(CharDriverState *s,
328 IOCanRWHandler *fd_can_read,
329 IOReadHandler *fd_read,
330 IOEventHandler *fd_event,
331 void *opaque);
332 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
333 void qemu_chr_reset(CharDriverState *s);
334 int qemu_chr_can_read(CharDriverState *s);
335 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
336
337 /* consoles */
338
339 typedef struct DisplayState DisplayState;
340 typedef struct TextConsole TextConsole;
341
342 typedef void (*vga_hw_update_ptr)(void *);
343 typedef void (*vga_hw_invalidate_ptr)(void *);
344 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
345
346 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
347 vga_hw_invalidate_ptr invalidate,
348 vga_hw_screen_dump_ptr screen_dump,
349 void *opaque);
350 void vga_hw_update(void);
351 void vga_hw_invalidate(void);
352 void vga_hw_screen_dump(const char *filename);
353
354 int is_graphic_console(void);
355 CharDriverState *text_console_init(DisplayState *ds, const char *p);
356 void console_select(unsigned int index);
357
358 /* serial ports */
359
360 #define MAX_SERIAL_PORTS 4
361
362 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
363
364 /* parallel ports */
365
366 #define MAX_PARALLEL_PORTS 3
367
368 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
369
370 struct ParallelIOArg {
371 void *buffer;
372 int count;
373 };
374
375 /* VLANs support */
376
377 typedef struct VLANClientState VLANClientState;
378
379 struct VLANClientState {
380 IOReadHandler *fd_read;
381 /* Packets may still be sent if this returns zero. It's used to
382 rate-limit the slirp code. */
383 IOCanRWHandler *fd_can_read;
384 void *opaque;
385 struct VLANClientState *next;
386 struct VLANState *vlan;
387 char info_str[256];
388 };
389
390 typedef struct VLANState {
391 int id;
392 VLANClientState *first_client;
393 struct VLANState *next;
394 unsigned int nb_guest_devs, nb_host_devs;
395 } VLANState;
396
397 VLANState *qemu_find_vlan(int id);
398 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
399 IOReadHandler *fd_read,
400 IOCanRWHandler *fd_can_read,
401 void *opaque);
402 int qemu_can_send_packet(VLANClientState *vc);
403 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
404 void qemu_handler_true(void *opaque);
405
406 void do_info_network(void);
407
408 /* TAP win32 */
409 int tap_win32_init(VLANState *vlan, const char *ifname);
410
411 /* NIC info */
412
413 #define MAX_NICS 8
414
415 typedef struct NICInfo {
416 uint8_t macaddr[6];
417 const char *model;
418 VLANState *vlan;
419 } NICInfo;
420
421 extern int nb_nics;
422 extern NICInfo nd_table[MAX_NICS];
423
424 /* timers */
425
426 typedef struct QEMUClock QEMUClock;
427 typedef struct QEMUTimer QEMUTimer;
428 typedef void QEMUTimerCB(void *opaque);
429
430 /* The real time clock should be used only for stuff which does not
431 change the virtual machine state, as it is run even if the virtual
432 machine is stopped. The real time clock has a frequency of 1000
433 Hz. */
434 extern QEMUClock *rt_clock;
435
436 /* The virtual clock is only run during the emulation. It is stopped
437 when the virtual machine is stopped. Virtual timers use a high
438 precision clock, usually cpu cycles (use ticks_per_sec). */
439 extern QEMUClock *vm_clock;
440
441 int64_t qemu_get_clock(QEMUClock *clock);
442
443 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
444 void qemu_free_timer(QEMUTimer *ts);
445 void qemu_del_timer(QEMUTimer *ts);
446 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
447 int qemu_timer_pending(QEMUTimer *ts);
448
449 extern int64_t ticks_per_sec;
450 extern int pit_min_timer_count;
451
452 int64_t cpu_get_ticks(void);
453 void cpu_enable_ticks(void);
454 void cpu_disable_ticks(void);
455
456 /* VM Load/Save */
457
458 typedef struct QEMUFile QEMUFile;
459
460 QEMUFile *qemu_fopen(const char *filename, const char *mode);
461 void qemu_fflush(QEMUFile *f);
462 void qemu_fclose(QEMUFile *f);
463 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
464 void qemu_put_byte(QEMUFile *f, int v);
465 void qemu_put_be16(QEMUFile *f, unsigned int v);
466 void qemu_put_be32(QEMUFile *f, unsigned int v);
467 void qemu_put_be64(QEMUFile *f, uint64_t v);
468 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
469 int qemu_get_byte(QEMUFile *f);
470 unsigned int qemu_get_be16(QEMUFile *f);
471 unsigned int qemu_get_be32(QEMUFile *f);
472 uint64_t qemu_get_be64(QEMUFile *f);
473
474 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
475 {
476 qemu_put_be64(f, *pv);
477 }
478
479 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
480 {
481 qemu_put_be32(f, *pv);
482 }
483
484 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
485 {
486 qemu_put_be16(f, *pv);
487 }
488
489 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
490 {
491 qemu_put_byte(f, *pv);
492 }
493
494 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
495 {
496 *pv = qemu_get_be64(f);
497 }
498
499 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
500 {
501 *pv = qemu_get_be32(f);
502 }
503
504 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
505 {
506 *pv = qemu_get_be16(f);
507 }
508
509 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
510 {
511 *pv = qemu_get_byte(f);
512 }
513
514 #if TARGET_LONG_BITS == 64
515 #define qemu_put_betl qemu_put_be64
516 #define qemu_get_betl qemu_get_be64
517 #define qemu_put_betls qemu_put_be64s
518 #define qemu_get_betls qemu_get_be64s
519 #else
520 #define qemu_put_betl qemu_put_be32
521 #define qemu_get_betl qemu_get_be32
522 #define qemu_put_betls qemu_put_be32s
523 #define qemu_get_betls qemu_get_be32s
524 #endif
525
526 int64_t qemu_ftell(QEMUFile *f);
527 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
528
529 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
530 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
531
532 int register_savevm(const char *idstr,
533 int instance_id,
534 int version_id,
535 SaveStateHandler *save_state,
536 LoadStateHandler *load_state,
537 void *opaque);
538 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
539 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
540
541 void cpu_save(QEMUFile *f, void *opaque);
542 int cpu_load(QEMUFile *f, void *opaque, int version_id);
543
544 void do_savevm(const char *name);
545 void do_loadvm(const char *name);
546 void do_delvm(const char *name);
547 void do_info_snapshots(void);
548
549 /* bottom halves */
550 typedef void QEMUBHFunc(void *opaque);
551
552 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
553 void qemu_bh_schedule(QEMUBH *bh);
554 void qemu_bh_cancel(QEMUBH *bh);
555 void qemu_bh_delete(QEMUBH *bh);
556 int qemu_bh_poll(void);
557
558 /* block.c */
559 typedef struct BlockDriverState BlockDriverState;
560 typedef struct BlockDriver BlockDriver;
561
562 extern BlockDriver bdrv_raw;
563 extern BlockDriver bdrv_host_device;
564 extern BlockDriver bdrv_cow;
565 extern BlockDriver bdrv_qcow;
566 extern BlockDriver bdrv_vmdk;
567 extern BlockDriver bdrv_cloop;
568 extern BlockDriver bdrv_dmg;
569 extern BlockDriver bdrv_bochs;
570 extern BlockDriver bdrv_vpc;
571 extern BlockDriver bdrv_vvfat;
572 extern BlockDriver bdrv_qcow2;
573 extern BlockDriver bdrv_parallels;
574
575 typedef struct BlockDriverInfo {
576 /* in bytes, 0 if irrelevant */
577 int cluster_size;
578 /* offset at which the VM state can be saved (0 if not possible) */
579 int64_t vm_state_offset;
580 } BlockDriverInfo;
581
582 typedef struct QEMUSnapshotInfo {
583 char id_str[128]; /* unique snapshot id */
584 /* the following fields are informative. They are not needed for
585 the consistency of the snapshot */
586 char name[256]; /* user choosen name */
587 uint32_t vm_state_size; /* VM state info size */
588 uint32_t date_sec; /* UTC date of the snapshot */
589 uint32_t date_nsec;
590 uint64_t vm_clock_nsec; /* VM clock relative to boot */
591 } QEMUSnapshotInfo;
592
593 #define BDRV_O_RDONLY 0x0000
594 #define BDRV_O_RDWR 0x0002
595 #define BDRV_O_ACCESS 0x0003
596 #define BDRV_O_CREAT 0x0004 /* create an empty file */
597 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
598 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
599 use a disk image format on top of
600 it (default for
601 bdrv_file_open()) */
602
603 void bdrv_init(void);
604 BlockDriver *bdrv_find_format(const char *format_name);
605 int bdrv_create(BlockDriver *drv,
606 const char *filename, int64_t size_in_sectors,
607 const char *backing_file, int flags);
608 BlockDriverState *bdrv_new(const char *device_name);
609 void bdrv_delete(BlockDriverState *bs);
610 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
611 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
612 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
613 BlockDriver *drv);
614 void bdrv_close(BlockDriverState *bs);
615 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
616 uint8_t *buf, int nb_sectors);
617 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
618 const uint8_t *buf, int nb_sectors);
619 int bdrv_pread(BlockDriverState *bs, int64_t offset,
620 void *buf, int count);
621 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
622 const void *buf, int count);
623 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
624 int64_t bdrv_getlength(BlockDriverState *bs);
625 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
626 int bdrv_commit(BlockDriverState *bs);
627 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
628 /* async block I/O */
629 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
630 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
631
632 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
633 uint8_t *buf, int nb_sectors,
634 BlockDriverCompletionFunc *cb, void *opaque);
635 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
636 const uint8_t *buf, int nb_sectors,
637 BlockDriverCompletionFunc *cb, void *opaque);
638 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
639
640 void qemu_aio_init(void);
641 void qemu_aio_poll(void);
642 void qemu_aio_flush(void);
643 void qemu_aio_wait_start(void);
644 void qemu_aio_wait(void);
645 void qemu_aio_wait_end(void);
646
647 int qemu_key_check(BlockDriverState *bs, const char *name);
648
649 /* Ensure contents are flushed to disk. */
650 void bdrv_flush(BlockDriverState *bs);
651
652 #define BDRV_TYPE_HD 0
653 #define BDRV_TYPE_CDROM 1
654 #define BDRV_TYPE_FLOPPY 2
655 #define BIOS_ATA_TRANSLATION_AUTO 0
656 #define BIOS_ATA_TRANSLATION_NONE 1
657 #define BIOS_ATA_TRANSLATION_LBA 2
658 #define BIOS_ATA_TRANSLATION_LARGE 3
659 #define BIOS_ATA_TRANSLATION_RECHS 4
660
661 void bdrv_set_geometry_hint(BlockDriverState *bs,
662 int cyls, int heads, int secs);
663 void bdrv_set_type_hint(BlockDriverState *bs, int type);
664 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
665 void bdrv_get_geometry_hint(BlockDriverState *bs,
666 int *pcyls, int *pheads, int *psecs);
667 int bdrv_get_type_hint(BlockDriverState *bs);
668 int bdrv_get_translation_hint(BlockDriverState *bs);
669 int bdrv_is_removable(BlockDriverState *bs);
670 int bdrv_is_read_only(BlockDriverState *bs);
671 int bdrv_is_inserted(BlockDriverState *bs);
672 int bdrv_media_changed(BlockDriverState *bs);
673 int bdrv_is_locked(BlockDriverState *bs);
674 void bdrv_set_locked(BlockDriverState *bs, int locked);
675 void bdrv_eject(BlockDriverState *bs, int eject_flag);
676 void bdrv_set_change_cb(BlockDriverState *bs,
677 void (*change_cb)(void *opaque), void *opaque);
678 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
679 void bdrv_info(void);
680 BlockDriverState *bdrv_find(const char *name);
681 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
682 int bdrv_is_encrypted(BlockDriverState *bs);
683 int bdrv_set_key(BlockDriverState *bs, const char *key);
684 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
685 void *opaque);
686 const char *bdrv_get_device_name(BlockDriverState *bs);
687 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
688 const uint8_t *buf, int nb_sectors);
689 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
690
691 void bdrv_get_backing_filename(BlockDriverState *bs,
692 char *filename, int filename_size);
693 int bdrv_snapshot_create(BlockDriverState *bs,
694 QEMUSnapshotInfo *sn_info);
695 int bdrv_snapshot_goto(BlockDriverState *bs,
696 const char *snapshot_id);
697 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
698 int bdrv_snapshot_list(BlockDriverState *bs,
699 QEMUSnapshotInfo **psn_info);
700 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
701
702 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
703 int path_is_absolute(const char *path);
704 void path_combine(char *dest, int dest_size,
705 const char *base_path,
706 const char *filename);
707
708 #ifndef QEMU_TOOL
709
710 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
711 int boot_device,
712 DisplayState *ds, const char **fd_filename, int snapshot,
713 const char *kernel_filename, const char *kernel_cmdline,
714 const char *initrd_filename, const char *cpu_model);
715
716 typedef struct QEMUMachine {
717 const char *name;
718 const char *desc;
719 QEMUMachineInitFunc *init;
720 struct QEMUMachine *next;
721 } QEMUMachine;
722
723 int qemu_register_machine(QEMUMachine *m);
724
725 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
726
727 #if defined(TARGET_PPC)
728 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
729 #endif
730
731 #if defined(TARGET_MIPS)
732 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
733 #endif
734
735 #include "hw/irq.h"
736
737 /* ISA bus */
738
739 extern target_phys_addr_t isa_mem_base;
740
741 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
742 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
743
744 int register_ioport_read(int start, int length, int size,
745 IOPortReadFunc *func, void *opaque);
746 int register_ioport_write(int start, int length, int size,
747 IOPortWriteFunc *func, void *opaque);
748 void isa_unassign_ioport(int start, int length);
749
750 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
751
752 /* PCI bus */
753
754 extern target_phys_addr_t pci_mem_base;
755
756 typedef struct PCIBus PCIBus;
757 typedef struct PCIDevice PCIDevice;
758
759 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
760 uint32_t address, uint32_t data, int len);
761 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
762 uint32_t address, int len);
763 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
764 uint32_t addr, uint32_t size, int type);
765
766 #define PCI_ADDRESS_SPACE_MEM 0x00
767 #define PCI_ADDRESS_SPACE_IO 0x01
768 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
769
770 typedef struct PCIIORegion {
771 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
772 uint32_t size;
773 uint8_t type;
774 PCIMapIORegionFunc *map_func;
775 } PCIIORegion;
776
777 #define PCI_ROM_SLOT 6
778 #define PCI_NUM_REGIONS 7
779
780 #define PCI_DEVICES_MAX 64
781
782 #define PCI_VENDOR_ID 0x00 /* 16 bits */
783 #define PCI_DEVICE_ID 0x02 /* 16 bits */
784 #define PCI_COMMAND 0x04 /* 16 bits */
785 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
786 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
787 #define PCI_CLASS_DEVICE 0x0a /* Device class */
788 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
789 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
790 #define PCI_MIN_GNT 0x3e /* 8 bits */
791 #define PCI_MAX_LAT 0x3f /* 8 bits */
792
793 struct PCIDevice {
794 /* PCI config space */
795 uint8_t config[256];
796
797 /* the following fields are read only */
798 PCIBus *bus;
799 int devfn;
800 char name[64];
801 PCIIORegion io_regions[PCI_NUM_REGIONS];
802
803 /* do not access the following fields */
804 PCIConfigReadFunc *config_read;
805 PCIConfigWriteFunc *config_write;
806 /* ??? This is a PC-specific hack, and should be removed. */
807 int irq_index;
808
809 /* IRQ objects for the INTA-INTD pins. */
810 qemu_irq *irq;
811
812 /* Current IRQ levels. Used internally by the generic PCI code. */
813 int irq_state[4];
814 };
815
816 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
817 int instance_size, int devfn,
818 PCIConfigReadFunc *config_read,
819 PCIConfigWriteFunc *config_write);
820
821 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
822 uint32_t size, int type,
823 PCIMapIORegionFunc *map_func);
824
825 uint32_t pci_default_read_config(PCIDevice *d,
826 uint32_t address, int len);
827 void pci_default_write_config(PCIDevice *d,
828 uint32_t address, uint32_t val, int len);
829 void pci_device_save(PCIDevice *s, QEMUFile *f);
830 int pci_device_load(PCIDevice *s, QEMUFile *f);
831
832 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
833 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
834 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
835 qemu_irq *pic, int devfn_min, int nirq);
836
837 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
838 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
839 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
840 int pci_bus_num(PCIBus *s);
841 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
842
843 void pci_info(void);
844 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
845 pci_map_irq_fn map_irq, const char *name);
846
847 /* prep_pci.c */
848 PCIBus *pci_prep_init(qemu_irq *pic);
849
850 /* grackle_pci.c */
851 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
852
853 /* unin_pci.c */
854 PCIBus *pci_pmac_init(qemu_irq *pic);
855
856 /* apb_pci.c */
857 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
858 qemu_irq *pic);
859
860 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
861
862 /* piix_pci.c */
863 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
864 void i440fx_set_smm(PCIDevice *d, int val);
865 int piix3_init(PCIBus *bus, int devfn);
866 void i440fx_init_memory_mappings(PCIDevice *d);
867
868 int piix4_init(PCIBus *bus, int devfn);
869
870 /* openpic.c */
871 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
872 enum {
873 OPENPIC_OUTPUT_INT = 0, /* IRQ */
874 OPENPIC_OUTPUT_CINT, /* critical IRQ */
875 OPENPIC_OUTPUT_MCK, /* Machine check event */
876 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
877 OPENPIC_OUTPUT_RESET, /* Core reset event */
878 OPENPIC_OUTPUT_NB,
879 };
880 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
881 qemu_irq **irqs, qemu_irq irq_out);
882
883 /* heathrow_pic.c */
884 qemu_irq *heathrow_pic_init(int *pmem_index);
885
886 /* gt64xxx.c */
887 PCIBus *pci_gt64120_init(qemu_irq *pic);
888
889 #ifdef HAS_AUDIO
890 struct soundhw {
891 const char *name;
892 const char *descr;
893 int enabled;
894 int isa;
895 union {
896 int (*init_isa) (AudioState *s, qemu_irq *pic);
897 int (*init_pci) (PCIBus *bus, AudioState *s);
898 } init;
899 };
900
901 extern struct soundhw soundhw[];
902 #endif
903
904 /* vga.c */
905
906 #ifndef TARGET_SPARC
907 #define VGA_RAM_SIZE (8192 * 1024)
908 #else
909 #define VGA_RAM_SIZE (9 * 1024 * 1024)
910 #endif
911
912 struct DisplayState {
913 uint8_t *data;
914 int linesize;
915 int depth;
916 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
917 int width;
918 int height;
919 void *opaque;
920 QEMUTimer *gui_timer;
921
922 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
923 void (*dpy_resize)(struct DisplayState *s, int w, int h);
924 void (*dpy_refresh)(struct DisplayState *s);
925 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
926 int dst_x, int dst_y, int w, int h);
927 void (*dpy_fill)(struct DisplayState *s, int x, int y,
928 int w, int h, uint32_t c);
929 void (*mouse_set)(int x, int y, int on);
930 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
931 uint8_t *image, uint8_t *mask);
932 };
933
934 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
935 {
936 s->dpy_update(s, x, y, w, h);
937 }
938
939 static inline void dpy_resize(DisplayState *s, int w, int h)
940 {
941 s->dpy_resize(s, w, h);
942 }
943
944 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
945 unsigned long vga_ram_offset, int vga_ram_size);
946 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
947 unsigned long vga_ram_offset, int vga_ram_size,
948 unsigned long vga_bios_offset, int vga_bios_size);
949 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
950 unsigned long vga_ram_offset, int vga_ram_size,
951 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
952 int it_shift);
953
954 /* cirrus_vga.c */
955 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
956 unsigned long vga_ram_offset, int vga_ram_size);
957 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
958 unsigned long vga_ram_offset, int vga_ram_size);
959
960 /* vmware_vga.c */
961 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
962 unsigned long vga_ram_offset, int vga_ram_size);
963
964 /* sdl.c */
965 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
966
967 /* cocoa.m */
968 void cocoa_display_init(DisplayState *ds, int full_screen);
969
970 /* vnc.c */
971 void vnc_display_init(DisplayState *ds, const char *display);
972 void do_info_vnc(void);
973
974 /* x_keymap.c */
975 extern uint8_t _translate_keycode(const int key);
976
977 /* ide.c */
978 #define MAX_DISKS 4
979
980 extern BlockDriverState *bs_table[MAX_DISKS + 1];
981 extern BlockDriverState *sd_bdrv;
982 extern BlockDriverState *mtd_bdrv;
983
984 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
985 BlockDriverState *hd0, BlockDriverState *hd1);
986 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
987 int secondary_ide_enabled);
988 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
989 qemu_irq *pic);
990 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
991 qemu_irq *pic);
992 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
993
994 /* cdrom.c */
995 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
996 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
997
998 /* ds1225y.c */
999 typedef struct ds1225y_t ds1225y_t;
1000 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1001
1002 /* es1370.c */
1003 int es1370_init (PCIBus *bus, AudioState *s);
1004
1005 /* sb16.c */
1006 int SB16_init (AudioState *s, qemu_irq *pic);
1007
1008 /* adlib.c */
1009 int Adlib_init (AudioState *s, qemu_irq *pic);
1010
1011 /* gus.c */
1012 int GUS_init (AudioState *s, qemu_irq *pic);
1013
1014 /* dma.c */
1015 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1016 int DMA_get_channel_mode (int nchan);
1017 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1018 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1019 void DMA_hold_DREQ (int nchan);
1020 void DMA_release_DREQ (int nchan);
1021 void DMA_schedule(int nchan);
1022 void DMA_run (void);
1023 void DMA_init (int high_page_enable);
1024 void DMA_register_channel (int nchan,
1025 DMA_transfer_handler transfer_handler,
1026 void *opaque);
1027 /* fdc.c */
1028 #define MAX_FD 2
1029 extern BlockDriverState *fd_table[MAX_FD];
1030
1031 typedef struct fdctrl_t fdctrl_t;
1032
1033 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1034 target_phys_addr_t io_base,
1035 BlockDriverState **fds);
1036 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1037
1038 /* eepro100.c */
1039
1040 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1041 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1042 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1043
1044 /* ne2000.c */
1045
1046 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1047 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1048
1049 /* rtl8139.c */
1050
1051 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1052
1053 /* pcnet.c */
1054
1055 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1056 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1057 qemu_irq irq, qemu_irq *reset);
1058
1059 /* vmmouse.c */
1060 void *vmmouse_init(void *m);
1061
1062 /* pckbd.c */
1063
1064 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1065 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1066 target_phys_addr_t base, int it_shift);
1067
1068 /* mc146818rtc.c */
1069
1070 typedef struct RTCState RTCState;
1071
1072 RTCState *rtc_init(int base, qemu_irq irq);
1073 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1074 void rtc_set_memory(RTCState *s, int addr, int val);
1075 void rtc_set_date(RTCState *s, const struct tm *tm);
1076
1077 /* serial.c */
1078
1079 typedef struct SerialState SerialState;
1080 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1081 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1082 qemu_irq irq, CharDriverState *chr,
1083 int ioregister);
1084 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1085 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1086 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1087 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1088 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1089 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1090
1091 /* parallel.c */
1092
1093 typedef struct ParallelState ParallelState;
1094 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1095 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1096
1097 /* i8259.c */
1098
1099 typedef struct PicState2 PicState2;
1100 extern PicState2 *isa_pic;
1101 void pic_set_irq(int irq, int level);
1102 void pic_set_irq_new(void *opaque, int irq, int level);
1103 qemu_irq *i8259_init(qemu_irq parent_irq);
1104 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1105 void *alt_irq_opaque);
1106 int pic_read_irq(PicState2 *s);
1107 void pic_update_irq(PicState2 *s);
1108 uint32_t pic_intack_read(PicState2 *s);
1109 void pic_info(void);
1110 void irq_info(void);
1111
1112 /* APIC */
1113 typedef struct IOAPICState IOAPICState;
1114
1115 int apic_init(CPUState *env);
1116 int apic_get_interrupt(CPUState *env);
1117 IOAPICState *ioapic_init(void);
1118 void ioapic_set_irq(void *opaque, int vector, int level);
1119
1120 /* i8254.c */
1121
1122 #define PIT_FREQ 1193182
1123
1124 typedef struct PITState PITState;
1125
1126 PITState *pit_init(int base, qemu_irq irq);
1127 void pit_set_gate(PITState *pit, int channel, int val);
1128 int pit_get_gate(PITState *pit, int channel);
1129 int pit_get_initial_count(PITState *pit, int channel);
1130 int pit_get_mode(PITState *pit, int channel);
1131 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1132
1133 /* jazz_led.c */
1134 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1135
1136 /* pcspk.c */
1137 void pcspk_init(PITState *);
1138 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1139
1140 #include "hw/i2c.h"
1141
1142 #include "hw/smbus.h"
1143
1144 /* acpi.c */
1145 extern int acpi_enabled;
1146 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1147 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1148 void acpi_bios_init(void);
1149
1150 /* pc.c */
1151 extern QEMUMachine pc_machine;
1152 extern QEMUMachine isapc_machine;
1153 extern int fd_bootchk;
1154
1155 void ioport_set_a20(int enable);
1156 int ioport_get_a20(void);
1157
1158 /* ppc.c */
1159 extern QEMUMachine prep_machine;
1160 extern QEMUMachine core99_machine;
1161 extern QEMUMachine heathrow_machine;
1162 extern QEMUMachine ref405ep_machine;
1163 extern QEMUMachine taihu_machine;
1164
1165 /* mips_r4k.c */
1166 extern QEMUMachine mips_machine;
1167
1168 /* mips_malta.c */
1169 extern QEMUMachine mips_malta_machine;
1170
1171 /* mips_int.c */
1172 extern void cpu_mips_irq_init_cpu(CPUState *env);
1173
1174 /* mips_pica61.c */
1175 extern QEMUMachine mips_pica61_machine;
1176
1177 /* mips_timer.c */
1178 extern void cpu_mips_clock_init(CPUState *);
1179 extern void cpu_mips_irqctrl_init (void);
1180
1181 /* shix.c */
1182 extern QEMUMachine shix_machine;
1183
1184 #ifdef TARGET_PPC
1185 /* PowerPC hardware exceptions management helpers */
1186 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1187 typedef struct clk_setup_t clk_setup_t;
1188 struct clk_setup_t {
1189 clk_setup_cb cb;
1190 void *opaque;
1191 };
1192 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1193 {
1194 if (clk->cb != NULL)
1195 (*clk->cb)(clk->opaque, freq);
1196 }
1197
1198 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1199 /* Embedded PowerPC DCR management */
1200 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1201 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1202 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1203 int (*dcr_write_error)(int dcrn));
1204 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1205 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1206 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1207 /* Embedded PowerPC reset */
1208 void ppc40x_core_reset (CPUState *env);
1209 void ppc40x_chip_reset (CPUState *env);
1210 void ppc40x_system_reset (CPUState *env);
1211 #endif
1212 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1213
1214 extern CPUWriteMemoryFunc *PPC_io_write[];
1215 extern CPUReadMemoryFunc *PPC_io_read[];
1216 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1217
1218 /* sun4m.c */
1219 extern QEMUMachine ss5_machine, ss10_machine;
1220
1221 /* iommu.c */
1222 void *iommu_init(target_phys_addr_t addr);
1223 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1224 uint8_t *buf, int len, int is_write);
1225 static inline void sparc_iommu_memory_read(void *opaque,
1226 target_phys_addr_t addr,
1227 uint8_t *buf, int len)
1228 {
1229 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1230 }
1231
1232 static inline void sparc_iommu_memory_write(void *opaque,
1233 target_phys_addr_t addr,
1234 uint8_t *buf, int len)
1235 {
1236 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1237 }
1238
1239 /* tcx.c */
1240 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1241 unsigned long vram_offset, int vram_size, int width, int height,
1242 int depth);
1243
1244 /* slavio_intctl.c */
1245 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1246 const uint32_t *intbit_to_level,
1247 qemu_irq **irq, qemu_irq **cpu_irq,
1248 qemu_irq **parent_irq, unsigned int cputimer);
1249 void slavio_pic_info(void *opaque);
1250 void slavio_irq_info(void *opaque);
1251
1252 /* loader.c */
1253 int get_image_size(const char *filename);
1254 int load_image(const char *filename, uint8_t *addr);
1255 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1256 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1257 int load_aout(const char *filename, uint8_t *addr);
1258 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1259
1260 /* slavio_timer.c */
1261 void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
1262
1263 /* slavio_serial.c */
1264 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1265 CharDriverState *chr1, CharDriverState *chr2);
1266 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1267
1268 /* slavio_misc.c */
1269 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1270 qemu_irq irq);
1271 void slavio_set_power_fail(void *opaque, int power_failing);
1272
1273 /* esp.c */
1274 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1275 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1276 void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1277
1278 /* sparc32_dma.c */
1279 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1280 void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1281 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1282 uint8_t *buf, int len, int do_bswap);
1283 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1284 uint8_t *buf, int len, int do_bswap);
1285 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1286 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1287
1288 /* cs4231.c */
1289 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1290
1291 /* sun4u.c */
1292 extern QEMUMachine sun4u_machine;
1293
1294 /* NVRAM helpers */
1295 #include "hw/m48t59.h"
1296
1297 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1298 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1299 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1300 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1301 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1302 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1303 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1304 const unsigned char *str, uint32_t max);
1305 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1306 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1307 uint32_t start, uint32_t count);
1308 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1309 const unsigned char *arch,
1310 uint32_t RAM_size, int boot_device,
1311 uint32_t kernel_image, uint32_t kernel_size,
1312 const char *cmdline,
1313 uint32_t initrd_image, uint32_t initrd_size,
1314 uint32_t NVRAM_image,
1315 int width, int height, int depth);
1316
1317 /* adb.c */
1318
1319 #define MAX_ADB_DEVICES 16
1320
1321 #define ADB_MAX_OUT_LEN 16
1322
1323 typedef struct ADBDevice ADBDevice;
1324
1325 /* buf = NULL means polling */
1326 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1327 const uint8_t *buf, int len);
1328 typedef int ADBDeviceReset(ADBDevice *d);
1329
1330 struct ADBDevice {
1331 struct ADBBusState *bus;
1332 int devaddr;
1333 int handler;
1334 ADBDeviceRequest *devreq;
1335 ADBDeviceReset *devreset;
1336 void *opaque;
1337 };
1338
1339 typedef struct ADBBusState {
1340 ADBDevice devices[MAX_ADB_DEVICES];
1341 int nb_devices;
1342 int poll_index;
1343 } ADBBusState;
1344
1345 int adb_request(ADBBusState *s, uint8_t *buf_out,
1346 const uint8_t *buf, int len);
1347 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1348
1349 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1350 ADBDeviceRequest *devreq,
1351 ADBDeviceReset *devreset,
1352 void *opaque);
1353 void adb_kbd_init(ADBBusState *bus);
1354 void adb_mouse_init(ADBBusState *bus);
1355
1356 /* cuda.c */
1357
1358 extern ADBBusState adb_bus;
1359 int cuda_init(qemu_irq irq);
1360
1361 #include "hw/usb.h"
1362
1363 /* usb ports of the VM */
1364
1365 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1366 usb_attachfn attach);
1367
1368 #define VM_USB_HUB_SIZE 8
1369
1370 void do_usb_add(const char *devname);
1371 void do_usb_del(const char *devname);
1372 void usb_info(void);
1373
1374 /* scsi-disk.c */
1375 enum scsi_reason {
1376 SCSI_REASON_DONE, /* Command complete. */
1377 SCSI_REASON_DATA /* Transfer complete, more data required. */
1378 };
1379
1380 typedef struct SCSIDevice SCSIDevice;
1381 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1382 uint32_t arg);
1383
1384 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1385 int tcq,
1386 scsi_completionfn completion,
1387 void *opaque);
1388 void scsi_disk_destroy(SCSIDevice *s);
1389
1390 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1391 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1392 layer the completion routine may be called directly by
1393 scsi_{read,write}_data. */
1394 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1395 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1396 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1397 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1398
1399 /* lsi53c895a.c */
1400 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1401 void *lsi_scsi_init(PCIBus *bus, int devfn);
1402
1403 /* integratorcp.c */
1404 extern QEMUMachine integratorcp_machine;
1405
1406 /* versatilepb.c */
1407 extern QEMUMachine versatilepb_machine;
1408 extern QEMUMachine versatileab_machine;
1409
1410 /* realview.c */
1411 extern QEMUMachine realview_machine;
1412
1413 /* spitz.c */
1414 extern QEMUMachine akitapda_machine;
1415 extern QEMUMachine spitzpda_machine;
1416 extern QEMUMachine borzoipda_machine;
1417 extern QEMUMachine terrierpda_machine;
1418
1419 /* palm.c */
1420 extern QEMUMachine palmte_machine;
1421
1422 /* ps2.c */
1423 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1424 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1425 void ps2_write_mouse(void *, int val);
1426 void ps2_write_keyboard(void *, int val);
1427 uint32_t ps2_read_data(void *);
1428 void ps2_queue(void *, int b);
1429 void ps2_keyboard_set_translation(void *opaque, int mode);
1430 void ps2_mouse_fake_event(void *opaque);
1431
1432 /* smc91c111.c */
1433 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1434
1435 /* pl031.c */
1436 void pl031_init(uint32_t base, qemu_irq irq);
1437
1438 /* pl110.c */
1439 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1440
1441 /* pl011.c */
1442 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1443
1444 /* pl050.c */
1445 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1446
1447 /* pl080.c */
1448 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1449
1450 /* pl181.c */
1451 void pl181_init(uint32_t base, BlockDriverState *bd,
1452 qemu_irq irq0, qemu_irq irq1);
1453
1454 /* pl190.c */
1455 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1456
1457 /* arm-timer.c */
1458 void sp804_init(uint32_t base, qemu_irq irq);
1459 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1460
1461 /* arm_sysctl.c */
1462 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1463
1464 /* arm_gic.c */
1465 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1466
1467 /* arm_boot.c */
1468
1469 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1470 const char *kernel_cmdline, const char *initrd_filename,
1471 int board_id, target_phys_addr_t loader_start);
1472
1473 /* sh7750.c */
1474 struct SH7750State;
1475
1476 struct SH7750State *sh7750_init(CPUState * cpu);
1477
1478 typedef struct {
1479 /* The callback will be triggered if any of the designated lines change */
1480 uint16_t portamask_trigger;
1481 uint16_t portbmask_trigger;
1482 /* Return 0 if no action was taken */
1483 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1484 uint16_t * periph_pdtra,
1485 uint16_t * periph_portdira,
1486 uint16_t * periph_pdtrb,
1487 uint16_t * periph_portdirb);
1488 } sh7750_io_device;
1489
1490 int sh7750_register_io_device(struct SH7750State *s,
1491 sh7750_io_device * device);
1492 /* tc58128.c */
1493 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1494
1495 /* NOR flash devices */
1496 #define MAX_PFLASH 4
1497 extern BlockDriverState *pflash_table[MAX_PFLASH];
1498 typedef struct pflash_t pflash_t;
1499
1500 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1501 BlockDriverState *bs,
1502 uint32_t sector_len, int nb_blocs, int width,
1503 uint16_t id0, uint16_t id1,
1504 uint16_t id2, uint16_t id3);
1505
1506 /* nand.c */
1507 struct nand_flash_s;
1508 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1509 void nand_done(struct nand_flash_s *s);
1510 void nand_setpins(struct nand_flash_s *s,
1511 int cle, int ale, int ce, int wp, int gnd);
1512 void nand_getpins(struct nand_flash_s *s, int *rb);
1513 void nand_setio(struct nand_flash_s *s, uint8_t value);
1514 uint8_t nand_getio(struct nand_flash_s *s);
1515
1516 #define NAND_MFR_TOSHIBA 0x98
1517 #define NAND_MFR_SAMSUNG 0xec
1518 #define NAND_MFR_FUJITSU 0x04
1519 #define NAND_MFR_NATIONAL 0x8f
1520 #define NAND_MFR_RENESAS 0x07
1521 #define NAND_MFR_STMICRO 0x20
1522 #define NAND_MFR_HYNIX 0xad
1523 #define NAND_MFR_MICRON 0x2c
1524
1525 #include "ecc.h"
1526
1527 /* GPIO */
1528 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1529
1530 /* ads7846.c */
1531 struct ads7846_state_s;
1532 uint32_t ads7846_read(void *opaque);
1533 void ads7846_write(void *opaque, uint32_t value);
1534 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1535
1536 /* max111x.c */
1537 struct max111x_s;
1538 uint32_t max111x_read(void *opaque);
1539 void max111x_write(void *opaque, uint32_t value);
1540 struct max111x_s *max1110_init(qemu_irq cb);
1541 struct max111x_s *max1111_init(qemu_irq cb);
1542 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1543
1544 /* PCMCIA/Cardbus */
1545
1546 struct pcmcia_socket_s {
1547 qemu_irq irq;
1548 int attached;
1549 const char *slot_string;
1550 const char *card_string;
1551 };
1552
1553 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1554 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1555 void pcmcia_info(void);
1556
1557 struct pcmcia_card_s {
1558 void *state;
1559 struct pcmcia_socket_s *slot;
1560 int (*attach)(void *state);
1561 int (*detach)(void *state);
1562 const uint8_t *cis;
1563 int cis_len;
1564
1565 /* Only valid if attached */
1566 uint8_t (*attr_read)(void *state, uint32_t address);
1567 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1568 uint16_t (*common_read)(void *state, uint32_t address);
1569 void (*common_write)(void *state, uint32_t address, uint16_t value);
1570 uint16_t (*io_read)(void *state, uint32_t address);
1571 void (*io_write)(void *state, uint32_t address, uint16_t value);
1572 };
1573
1574 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1575 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1576 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1577 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1578 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1579 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1580 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1581 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1582 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1583 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1584 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1585 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1586 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1587 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1588 #define CISTPL_END 0xff /* Tuple End */
1589 #define CISTPL_ENDMARK 0xff
1590
1591 /* dscm1xxxx.c */
1592 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1593
1594 /* ptimer.c */
1595 typedef struct ptimer_state ptimer_state;
1596 typedef void (*ptimer_cb)(void *opaque);
1597
1598 ptimer_state *ptimer_init(QEMUBH *bh);
1599 void ptimer_set_period(ptimer_state *s, int64_t period);
1600 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1601 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1602 uint64_t ptimer_get_count(ptimer_state *s);
1603 void ptimer_set_count(ptimer_state *s, uint64_t count);
1604 void ptimer_run(ptimer_state *s, int oneshot);
1605 void ptimer_stop(ptimer_state *s);
1606 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1607 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1608
1609 #include "hw/pxa.h"
1610
1611 #include "hw/omap.h"
1612
1613 /* mcf_uart.c */
1614 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1615 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1616 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1617 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1618 CharDriverState *chr);
1619
1620 /* mcf_intc.c */
1621 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1622
1623 /* mcf_fec.c */
1624 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1625
1626 /* mcf5206.c */
1627 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1628
1629 /* an5206.c */
1630 extern QEMUMachine an5206_machine;
1631
1632 /* mcf5208.c */
1633 extern QEMUMachine mcf5208evb_machine;
1634
1635 #include "gdbstub.h"
1636
1637 #endif /* defined(QEMU_TOOL) */
1638
1639 /* monitor.c */
1640 void monitor_init(CharDriverState *hd, int show_banner);
1641 void term_puts(const char *str);
1642 void term_vprintf(const char *fmt, va_list ap);
1643 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1644 void term_print_filename(const char *filename);
1645 void term_flush(void);
1646 void term_print_help(void);
1647 void monitor_readline(const char *prompt, int is_password,
1648 char *buf, int buf_size);
1649
1650 /* readline.c */
1651 typedef void ReadLineFunc(void *opaque, const char *str);
1652
1653 extern int completion_index;
1654 void add_completion(const char *str);
1655 void readline_handle_byte(int ch);
1656 void readline_find_completion(const char *cmdline);
1657 const char *readline_get_history(unsigned int index);
1658 void readline_start(const char *prompt, int is_password,
1659 ReadLineFunc *readline_func, void *opaque);
1660
1661 void kqemu_record_dump(void);
1662
1663 #endif /* VL_H */
Stable branch of Qemu 0.9.1