4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #define raise_exception_err(a, b)\
28 fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
29 (raise_exception_err)(a, b);\
33 const uint8_t parity_table
[256] = {
34 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
35 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
36 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
37 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
38 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
39 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
40 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
41 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
42 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
43 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
44 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
45 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
46 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
47 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
48 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
49 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
50 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
51 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
52 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
53 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
54 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
55 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
56 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
57 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
58 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
59 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
60 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
61 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
62 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
63 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
64 CC_P
, 0, 0, CC_P
, 0, CC_P
, CC_P
, 0,
65 0, CC_P
, CC_P
, 0, CC_P
, 0, 0, CC_P
,
69 const uint8_t rclw_table
[32] = {
70 0, 1, 2, 3, 4, 5, 6, 7,
71 8, 9,10,11,12,13,14,15,
72 16, 0, 1, 2, 3, 4, 5, 6,
73 7, 8, 9,10,11,12,13,14,
77 const uint8_t rclb_table
[32] = {
78 0, 1, 2, 3, 4, 5, 6, 7,
79 8, 0, 1, 2, 3, 4, 5, 6,
80 7, 8, 0, 1, 2, 3, 4, 5,
81 6, 7, 8, 0, 1, 2, 3, 4,
84 const CPU86_LDouble f15rk
[7] =
86 0.00000000000000000000L,
87 1.00000000000000000000L,
88 3.14159265358979323851L, /*pi*/
89 0.30102999566398119523L, /*lg2*/
90 0.69314718055994530943L, /*ln2*/
91 1.44269504088896340739L, /*l2e*/
92 3.32192809488736234781L, /*l2t*/
97 spinlock_t global_cpu_lock
= SPIN_LOCK_UNLOCKED
;
101 spin_lock(&global_cpu_lock
);
104 void cpu_unlock(void)
106 spin_unlock(&global_cpu_lock
);
109 /* return non zero if error */
110 static inline int load_segment(uint32_t *e1_ptr
, uint32_t *e2_ptr
,
121 index
= selector
& ~7;
122 if ((index
+ 7) > dt
->limit
)
124 ptr
= dt
->base
+ index
;
125 *e1_ptr
= ldl_kernel(ptr
);
126 *e2_ptr
= ldl_kernel(ptr
+ 4);
130 static inline unsigned int get_seg_limit(uint32_t e1
, uint32_t e2
)
133 limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
134 if (e2
& DESC_G_MASK
)
135 limit
= (limit
<< 12) | 0xfff;
139 static inline uint32_t get_seg_base(uint32_t e1
, uint32_t e2
)
141 return ((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
144 static inline void load_seg_cache_raw_dt(SegmentCache
*sc
, uint32_t e1
, uint32_t e2
)
146 sc
->base
= get_seg_base(e1
, e2
);
147 sc
->limit
= get_seg_limit(e1
, e2
);
151 /* init the segment cache in vm86 mode. */
152 static inline void load_seg_vm(int seg
, int selector
)
155 cpu_x86_load_seg_cache(env
, seg
, selector
,
156 (selector
<< 4), 0xffff, 0);
159 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr
,
160 uint32_t *esp_ptr
, int dpl
)
162 int type
, index
, shift
;
167 printf("TR: base=%p limit=%x\n", env
->tr
.base
, env
->tr
.limit
);
168 for(i
=0;i
<env
->tr
.limit
;i
++) {
169 printf("%02x ", env
->tr
.base
[i
]);
170 if ((i
& 7) == 7) printf("\n");
176 if (!(env
->tr
.flags
& DESC_P_MASK
))
177 cpu_abort(env
, "invalid tss");
178 type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
180 cpu_abort(env
, "invalid tss type");
182 index
= (dpl
* 4 + 2) << shift
;
183 if (index
+ (4 << shift
) - 1 > env
->tr
.limit
)
184 raise_exception_err(EXCP0A_TSS
, env
->tr
.selector
& 0xfffc);
186 *esp_ptr
= lduw_kernel(env
->tr
.base
+ index
);
187 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 2);
189 *esp_ptr
= ldl_kernel(env
->tr
.base
+ index
);
190 *ss_ptr
= lduw_kernel(env
->tr
.base
+ index
+ 4);
194 /* XXX: merge with load_seg() */
195 static void tss_load_seg(int seg_reg
, int selector
)
200 if ((selector
& 0xfffc) != 0) {
201 if (load_segment(&e1
, &e2
, selector
) != 0)
202 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
203 if (!(e2
& DESC_S_MASK
))
204 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
206 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
207 cpl
= env
->hflags
& HF_CPL_MASK
;
208 if (seg_reg
== R_CS
) {
209 if (!(e2
& DESC_CS_MASK
))
210 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
211 /* XXX: is it correct ? */
213 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
214 if ((e2
& DESC_C_MASK
) && dpl
> rpl
)
215 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
216 } else if (seg_reg
== R_SS
) {
217 /* SS must be writable data */
218 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
))
219 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
220 if (dpl
!= cpl
|| dpl
!= rpl
)
221 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
223 /* not readable code */
224 if ((e2
& DESC_CS_MASK
) && !(e2
& DESC_R_MASK
))
225 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
226 /* if data or non conforming code, checks the rights */
227 if (((e2
>> DESC_TYPE_SHIFT
) & 0xf) < 12) {
228 if (dpl
< cpl
|| dpl
< rpl
)
229 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
232 if (!(e2
& DESC_P_MASK
))
233 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
234 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
235 get_seg_base(e1
, e2
),
236 get_seg_limit(e1
, e2
),
239 if (seg_reg
== R_SS
|| seg_reg
== R_CS
)
240 raise_exception_err(EXCP0A_TSS
, selector
& 0xfffc);
244 #define SWITCH_TSS_JMP 0
245 #define SWITCH_TSS_IRET 1
246 #define SWITCH_TSS_CALL 2
248 /* XXX: restore CPU state in registers (PowerPC case) */
249 static void switch_tss(int tss_selector
,
250 uint32_t e1
, uint32_t e2
, int source
,
253 int tss_limit
, tss_limit_max
, type
, old_tss_limit_max
, old_type
, v1
, v2
, i
;
254 target_ulong tss_base
;
255 uint32_t new_regs
[8], new_segs
[6];
256 uint32_t new_eflags
, new_eip
, new_cr3
, new_ldt
, new_trap
;
257 uint32_t old_eflags
, eflags_mask
;
262 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
264 if (loglevel
& CPU_LOG_PCALL
)
265 fprintf(logfile
, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector
, type
, source
);
268 /* if task gate, we read the TSS segment and we load it */
270 if (!(e2
& DESC_P_MASK
))
271 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
272 tss_selector
= e1
>> 16;
273 if (tss_selector
& 4)
274 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
275 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
276 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
277 if (e2
& DESC_S_MASK
)
278 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
279 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
281 raise_exception_err(EXCP0D_GPF
, tss_selector
& 0xfffc);
284 if (!(e2
& DESC_P_MASK
))
285 raise_exception_err(EXCP0B_NOSEG
, tss_selector
& 0xfffc);
291 tss_limit
= get_seg_limit(e1
, e2
);
292 tss_base
= get_seg_base(e1
, e2
);
293 if ((tss_selector
& 4) != 0 ||
294 tss_limit
< tss_limit_max
)
295 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
296 old_type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
298 old_tss_limit_max
= 103;
300 old_tss_limit_max
= 43;
302 /* read all the registers from the new TSS */
305 new_cr3
= ldl_kernel(tss_base
+ 0x1c);
306 new_eip
= ldl_kernel(tss_base
+ 0x20);
307 new_eflags
= ldl_kernel(tss_base
+ 0x24);
308 for(i
= 0; i
< 8; i
++)
309 new_regs
[i
] = ldl_kernel(tss_base
+ (0x28 + i
* 4));
310 for(i
= 0; i
< 6; i
++)
311 new_segs
[i
] = lduw_kernel(tss_base
+ (0x48 + i
* 4));
312 new_ldt
= lduw_kernel(tss_base
+ 0x60);
313 new_trap
= ldl_kernel(tss_base
+ 0x64);
317 new_eip
= lduw_kernel(tss_base
+ 0x0e);
318 new_eflags
= lduw_kernel(tss_base
+ 0x10);
319 for(i
= 0; i
< 8; i
++)
320 new_regs
[i
] = lduw_kernel(tss_base
+ (0x12 + i
* 2)) | 0xffff0000;
321 for(i
= 0; i
< 4; i
++)
322 new_segs
[i
] = lduw_kernel(tss_base
+ (0x22 + i
* 4));
323 new_ldt
= lduw_kernel(tss_base
+ 0x2a);
329 /* NOTE: we must avoid memory exceptions during the task switch,
330 so we make dummy accesses before */
331 /* XXX: it can still fail in some cases, so a bigger hack is
332 necessary to valid the TLB after having done the accesses */
334 v1
= ldub_kernel(env
->tr
.base
);
335 v2
= ldub_kernel(env
->tr
.base
+ old_tss_limit_max
);
336 stb_kernel(env
->tr
.base
, v1
);
337 stb_kernel(env
->tr
.base
+ old_tss_limit_max
, v2
);
339 /* clear busy bit (it is restartable) */
340 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_IRET
) {
343 ptr
= env
->gdt
.base
+ (env
->tr
.selector
& ~7);
344 e2
= ldl_kernel(ptr
+ 4);
345 e2
&= ~DESC_TSS_BUSY_MASK
;
346 stl_kernel(ptr
+ 4, e2
);
348 old_eflags
= compute_eflags();
349 if (source
== SWITCH_TSS_IRET
)
350 old_eflags
&= ~NT_MASK
;
352 /* save the current state in the old TSS */
355 stl_kernel(env
->tr
.base
+ 0x20, next_eip
);
356 stl_kernel(env
->tr
.base
+ 0x24, old_eflags
);
357 stl_kernel(env
->tr
.base
+ (0x28 + 0 * 4), EAX
);
358 stl_kernel(env
->tr
.base
+ (0x28 + 1 * 4), ECX
);
359 stl_kernel(env
->tr
.base
+ (0x28 + 2 * 4), EDX
);
360 stl_kernel(env
->tr
.base
+ (0x28 + 3 * 4), EBX
);
361 stl_kernel(env
->tr
.base
+ (0x28 + 4 * 4), ESP
);
362 stl_kernel(env
->tr
.base
+ (0x28 + 5 * 4), EBP
);
363 stl_kernel(env
->tr
.base
+ (0x28 + 6 * 4), ESI
);
364 stl_kernel(env
->tr
.base
+ (0x28 + 7 * 4), EDI
);
365 for(i
= 0; i
< 6; i
++)
366 stw_kernel(env
->tr
.base
+ (0x48 + i
* 4), env
->segs
[i
].selector
);
369 stw_kernel(env
->tr
.base
+ 0x0e, next_eip
);
370 stw_kernel(env
->tr
.base
+ 0x10, old_eflags
);
371 stw_kernel(env
->tr
.base
+ (0x12 + 0 * 2), EAX
);
372 stw_kernel(env
->tr
.base
+ (0x12 + 1 * 2), ECX
);
373 stw_kernel(env
->tr
.base
+ (0x12 + 2 * 2), EDX
);
374 stw_kernel(env
->tr
.base
+ (0x12 + 3 * 2), EBX
);
375 stw_kernel(env
->tr
.base
+ (0x12 + 4 * 2), ESP
);
376 stw_kernel(env
->tr
.base
+ (0x12 + 5 * 2), EBP
);
377 stw_kernel(env
->tr
.base
+ (0x12 + 6 * 2), ESI
);
378 stw_kernel(env
->tr
.base
+ (0x12 + 7 * 2), EDI
);
379 for(i
= 0; i
< 4; i
++)
380 stw_kernel(env
->tr
.base
+ (0x22 + i
* 4), env
->segs
[i
].selector
);
383 /* now if an exception occurs, it will occurs in the next task
386 if (source
== SWITCH_TSS_CALL
) {
387 stw_kernel(tss_base
, env
->tr
.selector
);
388 new_eflags
|= NT_MASK
;
392 if (source
== SWITCH_TSS_JMP
|| source
== SWITCH_TSS_CALL
) {
395 ptr
= env
->gdt
.base
+ (tss_selector
& ~7);
396 e2
= ldl_kernel(ptr
+ 4);
397 e2
|= DESC_TSS_BUSY_MASK
;
398 stl_kernel(ptr
+ 4, e2
);
401 /* set the new CPU state */
402 /* from this point, any exception which occurs can give problems */
403 env
->cr
[0] |= CR0_TS_MASK
;
404 env
->hflags
|= HF_TS_MASK
;
405 env
->tr
.selector
= tss_selector
;
406 env
->tr
.base
= tss_base
;
407 env
->tr
.limit
= tss_limit
;
408 env
->tr
.flags
= e2
& ~DESC_TSS_BUSY_MASK
;
410 if ((type
& 8) && (env
->cr
[0] & CR0_PG_MASK
)) {
411 cpu_x86_update_cr3(env
, new_cr3
);
414 /* load all registers without an exception, then reload them with
415 possible exception */
417 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
|
418 IF_MASK
| IOPL_MASK
| VM_MASK
| RF_MASK
| NT_MASK
;
420 eflags_mask
&= 0xffff;
421 load_eflags(new_eflags
, eflags_mask
);
422 /* XXX: what to do in 16 bit case ? */
431 if (new_eflags
& VM_MASK
) {
432 for(i
= 0; i
< 6; i
++)
433 load_seg_vm(i
, new_segs
[i
]);
434 /* in vm86, CPL is always 3 */
435 cpu_x86_set_cpl(env
, 3);
437 /* CPL is set the RPL of CS */
438 cpu_x86_set_cpl(env
, new_segs
[R_CS
] & 3);
439 /* first just selectors as the rest may trigger exceptions */
440 for(i
= 0; i
< 6; i
++)
441 cpu_x86_load_seg_cache(env
, i
, new_segs
[i
], 0, 0, 0);
444 env
->ldt
.selector
= new_ldt
& ~4;
451 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
453 if ((new_ldt
& 0xfffc) != 0) {
455 index
= new_ldt
& ~7;
456 if ((index
+ 7) > dt
->limit
)
457 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
458 ptr
= dt
->base
+ index
;
459 e1
= ldl_kernel(ptr
);
460 e2
= ldl_kernel(ptr
+ 4);
461 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
462 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
463 if (!(e2
& DESC_P_MASK
))
464 raise_exception_err(EXCP0A_TSS
, new_ldt
& 0xfffc);
465 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
468 /* load the segments */
469 if (!(new_eflags
& VM_MASK
)) {
470 tss_load_seg(R_CS
, new_segs
[R_CS
]);
471 tss_load_seg(R_SS
, new_segs
[R_SS
]);
472 tss_load_seg(R_ES
, new_segs
[R_ES
]);
473 tss_load_seg(R_DS
, new_segs
[R_DS
]);
474 tss_load_seg(R_FS
, new_segs
[R_FS
]);
475 tss_load_seg(R_GS
, new_segs
[R_GS
]);
478 /* check that EIP is in the CS segment limits */
479 if (new_eip
> env
->segs
[R_CS
].limit
) {
480 /* XXX: different exception if CALL ? */
481 raise_exception_err(EXCP0D_GPF
, 0);
485 /* check if Port I/O is allowed in TSS */
486 static inline void check_io(int addr
, int size
)
488 int io_offset
, val
, mask
;
490 /* TSS must be a valid 32 bit one */
491 if (!(env
->tr
.flags
& DESC_P_MASK
) ||
492 ((env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf) != 9 ||
495 io_offset
= lduw_kernel(env
->tr
.base
+ 0x66);
496 io_offset
+= (addr
>> 3);
497 /* Note: the check needs two bytes */
498 if ((io_offset
+ 1) > env
->tr
.limit
)
500 val
= lduw_kernel(env
->tr
.base
+ io_offset
);
502 mask
= (1 << size
) - 1;
503 /* all bits must be zero to allow the I/O */
504 if ((val
& mask
) != 0) {
506 raise_exception_err(EXCP0D_GPF
, 0);
510 void check_iob_T0(void)
515 void check_iow_T0(void)
520 void check_iol_T0(void)
525 void check_iob_DX(void)
527 check_io(EDX
& 0xffff, 1);
530 void check_iow_DX(void)
532 check_io(EDX
& 0xffff, 2);
535 void check_iol_DX(void)
537 check_io(EDX
& 0xffff, 4);
540 static inline unsigned int get_sp_mask(unsigned int e2
)
542 if (e2
& DESC_B_MASK
)
549 #define SET_ESP(val, sp_mask)\
551 if ((sp_mask) == 0xffff)\
552 ESP = (ESP & ~0xffff) | ((val) & 0xffff);\
553 else if ((sp_mask) == 0xffffffffLL)\
554 ESP = (uint32_t)(val);\
559 #define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask))
562 /* XXX: add a is_user flag to have proper security support */
563 #define PUSHW(ssp, sp, sp_mask, val)\
566 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
569 #define PUSHL(ssp, sp, sp_mask, val)\
572 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
575 #define POPW(ssp, sp, sp_mask, val)\
577 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
581 #define POPL(ssp, sp, sp_mask, val)\
583 val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
587 /* protected mode interrupt */
588 static void do_interrupt_protected(int intno
, int is_int
, int error_code
,
589 unsigned int next_eip
, int is_hw
)
592 target_ulong ptr
, ssp
;
593 int type
, dpl
, selector
, ss_dpl
, cpl
;
594 int has_error_code
, new_stack
, shift
;
595 uint32_t e1
, e2
, offset
, ss
, esp
, ss_e1
, ss_e2
;
596 uint32_t old_eip
, sp_mask
;
599 if (!is_int
&& !is_hw
) {
618 if (intno
* 8 + 7 > dt
->limit
)
619 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
620 ptr
= dt
->base
+ intno
* 8;
621 e1
= ldl_kernel(ptr
);
622 e2
= ldl_kernel(ptr
+ 4);
623 /* check gate type */
624 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
626 case 5: /* task gate */
627 /* must do that check here to return the correct error code */
628 if (!(e2
& DESC_P_MASK
))
629 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
630 switch_tss(intno
* 8, e1
, e2
, SWITCH_TSS_CALL
, old_eip
);
631 if (has_error_code
) {
634 /* push the error code */
635 type
= (env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf;
637 if (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
641 esp
= (ESP
- (2 << shift
)) & mask
;
642 ssp
= env
->segs
[R_SS
].base
+ esp
;
644 stl_kernel(ssp
, error_code
);
646 stw_kernel(ssp
, error_code
);
650 case 6: /* 286 interrupt gate */
651 case 7: /* 286 trap gate */
652 case 14: /* 386 interrupt gate */
653 case 15: /* 386 trap gate */
656 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
659 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
660 cpl
= env
->hflags
& HF_CPL_MASK
;
661 /* check privledge if software int */
662 if (is_int
&& dpl
< cpl
)
663 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
664 /* check valid bit */
665 if (!(e2
& DESC_P_MASK
))
666 raise_exception_err(EXCP0B_NOSEG
, intno
* 8 + 2);
668 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
669 if ((selector
& 0xfffc) == 0)
670 raise_exception_err(EXCP0D_GPF
, 0);
672 if (load_segment(&e1
, &e2
, selector
) != 0)
673 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
674 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
675 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
676 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
678 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
679 if (!(e2
& DESC_P_MASK
))
680 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
681 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
682 /* to inner privilege */
683 get_ss_esp_from_tss(&ss
, &esp
, dpl
);
684 if ((ss
& 0xfffc) == 0)
685 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
687 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
688 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
689 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
690 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
692 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
693 if (!(ss_e2
& DESC_S_MASK
) ||
694 (ss_e2
& DESC_CS_MASK
) ||
695 !(ss_e2
& DESC_W_MASK
))
696 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
697 if (!(ss_e2
& DESC_P_MASK
))
698 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
700 sp_mask
= get_sp_mask(ss_e2
);
701 ssp
= get_seg_base(ss_e1
, ss_e2
);
702 } else if ((e2
& DESC_C_MASK
) || dpl
== cpl
) {
703 /* to same privilege */
704 if (env
->eflags
& VM_MASK
)
705 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
707 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
708 ssp
= env
->segs
[R_SS
].base
;
712 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
713 new_stack
= 0; /* avoid warning */
714 sp_mask
= 0; /* avoid warning */
715 ssp
= 0; /* avoid warning */
716 esp
= 0; /* avoid warning */
722 /* XXX: check that enough room is available */
723 push_size
= 6 + (new_stack
<< 2) + (has_error_code
<< 1);
724 if (env
->eflags
& VM_MASK
)
730 if (env
->eflags
& VM_MASK
) {
731 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
732 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
733 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
734 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
736 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
737 PUSHL(ssp
, esp
, sp_mask
, ESP
);
739 PUSHL(ssp
, esp
, sp_mask
, compute_eflags());
740 PUSHL(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
741 PUSHL(ssp
, esp
, sp_mask
, old_eip
);
742 if (has_error_code
) {
743 PUSHL(ssp
, esp
, sp_mask
, error_code
);
747 if (env
->eflags
& VM_MASK
) {
748 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_GS
].selector
);
749 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_FS
].selector
);
750 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_DS
].selector
);
751 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_ES
].selector
);
753 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_SS
].selector
);
754 PUSHW(ssp
, esp
, sp_mask
, ESP
);
756 PUSHW(ssp
, esp
, sp_mask
, compute_eflags());
757 PUSHW(ssp
, esp
, sp_mask
, env
->segs
[R_CS
].selector
);
758 PUSHW(ssp
, esp
, sp_mask
, old_eip
);
759 if (has_error_code
) {
760 PUSHW(ssp
, esp
, sp_mask
, error_code
);
765 if (env
->eflags
& VM_MASK
) {
766 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0, 0);
767 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0, 0);
768 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0, 0);
769 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0, 0);
771 ss
= (ss
& ~3) | dpl
;
772 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
773 ssp
, get_seg_limit(ss_e1
, ss_e2
), ss_e2
);
775 SET_ESP(esp
, sp_mask
);
777 selector
= (selector
& ~3) | dpl
;
778 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
779 get_seg_base(e1
, e2
),
780 get_seg_limit(e1
, e2
),
782 cpu_x86_set_cpl(env
, dpl
);
785 /* interrupt gate clear IF mask */
786 if ((type
& 1) == 0) {
787 env
->eflags
&= ~IF_MASK
;
789 env
->eflags
&= ~(TF_MASK
| VM_MASK
| RF_MASK
| NT_MASK
);
794 #define PUSHQ(sp, val)\
797 stq_kernel(sp, (val));\
800 #define POPQ(sp, val)\
802 val = ldq_kernel(sp);\
806 static inline target_ulong
get_rsp_from_tss(int level
)
811 printf("TR: base=" TARGET_FMT_lx
" limit=%x\n",
812 env
->tr
.base
, env
->tr
.limit
);
815 if (!(env
->tr
.flags
& DESC_P_MASK
))
816 cpu_abort(env
, "invalid tss");
817 index
= 8 * level
+ 4;
818 if ((index
+ 7) > env
->tr
.limit
)
819 raise_exception_err(EXCP0A_TSS
, env
->tr
.selector
& 0xfffc);
820 return ldq_kernel(env
->tr
.base
+ index
);
823 /* 64 bit interrupt */
824 static void do_interrupt64(int intno
, int is_int
, int error_code
,
825 target_ulong next_eip
, int is_hw
)
829 int type
, dpl
, selector
, cpl
, ist
;
830 int has_error_code
, new_stack
;
831 uint32_t e1
, e2
, e3
, ss
;
832 target_ulong old_eip
, esp
, offset
;
835 if (!is_int
&& !is_hw
) {
854 if (intno
* 16 + 15 > dt
->limit
)
855 raise_exception_err(EXCP0D_GPF
, intno
* 16 + 2);
856 ptr
= dt
->base
+ intno
* 16;
857 e1
= ldl_kernel(ptr
);
858 e2
= ldl_kernel(ptr
+ 4);
859 e3
= ldl_kernel(ptr
+ 8);
860 /* check gate type */
861 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
863 case 14: /* 386 interrupt gate */
864 case 15: /* 386 trap gate */
867 raise_exception_err(EXCP0D_GPF
, intno
* 16 + 2);
870 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
871 cpl
= env
->hflags
& HF_CPL_MASK
;
872 /* check privledge if software int */
873 if (is_int
&& dpl
< cpl
)
874 raise_exception_err(EXCP0D_GPF
, intno
* 16 + 2);
875 /* check valid bit */
876 if (!(e2
& DESC_P_MASK
))
877 raise_exception_err(EXCP0B_NOSEG
, intno
* 16 + 2);
879 offset
= ((target_ulong
)e3
<< 32) | (e2
& 0xffff0000) | (e1
& 0x0000ffff);
881 if ((selector
& 0xfffc) == 0)
882 raise_exception_err(EXCP0D_GPF
, 0);
884 if (load_segment(&e1
, &e2
, selector
) != 0)
885 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
886 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
887 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
888 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
890 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
891 if (!(e2
& DESC_P_MASK
))
892 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
893 if (!(e2
& DESC_L_MASK
) || (e2
& DESC_B_MASK
))
894 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
895 if ((!(e2
& DESC_C_MASK
) && dpl
< cpl
) || ist
!= 0) {
896 /* to inner privilege */
898 esp
= get_rsp_from_tss(ist
+ 3);
900 esp
= get_rsp_from_tss(dpl
);
901 esp
&= ~0xfLL
; /* align stack */
904 } else if ((e2
& DESC_C_MASK
) || dpl
== cpl
) {
905 /* to same privilege */
906 if (env
->eflags
& VM_MASK
)
907 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
910 esp
= get_rsp_from_tss(ist
+ 3);
913 esp
&= ~0xfLL
; /* align stack */
916 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
917 new_stack
= 0; /* avoid warning */
918 esp
= 0; /* avoid warning */
921 PUSHQ(esp
, env
->segs
[R_SS
].selector
);
923 PUSHQ(esp
, compute_eflags());
924 PUSHQ(esp
, env
->segs
[R_CS
].selector
);
926 if (has_error_code
) {
927 PUSHQ(esp
, error_code
);
932 cpu_x86_load_seg_cache(env
, R_SS
, ss
, 0, 0, 0);
936 selector
= (selector
& ~3) | dpl
;
937 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
938 get_seg_base(e1
, e2
),
939 get_seg_limit(e1
, e2
),
941 cpu_x86_set_cpl(env
, dpl
);
944 /* interrupt gate clear IF mask */
945 if ((type
& 1) == 0) {
946 env
->eflags
&= ~IF_MASK
;
948 env
->eflags
&= ~(TF_MASK
| VM_MASK
| RF_MASK
| NT_MASK
);
952 void helper_syscall(int next_eip_addend
)
956 if (!(env
->efer
& MSR_EFER_SCE
)) {
957 raise_exception_err(EXCP06_ILLOP
, 0);
959 selector
= (env
->star
>> 32) & 0xffff;
961 if (env
->hflags
& HF_LMA_MASK
) {
964 ECX
= env
->eip
+ next_eip_addend
;
965 env
->regs
[11] = compute_eflags();
967 code64
= env
->hflags
& HF_CS64_MASK
;
969 cpu_x86_set_cpl(env
, 0);
970 cpu_x86_load_seg_cache(env
, R_CS
, selector
& 0xfffc,
972 DESC_G_MASK
| DESC_P_MASK
|
974 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
| DESC_L_MASK
);
975 cpu_x86_load_seg_cache(env
, R_SS
, (selector
+ 8) & 0xfffc,
977 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
979 DESC_W_MASK
| DESC_A_MASK
);
980 env
->eflags
&= ~env
->fmask
;
982 env
->eip
= env
->lstar
;
984 env
->eip
= env
->cstar
;
988 ECX
= (uint32_t)(env
->eip
+ next_eip_addend
);
990 cpu_x86_set_cpl(env
, 0);
991 cpu_x86_load_seg_cache(env
, R_CS
, selector
& 0xfffc,
993 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
995 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
996 cpu_x86_load_seg_cache(env
, R_SS
, (selector
+ 8) & 0xfffc,
998 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
1000 DESC_W_MASK
| DESC_A_MASK
);
1001 env
->eflags
&= ~(IF_MASK
| RF_MASK
| VM_MASK
);
1002 env
->eip
= (uint32_t)env
->star
;
1006 void helper_sysret(int dflag
)
1010 if (!(env
->efer
& MSR_EFER_SCE
)) {
1011 raise_exception_err(EXCP06_ILLOP
, 0);
1013 cpl
= env
->hflags
& HF_CPL_MASK
;
1014 if (!(env
->cr
[0] & CR0_PE_MASK
) || cpl
!= 0) {
1015 raise_exception_err(EXCP0D_GPF
, 0);
1017 selector
= (env
->star
>> 48) & 0xffff;
1018 #ifdef TARGET_X86_64
1019 if (env
->hflags
& HF_LMA_MASK
) {
1021 cpu_x86_load_seg_cache(env
, R_CS
, (selector
+ 16) | 3,
1023 DESC_G_MASK
| DESC_P_MASK
|
1024 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1025 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
|
1029 cpu_x86_load_seg_cache(env
, R_CS
, selector
| 3,
1031 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
1032 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1033 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
1034 env
->eip
= (uint32_t)ECX
;
1036 cpu_x86_load_seg_cache(env
, R_SS
, selector
+ 8,
1038 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
1039 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1040 DESC_W_MASK
| DESC_A_MASK
);
1041 load_eflags((uint32_t)(env
->regs
[11]), TF_MASK
| AC_MASK
| ID_MASK
|
1042 IF_MASK
| IOPL_MASK
| VM_MASK
| RF_MASK
| NT_MASK
);
1043 cpu_x86_set_cpl(env
, 3);
1047 cpu_x86_load_seg_cache(env
, R_CS
, selector
| 3,
1049 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
1050 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1051 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
1052 env
->eip
= (uint32_t)ECX
;
1053 cpu_x86_load_seg_cache(env
, R_SS
, selector
+ 8,
1055 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
1056 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
1057 DESC_W_MASK
| DESC_A_MASK
);
1058 env
->eflags
|= IF_MASK
;
1059 cpu_x86_set_cpl(env
, 3);
1062 if (kqemu_is_ok(env
)) {
1063 if (env
->hflags
& HF_LMA_MASK
)
1064 CC_OP
= CC_OP_EFLAGS
;
1065 env
->exception_index
= -1;
1071 /* real mode interrupt */
1072 static void do_interrupt_real(int intno
, int is_int
, int error_code
,
1073 unsigned int next_eip
)
1076 target_ulong ptr
, ssp
;
1078 uint32_t offset
, esp
;
1079 uint32_t old_cs
, old_eip
;
1081 /* real mode (simpler !) */
1083 if (intno
* 4 + 3 > dt
->limit
)
1084 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
1085 ptr
= dt
->base
+ intno
* 4;
1086 offset
= lduw_kernel(ptr
);
1087 selector
= lduw_kernel(ptr
+ 2);
1089 ssp
= env
->segs
[R_SS
].base
;
1094 old_cs
= env
->segs
[R_CS
].selector
;
1095 /* XXX: use SS segment size ? */
1096 PUSHW(ssp
, esp
, 0xffff, compute_eflags());
1097 PUSHW(ssp
, esp
, 0xffff, old_cs
);
1098 PUSHW(ssp
, esp
, 0xffff, old_eip
);
1100 /* update processor state */
1101 ESP
= (ESP
& ~0xffff) | (esp
& 0xffff);
1103 env
->segs
[R_CS
].selector
= selector
;
1104 env
->segs
[R_CS
].base
= (selector
<< 4);
1105 env
->eflags
&= ~(IF_MASK
| TF_MASK
| AC_MASK
| RF_MASK
);
1108 /* fake user mode interrupt */
1109 void do_interrupt_user(int intno
, int is_int
, int error_code
,
1110 target_ulong next_eip
)
1118 ptr
= dt
->base
+ (intno
* 8);
1119 e2
= ldl_kernel(ptr
+ 4);
1121 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1122 cpl
= env
->hflags
& HF_CPL_MASK
;
1123 /* check privledge if software int */
1124 if (is_int
&& dpl
< cpl
)
1125 raise_exception_err(EXCP0D_GPF
, intno
* 8 + 2);
1127 /* Since we emulate only user space, we cannot do more than
1128 exiting the emulation with the suitable exception and error
1135 * Begin execution of an interruption. is_int is TRUE if coming from
1136 * the int instruction. next_eip is the EIP value AFTER the interrupt
1137 * instruction. It is only relevant if is_int is TRUE.
1139 void do_interrupt(int intno
, int is_int
, int error_code
,
1140 target_ulong next_eip
, int is_hw
)
1142 if (loglevel
& CPU_LOG_INT
) {
1143 if ((env
->cr
[0] & CR0_PE_MASK
)) {
1145 fprintf(logfile
, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
" pc=" TARGET_FMT_lx
" SP=%04x:" TARGET_FMT_lx
,
1146 count
, intno
, error_code
, is_int
,
1147 env
->hflags
& HF_CPL_MASK
,
1148 env
->segs
[R_CS
].selector
, EIP
,
1149 (int)env
->segs
[R_CS
].base
+ EIP
,
1150 env
->segs
[R_SS
].selector
, ESP
);
1151 if (intno
== 0x0e) {
1152 fprintf(logfile
, " CR2=" TARGET_FMT_lx
, env
->cr
[2]);
1154 fprintf(logfile
, " EAX=" TARGET_FMT_lx
, EAX
);
1156 fprintf(logfile
, "\n");
1157 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
1162 fprintf(logfile
, " code=");
1163 ptr
= env
->segs
[R_CS
].base
+ env
->eip
;
1164 for(i
= 0; i
< 16; i
++) {
1165 fprintf(logfile
, " %02x", ldub(ptr
+ i
));
1167 fprintf(logfile
, "\n");
1173 if (env
->cr
[0] & CR0_PE_MASK
) {
1175 if (env
->hflags
& HF_LMA_MASK
) {
1176 do_interrupt64(intno
, is_int
, error_code
, next_eip
, is_hw
);
1180 do_interrupt_protected(intno
, is_int
, error_code
, next_eip
, is_hw
);
1183 do_interrupt_real(intno
, is_int
, error_code
, next_eip
);
1188 * Check nested exceptions and change to double or triple fault if
1189 * needed. It should only be called, if this is not an interrupt.
1190 * Returns the new exception number.
1192 int check_exception(int intno
, int *error_code
)
1194 char first_contributory
= env
->old_exception
== 0 ||
1195 (env
->old_exception
>= 10 &&
1196 env
->old_exception
<= 13);
1197 char second_contributory
= intno
== 0 ||
1198 (intno
>= 10 && intno
<= 13);
1200 if (loglevel
& CPU_LOG_INT
)
1201 fprintf(logfile
, "check_exception old: %x new %x\n",
1202 env
->old_exception
, intno
);
1204 if (env
->old_exception
== EXCP08_DBLE
)
1205 cpu_abort(env
, "triple fault");
1207 if ((first_contributory
&& second_contributory
)
1208 || (env
->old_exception
== EXCP0E_PAGE
&&
1209 (second_contributory
|| (intno
== EXCP0E_PAGE
)))) {
1210 intno
= EXCP08_DBLE
;
1214 if (second_contributory
|| (intno
== EXCP0E_PAGE
) ||
1215 (intno
== EXCP08_DBLE
))
1216 env
->old_exception
= intno
;
1222 * Signal an interruption. It is executed in the main CPU loop.
1223 * is_int is TRUE if coming from the int instruction. next_eip is the
1224 * EIP value AFTER the interrupt instruction. It is only relevant if
1227 void raise_interrupt(int intno
, int is_int
, int error_code
,
1228 int next_eip_addend
)
1231 intno
= check_exception(intno
, &error_code
);
1233 env
->exception_index
= intno
;
1234 env
->error_code
= error_code
;
1235 env
->exception_is_int
= is_int
;
1236 env
->exception_next_eip
= env
->eip
+ next_eip_addend
;
1240 /* same as raise_exception_err, but do not restore global registers */
1241 static void raise_exception_err_norestore(int exception_index
, int error_code
)
1243 exception_index
= check_exception(exception_index
, &error_code
);
1245 env
->exception_index
= exception_index
;
1246 env
->error_code
= error_code
;
1247 env
->exception_is_int
= 0;
1248 env
->exception_next_eip
= 0;
1249 longjmp(env
->jmp_env
, 1);
1252 /* shortcuts to generate exceptions */
1254 void (raise_exception_err
)(int exception_index
, int error_code
)
1256 raise_interrupt(exception_index
, 0, error_code
, 0);
1259 void raise_exception(int exception_index
)
1261 raise_interrupt(exception_index
, 0, 0, 0);
1266 #if defined(CONFIG_USER_ONLY)
1268 void do_smm_enter(void)
1272 void helper_rsm(void)
1278 #ifdef TARGET_X86_64
1279 #define SMM_REVISION_ID 0x00020064
1281 #define SMM_REVISION_ID 0x00020000
1284 void do_smm_enter(void)
1286 target_ulong sm_state
;
1290 if (loglevel
& CPU_LOG_INT
) {
1291 fprintf(logfile
, "SMM: enter\n");
1292 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
1295 env
->hflags
|= HF_SMM_MASK
;
1296 cpu_smm_update(env
);
1298 sm_state
= env
->smbase
+ 0x8000;
1300 #ifdef TARGET_X86_64
1301 for(i
= 0; i
< 6; i
++) {
1303 offset
= 0x7e00 + i
* 16;
1304 stw_phys(sm_state
+ offset
, dt
->selector
);
1305 stw_phys(sm_state
+ offset
+ 2, (dt
->flags
>> 8) & 0xf0ff);
1306 stl_phys(sm_state
+ offset
+ 4, dt
->limit
);
1307 stq_phys(sm_state
+ offset
+ 8, dt
->base
);
1310 stq_phys(sm_state
+ 0x7e68, env
->gdt
.base
);
1311 stl_phys(sm_state
+ 0x7e64, env
->gdt
.limit
);
1313 stw_phys(sm_state
+ 0x7e70, env
->ldt
.selector
);
1314 stq_phys(sm_state
+ 0x7e78, env
->ldt
.base
);
1315 stl_phys(sm_state
+ 0x7e74, env
->ldt
.limit
);
1316 stw_phys(sm_state
+ 0x7e72, (env
->ldt
.flags
>> 8) & 0xf0ff);
1318 stq_phys(sm_state
+ 0x7e88, env
->idt
.base
);
1319 stl_phys(sm_state
+ 0x7e84, env
->idt
.limit
);
1321 stw_phys(sm_state
+ 0x7e90, env
->tr
.selector
);
1322 stq_phys(sm_state
+ 0x7e98, env
->tr
.base
);
1323 stl_phys(sm_state
+ 0x7e94, env
->tr
.limit
);
1324 stw_phys(sm_state
+ 0x7e92, (env
->tr
.flags
>> 8) & 0xf0ff);
1326 stq_phys(sm_state
+ 0x7ed0, env
->efer
);
1328 stq_phys(sm_state
+ 0x7ff8, EAX
);
1329 stq_phys(sm_state
+ 0x7ff0, ECX
);
1330 stq_phys(sm_state
+ 0x7fe8, EDX
);
1331 stq_phys(sm_state
+ 0x7fe0, EBX
);
1332 stq_phys(sm_state
+ 0x7fd8, ESP
);
1333 stq_phys(sm_state
+ 0x7fd0, EBP
);
1334 stq_phys(sm_state
+ 0x7fc8, ESI
);
1335 stq_phys(sm_state
+ 0x7fc0, EDI
);
1336 for(i
= 8; i
< 16; i
++)
1337 stq_phys(sm_state
+ 0x7ff8 - i
* 8, env
->regs
[i
]);
1338 stq_phys(sm_state
+ 0x7f78, env
->eip
);
1339 stl_phys(sm_state
+ 0x7f70, compute_eflags());
1340 stl_phys(sm_state
+ 0x7f68, env
->dr
[6]);
1341 stl_phys(sm_state
+ 0x7f60, env
->dr
[7]);
1343 stl_phys(sm_state
+ 0x7f48, env
->cr
[4]);
1344 stl_phys(sm_state
+ 0x7f50, env
->cr
[3]);
1345 stl_phys(sm_state
+ 0x7f58, env
->cr
[0]);
1347 stl_phys(sm_state
+ 0x7efc, SMM_REVISION_ID
);
1348 stl_phys(sm_state
+ 0x7f00, env
->smbase
);
1350 stl_phys(sm_state
+ 0x7ffc, env
->cr
[0]);
1351 stl_phys(sm_state
+ 0x7ff8, env
->cr
[3]);
1352 stl_phys(sm_state
+ 0x7ff4, compute_eflags());
1353 stl_phys(sm_state
+ 0x7ff0, env
->eip
);
1354 stl_phys(sm_state
+ 0x7fec, EDI
);
1355 stl_phys(sm_state
+ 0x7fe8, ESI
);
1356 stl_phys(sm_state
+ 0x7fe4, EBP
);
1357 stl_phys(sm_state
+ 0x7fe0, ESP
);
1358 stl_phys(sm_state
+ 0x7fdc, EBX
);
1359 stl_phys(sm_state
+ 0x7fd8, EDX
);
1360 stl_phys(sm_state
+ 0x7fd4, ECX
);
1361 stl_phys(sm_state
+ 0x7fd0, EAX
);
1362 stl_phys(sm_state
+ 0x7fcc, env
->dr
[6]);
1363 stl_phys(sm_state
+ 0x7fc8, env
->dr
[7]);
1365 stl_phys(sm_state
+ 0x7fc4, env
->tr
.selector
);
1366 stl_phys(sm_state
+ 0x7f64, env
->tr
.base
);
1367 stl_phys(sm_state
+ 0x7f60, env
->tr
.limit
);
1368 stl_phys(sm_state
+ 0x7f5c, (env
->tr
.flags
>> 8) & 0xf0ff);
1370 stl_phys(sm_state
+ 0x7fc0, env
->ldt
.selector
);
1371 stl_phys(sm_state
+ 0x7f80, env
->ldt
.base
);
1372 stl_phys(sm_state
+ 0x7f7c, env
->ldt
.limit
);
1373 stl_phys(sm_state
+ 0x7f78, (env
->ldt
.flags
>> 8) & 0xf0ff);
1375 stl_phys(sm_state
+ 0x7f74, env
->gdt
.base
);
1376 stl_phys(sm_state
+ 0x7f70, env
->gdt
.limit
);
1378 stl_phys(sm_state
+ 0x7f58, env
->idt
.base
);
1379 stl_phys(sm_state
+ 0x7f54, env
->idt
.limit
);
1381 for(i
= 0; i
< 6; i
++) {
1384 offset
= 0x7f84 + i
* 12;
1386 offset
= 0x7f2c + (i
- 3) * 12;
1387 stl_phys(sm_state
+ 0x7fa8 + i
* 4, dt
->selector
);
1388 stl_phys(sm_state
+ offset
+ 8, dt
->base
);
1389 stl_phys(sm_state
+ offset
+ 4, dt
->limit
);
1390 stl_phys(sm_state
+ offset
, (dt
->flags
>> 8) & 0xf0ff);
1392 stl_phys(sm_state
+ 0x7f14, env
->cr
[4]);
1394 stl_phys(sm_state
+ 0x7efc, SMM_REVISION_ID
);
1395 stl_phys(sm_state
+ 0x7ef8, env
->smbase
);
1397 /* init SMM cpu state */
1399 #ifdef TARGET_X86_64
1401 env
->hflags
&= ~HF_LMA_MASK
;
1403 load_eflags(0, ~(CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
| DF_MASK
));
1404 env
->eip
= 0x00008000;
1405 cpu_x86_load_seg_cache(env
, R_CS
, (env
->smbase
>> 4) & 0xffff, env
->smbase
,
1407 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffffffff, 0);
1408 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffffffff, 0);
1409 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffffffff, 0);
1410 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffffffff, 0);
1411 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffffffff, 0);
1413 cpu_x86_update_cr0(env
,
1414 env
->cr
[0] & ~(CR0_PE_MASK
| CR0_EM_MASK
| CR0_TS_MASK
| CR0_PG_MASK
));
1415 cpu_x86_update_cr4(env
, 0);
1416 env
->dr
[7] = 0x00000400;
1417 CC_OP
= CC_OP_EFLAGS
;
1420 void helper_rsm(void)
1422 target_ulong sm_state
;
1426 sm_state
= env
->smbase
+ 0x8000;
1427 #ifdef TARGET_X86_64
1428 env
->efer
= ldq_phys(sm_state
+ 0x7ed0);
1429 if (env
->efer
& MSR_EFER_LMA
)
1430 env
->hflags
|= HF_LMA_MASK
;
1432 env
->hflags
&= ~HF_LMA_MASK
;
1434 for(i
= 0; i
< 6; i
++) {
1435 offset
= 0x7e00 + i
* 16;
1436 cpu_x86_load_seg_cache(env
, i
,
1437 lduw_phys(sm_state
+ offset
),
1438 ldq_phys(sm_state
+ offset
+ 8),
1439 ldl_phys(sm_state
+ offset
+ 4),
1440 (lduw_phys(sm_state
+ offset
+ 2) & 0xf0ff) << 8);
1443 env
->gdt
.base
= ldq_phys(sm_state
+ 0x7e68);
1444 env
->gdt
.limit
= ldl_phys(sm_state
+ 0x7e64);
1446 env
->ldt
.selector
= lduw_phys(sm_state
+ 0x7e70);
1447 env
->ldt
.base
= ldq_phys(sm_state
+ 0x7e78);
1448 env
->ldt
.limit
= ldl_phys(sm_state
+ 0x7e74);
1449 env
->ldt
.flags
= (lduw_phys(sm_state
+ 0x7e72) & 0xf0ff) << 8;
1451 env
->idt
.base
= ldq_phys(sm_state
+ 0x7e88);
1452 env
->idt
.limit
= ldl_phys(sm_state
+ 0x7e84);
1454 env
->tr
.selector
= lduw_phys(sm_state
+ 0x7e90);
1455 env
->tr
.base
= ldq_phys(sm_state
+ 0x7e98);
1456 env
->tr
.limit
= ldl_phys(sm_state
+ 0x7e94);
1457 env
->tr
.flags
= (lduw_phys(sm_state
+ 0x7e92) & 0xf0ff) << 8;
1459 EAX
= ldq_phys(sm_state
+ 0x7ff8);
1460 ECX
= ldq_phys(sm_state
+ 0x7ff0);
1461 EDX
= ldq_phys(sm_state
+ 0x7fe8);
1462 EBX
= ldq_phys(sm_state
+ 0x7fe0);
1463 ESP
= ldq_phys(sm_state
+ 0x7fd8);
1464 EBP
= ldq_phys(sm_state
+ 0x7fd0);
1465 ESI
= ldq_phys(sm_state
+ 0x7fc8);
1466 EDI
= ldq_phys(sm_state
+ 0x7fc0);
1467 for(i
= 8; i
< 16; i
++)
1468 env
->regs
[i
] = ldq_phys(sm_state
+ 0x7ff8 - i
* 8);
1469 env
->eip
= ldq_phys(sm_state
+ 0x7f78);
1470 load_eflags(ldl_phys(sm_state
+ 0x7f70),
1471 ~(CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
| DF_MASK
));
1472 env
->dr
[6] = ldl_phys(sm_state
+ 0x7f68);
1473 env
->dr
[7] = ldl_phys(sm_state
+ 0x7f60);
1475 cpu_x86_update_cr4(env
, ldl_phys(sm_state
+ 0x7f48));
1476 cpu_x86_update_cr3(env
, ldl_phys(sm_state
+ 0x7f50));
1477 cpu_x86_update_cr0(env
, ldl_phys(sm_state
+ 0x7f58));
1479 val
= ldl_phys(sm_state
+ 0x7efc); /* revision ID */
1480 if (val
& 0x20000) {
1481 env
->smbase
= ldl_phys(sm_state
+ 0x7f00) & ~0x7fff;
1484 cpu_x86_update_cr0(env
, ldl_phys(sm_state
+ 0x7ffc));
1485 cpu_x86_update_cr3(env
, ldl_phys(sm_state
+ 0x7ff8));
1486 load_eflags(ldl_phys(sm_state
+ 0x7ff4),
1487 ~(CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
| DF_MASK
));
1488 env
->eip
= ldl_phys(sm_state
+ 0x7ff0);
1489 EDI
= ldl_phys(sm_state
+ 0x7fec);
1490 ESI
= ldl_phys(sm_state
+ 0x7fe8);
1491 EBP
= ldl_phys(sm_state
+ 0x7fe4);
1492 ESP
= ldl_phys(sm_state
+ 0x7fe0);
1493 EBX
= ldl_phys(sm_state
+ 0x7fdc);
1494 EDX
= ldl_phys(sm_state
+ 0x7fd8);
1495 ECX
= ldl_phys(sm_state
+ 0x7fd4);
1496 EAX
= ldl_phys(sm_state
+ 0x7fd0);
1497 env
->dr
[6] = ldl_phys(sm_state
+ 0x7fcc);
1498 env
->dr
[7] = ldl_phys(sm_state
+ 0x7fc8);
1500 env
->tr
.selector
= ldl_phys(sm_state
+ 0x7fc4) & 0xffff;
1501 env
->tr
.base
= ldl_phys(sm_state
+ 0x7f64);
1502 env
->tr
.limit
= ldl_phys(sm_state
+ 0x7f60);
1503 env
->tr
.flags
= (ldl_phys(sm_state
+ 0x7f5c) & 0xf0ff) << 8;
1505 env
->ldt
.selector
= ldl_phys(sm_state
+ 0x7fc0) & 0xffff;
1506 env
->ldt
.base
= ldl_phys(sm_state
+ 0x7f80);
1507 env
->ldt
.limit
= ldl_phys(sm_state
+ 0x7f7c);
1508 env
->ldt
.flags
= (ldl_phys(sm_state
+ 0x7f78) & 0xf0ff) << 8;
1510 env
->gdt
.base
= ldl_phys(sm_state
+ 0x7f74);
1511 env
->gdt
.limit
= ldl_phys(sm_state
+ 0x7f70);
1513 env
->idt
.base
= ldl_phys(sm_state
+ 0x7f58);
1514 env
->idt
.limit
= ldl_phys(sm_state
+ 0x7f54);
1516 for(i
= 0; i
< 6; i
++) {
1518 offset
= 0x7f84 + i
* 12;
1520 offset
= 0x7f2c + (i
- 3) * 12;
1521 cpu_x86_load_seg_cache(env
, i
,
1522 ldl_phys(sm_state
+ 0x7fa8 + i
* 4) & 0xffff,
1523 ldl_phys(sm_state
+ offset
+ 8),
1524 ldl_phys(sm_state
+ offset
+ 4),
1525 (ldl_phys(sm_state
+ offset
) & 0xf0ff) << 8);
1527 cpu_x86_update_cr4(env
, ldl_phys(sm_state
+ 0x7f14));
1529 val
= ldl_phys(sm_state
+ 0x7efc); /* revision ID */
1530 if (val
& 0x20000) {
1531 env
->smbase
= ldl_phys(sm_state
+ 0x7ef8) & ~0x7fff;
1534 CC_OP
= CC_OP_EFLAGS
;
1535 env
->hflags
&= ~HF_SMM_MASK
;
1536 cpu_smm_update(env
);
1538 if (loglevel
& CPU_LOG_INT
) {
1539 fprintf(logfile
, "SMM: after RSM\n");
1540 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
1544 #endif /* !CONFIG_USER_ONLY */
1547 #ifdef BUGGY_GCC_DIV64
1548 /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1549 call it from another function */
1550 uint32_t div32(uint64_t *q_ptr
, uint64_t num
, uint32_t den
)
1556 int32_t idiv32(int64_t *q_ptr
, int64_t num
, int32_t den
)
1563 void helper_divl_EAX_T0(void)
1565 unsigned int den
, r
;
1568 num
= ((uint32_t)EAX
) | ((uint64_t)((uint32_t)EDX
) << 32);
1571 raise_exception(EXCP00_DIVZ
);
1573 #ifdef BUGGY_GCC_DIV64
1574 r
= div32(&q
, num
, den
);
1580 raise_exception(EXCP00_DIVZ
);
1585 void helper_idivl_EAX_T0(void)
1590 num
= ((uint32_t)EAX
) | ((uint64_t)((uint32_t)EDX
) << 32);
1593 raise_exception(EXCP00_DIVZ
);
1595 #ifdef BUGGY_GCC_DIV64
1596 r
= idiv32(&q
, num
, den
);
1601 if (q
!= (int32_t)q
)
1602 raise_exception(EXCP00_DIVZ
);
1607 void helper_cmpxchg8b(void)
1612 eflags
= cc_table
[CC_OP
].compute_all();
1614 if (d
== (((uint64_t)EDX
<< 32) | EAX
)) {
1615 stq(A0
, ((uint64_t)ECX
<< 32) | EBX
);
1625 void helper_single_step()
1627 env
->dr
[6] |= 0x4000;
1628 raise_exception(EXCP01_SSTP
);
1631 void helper_cpuid(void)
1634 index
= (uint32_t)EAX
;
1636 /* test if maximum index reached */
1637 if (index
& 0x80000000) {
1638 if (index
> env
->cpuid_xlevel
)
1639 index
= env
->cpuid_level
;
1641 if (index
> env
->cpuid_level
)
1642 index
= env
->cpuid_level
;
1647 EAX
= env
->cpuid_level
;
1648 EBX
= env
->cpuid_vendor1
;
1649 EDX
= env
->cpuid_vendor2
;
1650 ECX
= env
->cpuid_vendor3
;
1653 EAX
= env
->cpuid_version
;
1654 EBX
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1655 ECX
= env
->cpuid_ext_features
;
1656 EDX
= env
->cpuid_features
;
1659 /* cache info: needed for Pentium Pro compatibility */
1666 EAX
= env
->cpuid_xlevel
;
1667 EBX
= env
->cpuid_vendor1
;
1668 EDX
= env
->cpuid_vendor2
;
1669 ECX
= env
->cpuid_vendor3
;
1672 EAX
= env
->cpuid_features
;
1675 EDX
= env
->cpuid_ext2_features
;
1680 EAX
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
1681 EBX
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
1682 ECX
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
1683 EDX
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
1686 /* cache info (L1 cache) */
1693 /* cache info (L2 cache) */
1700 /* virtual & phys address size in low 2 bytes. */
1707 /* reserved values: zero */
1716 void helper_enter_level(int level
, int data32
)
1719 uint32_t esp_mask
, esp
, ebp
;
1721 esp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
1722 ssp
= env
->segs
[R_SS
].base
;
1731 stl(ssp
+ (esp
& esp_mask
), ldl(ssp
+ (ebp
& esp_mask
)));
1734 stl(ssp
+ (esp
& esp_mask
), T1
);
1741 stw(ssp
+ (esp
& esp_mask
), lduw(ssp
+ (ebp
& esp_mask
)));
1744 stw(ssp
+ (esp
& esp_mask
), T1
);
1748 #ifdef TARGET_X86_64
1749 void helper_enter64_level(int level
, int data64
)
1751 target_ulong esp
, ebp
;
1771 stw(esp
, lduw(ebp
));
1779 void helper_lldt_T0(void)
1784 int index
, entry_limit
;
1787 selector
= T0
& 0xffff;
1788 if ((selector
& 0xfffc) == 0) {
1789 /* XXX: NULL selector case: invalid LDT */
1794 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1796 index
= selector
& ~7;
1797 #ifdef TARGET_X86_64
1798 if (env
->hflags
& HF_LMA_MASK
)
1803 if ((index
+ entry_limit
) > dt
->limit
)
1804 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1805 ptr
= dt
->base
+ index
;
1806 e1
= ldl_kernel(ptr
);
1807 e2
= ldl_kernel(ptr
+ 4);
1808 if ((e2
& DESC_S_MASK
) || ((e2
>> DESC_TYPE_SHIFT
) & 0xf) != 2)
1809 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1810 if (!(e2
& DESC_P_MASK
))
1811 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1812 #ifdef TARGET_X86_64
1813 if (env
->hflags
& HF_LMA_MASK
) {
1815 e3
= ldl_kernel(ptr
+ 8);
1816 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
1817 env
->ldt
.base
|= (target_ulong
)e3
<< 32;
1821 load_seg_cache_raw_dt(&env
->ldt
, e1
, e2
);
1824 env
->ldt
.selector
= selector
;
1827 void helper_ltr_T0(void)
1832 int index
, type
, entry_limit
;
1835 selector
= T0
& 0xffff;
1836 if ((selector
& 0xfffc) == 0) {
1837 /* NULL selector case: invalid TR */
1843 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1845 index
= selector
& ~7;
1846 #ifdef TARGET_X86_64
1847 if (env
->hflags
& HF_LMA_MASK
)
1852 if ((index
+ entry_limit
) > dt
->limit
)
1853 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1854 ptr
= dt
->base
+ index
;
1855 e1
= ldl_kernel(ptr
);
1856 e2
= ldl_kernel(ptr
+ 4);
1857 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
1858 if ((e2
& DESC_S_MASK
) ||
1859 (type
!= 1 && type
!= 9))
1860 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1861 if (!(e2
& DESC_P_MASK
))
1862 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1863 #ifdef TARGET_X86_64
1864 if (env
->hflags
& HF_LMA_MASK
) {
1866 e3
= ldl_kernel(ptr
+ 8);
1867 e4
= ldl_kernel(ptr
+ 12);
1868 if ((e4
>> DESC_TYPE_SHIFT
) & 0xf)
1869 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1870 load_seg_cache_raw_dt(&env
->tr
, e1
, e2
);
1871 env
->tr
.base
|= (target_ulong
)e3
<< 32;
1875 load_seg_cache_raw_dt(&env
->tr
, e1
, e2
);
1877 e2
|= DESC_TSS_BUSY_MASK
;
1878 stl_kernel(ptr
+ 4, e2
);
1880 env
->tr
.selector
= selector
;
1883 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1884 void load_seg(int seg_reg
, int selector
)
1893 cpl
= env
->hflags
& HF_CPL_MASK
;
1894 if ((selector
& 0xfffc) == 0) {
1895 /* null selector case */
1897 #ifdef TARGET_X86_64
1898 && (!(env
->hflags
& HF_CS64_MASK
) || cpl
== 3)
1901 raise_exception_err(EXCP0D_GPF
, 0);
1902 cpu_x86_load_seg_cache(env
, seg_reg
, selector
, 0, 0, 0);
1909 index
= selector
& ~7;
1910 if ((index
+ 7) > dt
->limit
)
1911 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1912 ptr
= dt
->base
+ index
;
1913 e1
= ldl_kernel(ptr
);
1914 e2
= ldl_kernel(ptr
+ 4);
1916 if (!(e2
& DESC_S_MASK
))
1917 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1919 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1920 if (seg_reg
== R_SS
) {
1921 /* must be writable segment */
1922 if ((e2
& DESC_CS_MASK
) || !(e2
& DESC_W_MASK
))
1923 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1924 if (rpl
!= cpl
|| dpl
!= cpl
)
1925 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1927 /* must be readable segment */
1928 if ((e2
& (DESC_CS_MASK
| DESC_R_MASK
)) == DESC_CS_MASK
)
1929 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1931 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
1932 /* if not conforming code, test rights */
1933 if (dpl
< cpl
|| dpl
< rpl
)
1934 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
1938 if (!(e2
& DESC_P_MASK
)) {
1939 if (seg_reg
== R_SS
)
1940 raise_exception_err(EXCP0C_STACK
, selector
& 0xfffc);
1942 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
1945 /* set the access bit if not already set */
1946 if (!(e2
& DESC_A_MASK
)) {
1948 stl_kernel(ptr
+ 4, e2
);
1951 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
1952 get_seg_base(e1
, e2
),
1953 get_seg_limit(e1
, e2
),
1956 fprintf(logfile
, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1957 selector
, (unsigned long)sc
->base
, sc
->limit
, sc
->flags
);
1962 /* protected mode jump */
1963 void helper_ljmp_protected_T0_T1(int next_eip_addend
)
1965 int new_cs
, gate_cs
, type
;
1966 uint32_t e1
, e2
, cpl
, dpl
, rpl
, limit
;
1967 target_ulong new_eip
, next_eip
;
1971 if ((new_cs
& 0xfffc) == 0)
1972 raise_exception_err(EXCP0D_GPF
, 0);
1973 if (load_segment(&e1
, &e2
, new_cs
) != 0)
1974 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1975 cpl
= env
->hflags
& HF_CPL_MASK
;
1976 if (e2
& DESC_S_MASK
) {
1977 if (!(e2
& DESC_CS_MASK
))
1978 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1979 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
1980 if (e2
& DESC_C_MASK
) {
1981 /* conforming code segment */
1983 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1985 /* non conforming code segment */
1988 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1990 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1992 if (!(e2
& DESC_P_MASK
))
1993 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
1994 limit
= get_seg_limit(e1
, e2
);
1995 if (new_eip
> limit
&&
1996 !(env
->hflags
& HF_LMA_MASK
) && !(e2
& DESC_L_MASK
))
1997 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
1998 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
1999 get_seg_base(e1
, e2
), limit
, e2
);
2002 /* jump to call or task gate */
2003 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2005 cpl
= env
->hflags
& HF_CPL_MASK
;
2006 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
2008 case 1: /* 286 TSS */
2009 case 9: /* 386 TSS */
2010 case 5: /* task gate */
2011 if (dpl
< cpl
|| dpl
< rpl
)
2012 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2013 next_eip
= env
->eip
+ next_eip_addend
;
2014 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_JMP
, next_eip
);
2015 CC_OP
= CC_OP_EFLAGS
;
2017 case 4: /* 286 call gate */
2018 case 12: /* 386 call gate */
2019 if ((dpl
< cpl
) || (dpl
< rpl
))
2020 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2021 if (!(e2
& DESC_P_MASK
))
2022 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
2024 new_eip
= (e1
& 0xffff);
2026 new_eip
|= (e2
& 0xffff0000);
2027 if (load_segment(&e1
, &e2
, gate_cs
) != 0)
2028 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
2029 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2030 /* must be code segment */
2031 if (((e2
& (DESC_S_MASK
| DESC_CS_MASK
)) !=
2032 (DESC_S_MASK
| DESC_CS_MASK
)))
2033 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
2034 if (((e2
& DESC_C_MASK
) && (dpl
> cpl
)) ||
2035 (!(e2
& DESC_C_MASK
) && (dpl
!= cpl
)))
2036 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
2037 if (!(e2
& DESC_P_MASK
))
2038 raise_exception_err(EXCP0D_GPF
, gate_cs
& 0xfffc);
2039 limit
= get_seg_limit(e1
, e2
);
2040 if (new_eip
> limit
)
2041 raise_exception_err(EXCP0D_GPF
, 0);
2042 cpu_x86_load_seg_cache(env
, R_CS
, (gate_cs
& 0xfffc) | cpl
,
2043 get_seg_base(e1
, e2
), limit
, e2
);
2047 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2053 /* real mode call */
2054 void helper_lcall_real_T0_T1(int shift
, int next_eip
)
2056 int new_cs
, new_eip
;
2057 uint32_t esp
, esp_mask
;
2063 esp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
2064 ssp
= env
->segs
[R_SS
].base
;
2066 PUSHL(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
2067 PUSHL(ssp
, esp
, esp_mask
, next_eip
);
2069 PUSHW(ssp
, esp
, esp_mask
, env
->segs
[R_CS
].selector
);
2070 PUSHW(ssp
, esp
, esp_mask
, next_eip
);
2073 SET_ESP(esp
, esp_mask
);
2075 env
->segs
[R_CS
].selector
= new_cs
;
2076 env
->segs
[R_CS
].base
= (new_cs
<< 4);
2079 /* protected mode call */
2080 void helper_lcall_protected_T0_T1(int shift
, int next_eip_addend
)
2082 int new_cs
, new_stack
, i
;
2083 uint32_t e1
, e2
, cpl
, dpl
, rpl
, selector
, offset
, param_count
;
2084 uint32_t ss
, ss_e1
, ss_e2
, sp
, type
, ss_dpl
, sp_mask
;
2085 uint32_t val
, limit
, old_sp_mask
;
2086 target_ulong ssp
, old_ssp
, next_eip
, new_eip
;
2090 next_eip
= env
->eip
+ next_eip_addend
;
2092 if (loglevel
& CPU_LOG_PCALL
) {
2093 fprintf(logfile
, "lcall %04x:%08x s=%d\n",
2094 new_cs
, (uint32_t)new_eip
, shift
);
2095 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
2098 if ((new_cs
& 0xfffc) == 0)
2099 raise_exception_err(EXCP0D_GPF
, 0);
2100 if (load_segment(&e1
, &e2
, new_cs
) != 0)
2101 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2102 cpl
= env
->hflags
& HF_CPL_MASK
;
2104 if (loglevel
& CPU_LOG_PCALL
) {
2105 fprintf(logfile
, "desc=%08x:%08x\n", e1
, e2
);
2108 if (e2
& DESC_S_MASK
) {
2109 if (!(e2
& DESC_CS_MASK
))
2110 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2111 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2112 if (e2
& DESC_C_MASK
) {
2113 /* conforming code segment */
2115 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2117 /* non conforming code segment */
2120 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2122 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2124 if (!(e2
& DESC_P_MASK
))
2125 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
2127 #ifdef TARGET_X86_64
2128 /* XXX: check 16/32 bit cases in long mode */
2133 PUSHQ(rsp
, env
->segs
[R_CS
].selector
);
2134 PUSHQ(rsp
, next_eip
);
2135 /* from this point, not restartable */
2137 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
2138 get_seg_base(e1
, e2
),
2139 get_seg_limit(e1
, e2
), e2
);
2145 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
2146 ssp
= env
->segs
[R_SS
].base
;
2148 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
2149 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
2151 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
2152 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
2155 limit
= get_seg_limit(e1
, e2
);
2156 if (new_eip
> limit
)
2157 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2158 /* from this point, not restartable */
2159 SET_ESP(sp
, sp_mask
);
2160 cpu_x86_load_seg_cache(env
, R_CS
, (new_cs
& 0xfffc) | cpl
,
2161 get_seg_base(e1
, e2
), limit
, e2
);
2165 /* check gate type */
2166 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x1f;
2167 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2170 case 1: /* available 286 TSS */
2171 case 9: /* available 386 TSS */
2172 case 5: /* task gate */
2173 if (dpl
< cpl
|| dpl
< rpl
)
2174 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2175 switch_tss(new_cs
, e1
, e2
, SWITCH_TSS_CALL
, next_eip
);
2176 CC_OP
= CC_OP_EFLAGS
;
2178 case 4: /* 286 call gate */
2179 case 12: /* 386 call gate */
2182 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2187 if (dpl
< cpl
|| dpl
< rpl
)
2188 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2189 /* check valid bit */
2190 if (!(e2
& DESC_P_MASK
))
2191 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
2192 selector
= e1
>> 16;
2193 offset
= (e2
& 0xffff0000) | (e1
& 0x0000ffff);
2194 param_count
= e2
& 0x1f;
2195 if ((selector
& 0xfffc) == 0)
2196 raise_exception_err(EXCP0D_GPF
, 0);
2198 if (load_segment(&e1
, &e2
, selector
) != 0)
2199 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
2200 if (!(e2
& DESC_S_MASK
) || !(e2
& (DESC_CS_MASK
)))
2201 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
2202 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2204 raise_exception_err(EXCP0D_GPF
, selector
& 0xfffc);
2205 if (!(e2
& DESC_P_MASK
))
2206 raise_exception_err(EXCP0B_NOSEG
, selector
& 0xfffc);
2208 if (!(e2
& DESC_C_MASK
) && dpl
< cpl
) {
2209 /* to inner privilege */
2210 get_ss_esp_from_tss(&ss
, &sp
, dpl
);
2212 if (loglevel
& CPU_LOG_PCALL
)
2213 fprintf(logfile
, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx
"\n",
2214 ss
, sp
, param_count
, ESP
);
2216 if ((ss
& 0xfffc) == 0)
2217 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
2218 if ((ss
& 3) != dpl
)
2219 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
2220 if (load_segment(&ss_e1
, &ss_e2
, ss
) != 0)
2221 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
2222 ss_dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
2224 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
2225 if (!(ss_e2
& DESC_S_MASK
) ||
2226 (ss_e2
& DESC_CS_MASK
) ||
2227 !(ss_e2
& DESC_W_MASK
))
2228 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
2229 if (!(ss_e2
& DESC_P_MASK
))
2230 raise_exception_err(EXCP0A_TSS
, ss
& 0xfffc);
2232 // push_size = ((param_count * 2) + 8) << shift;
2234 old_sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
2235 old_ssp
= env
->segs
[R_SS
].base
;
2237 sp_mask
= get_sp_mask(ss_e2
);
2238 ssp
= get_seg_base(ss_e1
, ss_e2
);
2240 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
2241 PUSHL(ssp
, sp
, sp_mask
, ESP
);
2242 for(i
= param_count
- 1; i
>= 0; i
--) {
2243 val
= ldl_kernel(old_ssp
+ ((ESP
+ i
* 4) & old_sp_mask
));
2244 PUSHL(ssp
, sp
, sp_mask
, val
);
2247 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_SS
].selector
);
2248 PUSHW(ssp
, sp
, sp_mask
, ESP
);
2249 for(i
= param_count
- 1; i
>= 0; i
--) {
2250 val
= lduw_kernel(old_ssp
+ ((ESP
+ i
* 2) & old_sp_mask
));
2251 PUSHW(ssp
, sp
, sp_mask
, val
);
2256 /* to same privilege */
2258 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
2259 ssp
= env
->segs
[R_SS
].base
;
2260 // push_size = (4 << shift);
2265 PUSHL(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
2266 PUSHL(ssp
, sp
, sp_mask
, next_eip
);
2268 PUSHW(ssp
, sp
, sp_mask
, env
->segs
[R_CS
].selector
);
2269 PUSHW(ssp
, sp
, sp_mask
, next_eip
);
2272 /* from this point, not restartable */
2275 ss
= (ss
& ~3) | dpl
;
2276 cpu_x86_load_seg_cache(env
, R_SS
, ss
,
2278 get_seg_limit(ss_e1
, ss_e2
),
2282 selector
= (selector
& ~3) | dpl
;
2283 cpu_x86_load_seg_cache(env
, R_CS
, selector
,
2284 get_seg_base(e1
, e2
),
2285 get_seg_limit(e1
, e2
),
2287 cpu_x86_set_cpl(env
, dpl
);
2288 SET_ESP(sp
, sp_mask
);
2292 if (kqemu_is_ok(env
)) {
2293 env
->exception_index
= -1;
2299 /* real and vm86 mode iret */
2300 void helper_iret_real(int shift
)
2302 uint32_t sp
, new_cs
, new_eip
, new_eflags
, sp_mask
;
2306 sp_mask
= 0xffff; /* XXXX: use SS segment size ? */
2308 ssp
= env
->segs
[R_SS
].base
;
2311 POPL(ssp
, sp
, sp_mask
, new_eip
);
2312 POPL(ssp
, sp
, sp_mask
, new_cs
);
2314 POPL(ssp
, sp
, sp_mask
, new_eflags
);
2317 POPW(ssp
, sp
, sp_mask
, new_eip
);
2318 POPW(ssp
, sp
, sp_mask
, new_cs
);
2319 POPW(ssp
, sp
, sp_mask
, new_eflags
);
2321 ESP
= (ESP
& ~sp_mask
) | (sp
& sp_mask
);
2322 load_seg_vm(R_CS
, new_cs
);
2324 if (env
->eflags
& VM_MASK
)
2325 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| RF_MASK
| NT_MASK
;
2327 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| IF_MASK
| IOPL_MASK
| RF_MASK
| NT_MASK
;
2329 eflags_mask
&= 0xffff;
2330 load_eflags(new_eflags
, eflags_mask
);
2333 static inline void validate_seg(int seg_reg
, int cpl
)
2338 /* XXX: on x86_64, we do not want to nullify FS and GS because
2339 they may still contain a valid base. I would be interested to
2340 know how a real x86_64 CPU behaves */
2341 if ((seg_reg
== R_FS
|| seg_reg
== R_GS
) &&
2342 (env
->segs
[seg_reg
].selector
& 0xfffc) == 0)
2345 e2
= env
->segs
[seg_reg
].flags
;
2346 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2347 if (!(e2
& DESC_CS_MASK
) || !(e2
& DESC_C_MASK
)) {
2348 /* data or non conforming code segment */
2350 cpu_x86_load_seg_cache(env
, seg_reg
, 0, 0, 0, 0);
2355 /* protected mode iret */
2356 static inline void helper_ret_protected(int shift
, int is_iret
, int addend
)
2358 uint32_t new_cs
, new_eflags
, new_ss
;
2359 uint32_t new_es
, new_ds
, new_fs
, new_gs
;
2360 uint32_t e1
, e2
, ss_e1
, ss_e2
;
2361 int cpl
, dpl
, rpl
, eflags_mask
, iopl
;
2362 target_ulong ssp
, sp
, new_eip
, new_esp
, sp_mask
;
2364 #ifdef TARGET_X86_64
2369 sp_mask
= get_sp_mask(env
->segs
[R_SS
].flags
);
2371 ssp
= env
->segs
[R_SS
].base
;
2372 new_eflags
= 0; /* avoid warning */
2373 #ifdef TARGET_X86_64
2379 POPQ(sp
, new_eflags
);
2385 POPL(ssp
, sp
, sp_mask
, new_eip
);
2386 POPL(ssp
, sp
, sp_mask
, new_cs
);
2389 POPL(ssp
, sp
, sp_mask
, new_eflags
);
2390 if (new_eflags
& VM_MASK
)
2391 goto return_to_vm86
;
2395 POPW(ssp
, sp
, sp_mask
, new_eip
);
2396 POPW(ssp
, sp
, sp_mask
, new_cs
);
2398 POPW(ssp
, sp
, sp_mask
, new_eflags
);
2401 if (loglevel
& CPU_LOG_PCALL
) {
2402 fprintf(logfile
, "lret new %04x:" TARGET_FMT_lx
" s=%d addend=0x%x\n",
2403 new_cs
, new_eip
, shift
, addend
);
2404 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
2407 if ((new_cs
& 0xfffc) == 0)
2408 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2409 if (load_segment(&e1
, &e2
, new_cs
) != 0)
2410 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2411 if (!(e2
& DESC_S_MASK
) ||
2412 !(e2
& DESC_CS_MASK
))
2413 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2414 cpl
= env
->hflags
& HF_CPL_MASK
;
2417 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2418 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2419 if (e2
& DESC_C_MASK
) {
2421 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2424 raise_exception_err(EXCP0D_GPF
, new_cs
& 0xfffc);
2426 if (!(e2
& DESC_P_MASK
))
2427 raise_exception_err(EXCP0B_NOSEG
, new_cs
& 0xfffc);
2430 if (rpl
== cpl
&& (!(env
->hflags
& HF_CS64_MASK
) ||
2431 ((env
->hflags
& HF_CS64_MASK
) && !is_iret
))) {
2432 /* return to same priledge level */
2433 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
2434 get_seg_base(e1
, e2
),
2435 get_seg_limit(e1
, e2
),
2438 /* return to different privilege level */
2439 #ifdef TARGET_X86_64
2448 POPL(ssp
, sp
, sp_mask
, new_esp
);
2449 POPL(ssp
, sp
, sp_mask
, new_ss
);
2453 POPW(ssp
, sp
, sp_mask
, new_esp
);
2454 POPW(ssp
, sp
, sp_mask
, new_ss
);
2457 if (loglevel
& CPU_LOG_PCALL
) {
2458 fprintf(logfile
, "new ss:esp=%04x:" TARGET_FMT_lx
"\n",
2462 if ((new_ss
& 0xfffc) == 0) {
2463 #ifdef TARGET_X86_64
2464 /* NULL ss is allowed in long mode if cpl != 3*/
2465 /* XXX: test CS64 ? */
2466 if ((env
->hflags
& HF_LMA_MASK
) && rpl
!= 3) {
2467 cpu_x86_load_seg_cache(env
, R_SS
, new_ss
,
2469 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2470 DESC_S_MASK
| (rpl
<< DESC_DPL_SHIFT
) |
2471 DESC_W_MASK
| DESC_A_MASK
);
2472 ss_e2
= DESC_B_MASK
; /* XXX: should not be needed ? */
2476 raise_exception_err(EXCP0D_GPF
, 0);
2479 if ((new_ss
& 3) != rpl
)
2480 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
2481 if (load_segment(&ss_e1
, &ss_e2
, new_ss
) != 0)
2482 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
2483 if (!(ss_e2
& DESC_S_MASK
) ||
2484 (ss_e2
& DESC_CS_MASK
) ||
2485 !(ss_e2
& DESC_W_MASK
))
2486 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
2487 dpl
= (ss_e2
>> DESC_DPL_SHIFT
) & 3;
2489 raise_exception_err(EXCP0D_GPF
, new_ss
& 0xfffc);
2490 if (!(ss_e2
& DESC_P_MASK
))
2491 raise_exception_err(EXCP0B_NOSEG
, new_ss
& 0xfffc);
2492 cpu_x86_load_seg_cache(env
, R_SS
, new_ss
,
2493 get_seg_base(ss_e1
, ss_e2
),
2494 get_seg_limit(ss_e1
, ss_e2
),
2498 cpu_x86_load_seg_cache(env
, R_CS
, new_cs
,
2499 get_seg_base(e1
, e2
),
2500 get_seg_limit(e1
, e2
),
2502 cpu_x86_set_cpl(env
, rpl
);
2504 #ifdef TARGET_X86_64
2505 if (env
->hflags
& HF_CS64_MASK
)
2509 sp_mask
= get_sp_mask(ss_e2
);
2511 /* validate data segments */
2512 validate_seg(R_ES
, rpl
);
2513 validate_seg(R_DS
, rpl
);
2514 validate_seg(R_FS
, rpl
);
2515 validate_seg(R_GS
, rpl
);
2519 SET_ESP(sp
, sp_mask
);
2522 /* NOTE: 'cpl' is the _old_ CPL */
2523 eflags_mask
= TF_MASK
| AC_MASK
| ID_MASK
| RF_MASK
| NT_MASK
;
2525 eflags_mask
|= IOPL_MASK
;
2526 iopl
= (env
->eflags
>> IOPL_SHIFT
) & 3;
2528 eflags_mask
|= IF_MASK
;
2530 eflags_mask
&= 0xffff;
2531 load_eflags(new_eflags
, eflags_mask
);
2536 POPL(ssp
, sp
, sp_mask
, new_esp
);
2537 POPL(ssp
, sp
, sp_mask
, new_ss
);
2538 POPL(ssp
, sp
, sp_mask
, new_es
);
2539 POPL(ssp
, sp
, sp_mask
, new_ds
);
2540 POPL(ssp
, sp
, sp_mask
, new_fs
);
2541 POPL(ssp
, sp
, sp_mask
, new_gs
);
2543 /* modify processor state */
2544 load_eflags(new_eflags
, TF_MASK
| AC_MASK
| ID_MASK
|
2545 IF_MASK
| IOPL_MASK
| VM_MASK
| NT_MASK
| VIF_MASK
| VIP_MASK
);
2546 load_seg_vm(R_CS
, new_cs
& 0xffff);
2547 cpu_x86_set_cpl(env
, 3);
2548 load_seg_vm(R_SS
, new_ss
& 0xffff);
2549 load_seg_vm(R_ES
, new_es
& 0xffff);
2550 load_seg_vm(R_DS
, new_ds
& 0xffff);
2551 load_seg_vm(R_FS
, new_fs
& 0xffff);
2552 load_seg_vm(R_GS
, new_gs
& 0xffff);
2554 env
->eip
= new_eip
& 0xffff;
2558 void helper_iret_protected(int shift
, int next_eip
)
2560 int tss_selector
, type
;
2563 /* specific case for TSS */
2564 if (env
->eflags
& NT_MASK
) {
2565 #ifdef TARGET_X86_64
2566 if (env
->hflags
& HF_LMA_MASK
)
2567 raise_exception_err(EXCP0D_GPF
, 0);
2569 tss_selector
= lduw_kernel(env
->tr
.base
+ 0);
2570 if (tss_selector
& 4)
2571 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
2572 if (load_segment(&e1
, &e2
, tss_selector
) != 0)
2573 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
2574 type
= (e2
>> DESC_TYPE_SHIFT
) & 0x17;
2575 /* NOTE: we check both segment and busy TSS */
2577 raise_exception_err(EXCP0A_TSS
, tss_selector
& 0xfffc);
2578 switch_tss(tss_selector
, e1
, e2
, SWITCH_TSS_IRET
, next_eip
);
2580 helper_ret_protected(shift
, 1, 0);
2583 if (kqemu_is_ok(env
)) {
2584 CC_OP
= CC_OP_EFLAGS
;
2585 env
->exception_index
= -1;
2591 void helper_lret_protected(int shift
, int addend
)
2593 helper_ret_protected(shift
, 0, addend
);
2595 if (kqemu_is_ok(env
)) {
2596 env
->exception_index
= -1;
2602 void helper_sysenter(void)
2604 if (env
->sysenter_cs
== 0) {
2605 raise_exception_err(EXCP0D_GPF
, 0);
2607 env
->eflags
&= ~(VM_MASK
| IF_MASK
| RF_MASK
);
2608 cpu_x86_set_cpl(env
, 0);
2609 cpu_x86_load_seg_cache(env
, R_CS
, env
->sysenter_cs
& 0xfffc,
2611 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2613 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
2614 cpu_x86_load_seg_cache(env
, R_SS
, (env
->sysenter_cs
+ 8) & 0xfffc,
2616 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2618 DESC_W_MASK
| DESC_A_MASK
);
2619 ESP
= env
->sysenter_esp
;
2620 EIP
= env
->sysenter_eip
;
2623 void helper_sysexit(void)
2627 cpl
= env
->hflags
& HF_CPL_MASK
;
2628 if (env
->sysenter_cs
== 0 || cpl
!= 0) {
2629 raise_exception_err(EXCP0D_GPF
, 0);
2631 cpu_x86_set_cpl(env
, 3);
2632 cpu_x86_load_seg_cache(env
, R_CS
, ((env
->sysenter_cs
+ 16) & 0xfffc) | 3,
2634 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2635 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
2636 DESC_CS_MASK
| DESC_R_MASK
| DESC_A_MASK
);
2637 cpu_x86_load_seg_cache(env
, R_SS
, ((env
->sysenter_cs
+ 24) & 0xfffc) | 3,
2639 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
|
2640 DESC_S_MASK
| (3 << DESC_DPL_SHIFT
) |
2641 DESC_W_MASK
| DESC_A_MASK
);
2645 if (kqemu_is_ok(env
)) {
2646 env
->exception_index
= -1;
2652 void helper_movl_crN_T0(int reg
)
2654 #if !defined(CONFIG_USER_ONLY)
2657 cpu_x86_update_cr0(env
, T0
);
2660 cpu_x86_update_cr3(env
, T0
);
2663 cpu_x86_update_cr4(env
, T0
);
2666 cpu_set_apic_tpr(env
, T0
);
2676 void helper_movl_drN_T0(int reg
)
2681 void helper_invlpg(target_ulong addr
)
2683 cpu_x86_flush_tlb(env
, addr
);
2686 void helper_rdtsc(void)
2690 if ((env
->cr
[4] & CR4_TSD_MASK
) && ((env
->hflags
& HF_CPL_MASK
) != 0)) {
2691 raise_exception(EXCP0D_GPF
);
2693 val
= cpu_get_tsc(env
);
2694 EAX
= (uint32_t)(val
);
2695 EDX
= (uint32_t)(val
>> 32);
2698 #if defined(CONFIG_USER_ONLY)
2699 void helper_wrmsr(void)
2703 void helper_rdmsr(void)
2707 void helper_wrmsr(void)
2711 val
= ((uint32_t)EAX
) | ((uint64_t)((uint32_t)EDX
) << 32);
2713 switch((uint32_t)ECX
) {
2714 case MSR_IA32_SYSENTER_CS
:
2715 env
->sysenter_cs
= val
& 0xffff;
2717 case MSR_IA32_SYSENTER_ESP
:
2718 env
->sysenter_esp
= val
;
2720 case MSR_IA32_SYSENTER_EIP
:
2721 env
->sysenter_eip
= val
;
2723 case MSR_IA32_APICBASE
:
2724 cpu_set_apic_base(env
, val
);
2728 uint64_t update_mask
;
2730 if (env
->cpuid_ext2_features
& CPUID_EXT2_SYSCALL
)
2731 update_mask
|= MSR_EFER_SCE
;
2732 if (env
->cpuid_ext2_features
& CPUID_EXT2_LM
)
2733 update_mask
|= MSR_EFER_LME
;
2734 if (env
->cpuid_ext2_features
& CPUID_EXT2_FFXSR
)
2735 update_mask
|= MSR_EFER_FFXSR
;
2736 if (env
->cpuid_ext2_features
& CPUID_EXT2_NX
)
2737 update_mask
|= MSR_EFER_NXE
;
2738 env
->efer
= (env
->efer
& ~update_mask
) |
2739 (val
& update_mask
);
2748 #ifdef TARGET_X86_64
2759 env
->segs
[R_FS
].base
= val
;
2762 env
->segs
[R_GS
].base
= val
;
2764 case MSR_KERNELGSBASE
:
2765 env
->kernelgsbase
= val
;
2769 /* XXX: exception ? */
2774 void helper_rdmsr(void)
2777 switch((uint32_t)ECX
) {
2778 case MSR_IA32_SYSENTER_CS
:
2779 val
= env
->sysenter_cs
;
2781 case MSR_IA32_SYSENTER_ESP
:
2782 val
= env
->sysenter_esp
;
2784 case MSR_IA32_SYSENTER_EIP
:
2785 val
= env
->sysenter_eip
;
2787 case MSR_IA32_APICBASE
:
2788 val
= cpu_get_apic_base(env
);
2799 #ifdef TARGET_X86_64
2810 val
= env
->segs
[R_FS
].base
;
2813 val
= env
->segs
[R_GS
].base
;
2815 case MSR_KERNELGSBASE
:
2816 val
= env
->kernelgsbase
;
2820 /* XXX: exception ? */
2824 EAX
= (uint32_t)(val
);
2825 EDX
= (uint32_t)(val
>> 32);
2829 void helper_lsl(void)
2831 unsigned int selector
, limit
;
2832 uint32_t e1
, e2
, eflags
;
2833 int rpl
, dpl
, cpl
, type
;
2835 eflags
= cc_table
[CC_OP
].compute_all();
2836 selector
= T0
& 0xffff;
2837 if (load_segment(&e1
, &e2
, selector
) != 0)
2840 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2841 cpl
= env
->hflags
& HF_CPL_MASK
;
2842 if (e2
& DESC_S_MASK
) {
2843 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
2846 if (dpl
< cpl
|| dpl
< rpl
)
2850 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
2861 if (dpl
< cpl
|| dpl
< rpl
) {
2863 CC_SRC
= eflags
& ~CC_Z
;
2867 limit
= get_seg_limit(e1
, e2
);
2869 CC_SRC
= eflags
| CC_Z
;
2872 void helper_lar(void)
2874 unsigned int selector
;
2875 uint32_t e1
, e2
, eflags
;
2876 int rpl
, dpl
, cpl
, type
;
2878 eflags
= cc_table
[CC_OP
].compute_all();
2879 selector
= T0
& 0xffff;
2880 if ((selector
& 0xfffc) == 0)
2882 if (load_segment(&e1
, &e2
, selector
) != 0)
2885 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2886 cpl
= env
->hflags
& HF_CPL_MASK
;
2887 if (e2
& DESC_S_MASK
) {
2888 if ((e2
& DESC_CS_MASK
) && (e2
& DESC_C_MASK
)) {
2891 if (dpl
< cpl
|| dpl
< rpl
)
2895 type
= (e2
>> DESC_TYPE_SHIFT
) & 0xf;
2909 if (dpl
< cpl
|| dpl
< rpl
) {
2911 CC_SRC
= eflags
& ~CC_Z
;
2915 T1
= e2
& 0x00f0ff00;
2916 CC_SRC
= eflags
| CC_Z
;
2919 void helper_verr(void)
2921 unsigned int selector
;
2922 uint32_t e1
, e2
, eflags
;
2925 eflags
= cc_table
[CC_OP
].compute_all();
2926 selector
= T0
& 0xffff;
2927 if ((selector
& 0xfffc) == 0)
2929 if (load_segment(&e1
, &e2
, selector
) != 0)
2931 if (!(e2
& DESC_S_MASK
))
2934 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2935 cpl
= env
->hflags
& HF_CPL_MASK
;
2936 if (e2
& DESC_CS_MASK
) {
2937 if (!(e2
& DESC_R_MASK
))
2939 if (!(e2
& DESC_C_MASK
)) {
2940 if (dpl
< cpl
|| dpl
< rpl
)
2944 if (dpl
< cpl
|| dpl
< rpl
) {
2946 CC_SRC
= eflags
& ~CC_Z
;
2950 CC_SRC
= eflags
| CC_Z
;
2953 void helper_verw(void)
2955 unsigned int selector
;
2956 uint32_t e1
, e2
, eflags
;
2959 eflags
= cc_table
[CC_OP
].compute_all();
2960 selector
= T0
& 0xffff;
2961 if ((selector
& 0xfffc) == 0)
2963 if (load_segment(&e1
, &e2
, selector
) != 0)
2965 if (!(e2
& DESC_S_MASK
))
2968 dpl
= (e2
>> DESC_DPL_SHIFT
) & 3;
2969 cpl
= env
->hflags
& HF_CPL_MASK
;
2970 if (e2
& DESC_CS_MASK
) {
2973 if (dpl
< cpl
|| dpl
< rpl
)
2975 if (!(e2
& DESC_W_MASK
)) {
2977 CC_SRC
= eflags
& ~CC_Z
;
2981 CC_SRC
= eflags
| CC_Z
;
2986 void helper_fldt_ST0_A0(void)
2989 new_fpstt
= (env
->fpstt
- 1) & 7;
2990 env
->fpregs
[new_fpstt
].d
= helper_fldt(A0
);
2991 env
->fpstt
= new_fpstt
;
2992 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
2995 void helper_fstt_ST0_A0(void)
2997 helper_fstt(ST0
, A0
);
3000 void fpu_set_exception(int mask
)
3003 if (env
->fpus
& (~env
->fpuc
& FPUC_EM
))
3004 env
->fpus
|= FPUS_SE
| FPUS_B
;
3007 CPU86_LDouble
helper_fdiv(CPU86_LDouble a
, CPU86_LDouble b
)
3010 fpu_set_exception(FPUS_ZE
);
3014 void fpu_raise_exception(void)
3016 if (env
->cr
[0] & CR0_NE_MASK
) {
3017 raise_exception(EXCP10_COPR
);
3019 #if !defined(CONFIG_USER_ONLY)
3028 void helper_fbld_ST0_A0(void)
3036 for(i
= 8; i
>= 0; i
--) {
3038 val
= (val
* 100) + ((v
>> 4) * 10) + (v
& 0xf);
3041 if (ldub(A0
+ 9) & 0x80)
3047 void helper_fbst_ST0_A0(void)
3050 target_ulong mem_ref
, mem_end
;
3053 val
= floatx_to_int64(ST0
, &env
->fp_status
);
3055 mem_end
= mem_ref
+ 9;
3062 while (mem_ref
< mem_end
) {
3067 v
= ((v
/ 10) << 4) | (v
% 10);
3070 while (mem_ref
< mem_end
) {
3075 void helper_f2xm1(void)
3077 ST0
= pow(2.0,ST0
) - 1.0;
3080 void helper_fyl2x(void)
3082 CPU86_LDouble fptemp
;
3086 fptemp
= log(fptemp
)/log(2.0); /* log2(ST) */
3090 env
->fpus
&= (~0x4700);
3095 void helper_fptan(void)
3097 CPU86_LDouble fptemp
;
3100 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
3106 env
->fpus
&= (~0x400); /* C2 <-- 0 */
3107 /* the above code is for |arg| < 2**52 only */
3111 void helper_fpatan(void)
3113 CPU86_LDouble fptemp
, fpsrcop
;
3117 ST1
= atan2(fpsrcop
,fptemp
);
3121 void helper_fxtract(void)
3123 CPU86_LDoubleU temp
;
3124 unsigned int expdif
;
3127 expdif
= EXPD(temp
) - EXPBIAS
;
3128 /*DP exponent bias*/
3135 void helper_fprem1(void)
3137 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
3138 CPU86_LDoubleU fpsrcop1
, fptemp1
;
3140 signed long long int q
;
3142 if (isinf(ST0
) || isnan(ST0
) || isnan(ST1
) || (ST1
== 0.0)) {
3143 ST0
= 0.0 / 0.0; /* NaN */
3144 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3150 fpsrcop1
.d
= fpsrcop
;
3152 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
3155 /* optimisation? taken from the AMD docs */
3156 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3157 /* ST0 is unchanged */
3162 dblq
= fpsrcop
/ fptemp
;
3163 /* round dblq towards nearest integer */
3165 ST0
= fpsrcop
- fptemp
* dblq
;
3167 /* convert dblq to q by truncating towards zero */
3169 q
= (signed long long int)(-dblq
);
3171 q
= (signed long long int)dblq
;
3173 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3174 /* (C0,C3,C1) <-- (q2,q1,q0) */
3175 env
->fpus
|= (q
& 0x4) << (8 - 2); /* (C0) <-- q2 */
3176 env
->fpus
|= (q
& 0x2) << (14 - 1); /* (C3) <-- q1 */
3177 env
->fpus
|= (q
& 0x1) << (9 - 0); /* (C1) <-- q0 */
3179 env
->fpus
|= 0x400; /* C2 <-- 1 */
3180 fptemp
= pow(2.0, expdif
- 50);
3181 fpsrcop
= (ST0
/ ST1
) / fptemp
;
3182 /* fpsrcop = integer obtained by chopping */
3183 fpsrcop
= (fpsrcop
< 0.0) ?
3184 -(floor(fabs(fpsrcop
))) : floor(fpsrcop
);
3185 ST0
-= (ST1
* fpsrcop
* fptemp
);
3189 void helper_fprem(void)
3191 CPU86_LDouble dblq
, fpsrcop
, fptemp
;
3192 CPU86_LDoubleU fpsrcop1
, fptemp1
;
3194 signed long long int q
;
3196 if (isinf(ST0
) || isnan(ST0
) || isnan(ST1
) || (ST1
== 0.0)) {
3197 ST0
= 0.0 / 0.0; /* NaN */
3198 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3202 fpsrcop
= (CPU86_LDouble
)ST0
;
3203 fptemp
= (CPU86_LDouble
)ST1
;
3204 fpsrcop1
.d
= fpsrcop
;
3206 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
3209 /* optimisation? taken from the AMD docs */
3210 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3211 /* ST0 is unchanged */
3215 if ( expdif
< 53 ) {
3216 dblq
= fpsrcop
/*ST0*/ / fptemp
/*ST1*/;
3217 /* round dblq towards zero */
3218 dblq
= (dblq
< 0.0) ? ceil(dblq
) : floor(dblq
);
3219 ST0
= fpsrcop
/*ST0*/ - fptemp
* dblq
;
3221 /* convert dblq to q by truncating towards zero */
3223 q
= (signed long long int)(-dblq
);
3225 q
= (signed long long int)dblq
;
3227 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3228 /* (C0,C3,C1) <-- (q2,q1,q0) */
3229 env
->fpus
|= (q
& 0x4) << (8 - 2); /* (C0) <-- q2 */
3230 env
->fpus
|= (q
& 0x2) << (14 - 1); /* (C3) <-- q1 */
3231 env
->fpus
|= (q
& 0x1) << (9 - 0); /* (C1) <-- q0 */
3233 int N
= 32 + (expdif
% 32); /* as per AMD docs */
3234 env
->fpus
|= 0x400; /* C2 <-- 1 */
3235 fptemp
= pow(2.0, (double)(expdif
- N
));
3236 fpsrcop
= (ST0
/ ST1
) / fptemp
;
3237 /* fpsrcop = integer obtained by chopping */
3238 fpsrcop
= (fpsrcop
< 0.0) ?
3239 -(floor(fabs(fpsrcop
))) : floor(fpsrcop
);
3240 ST0
-= (ST1
* fpsrcop
* fptemp
);
3244 void helper_fyl2xp1(void)
3246 CPU86_LDouble fptemp
;
3249 if ((fptemp
+1.0)>0.0) {
3250 fptemp
= log(fptemp
+1.0) / log(2.0); /* log2(ST+1.0) */
3254 env
->fpus
&= (~0x4700);
3259 void helper_fsqrt(void)
3261 CPU86_LDouble fptemp
;
3265 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3271 void helper_fsincos(void)
3273 CPU86_LDouble fptemp
;
3276 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
3282 env
->fpus
&= (~0x400); /* C2 <-- 0 */
3283 /* the above code is for |arg| < 2**63 only */
3287 void helper_frndint(void)
3289 ST0
= floatx_round_to_int(ST0
, &env
->fp_status
);
3292 void helper_fscale(void)
3294 ST0
= ldexp (ST0
, (int)(ST1
));
3297 void helper_fsin(void)
3299 CPU86_LDouble fptemp
;
3302 if ((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
3306 env
->fpus
&= (~0x400); /* C2 <-- 0 */
3307 /* the above code is for |arg| < 2**53 only */
3311 void helper_fcos(void)
3313 CPU86_LDouble fptemp
;
3316 if((fptemp
> MAXTAN
)||(fptemp
< -MAXTAN
)) {
3320 env
->fpus
&= (~0x400); /* C2 <-- 0 */
3321 /* the above code is for |arg5 < 2**63 only */
3325 void helper_fxam_ST0(void)
3327 CPU86_LDoubleU temp
;
3332 env
->fpus
&= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3334 env
->fpus
|= 0x200; /* C1 <-- 1 */
3336 /* XXX: test fptags too */
3337 expdif
= EXPD(temp
);
3338 if (expdif
== MAXEXPD
) {
3339 #ifdef USE_X86LDOUBLE
3340 if (MANTD(temp
) == 0x8000000000000000ULL
)
3342 if (MANTD(temp
) == 0)
3344 env
->fpus
|= 0x500 /*Infinity*/;
3346 env
->fpus
|= 0x100 /*NaN*/;
3347 } else if (expdif
== 0) {
3348 if (MANTD(temp
) == 0)
3349 env
->fpus
|= 0x4000 /*Zero*/;
3351 env
->fpus
|= 0x4400 /*Denormal*/;
3357 void helper_fstenv(target_ulong ptr
, int data32
)
3359 int fpus
, fptag
, exp
, i
;
3363 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
3365 for (i
=7; i
>=0; i
--) {
3367 if (env
->fptags
[i
]) {
3370 tmp
.d
= env
->fpregs
[i
].d
;
3373 if (exp
== 0 && mant
== 0) {
3376 } else if (exp
== 0 || exp
== MAXEXPD
3377 #ifdef USE_X86LDOUBLE
3378 || (mant
& (1LL << 63)) == 0
3381 /* NaNs, infinity, denormal */
3388 stl(ptr
, env
->fpuc
);
3390 stl(ptr
+ 8, fptag
);
3391 stl(ptr
+ 12, 0); /* fpip */
3392 stl(ptr
+ 16, 0); /* fpcs */
3393 stl(ptr
+ 20, 0); /* fpoo */
3394 stl(ptr
+ 24, 0); /* fpos */
3397 stw(ptr
, env
->fpuc
);
3399 stw(ptr
+ 4, fptag
);
3407 void helper_fldenv(target_ulong ptr
, int data32
)
3412 env
->fpuc
= lduw(ptr
);
3413 fpus
= lduw(ptr
+ 4);
3414 fptag
= lduw(ptr
+ 8);
3417 env
->fpuc
= lduw(ptr
);
3418 fpus
= lduw(ptr
+ 2);
3419 fptag
= lduw(ptr
+ 4);
3421 env
->fpstt
= (fpus
>> 11) & 7;
3422 env
->fpus
= fpus
& ~0x3800;
3423 for(i
= 0;i
< 8; i
++) {
3424 env
->fptags
[i
] = ((fptag
& 3) == 3);
3429 void helper_fsave(target_ulong ptr
, int data32
)
3434 helper_fstenv(ptr
, data32
);
3436 ptr
+= (14 << data32
);
3437 for(i
= 0;i
< 8; i
++) {
3439 helper_fstt(tmp
, ptr
);
3457 void helper_frstor(target_ulong ptr
, int data32
)
3462 helper_fldenv(ptr
, data32
);
3463 ptr
+= (14 << data32
);
3465 for(i
= 0;i
< 8; i
++) {
3466 tmp
= helper_fldt(ptr
);
3472 void helper_fxsave(target_ulong ptr
, int data64
)
3474 int fpus
, fptag
, i
, nb_xmm_regs
;
3478 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
3480 for(i
= 0; i
< 8; i
++) {
3481 fptag
|= (env
->fptags
[i
] << i
);
3483 stw(ptr
, env
->fpuc
);
3485 stw(ptr
+ 4, fptag
^ 0xff);
3488 for(i
= 0;i
< 8; i
++) {
3490 helper_fstt(tmp
, addr
);
3494 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
3495 /* XXX: finish it */
3496 stl(ptr
+ 0x18, env
->mxcsr
); /* mxcsr */
3497 stl(ptr
+ 0x1c, 0x0000ffff); /* mxcsr_mask */
3498 nb_xmm_regs
= 8 << data64
;
3500 for(i
= 0; i
< nb_xmm_regs
; i
++) {
3501 stq(addr
, env
->xmm_regs
[i
].XMM_Q(0));
3502 stq(addr
+ 8, env
->xmm_regs
[i
].XMM_Q(1));
3508 void helper_fxrstor(target_ulong ptr
, int data64
)
3510 int i
, fpus
, fptag
, nb_xmm_regs
;
3514 env
->fpuc
= lduw(ptr
);
3515 fpus
= lduw(ptr
+ 2);
3516 fptag
= lduw(ptr
+ 4);
3517 env
->fpstt
= (fpus
>> 11) & 7;
3518 env
->fpus
= fpus
& ~0x3800;
3520 for(i
= 0;i
< 8; i
++) {
3521 env
->fptags
[i
] = ((fptag
>> i
) & 1);
3525 for(i
= 0;i
< 8; i
++) {
3526 tmp
= helper_fldt(addr
);
3531 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
3532 /* XXX: finish it */
3533 env
->mxcsr
= ldl(ptr
+ 0x18);
3535 nb_xmm_regs
= 8 << data64
;
3537 for(i
= 0; i
< nb_xmm_regs
; i
++) {
3538 env
->xmm_regs
[i
].XMM_Q(0) = ldq(addr
);
3539 env
->xmm_regs
[i
].XMM_Q(1) = ldq(addr
+ 8);
3545 #ifndef USE_X86LDOUBLE
3547 void cpu_get_fp80(uint64_t *pmant
, uint16_t *pexp
, CPU86_LDouble f
)
3549 CPU86_LDoubleU temp
;
3554 *pmant
= (MANTD(temp
) << 11) | (1LL << 63);
3555 /* exponent + sign */
3556 e
= EXPD(temp
) - EXPBIAS
+ 16383;
3557 e
|= SIGND(temp
) >> 16;
3561 CPU86_LDouble
cpu_set_fp80(uint64_t mant
, uint16_t upper
)
3563 CPU86_LDoubleU temp
;
3567 /* XXX: handle overflow ? */
3568 e
= (upper
& 0x7fff) - 16383 + EXPBIAS
; /* exponent */
3569 e
|= (upper
>> 4) & 0x800; /* sign */
3570 ll
= (mant
>> 11) & ((1LL << 52) - 1);
3572 temp
.l
.upper
= (e
<< 20) | (ll
>> 32);
3575 temp
.ll
= ll
| ((uint64_t)e
<< 52);
3582 void cpu_get_fp80(uint64_t *pmant
, uint16_t *pexp
, CPU86_LDouble f
)
3584 CPU86_LDoubleU temp
;
3587 *pmant
= temp
.l
.lower
;
3588 *pexp
= temp
.l
.upper
;
3591 CPU86_LDouble
cpu_set_fp80(uint64_t mant
, uint16_t upper
)
3593 CPU86_LDoubleU temp
;
3595 temp
.l
.upper
= upper
;
3596 temp
.l
.lower
= mant
;
3601 #ifdef TARGET_X86_64
3603 //#define DEBUG_MULDIV
3605 static void add128(uint64_t *plow
, uint64_t *phigh
, uint64_t a
, uint64_t b
)
3614 static void neg128(uint64_t *plow
, uint64_t *phigh
)
3618 add128(plow
, phigh
, 1, 0);
3621 /* return TRUE if overflow */
3622 static int div64(uint64_t *plow
, uint64_t *phigh
, uint64_t b
)
3624 uint64_t q
, r
, a1
, a0
;
3637 /* XXX: use a better algorithm */
3638 for(i
= 0; i
< 64; i
++) {
3640 a1
= (a1
<< 1) | (a0
>> 63);
3641 if (ab
|| a1
>= b
) {
3647 a0
= (a0
<< 1) | qb
;
3649 #if defined(DEBUG_MULDIV)
3650 printf("div: 0x%016" PRIx64
"%016" PRIx64
" / 0x%016" PRIx64
": q=0x%016" PRIx64
" r=0x%016" PRIx64
"\n",
3651 *phigh
, *plow
, b
, a0
, a1
);
3659 /* return TRUE if overflow */
3660 static int idiv64(uint64_t *plow
, uint64_t *phigh
, int64_t b
)
3663 sa
= ((int64_t)*phigh
< 0);
3665 neg128(plow
, phigh
);
3669 if (div64(plow
, phigh
, b
) != 0)
3672 if (*plow
> (1ULL << 63))
3676 if (*plow
>= (1ULL << 63))
3684 void helper_mulq_EAX_T0(void)
3688 mulu64(&r1
, &r0
, EAX
, T0
);
3695 void helper_imulq_EAX_T0(void)
3699 muls64(&r1
, &r0
, EAX
, T0
);
3703 CC_SRC
= ((int64_t)r1
!= ((int64_t)r0
>> 63));
3706 void helper_imulq_T0_T1(void)
3710 muls64(&r1
, &r0
, T0
, T1
);
3713 CC_SRC
= ((int64_t)r1
!= ((int64_t)r0
>> 63));
3716 void helper_divq_EAX_T0(void)
3720 raise_exception(EXCP00_DIVZ
);
3724 if (div64(&r0
, &r1
, T0
))
3725 raise_exception(EXCP00_DIVZ
);
3730 void helper_idivq_EAX_T0(void)
3734 raise_exception(EXCP00_DIVZ
);
3738 if (idiv64(&r0
, &r1
, T0
))
3739 raise_exception(EXCP00_DIVZ
);
3744 void helper_bswapq_T0(void)
3750 void helper_hlt(void)
3752 env
->hflags
&= ~HF_INHIBIT_IRQ_MASK
; /* needed if sti is just before */
3753 env
->hflags
|= HF_HALTED_MASK
;
3754 env
->exception_index
= EXCP_HLT
;
3758 void helper_monitor(void)
3760 if ((uint32_t)ECX
!= 0)
3761 raise_exception(EXCP0D_GPF
);
3762 /* XXX: store address ? */
3765 void helper_mwait(void)
3767 if ((uint32_t)ECX
!= 0)
3768 raise_exception(EXCP0D_GPF
);
3769 /* XXX: not complete but not completely erroneous */
3770 if (env
->cpu_index
!= 0 || env
->next_cpu
!= NULL
) {
3771 /* more than one CPU: do not sleep because another CPU may
3778 float approx_rsqrt(float a
)
3780 return 1.0 / sqrt(a
);
3783 float approx_rcp(float a
)
3788 void update_fp_status(void)
3792 /* set rounding mode */
3793 switch(env
->fpuc
& RC_MASK
) {
3796 rnd_type
= float_round_nearest_even
;
3799 rnd_type
= float_round_down
;
3802 rnd_type
= float_round_up
;
3805 rnd_type
= float_round_to_zero
;
3808 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
3810 switch((env
->fpuc
>> 8) & 3) {
3822 set_floatx80_rounding_precision(rnd_type
, &env
->fp_status
);
3826 #if !defined(CONFIG_USER_ONLY)
3828 #define MMUSUFFIX _mmu
3829 #define GETPC() (__builtin_return_address(0))
3832 #include "softmmu_template.h"
3835 #include "softmmu_template.h"
3838 #include "softmmu_template.h"
3841 #include "softmmu_template.h"
3845 /* try to fill the TLB and return an exception if error. If retaddr is
3846 NULL, it means that the function was called in C code (i.e. not
3847 from generated code or from helper.c) */
3848 /* XXX: fix it to restore all registers */
3849 void tlb_fill(target_ulong addr
, int is_write
, int is_user
, void *retaddr
)
3851 TranslationBlock
*tb
;
3854 CPUX86State
*saved_env
;
3856 /* XXX: hack to restore env in all cases, even if not called from
3859 env
= cpu_single_env
;
3861 ret
= cpu_x86_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
3864 /* now we have a real cpu fault */
3865 pc
= (unsigned long)retaddr
;
3866 tb
= tb_find_pc(pc
);
3868 /* the PC is inside the translated code. It means that we have
3869 a virtual CPU fault */
3870 cpu_restore_state(tb
, env
, pc
, NULL
);
3874 raise_exception_err(env
->exception_index
, env
->error_code
);
3876 raise_exception_err_norestore(env
->exception_index
, env
->error_code
);