hw/slavio_timer.c

   1 /*
   2  * QEMU Sparc SLAVIO timer controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_TIMER
  27
  28 #ifdef DEBUG_TIMER
  29 #define DPRINTF(fmt, args...) \
  30 do { printf("TIMER: " fmt , ##args); } while (0)
  31 #else
  32 #define DPRINTF(fmt, args...)
  33 #endif
  34
  35 /*
  36  * Registers of hardware timer in sun4m.
  37  *
  38  * This is the timer/counter part of chip STP2001 (Slave I/O), also
  39  * produced as NCR89C105. See
  40  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  41  *
  42  * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  43  * are zero. Bit 31 is 1 when count has been reached.
  44  *
  45  * Per-CPU timers interrupt local CPU, system timer uses normal
  46  * interrupt routing.
  47  *
  48  */
  49
  50 typedef struct SLAVIO_TIMERState {
  51     ptimer_state *timer;
  52     uint32_t count, counthigh, reached;
  53     uint64_t limit;
  54     int irq;
  55     int stopped;
  56     int mode; // 0 = processor, 1 = user, 2 = system
  57     unsigned int cpu;
  58     void *intctl;
  59 } SLAVIO_TIMERState;
  60
  61 #define TIMER_MAXADDR 0x1f
  62 #define TIMER_SIZE (TIMER_MAXADDR + 1)
  63
  64 // Update count, set irq, update expire_time
  65 // Convert from ptimer countdown units
  66 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
  67 {
  68     uint64_t count;
  69
  70     count = s->limit - (ptimer_get_count(s->timer) << 9);
  71     DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
  72             s->count);
  73     s->count = count & 0xfffffe00;
  74     s->counthigh = count >> 32;
  75 }
  76
  77 // timer callback
  78 static void slavio_timer_irq(void *opaque)
  79 {
  80     SLAVIO_TIMERState *s = opaque;
  81
  82     slavio_timer_get_out(s);
  83     DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
  84     s->reached = 0x80000000;
  85     if (s->mode != 1)
  86         pic_set_irq_cpu(s->intctl, s->irq, 1, s->cpu);
  87 }
  88
  89 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
  90 {
  91     SLAVIO_TIMERState *s = opaque;
  92     uint32_t saddr, ret;
  93
  94     saddr = (addr & TIMER_MAXADDR) >> 2;
  95     switch (saddr) {
  96     case 0:
  97         // read limit (system counter mode) or read most signifying
  98         // part of counter (user mode)
  99         if (s->mode != 1) {
 100             // clear irq
 101             pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
 102             s->reached = 0;
 103             ret = s->limit & 0x7fffffff;
 104         }
 105         else {
 106             slavio_timer_get_out(s);
 107             ret = s->counthigh & 0x7fffffff;
 108         }
 109         break;
 110     case 1:
 111         // read counter and reached bit (system mode) or read lsbits
 112         // of counter (user mode)
 113         slavio_timer_get_out(s);
 114         if (s->mode != 1)
 115             ret = (s->count & 0x7fffffff) | s->reached;
 116         else
 117             ret = s->count;
 118         break;
 119     case 3:
 120         // read start/stop status
 121         ret = s->stopped;
 122         break;
 123     case 4:
 124         // read user/system mode
 125         ret = s->mode & 1;
 126         break;
 127     default:
 128         ret = 0;
 129         break;
 130     }
 131     DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
 132
 133     return ret;
 134 }
 135
 136 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 137 {
 138     SLAVIO_TIMERState *s = opaque;
 139     uint32_t saddr;
 140     int reload = 0;
 141
 142     DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
 143     saddr = (addr & TIMER_MAXADDR) >> 2;
 144     switch (saddr) {
 145     case 0:
 146         // set limit, reset counter
 147         reload = 1;
 148         pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
 149         // fall through
 150     case 2:
 151         // set limit without resetting counter
 152         s->limit = val & 0x7ffffe00ULL;
 153         if (!s->limit)
 154             s->limit = 0x7ffffe00ULL;
 155         ptimer_set_limit(s->timer, s->limit >> 9, reload);
 156         break;
 157     case 3:
 158         // start/stop user counter
 159         if (s->mode == 1) {
 160             if (val & 1) {
 161                 ptimer_stop(s->timer);
 162                 s->stopped = 1;
 163             }
 164             else {
 165                 ptimer_run(s->timer, 0);
 166                 s->stopped = 0;
 167             }
 168         }
 169         break;
 170     case 4:
 171         // bit 0: user (1) or system (0) counter mode
 172         if (s->mode == 0 || s->mode == 1)
 173             s->mode = val & 1;
 174         if (s->mode == 1) {
 175             pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
 176             s->limit = -1ULL;
 177         }
 178         ptimer_set_limit(s->timer, s->limit >> 9, 1);
 179         break;
 180     default:
 181         break;
 182     }
 183 }
 184
 185 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
 186     slavio_timer_mem_readl,
 187     slavio_timer_mem_readl,
 188     slavio_timer_mem_readl,
 189 };
 190
 191 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
 192     slavio_timer_mem_writel,
 193     slavio_timer_mem_writel,
 194     slavio_timer_mem_writel,
 195 };
 196
 197 static void slavio_timer_save(QEMUFile *f, void *opaque)
 198 {
 199     SLAVIO_TIMERState *s = opaque;
 200
 201     qemu_put_be64s(f, &s->limit);
 202     qemu_put_be32s(f, &s->count);
 203     qemu_put_be32s(f, &s->counthigh);
 204     qemu_put_be32s(f, &s->irq);
 205     qemu_put_be32s(f, &s->reached);
 206     qemu_put_be32s(f, &s->stopped);
 207     qemu_put_be32s(f, &s->mode);
 208     qemu_put_ptimer(f, s->timer);
 209 }
 210
 211 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
 212 {
 213     SLAVIO_TIMERState *s = opaque;
 214
 215     if (version_id != 2)
 216         return -EINVAL;
 217
 218     qemu_get_be64s(f, &s->limit);
 219     qemu_get_be32s(f, &s->count);
 220     qemu_get_be32s(f, &s->counthigh);
 221     qemu_get_be32s(f, &s->irq);
 222     qemu_get_be32s(f, &s->reached);
 223     qemu_get_be32s(f, &s->stopped);
 224     qemu_get_be32s(f, &s->mode);
 225     qemu_get_ptimer(f, s->timer);
 226
 227     return 0;
 228 }
 229
 230 static void slavio_timer_reset(void *opaque)
 231 {
 232     SLAVIO_TIMERState *s = opaque;
 233
 234     s->limit = 0x7ffffe00ULL;
 235     s->count = 0;
 236     s->reached = 0;
 237     s->mode &= 2;
 238     ptimer_set_limit(s->timer, s->limit >> 9, 1);
 239     ptimer_run(s->timer, 0);
 240     s->stopped = 1;
 241     slavio_timer_irq(s);
 242 }
 243
 244 void slavio_timer_init(target_phys_addr_t addr, int irq, int mode,
 245                        unsigned int cpu, void *intctl)
 246 {
 247     int slavio_timer_io_memory;
 248     SLAVIO_TIMERState *s;
 249     QEMUBH *bh;
 250
 251     s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
 252     if (!s)
 253         return;
 254     s->irq = irq;
 255     s->mode = mode;
 256     s->cpu = cpu;
 257     bh = qemu_bh_new(slavio_timer_irq, s);
 258     s->timer = ptimer_init(bh);
 259     ptimer_set_period(s->timer, 500ULL);
 260     s->intctl = intctl;
 261
 262     slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
 263                                                     slavio_timer_mem_write, s);
 264     cpu_register_physical_memory(addr, TIMER_SIZE, slavio_timer_io_memory);
 265     register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
 266     qemu_register_reset(slavio_timer_reset, s);
 267     slavio_timer_reset(s);
 268 }