hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 //#define DEBUG_IRQ_COUNT
  26 //#define DEBUG_IRQ
  27
  28 #ifdef DEBUG_IRQ
  29 #define DPRINTF(fmt, args...) \
  30 do { printf("IRQ: " fmt , ##args); } while (0)
  31 #else
  32 #define DPRINTF(fmt, args...)
  33 #endif
  34
  35 /*
  36  * Registers of interrupt controller in sun4m.
  37  *
  38  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  39  * produced as NCR89C105. See
  40  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  41  *
  42  * There is a system master controller and one for each cpu.
  43  *
  44  */
  45
  46 #define MAX_CPUS 16
  47
  48 typedef struct SLAVIO_INTCTLState {
  49     uint32_t intreg_pending[MAX_CPUS];
  50     uint32_t intregm_pending;
  51     uint32_t intregm_disabled;
  52     uint32_t target_cpu;
  53 #ifdef DEBUG_IRQ_COUNT
  54     uint64_t irq_count[32];
  55 #endif
  56     CPUState *cpu_envs[MAX_CPUS];
  57     const uint32_t *intbit_to_level;
  58 } SLAVIO_INTCTLState;
  59
  60 #define INTCTL_MAXADDR 0xf
  61 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  62 #define INTCTLM_MAXADDR 0x13
  63 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
  64 #define INTCTLM_MASK 0x1f
  65 static void slavio_check_interrupts(void *opaque);
  66
  67 // per-cpu interrupt controller
  68 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  69 {
  70     SLAVIO_INTCTLState *s = opaque;
  71     uint32_t saddr;
  72     int cpu;
  73
  74     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
  75     saddr = (addr & INTCTL_MAXADDR) >> 2;
  76     switch (saddr) {
  77     case 0:
  78         return s->intreg_pending[cpu];
  79     default:
  80         break;
  81     }
  82     return 0;
  83 }
  84
  85 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  86 {
  87     SLAVIO_INTCTLState *s = opaque;
  88     uint32_t saddr;
  89     int cpu;
  90
  91     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
  92     saddr = (addr & INTCTL_MAXADDR) >> 2;
  93     switch (saddr) {
  94     case 1: // clear pending softints
  95         if (val & 0x4000)
  96             val |= 80000000;
  97         val &= 0xfffe0000;
  98         s->intreg_pending[cpu] &= ~val;
  99         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 100         break;
 101     case 2: // set softint
 102         val &= 0xfffe0000;
 103         s->intreg_pending[cpu] |= val;
 104         slavio_check_interrupts(s);
 105         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 106         break;
 107     default:
 108         break;
 109     }
 110 }
 111
 112 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
 113     slavio_intctl_mem_readl,
 114     slavio_intctl_mem_readl,
 115     slavio_intctl_mem_readl,
 116 };
 117
 118 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 119     slavio_intctl_mem_writel,
 120     slavio_intctl_mem_writel,
 121     slavio_intctl_mem_writel,
 122 };
 123
 124 // master system interrupt controller
 125 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 126 {
 127     SLAVIO_INTCTLState *s = opaque;
 128     uint32_t saddr;
 129
 130     saddr = (addr & INTCTLM_MAXADDR) >> 2;
 131     switch (saddr) {
 132     case 0:
 133         return s->intregm_pending & 0x7fffffff;
 134     case 1:
 135         return s->intregm_disabled;
 136     case 4:
 137         return s->target_cpu;
 138     default:
 139         break;
 140     }
 141     return 0;
 142 }
 143
 144 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 145 {
 146     SLAVIO_INTCTLState *s = opaque;
 147     uint32_t saddr;
 148
 149     saddr = (addr & INTCTLM_MASK) >> 2;
 150     switch (saddr) {
 151     case 2: // clear (enable)
 152         // Force clear unused bits
 153         val &= ~0x4fb2007f;
 154         s->intregm_disabled &= ~val;
 155         DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 156         slavio_check_interrupts(s);
 157         break;
 158     case 3: // set (disable, clear pending)
 159         // Force clear unused bits
 160         val &= ~0x4fb2007f;
 161         s->intregm_disabled |= val;
 162         s->intregm_pending &= ~val;
 163         DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 164         break;
 165     case 4:
 166         s->target_cpu = val & (MAX_CPUS - 1);
 167         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 168         break;
 169     default:
 170         break;
 171     }
 172 }
 173
 174 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
 175     slavio_intctlm_mem_readl,
 176     slavio_intctlm_mem_readl,
 177     slavio_intctlm_mem_readl,
 178 };
 179
 180 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
 181     slavio_intctlm_mem_writel,
 182     slavio_intctlm_mem_writel,
 183     slavio_intctlm_mem_writel,
 184 };
 185
 186 void slavio_pic_info(void *opaque)
 187 {
 188     SLAVIO_INTCTLState *s = opaque;
 189     int i;
 190
 191     for (i = 0; i < MAX_CPUS; i++) {
 192         term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
 193     }
 194     term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
 195 }
 196
 197 void slavio_irq_info(void *opaque)
 198 {
 199 #ifndef DEBUG_IRQ_COUNT
 200     term_printf("irq statistic code not compiled.\n");
 201 #else
 202     SLAVIO_INTCTLState *s = opaque;
 203     int i;
 204     int64_t count;
 205
 206     term_printf("IRQ statistics:\n");
 207     for (i = 0; i < 32; i++) {
 208         count = s->irq_count[i];
 209         if (count > 0)
 210             term_printf("%2d: %" PRId64 "\n", i, count);
 211     }
 212 #endif
 213 }
 214
 215 static void slavio_check_interrupts(void *opaque)
 216 {
 217     CPUState *env;
 218     SLAVIO_INTCTLState *s = opaque;
 219     uint32_t pending = s->intregm_pending;
 220     unsigned int i, j, max = 0;
 221
 222     pending &= ~s->intregm_disabled;
 223
 224     if (pending && !(s->intregm_disabled & 0x80000000)) {
 225         for (i = 0; i < 32; i++) {
 226             if (pending & (1 << i)) {
 227                 if (max < s->intbit_to_level[i])
 228                     max = s->intbit_to_level[i];
 229             }
 230         }
 231         env = s->cpu_envs[s->target_cpu];
 232         if (!env) {
 233             DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
 234         }
 235         else {
 236             if (env->halted)
 237                 env->halted = 0;
 238             if (env->interrupt_index == 0) {
 239                 DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
 240 #ifdef DEBUG_IRQ_COUNT
 241                 s->irq_count[max]++;
 242 #endif
 243                 env->interrupt_index = TT_EXTINT | max;
 244                 cpu_interrupt(env, CPU_INTERRUPT_HARD);
 245             }
 246             else
 247                 DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
 248         }
 249     }
 250     else
 251         DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
 252
 253     for (i = 0; i < MAX_CPUS; i++) {
 254         max = 0;
 255         env = s->cpu_envs[i];
 256         if (!env)
 257             continue;
 258         for (j = 17; j < 32; j++) {
 259             if (s->intreg_pending[i] & (1 << j)) {
 260                 if (max < j - 16)
 261                     max = j - 16;
 262             }
 263         }
 264         if (max > 0) {
 265             if (env->halted)
 266                 env->halted = 0;
 267             if (env->interrupt_index == 0) {
 268                 DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
 269 #ifdef DEBUG_IRQ_COUNT
 270                 s->irq_count[max]++;
 271 #endif
 272                 env->interrupt_index = TT_EXTINT | max;
 273                 cpu_interrupt(env, CPU_INTERRUPT_HARD);
 274             }
 275         }
 276     }
 277 }
 278
 279 /*
 280  * "irq" here is the bit number in the system interrupt register to
 281  * separate serial and keyboard interrupts sharing a level.
 282  */
 283 void slavio_set_irq(void *opaque, int irq, int level)
 284 {
 285     SLAVIO_INTCTLState *s = opaque;
 286
 287     DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
 288     if (irq < 32) {
 289         uint32_t mask = 1 << irq;
 290         uint32_t pil = s->intbit_to_level[irq];
 291         if (pil > 0) {
 292             if (level) {
 293                 s->intregm_pending |= mask;
 294                 s->intreg_pending[s->target_cpu] |= 1 << pil;
 295                 slavio_check_interrupts(s);
 296             }
 297             else {
 298                 s->intregm_pending &= ~mask;
 299                 s->intreg_pending[s->target_cpu] &= ~(1 << pil);
 300             }
 301         }
 302     }
 303 }
 304
 305 void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
 306 {
 307     SLAVIO_INTCTLState *s = opaque;
 308
 309     DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
 310     if (cpu == (unsigned int)-1) {
 311         slavio_set_irq(opaque, irq, level);
 312         return;
 313     }
 314     if (irq < 32) {
 315         uint32_t pil = s->intbit_to_level[irq];
 316         if (pil > 0) {
 317             if (level) {
 318                 s->intreg_pending[cpu] |= 1 << pil;
 319             }
 320             else {
 321                 s->intreg_pending[cpu] &= ~(1 << pil);
 322             }
 323         }
 324     }
 325     slavio_check_interrupts(s);
 326 }
 327
 328 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 329 {
 330     SLAVIO_INTCTLState *s = opaque;
 331     int i;
 332
 333     for (i = 0; i < MAX_CPUS; i++) {
 334         qemu_put_be32s(f, &s->intreg_pending[i]);
 335     }
 336     qemu_put_be32s(f, &s->intregm_pending);
 337     qemu_put_be32s(f, &s->intregm_disabled);
 338     qemu_put_be32s(f, &s->target_cpu);
 339 }
 340
 341 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
 342 {
 343     SLAVIO_INTCTLState *s = opaque;
 344     int i;
 345
 346     if (version_id != 1)
 347         return -EINVAL;
 348
 349     for (i = 0; i < MAX_CPUS; i++) {
 350         qemu_get_be32s(f, &s->intreg_pending[i]);
 351     }
 352     qemu_get_be32s(f, &s->intregm_pending);
 353     qemu_get_be32s(f, &s->intregm_disabled);
 354     qemu_get_be32s(f, &s->target_cpu);
 355     return 0;
 356 }
 357
 358 static void slavio_intctl_reset(void *opaque)
 359 {
 360     SLAVIO_INTCTLState *s = opaque;
 361     int i;
 362
 363     for (i = 0; i < MAX_CPUS; i++) {
 364         s->intreg_pending[i] = 0;
 365     }
 366     s->intregm_disabled = ~0xffb2007f;
 367     s->intregm_pending = 0;
 368     s->target_cpu = 0;
 369 }
 370
 371 void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
 372 {
 373     SLAVIO_INTCTLState *s = opaque;
 374     s->cpu_envs[cpu] = env;
 375 }
 376
 377 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
 378                          const uint32_t *intbit_to_level,
 379                          qemu_irq **irq)
 380 {
 381     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
 382     SLAVIO_INTCTLState *s;
 383
 384     s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
 385     if (!s)
 386         return NULL;
 387
 388     s->intbit_to_level = intbit_to_level;
 389     for (i = 0; i < MAX_CPUS; i++) {
 390         slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
 391         cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
 392                                      slavio_intctl_io_memory);
 393     }
 394
 395     slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
 396     cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
 397
 398     register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
 399     qemu_register_reset(slavio_intctl_reset, s);
 400     *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
 401     slavio_intctl_reset(s);
 402     return s;
 403 }
 404