2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also
31 * produced as NCR89C100. See
32 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
38 #define DPRINTF(fmt, args...) \
39 do { printf("ESP: " fmt , ##args); } while (0)
41 #define DPRINTF(fmt, args...)
46 #define ESP_SIZE (ESP_REGS * 4)
48 /* The HBA is ID 7, so for simplicitly limit to 7 devices. */
49 #define ESP_MAX_DEVS 7
51 typedef struct ESPState ESPState
;
54 BlockDriverState
**bd
;
55 uint8_t rregs
[ESP_REGS
];
56 uint8_t wregs
[ESP_REGS
];
58 uint32_t ti_rptr
, ti_wptr
;
59 uint8_t ti_buf
[TI_BUFSZ
];
62 SCSIDevice
*scsi_dev
[MAX_DISKS
];
63 SCSIDevice
*current_dev
;
64 uint8_t cmdbuf
[TI_BUFSZ
];
68 /* The amount of data left in the current DMA transfer. */
70 /* The size of the current DMA transfer. Zero if no transfer is in
98 static int get_cmd(ESPState
*s
, uint8_t *buf
)
103 dmalen
= s
->rregs
[0] | (s
->rregs
[1] << 8);
104 target
= s
->wregs
[4] & 7;
105 DPRINTF("get_cmd: len %d target %d\n", dmalen
, target
);
107 espdma_memory_read(s
->dma_opaque
, buf
, dmalen
);
110 memcpy(&buf
[1], s
->ti_buf
, dmalen
);
118 if (s
->current_dev
) {
119 /* Started a new command before the old one finished. Cancel it. */
120 scsi_cancel_io(s
->current_dev
, 0);
124 if (target
>= MAX_DISKS
|| !s
->scsi_dev
[target
]) {
126 s
->rregs
[4] = STAT_IN
;
127 s
->rregs
[5] = INTR_DC
;
129 espdma_raise_irq(s
->dma_opaque
);
132 s
->current_dev
= s
->scsi_dev
[target
];
136 static void do_cmd(ESPState
*s
, uint8_t *buf
)
141 DPRINTF("do_cmd: busid 0x%x\n", buf
[0]);
143 datalen
= scsi_send_command(s
->current_dev
, 0, &buf
[1], lun
);
144 s
->ti_size
= datalen
;
146 s
->rregs
[4] = STAT_IN
| STAT_TC
;
150 s
->rregs
[4] |= STAT_DI
;
151 scsi_read_data(s
->current_dev
, 0);
153 s
->rregs
[4] |= STAT_DO
;
154 scsi_write_data(s
->current_dev
, 0);
157 s
->rregs
[5] = INTR_BS
| INTR_FC
;
158 s
->rregs
[6] = SEQ_CD
;
159 espdma_raise_irq(s
->dma_opaque
);
162 static void handle_satn(ESPState
*s
)
167 len
= get_cmd(s
, buf
);
172 static void handle_satn_stop(ESPState
*s
)
174 s
->cmdlen
= get_cmd(s
, s
->cmdbuf
);
176 DPRINTF("Set ATN & Stop: cmdlen %d\n", s
->cmdlen
);
178 s
->rregs
[4] = STAT_IN
| STAT_TC
| STAT_CD
;
179 s
->rregs
[5] = INTR_BS
| INTR_FC
;
180 s
->rregs
[6] = SEQ_CD
;
181 espdma_raise_irq(s
->dma_opaque
);
185 static void write_response(ESPState
*s
)
187 DPRINTF("Transfer status (sense=%d)\n", s
->sense
);
188 s
->ti_buf
[0] = s
->sense
;
191 espdma_memory_write(s
->dma_opaque
, s
->ti_buf
, 2);
192 s
->rregs
[4] = STAT_IN
| STAT_TC
| STAT_ST
;
193 s
->rregs
[5] = INTR_BS
| INTR_FC
;
194 s
->rregs
[6] = SEQ_CD
;
201 espdma_raise_irq(s
->dma_opaque
);
204 static void esp_dma_done(ESPState
*s
)
206 s
->rregs
[4] |= STAT_IN
| STAT_TC
;
207 s
->rregs
[5] = INTR_BS
;
212 espdma_raise_irq(s
->dma_opaque
);
215 static void esp_do_dma(ESPState
*s
)
220 to_device
= (s
->ti_size
< 0);
223 DPRINTF("command len %d + %d\n", s
->cmdlen
, len
);
224 espdma_memory_read(s
->dma_opaque
, &s
->cmdbuf
[s
->cmdlen
], len
);
228 do_cmd(s
, s
->cmdbuf
);
231 if (s
->async_len
== 0) {
232 /* Defer until data is available. */
235 if (len
> s
->async_len
) {
239 espdma_memory_read(s
->dma_opaque
, s
->async_buf
, len
);
241 espdma_memory_write(s
->dma_opaque
, s
->async_buf
, len
);
250 if (s
->async_len
== 0) {
252 // ti_size is negative
253 scsi_write_data(s
->current_dev
, 0);
255 scsi_read_data(s
->current_dev
, 0);
256 /* If there is still data to be read from the device then
257 complete the DMA operation immeriately. Otherwise defer
258 until the scsi layer has completed. */
259 if (s
->dma_left
== 0 && s
->ti_size
> 0) {
264 /* Partially filled a scsi buffer. Complete immediately. */
269 static void esp_command_complete(void *opaque
, int reason
, uint32_t tag
,
272 ESPState
*s
= (ESPState
*)opaque
;
274 if (reason
== SCSI_REASON_DONE
) {
275 DPRINTF("SCSI Command complete\n");
277 DPRINTF("SCSI command completed unexpectedly\n");
282 DPRINTF("Command failed\n");
284 s
->rregs
[4] = STAT_ST
;
286 s
->current_dev
= NULL
;
288 DPRINTF("transfer %d/%d\n", s
->dma_left
, s
->ti_size
);
290 s
->async_buf
= scsi_get_buf(s
->current_dev
, 0);
293 } else if (s
->dma_counter
!= 0 && s
->ti_size
<= 0) {
294 /* If this was the last part of a DMA transfer then the
295 completion interrupt is deferred to here. */
301 static void handle_ti(ESPState
*s
)
303 uint32_t dmalen
, minlen
;
305 dmalen
= s
->rregs
[0] | (s
->rregs
[1] << 8);
309 s
->dma_counter
= dmalen
;
312 minlen
= (dmalen
< 32) ? dmalen
: 32;
313 else if (s
->ti_size
< 0)
314 minlen
= (dmalen
< -s
->ti_size
) ? dmalen
: -s
->ti_size
;
316 minlen
= (dmalen
< s
->ti_size
) ? dmalen
: s
->ti_size
;
317 DPRINTF("Transfer Information len %d\n", minlen
);
319 s
->dma_left
= minlen
;
320 s
->rregs
[4] &= ~STAT_TC
;
322 } else if (s
->do_cmd
) {
323 DPRINTF("command len %d\n", s
->cmdlen
);
327 do_cmd(s
, s
->cmdbuf
);
332 static void esp_reset(void *opaque
)
334 ESPState
*s
= opaque
;
336 memset(s
->rregs
, 0, ESP_REGS
);
337 memset(s
->wregs
, 0, ESP_REGS
);
338 s
->rregs
[0x0e] = 0x4; // Indicate fas100a
346 static uint32_t esp_mem_readb(void *opaque
, target_phys_addr_t addr
)
348 ESPState
*s
= opaque
;
351 saddr
= (addr
& ESP_MASK
) >> 2;
352 DPRINTF("read reg[%d]: 0x%2.2x\n", saddr
, s
->rregs
[saddr
]);
356 if (s
->ti_size
> 0) {
358 if ((s
->rregs
[4] & 6) == 0) {
360 fprintf(stderr
, "esp: PIO data read not implemented\n");
363 s
->rregs
[2] = s
->ti_buf
[s
->ti_rptr
++];
365 espdma_raise_irq(s
->dma_opaque
);
367 if (s
->ti_size
== 0) {
374 // Clear interrupt/error status bits
375 s
->rregs
[4] &= ~(STAT_IN
| STAT_GE
| STAT_PE
);
376 espdma_clear_irq(s
->dma_opaque
);
381 return s
->rregs
[saddr
];
384 static void esp_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
386 ESPState
*s
= opaque
;
389 saddr
= (addr
& ESP_MASK
) >> 2;
390 DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr
, s
->wregs
[saddr
], val
);
394 s
->rregs
[4] &= ~STAT_TC
;
399 s
->cmdbuf
[s
->cmdlen
++] = val
& 0xff;
400 } else if ((s
->rregs
[4] & 6) == 0) {
404 fprintf(stderr
, "esp: PIO data write not implemented\n");
407 s
->ti_buf
[s
->ti_wptr
++] = val
& 0xff;
411 s
->rregs
[saddr
] = val
;
415 /* Reload DMA counter. */
416 s
->rregs
[0] = s
->wregs
[0];
417 s
->rregs
[1] = s
->wregs
[1];
423 DPRINTF("NOP (%2.2x)\n", val
);
426 DPRINTF("Flush FIFO (%2.2x)\n", val
);
428 s
->rregs
[5] = INTR_FC
;
432 DPRINTF("Chip reset (%2.2x)\n", val
);
436 DPRINTF("Bus reset (%2.2x)\n", val
);
437 s
->rregs
[5] = INTR_RST
;
438 if (!(s
->wregs
[8] & 0x40)) {
439 espdma_raise_irq(s
->dma_opaque
);
446 DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val
);
450 DPRINTF("Message Accepted (%2.2x)\n", val
);
452 s
->rregs
[5] = INTR_DC
;
456 DPRINTF("Set ATN (%2.2x)\n", val
);
459 DPRINTF("Set ATN (%2.2x)\n", val
);
463 DPRINTF("Set ATN & stop (%2.2x)\n", val
);
467 DPRINTF("Unhandled ESP command (%2.2x)\n", val
);
474 s
->rregs
[saddr
] = val
;
479 s
->rregs
[saddr
] = val
& 0x15;
482 s
->rregs
[saddr
] = val
;
487 s
->wregs
[saddr
] = val
;
490 static CPUReadMemoryFunc
*esp_mem_read
[3] = {
496 static CPUWriteMemoryFunc
*esp_mem_write
[3] = {
502 static void esp_save(QEMUFile
*f
, void *opaque
)
504 ESPState
*s
= opaque
;
506 qemu_put_buffer(f
, s
->rregs
, ESP_REGS
);
507 qemu_put_buffer(f
, s
->wregs
, ESP_REGS
);
508 qemu_put_be32s(f
, &s
->ti_size
);
509 qemu_put_be32s(f
, &s
->ti_rptr
);
510 qemu_put_be32s(f
, &s
->ti_wptr
);
511 qemu_put_buffer(f
, s
->ti_buf
, TI_BUFSZ
);
512 qemu_put_be32s(f
, &s
->sense
);
513 qemu_put_be32s(f
, &s
->dma
);
514 qemu_put_buffer(f
, s
->cmdbuf
, TI_BUFSZ
);
515 qemu_put_be32s(f
, &s
->cmdlen
);
516 qemu_put_be32s(f
, &s
->do_cmd
);
517 qemu_put_be32s(f
, &s
->dma_left
);
518 // There should be no transfers in progress, so dma_counter is not saved
521 static int esp_load(QEMUFile
*f
, void *opaque
, int version_id
)
523 ESPState
*s
= opaque
;
526 return -EINVAL
; // Cannot emulate 2
528 qemu_get_buffer(f
, s
->rregs
, ESP_REGS
);
529 qemu_get_buffer(f
, s
->wregs
, ESP_REGS
);
530 qemu_get_be32s(f
, &s
->ti_size
);
531 qemu_get_be32s(f
, &s
->ti_rptr
);
532 qemu_get_be32s(f
, &s
->ti_wptr
);
533 qemu_get_buffer(f
, s
->ti_buf
, TI_BUFSZ
);
534 qemu_get_be32s(f
, &s
->sense
);
535 qemu_get_be32s(f
, &s
->dma
);
536 qemu_get_buffer(f
, s
->cmdbuf
, TI_BUFSZ
);
537 qemu_get_be32s(f
, &s
->cmdlen
);
538 qemu_get_be32s(f
, &s
->do_cmd
);
539 qemu_get_be32s(f
, &s
->dma_left
);
544 void esp_scsi_attach(void *opaque
, BlockDriverState
*bd
, int id
)
546 ESPState
*s
= (ESPState
*)opaque
;
549 for (id
= 0; id
< ESP_MAX_DEVS
; id
++) {
550 if (s
->scsi_dev
[id
] == NULL
)
554 if (id
>= ESP_MAX_DEVS
) {
555 DPRINTF("Bad Device ID %d\n", id
);
558 if (s
->scsi_dev
[id
]) {
559 DPRINTF("Destroying device %d\n", id
);
560 scsi_disk_destroy(s
->scsi_dev
[id
]);
562 DPRINTF("Attaching block device %d\n", id
);
563 /* Command queueing is not implemented. */
564 s
->scsi_dev
[id
] = scsi_disk_init(bd
, 0, esp_command_complete
, s
);
567 void *esp_init(BlockDriverState
**bd
, target_phys_addr_t espaddr
,
573 s
= qemu_mallocz(sizeof(ESPState
));
578 s
->dma_opaque
= dma_opaque
;
579 sparc32_dma_set_reset_data(dma_opaque
, esp_reset
, s
);
581 esp_io_memory
= cpu_register_io_memory(0, esp_mem_read
, esp_mem_write
, s
);
582 cpu_register_physical_memory(espaddr
, ESP_SIZE
, esp_io_memory
);
586 register_savevm("esp", espaddr
, 3, esp_save
, esp_load
, s
);
587 qemu_register_reset(esp_reset
, s
);