2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licenced under the GPL.
13 target_phys_addr_t io_base
;
16 { 0x40100000, PXA2XX_PIC_FFUART
},
17 { 0x40200000, PXA2XX_PIC_BTUART
},
18 { 0x40700000, PXA2XX_PIC_STUART
},
19 { 0x41600000, PXA25X_PIC_HWUART
},
21 }, pxa270_serial
[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART
},
23 { 0x40200000, PXA2XX_PIC_BTUART
},
24 { 0x40700000, PXA2XX_PIC_STUART
},
29 target_phys_addr_t io_base
;
32 { 0x41000000, PXA2XX_PIC_SSP
},
35 { 0x41000000, PXA2XX_PIC_SSP
},
36 { 0x41400000, PXA25X_PIC_NSSP
},
39 { 0x41000000, PXA2XX_PIC_SSP
},
40 { 0x41400000, PXA25X_PIC_NSSP
},
41 { 0x41500000, PXA26X_PIC_ASSP
},
44 { 0x41000000, PXA2XX_PIC_SSP
},
45 { 0x41700000, PXA27X_PIC_SSP2
},
46 { 0x41900000, PXA2XX_PIC_SSP3
},
50 #define PMCR 0x00 /* Power Manager Control register */
51 #define PSSR 0x04 /* Power Manager Sleep Status register */
52 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
53 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
54 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
55 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
56 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
57 #define PCFR 0x1c /* Power Manager General Configuration register */
58 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
59 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
60 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
61 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
62 #define RCSR 0x30 /* Reset Controller Status register */
63 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
64 #define PTSR 0x38 /* Power Manager Standby Configuration register */
65 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
66 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
67 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
68 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
69 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
70 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
72 static uint32_t pxa2xx_i2c_read(void *, target_phys_addr_t
);
73 static void pxa2xx_i2c_write(void *, target_phys_addr_t
, uint32_t);
75 static uint32_t pxa2xx_pm_read(void *opaque
, target_phys_addr_t addr
)
77 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
78 if (addr
> s
->pm_base
+ PCMD31
) {
79 /* Special case: PWRI2C registers appear in the same range. */
80 return pxa2xx_i2c_read(s
->i2c
[1], addr
);
89 return s
->pm_regs
[addr
>> 2];
92 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
98 static void pxa2xx_pm_write(void *opaque
, target_phys_addr_t addr
,
101 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
102 if (addr
> s
->pm_base
+ PCMD31
) {
103 /* Special case: PWRI2C registers appear in the same range. */
104 pxa2xx_i2c_write(s
->i2c
[1], addr
, value
);
111 s
->pm_regs
[addr
>> 2] &= 0x15 & ~(value
& 0x2a);
112 s
->pm_regs
[addr
>> 2] |= value
& 0x15;
115 case PSSR
: /* Read-clean registers */
118 s
->pm_regs
[addr
>> 2] &= ~value
;
121 default: /* Read-write registers */
122 if (addr
>= PMCR
&& addr
<= PCMD31
&& !(addr
& 3)) {
123 s
->pm_regs
[addr
>> 2] = value
;
127 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
132 static CPUReadMemoryFunc
*pxa2xx_pm_readfn
[] = {
138 static CPUWriteMemoryFunc
*pxa2xx_pm_writefn
[] = {
144 static void pxa2xx_pm_save(QEMUFile
*f
, void *opaque
)
146 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
149 for (i
= 0; i
< 0x40; i
++)
150 qemu_put_be32s(f
, &s
->pm_regs
[i
]);
153 static int pxa2xx_pm_load(QEMUFile
*f
, void *opaque
, int version_id
)
155 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
158 for (i
= 0; i
< 0x40; i
++)
159 qemu_get_be32s(f
, &s
->pm_regs
[i
]);
164 #define CCCR 0x00 /* Core Clock Configuration register */
165 #define CKEN 0x04 /* Clock Enable register */
166 #define OSCC 0x08 /* Oscillator Configuration register */
167 #define CCSR 0x0c /* Core Clock Status register */
169 static uint32_t pxa2xx_cm_read(void *opaque
, target_phys_addr_t addr
)
171 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
178 return s
->cm_regs
[addr
>> 2];
181 return s
->cm_regs
[CCCR
>> 2] | (3 << 28);
184 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
190 static void pxa2xx_cm_write(void *opaque
, target_phys_addr_t addr
,
193 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
199 s
->cm_regs
[addr
>> 2] = value
;
203 s
->cm_regs
[addr
>> 2] &= ~0x6c;
204 s
->cm_regs
[addr
>> 2] |= value
& 0x6e;
205 if ((value
>> 1) & 1) /* OON */
206 s
->cm_regs
[addr
>> 2] |= 1 << 0; /* Oscillator is now stable */
210 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
215 static CPUReadMemoryFunc
*pxa2xx_cm_readfn
[] = {
221 static CPUWriteMemoryFunc
*pxa2xx_cm_writefn
[] = {
227 static void pxa2xx_cm_save(QEMUFile
*f
, void *opaque
)
229 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
232 for (i
= 0; i
< 4; i
++)
233 qemu_put_be32s(f
, &s
->cm_regs
[i
]);
234 qemu_put_be32s(f
, &s
->clkcfg
);
235 qemu_put_be32s(f
, &s
->pmnc
);
238 static int pxa2xx_cm_load(QEMUFile
*f
, void *opaque
, int version_id
)
240 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
243 for (i
= 0; i
< 4; i
++)
244 qemu_get_be32s(f
, &s
->cm_regs
[i
]);
245 qemu_get_be32s(f
, &s
->clkcfg
);
246 qemu_get_be32s(f
, &s
->pmnc
);
251 static uint32_t pxa2xx_clkpwr_read(void *opaque
, int op2
, int reg
, int crm
)
253 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
256 case 6: /* Clock Configuration register */
259 case 7: /* Power Mode register */
263 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
269 static void pxa2xx_clkpwr_write(void *opaque
, int op2
, int reg
, int crm
,
272 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
273 static const char *pwrmode
[8] = {
274 "Normal", "Idle", "Deep-idle", "Standby",
275 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
279 case 6: /* Clock Configuration register */
280 s
->clkcfg
= value
& 0xf;
282 printf("%s: CPU frequency change attempt\n", __FUNCTION__
);
285 case 7: /* Power Mode register */
287 printf("%s: CPU voltage change attempt\n", __FUNCTION__
);
295 if (!(s
->cm_regs
[CCCR
] & (1 << 31))) { /* CPDIS */
296 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
303 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
304 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
308 s
->env
->uncached_cpsr
=
309 ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
310 s
->env
->cp15
.c1_sys
= 0;
311 s
->env
->cp15
.c1_coproc
= 0;
312 s
->env
->cp15
.c2_base
= 0;
314 s
->pm_regs
[PSSR
>> 2] |= 0x8; /* Set STS */
315 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
318 * The scratch-pad register is almost universally used
319 * for storing the return address on suspend. For the
320 * lack of a resuming bootloader, perform a jump
321 * directly to that address.
323 memset(s
->env
->regs
, 0, 4 * 15);
324 s
->env
->regs
[15] = s
->pm_regs
[PSPR
>> 2];
327 buffer
= 0xe59ff000; /* ldr pc, [pc, #0] */
328 cpu_physical_memory_write(0, &buffer
, 4);
329 buffer
= s
->pm_regs
[PSPR
>> 2];
330 cpu_physical_memory_write(8, &buffer
, 4);
334 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
340 printf("%s: machine entered %s mode\n", __FUNCTION__
,
346 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
351 /* Performace Monitoring Registers */
352 #define CPPMNC 0 /* Performance Monitor Control register */
353 #define CPCCNT 1 /* Clock Counter register */
354 #define CPINTEN 4 /* Interrupt Enable register */
355 #define CPFLAG 5 /* Overflow Flag register */
356 #define CPEVTSEL 8 /* Event Selection register */
358 #define CPPMN0 0 /* Performance Count register 0 */
359 #define CPPMN1 1 /* Performance Count register 1 */
360 #define CPPMN2 2 /* Performance Count register 2 */
361 #define CPPMN3 3 /* Performance Count register 3 */
363 static uint32_t pxa2xx_perf_read(void *opaque
, int op2
, int reg
, int crm
)
365 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
372 return qemu_get_clock(vm_clock
);
381 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
387 static void pxa2xx_perf_write(void *opaque
, int op2
, int reg
, int crm
,
390 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
404 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
409 static uint32_t pxa2xx_cp14_read(void *opaque
, int op2
, int reg
, int crm
)
413 return pxa2xx_clkpwr_read(opaque
, op2
, reg
, crm
);
415 return pxa2xx_perf_read(opaque
, op2
, reg
, crm
);
426 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
432 static void pxa2xx_cp14_write(void *opaque
, int op2
, int reg
, int crm
,
437 pxa2xx_clkpwr_write(opaque
, op2
, reg
, crm
, value
);
440 pxa2xx_perf_write(opaque
, op2
, reg
, crm
, value
);
452 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
457 #define MDCNFG 0x00 /* SDRAM Configuration register */
458 #define MDREFR 0x04 /* SDRAM Refresh Control register */
459 #define MSC0 0x08 /* Static Memory Control register 0 */
460 #define MSC1 0x0c /* Static Memory Control register 1 */
461 #define MSC2 0x10 /* Static Memory Control register 2 */
462 #define MECR 0x14 /* Expansion Memory Bus Config register */
463 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
464 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
465 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
466 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
467 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
468 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
469 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
470 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
471 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
472 #define ARB_CNTL 0x48 /* Arbiter Control register */
473 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
474 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
475 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
476 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
477 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
478 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
479 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
481 static uint32_t pxa2xx_mm_read(void *opaque
, target_phys_addr_t addr
)
483 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
487 case MDCNFG
... SA1110
:
489 return s
->mm_regs
[addr
>> 2];
492 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
498 static void pxa2xx_mm_write(void *opaque
, target_phys_addr_t addr
,
501 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
505 case MDCNFG
... SA1110
:
506 if ((addr
& 3) == 0) {
507 s
->mm_regs
[addr
>> 2] = value
;
512 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
517 static CPUReadMemoryFunc
*pxa2xx_mm_readfn
[] = {
523 static CPUWriteMemoryFunc
*pxa2xx_mm_writefn
[] = {
529 static void pxa2xx_mm_save(QEMUFile
*f
, void *opaque
)
531 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
534 for (i
= 0; i
< 0x1a; i
++)
535 qemu_put_be32s(f
, &s
->mm_regs
[i
]);
538 static int pxa2xx_mm_load(QEMUFile
*f
, void *opaque
, int version_id
)
540 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
543 for (i
= 0; i
< 0x1a; i
++)
544 qemu_get_be32s(f
, &s
->mm_regs
[i
]);
549 /* Synchronous Serial Ports */
550 struct pxa2xx_ssp_s
{
551 target_phys_addr_t base
;
564 uint32_t rx_fifo
[16];
568 uint32_t (*readfn
)(void *opaque
);
569 void (*writefn
)(void *opaque
, uint32_t value
);
573 #define SSCR0 0x00 /* SSP Control register 0 */
574 #define SSCR1 0x04 /* SSP Control register 1 */
575 #define SSSR 0x08 /* SSP Status register */
576 #define SSITR 0x0c /* SSP Interrupt Test register */
577 #define SSDR 0x10 /* SSP Data register */
578 #define SSTO 0x28 /* SSP Time-Out register */
579 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
580 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
581 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
582 #define SSTSS 0x38 /* SSP Time Slot Status register */
583 #define SSACD 0x3c /* SSP Audio Clock Divider register */
585 /* Bitfields for above registers */
586 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
587 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
588 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
589 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
590 #define SSCR0_SSE (1 << 7)
591 #define SSCR0_RIM (1 << 22)
592 #define SSCR0_TIM (1 << 23)
593 #define SSCR0_MOD (1 << 31)
594 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
595 #define SSCR1_RIE (1 << 0)
596 #define SSCR1_TIE (1 << 1)
597 #define SSCR1_LBM (1 << 2)
598 #define SSCR1_MWDS (1 << 5)
599 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
600 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
601 #define SSCR1_EFWR (1 << 14)
602 #define SSCR1_PINTE (1 << 18)
603 #define SSCR1_TINTE (1 << 19)
604 #define SSCR1_RSRE (1 << 20)
605 #define SSCR1_TSRE (1 << 21)
606 #define SSCR1_EBCEI (1 << 29)
607 #define SSITR_INT (7 << 5)
608 #define SSSR_TNF (1 << 2)
609 #define SSSR_RNE (1 << 3)
610 #define SSSR_TFS (1 << 5)
611 #define SSSR_RFS (1 << 6)
612 #define SSSR_ROR (1 << 7)
613 #define SSSR_PINT (1 << 18)
614 #define SSSR_TINT (1 << 19)
615 #define SSSR_EOC (1 << 20)
616 #define SSSR_TUR (1 << 21)
617 #define SSSR_BCE (1 << 23)
618 #define SSSR_RW 0x00bc0080
620 static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s
*s
)
624 level
|= s
->ssitr
& SSITR_INT
;
625 level
|= (s
->sssr
& SSSR_BCE
) && (s
->sscr
[1] & SSCR1_EBCEI
);
626 level
|= (s
->sssr
& SSSR_TUR
) && !(s
->sscr
[0] & SSCR0_TIM
);
627 level
|= (s
->sssr
& SSSR_EOC
) && (s
->sssr
& (SSSR_TINT
| SSSR_PINT
));
628 level
|= (s
->sssr
& SSSR_TINT
) && (s
->sscr
[1] & SSCR1_TINTE
);
629 level
|= (s
->sssr
& SSSR_PINT
) && (s
->sscr
[1] & SSCR1_PINTE
);
630 level
|= (s
->sssr
& SSSR_ROR
) && !(s
->sscr
[0] & SSCR0_RIM
);
631 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
632 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
633 qemu_set_irq(s
->irq
, !!level
);
636 static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s
*s
)
638 s
->sssr
&= ~(0xf << 12); /* Clear RFL */
639 s
->sssr
&= ~(0xf << 8); /* Clear TFL */
640 s
->sssr
&= ~SSSR_TNF
;
642 s
->sssr
|= ((s
->rx_level
- 1) & 0xf) << 12;
643 if (s
->rx_level
>= SSCR1_RFT(s
->sscr
[1]))
646 s
->sssr
&= ~SSSR_RFS
;
647 if (0 <= SSCR1_TFT(s
->sscr
[1]))
650 s
->sssr
&= ~SSSR_TFS
;
654 s
->sssr
&= ~SSSR_RNE
;
658 pxa2xx_ssp_int_update(s
);
661 static uint32_t pxa2xx_ssp_read(void *opaque
, target_phys_addr_t addr
)
663 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
679 return s
->sssr
| s
->ssitr
;
683 if (s
->rx_level
< 1) {
684 printf("%s: SSP Rx Underrun\n", __FUNCTION__
);
688 retval
= s
->rx_fifo
[s
->rx_start
++];
690 pxa2xx_ssp_fifo_update(s
);
701 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
707 static void pxa2xx_ssp_write(void *opaque
, target_phys_addr_t addr
,
710 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
715 s
->sscr
[0] = value
& 0xc7ffffff;
716 s
->enable
= value
& SSCR0_SSE
;
717 if (value
& SSCR0_MOD
)
718 printf("%s: Attempt to use network mode\n", __FUNCTION__
);
719 if (s
->enable
&& SSCR0_DSS(value
) < 4)
720 printf("%s: Wrong data size: %i bits\n", __FUNCTION__
,
722 if (!(value
& SSCR0_SSE
)) {
727 pxa2xx_ssp_fifo_update(s
);
732 if (value
& (SSCR1_LBM
| SSCR1_EFWR
))
733 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__
);
734 pxa2xx_ssp_fifo_update(s
);
746 s
->ssitr
= value
& SSITR_INT
;
747 pxa2xx_ssp_int_update(s
);
751 s
->sssr
&= ~(value
& SSSR_RW
);
752 pxa2xx_ssp_int_update(s
);
756 if (SSCR0_UWIRE(s
->sscr
[0])) {
757 if (s
->sscr
[1] & SSCR1_MWDS
)
762 /* Note how 32bits overflow does no harm here */
763 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
765 /* Data goes from here to the Tx FIFO and is shifted out from
766 * there directly to the slave, no need to buffer it.
770 s
->writefn(s
->opaque
, value
);
772 if (s
->rx_level
< 0x10) {
774 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] =
775 s
->readfn(s
->opaque
);
777 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] = 0x0;
781 pxa2xx_ssp_fifo_update(s
);
797 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
802 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s
*port
,
803 uint32_t (*readfn
)(void *opaque
),
804 void (*writefn
)(void *opaque
, uint32_t value
), void *opaque
)
807 printf("%s: no such SSP\n", __FUNCTION__
);
811 port
->opaque
= opaque
;
812 port
->readfn
= readfn
;
813 port
->writefn
= writefn
;
816 static CPUReadMemoryFunc
*pxa2xx_ssp_readfn
[] = {
822 static CPUWriteMemoryFunc
*pxa2xx_ssp_writefn
[] = {
828 static void pxa2xx_ssp_save(QEMUFile
*f
, void *opaque
)
830 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
833 qemu_put_be32(f
, s
->enable
);
835 qemu_put_be32s(f
, &s
->sscr
[0]);
836 qemu_put_be32s(f
, &s
->sscr
[1]);
837 qemu_put_be32s(f
, &s
->sspsp
);
838 qemu_put_be32s(f
, &s
->ssto
);
839 qemu_put_be32s(f
, &s
->ssitr
);
840 qemu_put_be32s(f
, &s
->sssr
);
841 qemu_put_8s(f
, &s
->sstsa
);
842 qemu_put_8s(f
, &s
->ssrsa
);
843 qemu_put_8s(f
, &s
->ssacd
);
845 qemu_put_byte(f
, s
->rx_level
);
846 for (i
= 0; i
< s
->rx_level
; i
++)
847 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 0xf]);
850 static int pxa2xx_ssp_load(QEMUFile
*f
, void *opaque
, int version_id
)
852 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
855 s
->enable
= qemu_get_be32(f
);
857 qemu_get_be32s(f
, &s
->sscr
[0]);
858 qemu_get_be32s(f
, &s
->sscr
[1]);
859 qemu_get_be32s(f
, &s
->sspsp
);
860 qemu_get_be32s(f
, &s
->ssto
);
861 qemu_get_be32s(f
, &s
->ssitr
);
862 qemu_get_be32s(f
, &s
->sssr
);
863 qemu_get_8s(f
, &s
->sstsa
);
864 qemu_get_8s(f
, &s
->ssrsa
);
865 qemu_get_8s(f
, &s
->ssacd
);
867 s
->rx_level
= qemu_get_byte(f
);
869 for (i
= 0; i
< s
->rx_level
; i
++)
870 s
->rx_fifo
[i
] = qemu_get_byte(f
);
875 /* Real-Time Clock */
876 #define RCNR 0x00 /* RTC Counter register */
877 #define RTAR 0x04 /* RTC Alarm register */
878 #define RTSR 0x08 /* RTC Status register */
879 #define RTTR 0x0c /* RTC Timer Trim register */
880 #define RDCR 0x10 /* RTC Day Counter register */
881 #define RYCR 0x14 /* RTC Year Counter register */
882 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
883 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
884 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
885 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
886 #define SWCR 0x28 /* RTC Stopwatch Counter register */
887 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
888 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
889 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
890 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
892 static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s
*s
)
894 qemu_set_irq(s
->pic
[PXA2XX_PIC_RTCALARM
], !!(s
->rtsr
& 0x2553));
897 static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s
*s
)
899 int64_t rt
= qemu_get_clock(rt_clock
);
900 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
901 (1000 * ((s
->rttr
& 0xffff) + 1));
902 s
->last_rdcr
+= ((rt
- s
->last_hz
) << 15) /
903 (1000 * ((s
->rttr
& 0xffff) + 1));
907 static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s
*s
)
909 int64_t rt
= qemu_get_clock(rt_clock
);
910 if (s
->rtsr
& (1 << 12))
911 s
->last_swcr
+= (rt
- s
->last_sw
) / 10;
915 static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s
*s
)
917 int64_t rt
= qemu_get_clock(rt_clock
);
918 if (s
->rtsr
& (1 << 15))
919 s
->last_swcr
+= rt
- s
->last_pi
;
923 static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s
*s
,
926 if ((rtsr
& (1 << 2)) && !(rtsr
& (1 << 0)))
927 qemu_mod_timer(s
->rtc_hz
, s
->last_hz
+
928 (((s
->rtar
- s
->last_rcnr
) * 1000 *
929 ((s
->rttr
& 0xffff) + 1)) >> 15));
931 qemu_del_timer(s
->rtc_hz
);
933 if ((rtsr
& (1 << 5)) && !(rtsr
& (1 << 4)))
934 qemu_mod_timer(s
->rtc_rdal1
, s
->last_hz
+
935 (((s
->rdar1
- s
->last_rdcr
) * 1000 *
936 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
938 qemu_del_timer(s
->rtc_rdal1
);
940 if ((rtsr
& (1 << 7)) && !(rtsr
& (1 << 6)))
941 qemu_mod_timer(s
->rtc_rdal2
, s
->last_hz
+
942 (((s
->rdar2
- s
->last_rdcr
) * 1000 *
943 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
945 qemu_del_timer(s
->rtc_rdal2
);
947 if ((rtsr
& 0x1200) == 0x1200 && !(rtsr
& (1 << 8)))
948 qemu_mod_timer(s
->rtc_swal1
, s
->last_sw
+
949 (s
->swar1
- s
->last_swcr
) * 10); /* TODO: fixup */
951 qemu_del_timer(s
->rtc_swal1
);
953 if ((rtsr
& 0x1800) == 0x1800 && !(rtsr
& (1 << 10)))
954 qemu_mod_timer(s
->rtc_swal2
, s
->last_sw
+
955 (s
->swar2
- s
->last_swcr
) * 10); /* TODO: fixup */
957 qemu_del_timer(s
->rtc_swal2
);
959 if ((rtsr
& 0xc000) == 0xc000 && !(rtsr
& (1 << 13)))
960 qemu_mod_timer(s
->rtc_pi
, s
->last_pi
+
961 (s
->piar
& 0xffff) - s
->last_rtcpicr
);
963 qemu_del_timer(s
->rtc_pi
);
966 static inline void pxa2xx_rtc_hz_tick(void *opaque
)
968 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
970 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
971 pxa2xx_rtc_int_update(s
);
974 static inline void pxa2xx_rtc_rdal1_tick(void *opaque
)
976 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
978 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
979 pxa2xx_rtc_int_update(s
);
982 static inline void pxa2xx_rtc_rdal2_tick(void *opaque
)
984 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
986 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
987 pxa2xx_rtc_int_update(s
);
990 static inline void pxa2xx_rtc_swal1_tick(void *opaque
)
992 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
994 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
995 pxa2xx_rtc_int_update(s
);
998 static inline void pxa2xx_rtc_swal2_tick(void *opaque
)
1000 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1001 s
->rtsr
|= (1 << 10);
1002 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1003 pxa2xx_rtc_int_update(s
);
1006 static inline void pxa2xx_rtc_pi_tick(void *opaque
)
1008 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1009 s
->rtsr
|= (1 << 13);
1010 pxa2xx_rtc_piupdate(s
);
1011 s
->last_rtcpicr
= 0;
1012 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1013 pxa2xx_rtc_int_update(s
);
1016 static uint32_t pxa2xx_rtc_read(void *opaque
, target_phys_addr_t addr
)
1018 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1019 addr
-= s
->rtc_base
;
1043 return s
->last_rcnr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
1044 (1000 * ((s
->rttr
& 0xffff) + 1));
1046 return s
->last_rdcr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
1047 (1000 * ((s
->rttr
& 0xffff) + 1));
1049 return s
->last_rycr
;
1051 if (s
->rtsr
& (1 << 12))
1052 return s
->last_swcr
+ (qemu_get_clock(rt_clock
) - s
->last_sw
) / 10;
1054 return s
->last_swcr
;
1056 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1062 static void pxa2xx_rtc_write(void *opaque
, target_phys_addr_t addr
,
1065 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1066 addr
-= s
->rtc_base
;
1070 if (!(s
->rttr
& (1 << 31))) {
1071 pxa2xx_rtc_hzupdate(s
);
1073 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1078 if ((s
->rtsr
^ value
) & (1 << 15))
1079 pxa2xx_rtc_piupdate(s
);
1081 if ((s
->rtsr
^ value
) & (1 << 12))
1082 pxa2xx_rtc_swupdate(s
);
1084 if (((s
->rtsr
^ value
) & 0x4aac) | (value
& ~0xdaac))
1085 pxa2xx_rtc_alarm_update(s
, value
);
1087 s
->rtsr
= (value
& 0xdaac) | (s
->rtsr
& ~(value
& ~0xdaac));
1088 pxa2xx_rtc_int_update(s
);
1093 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1098 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1103 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1108 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1113 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1117 pxa2xx_rtc_swupdate(s
);
1120 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1125 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1130 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1134 pxa2xx_rtc_hzupdate(s
);
1135 s
->last_rcnr
= value
;
1136 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1140 pxa2xx_rtc_hzupdate(s
);
1141 s
->last_rdcr
= value
;
1142 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1146 s
->last_rycr
= value
;
1150 pxa2xx_rtc_swupdate(s
);
1151 s
->last_swcr
= value
;
1152 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1156 pxa2xx_rtc_piupdate(s
);
1157 s
->last_rtcpicr
= value
& 0xffff;
1158 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1162 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1166 static CPUReadMemoryFunc
*pxa2xx_rtc_readfn
[] = {
1172 static CPUWriteMemoryFunc
*pxa2xx_rtc_writefn
[] = {
1178 static void pxa2xx_rtc_init(struct pxa2xx_state_s
*s
)
1191 tm
= localtime(&ti
);
1192 wom
= ((tm
->tm_mday
- 1) / 7) + 1;
1194 s
->last_rcnr
= (uint32_t) ti
;
1195 s
->last_rdcr
= (wom
<< 20) | ((tm
->tm_wday
+ 1) << 17) |
1196 (tm
->tm_hour
<< 12) | (tm
->tm_min
<< 6) | tm
->tm_sec
;
1197 s
->last_rycr
= ((tm
->tm_year
+ 1900) << 9) |
1198 ((tm
->tm_mon
+ 1) << 5) | tm
->tm_mday
;
1199 s
->last_swcr
= (tm
->tm_hour
<< 19) |
1200 (tm
->tm_min
<< 13) | (tm
->tm_sec
<< 7);
1201 s
->last_rtcpicr
= 0;
1202 s
->last_hz
= s
->last_sw
= s
->last_pi
= qemu_get_clock(rt_clock
);
1204 s
->rtc_hz
= qemu_new_timer(rt_clock
, pxa2xx_rtc_hz_tick
, s
);
1205 s
->rtc_rdal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal1_tick
, s
);
1206 s
->rtc_rdal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal2_tick
, s
);
1207 s
->rtc_swal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal1_tick
, s
);
1208 s
->rtc_swal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal2_tick
, s
);
1209 s
->rtc_pi
= qemu_new_timer(rt_clock
, pxa2xx_rtc_pi_tick
, s
);
1212 static void pxa2xx_rtc_save(QEMUFile
*f
, void *opaque
)
1214 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1216 pxa2xx_rtc_hzupdate(s
);
1217 pxa2xx_rtc_piupdate(s
);
1218 pxa2xx_rtc_swupdate(s
);
1220 qemu_put_be32s(f
, &s
->rttr
);
1221 qemu_put_be32s(f
, &s
->rtsr
);
1222 qemu_put_be32s(f
, &s
->rtar
);
1223 qemu_put_be32s(f
, &s
->rdar1
);
1224 qemu_put_be32s(f
, &s
->rdar2
);
1225 qemu_put_be32s(f
, &s
->ryar1
);
1226 qemu_put_be32s(f
, &s
->ryar2
);
1227 qemu_put_be32s(f
, &s
->swar1
);
1228 qemu_put_be32s(f
, &s
->swar2
);
1229 qemu_put_be32s(f
, &s
->piar
);
1230 qemu_put_be32s(f
, &s
->last_rcnr
);
1231 qemu_put_be32s(f
, &s
->last_rdcr
);
1232 qemu_put_be32s(f
, &s
->last_rycr
);
1233 qemu_put_be32s(f
, &s
->last_swcr
);
1234 qemu_put_be32s(f
, &s
->last_rtcpicr
);
1235 qemu_put_be64s(f
, &s
->last_hz
);
1236 qemu_put_be64s(f
, &s
->last_sw
);
1237 qemu_put_be64s(f
, &s
->last_pi
);
1240 static int pxa2xx_rtc_load(QEMUFile
*f
, void *opaque
, int version_id
)
1242 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1244 qemu_get_be32s(f
, &s
->rttr
);
1245 qemu_get_be32s(f
, &s
->rtsr
);
1246 qemu_get_be32s(f
, &s
->rtar
);
1247 qemu_get_be32s(f
, &s
->rdar1
);
1248 qemu_get_be32s(f
, &s
->rdar2
);
1249 qemu_get_be32s(f
, &s
->ryar1
);
1250 qemu_get_be32s(f
, &s
->ryar2
);
1251 qemu_get_be32s(f
, &s
->swar1
);
1252 qemu_get_be32s(f
, &s
->swar2
);
1253 qemu_get_be32s(f
, &s
->piar
);
1254 qemu_get_be32s(f
, &s
->last_rcnr
);
1255 qemu_get_be32s(f
, &s
->last_rdcr
);
1256 qemu_get_be32s(f
, &s
->last_rycr
);
1257 qemu_get_be32s(f
, &s
->last_swcr
);
1258 qemu_get_be32s(f
, &s
->last_rtcpicr
);
1259 qemu_get_be64s(f
, &s
->last_hz
);
1260 qemu_get_be64s(f
, &s
->last_sw
);
1261 qemu_get_be64s(f
, &s
->last_pi
);
1263 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1269 struct pxa2xx_i2c_s
{
1272 target_phys_addr_t base
;
1281 #define IBMR 0x80 /* I2C Bus Monitor register */
1282 #define IDBR 0x88 /* I2C Data Buffer register */
1283 #define ICR 0x90 /* I2C Control register */
1284 #define ISR 0x98 /* I2C Status register */
1285 #define ISAR 0xa0 /* I2C Slave Address register */
1287 static void pxa2xx_i2c_update(struct pxa2xx_i2c_s
*s
)
1290 level
|= s
->status
& s
->control
& (1 << 10); /* BED */
1291 level
|= (s
->status
& (1 << 7)) && (s
->control
& (1 << 9)); /* IRF */
1292 level
|= (s
->status
& (1 << 6)) && (s
->control
& (1 << 8)); /* ITE */
1293 level
|= s
->status
& (1 << 9); /* SAD */
1294 qemu_set_irq(s
->irq
, !!level
);
1297 /* These are only stubs now. */
1298 static void pxa2xx_i2c_event(i2c_slave
*i2c
, enum i2c_event event
)
1300 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) i2c
;
1303 case I2C_START_SEND
:
1304 s
->status
|= (1 << 9); /* set SAD */
1305 s
->status
&= ~(1 << 0); /* clear RWM */
1307 case I2C_START_RECV
:
1308 s
->status
|= (1 << 9); /* set SAD */
1309 s
->status
|= 1 << 0; /* set RWM */
1312 s
->status
|= (1 << 4); /* set SSD */
1315 s
->status
|= 1 << 1; /* set ACKNAK */
1318 pxa2xx_i2c_update(s
);
1321 static int pxa2xx_i2c_rx(i2c_slave
*i2c
)
1323 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) i2c
;
1324 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1327 if (s
->status
& (1 << 0)) { /* RWM */
1328 s
->status
|= 1 << 6; /* set ITE */
1330 pxa2xx_i2c_update(s
);
1335 static int pxa2xx_i2c_tx(i2c_slave
*i2c
, uint8_t data
)
1337 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) i2c
;
1338 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1341 if (!(s
->status
& (1 << 0))) { /* RWM */
1342 s
->status
|= 1 << 7; /* set IRF */
1345 pxa2xx_i2c_update(s
);
1350 static uint32_t pxa2xx_i2c_read(void *opaque
, target_phys_addr_t addr
)
1352 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1359 return s
->status
| (i2c_bus_busy(s
->bus
) << 2);
1361 return s
->slave
.address
;
1365 if (s
->status
& (1 << 2))
1366 s
->ibmr
^= 3; /* Fake SCL and SDA pin changes */
1371 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1377 static void pxa2xx_i2c_write(void *opaque
, target_phys_addr_t addr
,
1380 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1386 s
->control
= value
& 0xfff7;
1387 if ((value
& (1 << 3)) && (value
& (1 << 6))) { /* TB and IUE */
1388 /* TODO: slave mode */
1389 if (value
& (1 << 0)) { /* START condition */
1391 s
->status
|= 1 << 0; /* set RWM */
1393 s
->status
&= ~(1 << 0); /* clear RWM */
1394 ack
= !i2c_start_transfer(s
->bus
, s
->data
>> 1, s
->data
& 1);
1396 if (s
->status
& (1 << 0)) { /* RWM */
1397 s
->data
= i2c_recv(s
->bus
);
1398 if (value
& (1 << 2)) /* ACKNAK */
1402 ack
= !i2c_send(s
->bus
, s
->data
);
1405 if (value
& (1 << 1)) /* STOP condition */
1406 i2c_end_transfer(s
->bus
);
1409 if (value
& (1 << 0)) /* START condition */
1410 s
->status
|= 1 << 6; /* set ITE */
1412 if (s
->status
& (1 << 0)) /* RWM */
1413 s
->status
|= 1 << 7; /* set IRF */
1415 s
->status
|= 1 << 6; /* set ITE */
1416 s
->status
&= ~(1 << 1); /* clear ACKNAK */
1418 s
->status
|= 1 << 6; /* set ITE */
1419 s
->status
|= 1 << 10; /* set BED */
1420 s
->status
|= 1 << 1; /* set ACKNAK */
1423 if (!(value
& (1 << 3)) && (value
& (1 << 6))) /* !TB and IUE */
1424 if (value
& (1 << 4)) /* MA */
1425 i2c_end_transfer(s
->bus
);
1426 pxa2xx_i2c_update(s
);
1430 s
->status
&= ~(value
& 0x07f0);
1431 pxa2xx_i2c_update(s
);
1435 i2c_set_slave_address(&s
->slave
, value
& 0x7f);
1439 s
->data
= value
& 0xff;
1443 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1447 static CPUReadMemoryFunc
*pxa2xx_i2c_readfn
[] = {
1453 static CPUWriteMemoryFunc
*pxa2xx_i2c_writefn
[] = {
1459 static void pxa2xx_i2c_save(QEMUFile
*f
, void *opaque
)
1461 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1463 qemu_put_be16s(f
, &s
->control
);
1464 qemu_put_be16s(f
, &s
->status
);
1465 qemu_put_8s(f
, &s
->ibmr
);
1466 qemu_put_8s(f
, &s
->data
);
1468 i2c_bus_save(f
, s
->bus
);
1469 i2c_slave_save(f
, &s
->slave
);
1472 static int pxa2xx_i2c_load(QEMUFile
*f
, void *opaque
, int version_id
)
1474 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1476 qemu_get_be16s(f
, &s
->control
);
1477 qemu_get_be16s(f
, &s
->status
);
1478 qemu_get_8s(f
, &s
->ibmr
);
1479 qemu_get_8s(f
, &s
->data
);
1481 i2c_bus_load(f
, s
->bus
);
1482 i2c_slave_load(f
, &s
->slave
);
1486 struct pxa2xx_i2c_s
*pxa2xx_i2c_init(target_phys_addr_t base
,
1487 qemu_irq irq
, int ioregister
)
1490 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*)
1491 i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s
));
1495 s
->slave
.event
= pxa2xx_i2c_event
;
1496 s
->slave
.recv
= pxa2xx_i2c_rx
;
1497 s
->slave
.send
= pxa2xx_i2c_tx
;
1498 s
->bus
= i2c_init_bus();
1501 iomemtype
= cpu_register_io_memory(0, pxa2xx_i2c_readfn
,
1502 pxa2xx_i2c_writefn
, s
);
1503 cpu_register_physical_memory(s
->base
& 0xfffff000, 0xfff, iomemtype
);
1506 register_savevm("pxa2xx_i2c", base
, 0,
1507 pxa2xx_i2c_save
, pxa2xx_i2c_load
, s
);
1512 i2c_bus
*pxa2xx_i2c_bus(struct pxa2xx_i2c_s
*s
)
1517 /* PXA Inter-IC Sound Controller */
1518 static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s
*i2s
)
1524 i2s
->control
[0] = 0x00;
1525 i2s
->control
[1] = 0x00;
1530 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1531 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1532 #define SACR_DREC(val) (val & (1 << 3))
1533 #define SACR_DPRL(val) (val & (1 << 4))
1535 static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s
*i2s
)
1538 rfs
= SACR_RFTH(i2s
->control
[0]) < i2s
->rx_len
&&
1539 !SACR_DREC(i2s
->control
[1]);
1540 tfs
= (i2s
->tx_len
|| i2s
->fifo_len
< SACR_TFTH(i2s
->control
[0])) &&
1541 i2s
->enable
&& !SACR_DPRL(i2s
->control
[1]);
1543 pxa2xx_dma_request(i2s
->dma
, PXA2XX_RX_RQ_I2S
, rfs
);
1544 pxa2xx_dma_request(i2s
->dma
, PXA2XX_TX_RQ_I2S
, tfs
);
1546 i2s
->status
&= 0xe0;
1548 i2s
->status
|= 1 << 1; /* RNE */
1550 i2s
->status
|= 1 << 2; /* BSY */
1552 i2s
->status
|= 1 << 3; /* TFS */
1554 i2s
->status
|= 1 << 4; /* RFS */
1555 if (!(i2s
->tx_len
&& i2s
->enable
))
1556 i2s
->status
|= i2s
->fifo_len
<< 8; /* TFL */
1557 i2s
->status
|= MAX(i2s
->rx_len
, 0xf) << 12; /* RFL */
1559 qemu_set_irq(i2s
->irq
, i2s
->status
& i2s
->mask
);
1562 #define SACR0 0x00 /* Serial Audio Global Control register */
1563 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1564 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1565 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1566 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1567 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1568 #define SADR 0x80 /* Serial Audio Data register */
1570 static uint32_t pxa2xx_i2s_read(void *opaque
, target_phys_addr_t addr
)
1572 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1577 return s
->control
[0];
1579 return s
->control
[1];
1589 if (s
->rx_len
> 0) {
1591 pxa2xx_i2s_update(s
);
1592 return s
->codec_in(s
->opaque
);
1596 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1602 static void pxa2xx_i2s_write(void *opaque
, target_phys_addr_t addr
,
1605 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1611 if (value
& (1 << 3)) /* RST */
1612 pxa2xx_i2s_reset(s
);
1613 s
->control
[0] = value
& 0xff3d;
1614 if (!s
->enable
&& (value
& 1) && s
->tx_len
) { /* ENB */
1615 for (sample
= s
->fifo
; s
->fifo_len
> 0; s
->fifo_len
--, sample
++)
1616 s
->codec_out(s
->opaque
, *sample
);
1617 s
->status
&= ~(1 << 7); /* I2SOFF */
1619 if (value
& (1 << 4)) /* EFWR */
1620 printf("%s: Attempt to use special function\n", __FUNCTION__
);
1621 s
->enable
= ((value
^ 4) & 5) == 5; /* ENB && !RST*/
1622 pxa2xx_i2s_update(s
);
1625 s
->control
[1] = value
& 0x0039;
1626 if (value
& (1 << 5)) /* ENLBF */
1627 printf("%s: Attempt to use loopback function\n", __FUNCTION__
);
1628 if (value
& (1 << 4)) /* DPRL */
1630 pxa2xx_i2s_update(s
);
1633 s
->mask
= value
& 0x0078;
1634 pxa2xx_i2s_update(s
);
1637 s
->status
&= ~(value
& (3 << 5));
1638 pxa2xx_i2s_update(s
);
1641 s
->clk
= value
& 0x007f;
1644 if (s
->tx_len
&& s
->enable
) {
1646 pxa2xx_i2s_update(s
);
1647 s
->codec_out(s
->opaque
, value
);
1648 } else if (s
->fifo_len
< 16) {
1649 s
->fifo
[s
->fifo_len
++] = value
;
1650 pxa2xx_i2s_update(s
);
1654 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1658 static CPUReadMemoryFunc
*pxa2xx_i2s_readfn
[] = {
1664 static CPUWriteMemoryFunc
*pxa2xx_i2s_writefn
[] = {
1670 static void pxa2xx_i2s_save(QEMUFile
*f
, void *opaque
)
1672 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1674 qemu_put_be32s(f
, &s
->control
[0]);
1675 qemu_put_be32s(f
, &s
->control
[1]);
1676 qemu_put_be32s(f
, &s
->status
);
1677 qemu_put_be32s(f
, &s
->mask
);
1678 qemu_put_be32s(f
, &s
->clk
);
1680 qemu_put_be32(f
, s
->enable
);
1681 qemu_put_be32(f
, s
->rx_len
);
1682 qemu_put_be32(f
, s
->tx_len
);
1683 qemu_put_be32(f
, s
->fifo_len
);
1686 static int pxa2xx_i2s_load(QEMUFile
*f
, void *opaque
, int version_id
)
1688 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1690 qemu_get_be32s(f
, &s
->control
[0]);
1691 qemu_get_be32s(f
, &s
->control
[1]);
1692 qemu_get_be32s(f
, &s
->status
);
1693 qemu_get_be32s(f
, &s
->mask
);
1694 qemu_get_be32s(f
, &s
->clk
);
1696 s
->enable
= qemu_get_be32(f
);
1697 s
->rx_len
= qemu_get_be32(f
);
1698 s
->tx_len
= qemu_get_be32(f
);
1699 s
->fifo_len
= qemu_get_be32(f
);
1704 static void pxa2xx_i2s_data_req(void *opaque
, int tx
, int rx
)
1706 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1709 /* Signal FIFO errors */
1710 if (s
->enable
&& s
->tx_len
)
1711 s
->status
|= 1 << 5; /* TUR */
1712 if (s
->enable
&& s
->rx_len
)
1713 s
->status
|= 1 << 6; /* ROR */
1715 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1716 * handle the cases where it makes a difference. */
1717 s
->tx_len
= tx
- s
->fifo_len
;
1719 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1721 for (sample
= s
->fifo
; s
->fifo_len
; s
->fifo_len
--, sample
++)
1722 s
->codec_out(s
->opaque
, *sample
);
1723 pxa2xx_i2s_update(s
);
1726 static struct pxa2xx_i2s_s
*pxa2xx_i2s_init(target_phys_addr_t base
,
1727 qemu_irq irq
, struct pxa2xx_dma_state_s
*dma
)
1730 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*)
1731 qemu_mallocz(sizeof(struct pxa2xx_i2s_s
));
1736 s
->data_req
= pxa2xx_i2s_data_req
;
1738 pxa2xx_i2s_reset(s
);
1740 iomemtype
= cpu_register_io_memory(0, pxa2xx_i2s_readfn
,
1741 pxa2xx_i2s_writefn
, s
);
1742 cpu_register_physical_memory(s
->base
& 0xfff00000, 0xfffff, iomemtype
);
1744 register_savevm("pxa2xx_i2s", base
, 0,
1745 pxa2xx_i2s_save
, pxa2xx_i2s_load
, s
);
1750 /* PXA Fast Infra-red Communications Port */
1751 struct pxa2xx_fir_s
{
1752 target_phys_addr_t base
;
1754 struct pxa2xx_dma_state_s
*dma
;
1756 CharDriverState
*chr
;
1763 uint8_t rx_fifo
[64];
1766 static void pxa2xx_fir_reset(struct pxa2xx_fir_s
*s
)
1768 s
->control
[0] = 0x00;
1769 s
->control
[1] = 0x00;
1770 s
->control
[2] = 0x00;
1771 s
->status
[0] = 0x00;
1772 s
->status
[1] = 0x00;
1776 static inline void pxa2xx_fir_update(struct pxa2xx_fir_s
*s
)
1778 static const int tresh
[4] = { 8, 16, 32, 0 };
1780 if ((s
->control
[0] & (1 << 4)) && /* RXE */
1781 s
->rx_len
>= tresh
[s
->control
[2] & 3]) /* TRIG */
1782 s
->status
[0] |= 1 << 4; /* RFS */
1784 s
->status
[0] &= ~(1 << 4); /* RFS */
1785 if (s
->control
[0] & (1 << 3)) /* TXE */
1786 s
->status
[0] |= 1 << 3; /* TFS */
1788 s
->status
[0] &= ~(1 << 3); /* TFS */
1790 s
->status
[1] |= 1 << 2; /* RNE */
1792 s
->status
[1] &= ~(1 << 2); /* RNE */
1793 if (s
->control
[0] & (1 << 4)) /* RXE */
1794 s
->status
[1] |= 1 << 0; /* RSY */
1796 s
->status
[1] &= ~(1 << 0); /* RSY */
1798 intr
|= (s
->control
[0] & (1 << 5)) && /* RIE */
1799 (s
->status
[0] & (1 << 4)); /* RFS */
1800 intr
|= (s
->control
[0] & (1 << 6)) && /* TIE */
1801 (s
->status
[0] & (1 << 3)); /* TFS */
1802 intr
|= (s
->control
[2] & (1 << 4)) && /* TRAIL */
1803 (s
->status
[0] & (1 << 6)); /* EOC */
1804 intr
|= (s
->control
[0] & (1 << 2)) && /* TUS */
1805 (s
->status
[0] & (1 << 1)); /* TUR */
1806 intr
|= s
->status
[0] & 0x25; /* FRE, RAB, EIF */
1808 pxa2xx_dma_request(s
->dma
, PXA2XX_RX_RQ_ICP
, (s
->status
[0] >> 4) & 1);
1809 pxa2xx_dma_request(s
->dma
, PXA2XX_TX_RQ_ICP
, (s
->status
[0] >> 3) & 1);
1811 qemu_set_irq(s
->irq
, intr
&& s
->enable
);
1814 #define ICCR0 0x00 /* FICP Control register 0 */
1815 #define ICCR1 0x04 /* FICP Control register 1 */
1816 #define ICCR2 0x08 /* FICP Control register 2 */
1817 #define ICDR 0x0c /* FICP Data register */
1818 #define ICSR0 0x14 /* FICP Status register 0 */
1819 #define ICSR1 0x18 /* FICP Status register 1 */
1820 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1822 static uint32_t pxa2xx_fir_read(void *opaque
, target_phys_addr_t addr
)
1824 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1830 return s
->control
[0];
1832 return s
->control
[1];
1834 return s
->control
[2];
1836 s
->status
[0] &= ~0x01;
1837 s
->status
[1] &= ~0x72;
1840 ret
= s
->rx_fifo
[s
->rx_start
++];
1842 pxa2xx_fir_update(s
);
1845 printf("%s: Rx FIFO underrun.\n", __FUNCTION__
);
1848 return s
->status
[0];
1850 return s
->status
[1] | (1 << 3); /* TNF */
1854 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1860 static void pxa2xx_fir_write(void *opaque
, target_phys_addr_t addr
,
1863 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1869 s
->control
[0] = value
;
1870 if (!(value
& (1 << 4))) /* RXE */
1871 s
->rx_len
= s
->rx_start
= 0;
1872 if (!(value
& (1 << 3))) /* TXE */
1874 s
->enable
= value
& 1; /* ITR */
1877 pxa2xx_fir_update(s
);
1880 s
->control
[1] = value
;
1883 s
->control
[2] = value
& 0x3f;
1884 pxa2xx_fir_update(s
);
1887 if (s
->control
[2] & (1 << 2)) /* TXP */
1891 if (s
->chr
&& s
->enable
&& (s
->control
[0] & (1 << 3))) /* TXE */
1892 qemu_chr_write(s
->chr
, &ch
, 1);
1895 s
->status
[0] &= ~(value
& 0x66);
1896 pxa2xx_fir_update(s
);
1901 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1905 static CPUReadMemoryFunc
*pxa2xx_fir_readfn
[] = {
1911 static CPUWriteMemoryFunc
*pxa2xx_fir_writefn
[] = {
1917 static int pxa2xx_fir_is_empty(void *opaque
)
1919 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1920 return (s
->rx_len
< 64);
1923 static void pxa2xx_fir_rx(void *opaque
, const uint8_t *buf
, int size
)
1925 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1926 if (!(s
->control
[0] & (1 << 4))) /* RXE */
1930 s
->status
[1] |= 1 << 4; /* EOF */
1931 if (s
->rx_len
>= 64) {
1932 s
->status
[1] |= 1 << 6; /* ROR */
1936 if (s
->control
[2] & (1 << 3)) /* RXP */
1937 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = *(buf
++);
1939 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = ~*(buf
++);
1942 pxa2xx_fir_update(s
);
1945 static void pxa2xx_fir_event(void *opaque
, int event
)
1949 static void pxa2xx_fir_save(QEMUFile
*f
, void *opaque
)
1951 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1954 qemu_put_be32(f
, s
->enable
);
1956 qemu_put_8s(f
, &s
->control
[0]);
1957 qemu_put_8s(f
, &s
->control
[1]);
1958 qemu_put_8s(f
, &s
->control
[2]);
1959 qemu_put_8s(f
, &s
->status
[0]);
1960 qemu_put_8s(f
, &s
->status
[1]);
1962 qemu_put_byte(f
, s
->rx_len
);
1963 for (i
= 0; i
< s
->rx_len
; i
++)
1964 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 63]);
1967 static int pxa2xx_fir_load(QEMUFile
*f
, void *opaque
, int version_id
)
1969 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1972 s
->enable
= qemu_get_be32(f
);
1974 qemu_get_8s(f
, &s
->control
[0]);
1975 qemu_get_8s(f
, &s
->control
[1]);
1976 qemu_get_8s(f
, &s
->control
[2]);
1977 qemu_get_8s(f
, &s
->status
[0]);
1978 qemu_get_8s(f
, &s
->status
[1]);
1980 s
->rx_len
= qemu_get_byte(f
);
1982 for (i
= 0; i
< s
->rx_len
; i
++)
1983 s
->rx_fifo
[i
] = qemu_get_byte(f
);
1988 static struct pxa2xx_fir_s
*pxa2xx_fir_init(target_phys_addr_t base
,
1989 qemu_irq irq
, struct pxa2xx_dma_state_s
*dma
,
1990 CharDriverState
*chr
)
1993 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*)
1994 qemu_mallocz(sizeof(struct pxa2xx_fir_s
));
2001 pxa2xx_fir_reset(s
);
2003 iomemtype
= cpu_register_io_memory(0, pxa2xx_fir_readfn
,
2004 pxa2xx_fir_writefn
, s
);
2005 cpu_register_physical_memory(s
->base
, 0xfff, iomemtype
);
2008 qemu_chr_add_handlers(chr
, pxa2xx_fir_is_empty
,
2009 pxa2xx_fir_rx
, pxa2xx_fir_event
, s
);
2011 register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save
, pxa2xx_fir_load
, s
);
2016 void pxa2xx_reset(int line
, int level
, void *opaque
)
2018 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
2019 if (level
&& (s
->pm_regs
[PCFR
>> 2] & 0x10)) { /* GPR_EN */
2021 /* TODO: reset peripherals */
2025 /* Initialise a PXA270 integrated chip (ARM based core). */
2026 struct pxa2xx_state_s
*pxa270_init(unsigned int sdram_size
,
2027 DisplayState
*ds
, const char *revision
)
2029 struct pxa2xx_state_s
*s
;
2030 struct pxa2xx_ssp_s
*ssp
;
2032 s
= (struct pxa2xx_state_s
*) qemu_mallocz(sizeof(struct pxa2xx_state_s
));
2034 if (revision
&& strncmp(revision
, "pxa27", 5)) {
2035 fprintf(stderr
, "Machine requires a PXA27x processor.\n");
2039 s
->env
= cpu_init();
2040 cpu_arm_set_model(s
->env
, revision
?: "pxa270");
2041 register_savevm("cpu", 0, 0, cpu_save
, cpu_load
, s
->env
);
2043 /* SDRAM & Internal Memory Storage */
2044 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
,
2045 sdram_size
, qemu_ram_alloc(sdram_size
) | IO_MEM_RAM
);
2046 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
,
2047 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM
);
2049 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2051 s
->dma
= pxa27x_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
2053 pxa27x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
],
2054 s
->pic
[PXA27X_PIC_OST_4_11
]);
2056 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 121);
2058 s
->mmc
= pxa2xx_mmci_init(0x41100000, s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
2060 for (i
= 0; pxa270_serial
[i
].io_base
; i
++)
2062 serial_mm_init(pxa270_serial
[i
].io_base
, 2,
2063 s
->pic
[pxa270_serial
[i
].irqn
], serial_hds
[i
], 1);
2067 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
2068 s
->dma
, serial_hds
[i
]);
2071 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
], ds
);
2073 s
->cm_base
= 0x41300000;
2074 s
->cm_regs
[CCCR
>> 4] = 0x02000210; /* 416.0 MHz */
2075 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2076 iomemtype
= cpu_register_io_memory(0, pxa2xx_cm_readfn
,
2077 pxa2xx_cm_writefn
, s
);
2078 cpu_register_physical_memory(s
->cm_base
, 0xfff, iomemtype
);
2079 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save
, pxa2xx_cm_load
, s
);
2081 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2083 s
->mm_base
= 0x48000000;
2084 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2085 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2086 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2087 iomemtype
= cpu_register_io_memory(0, pxa2xx_mm_readfn
,
2088 pxa2xx_mm_writefn
, s
);
2089 cpu_register_physical_memory(s
->mm_base
, 0xfff, iomemtype
);
2090 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save
, pxa2xx_mm_load
, s
);
2092 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++);
2093 s
->ssp
= (struct pxa2xx_ssp_s
**)
2094 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
*) * i
);
2095 ssp
= (struct pxa2xx_ssp_s
*)
2096 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
) * i
);
2097 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++) {
2098 s
->ssp
[i
] = &ssp
[i
];
2099 ssp
[i
].base
= pxa27x_ssp
[i
].io_base
;
2100 ssp
[i
].irq
= s
->pic
[pxa27x_ssp
[i
].irqn
];
2102 iomemtype
= cpu_register_io_memory(0, pxa2xx_ssp_readfn
,
2103 pxa2xx_ssp_writefn
, &ssp
[i
]);
2104 cpu_register_physical_memory(ssp
[i
].base
, 0xfff, iomemtype
);
2105 register_savevm("pxa2xx_ssp", i
, 0,
2106 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
2110 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
2113 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2114 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2116 s
->rtc_base
= 0x40900000;
2117 iomemtype
= cpu_register_io_memory(0, pxa2xx_rtc_readfn
,
2118 pxa2xx_rtc_writefn
, s
);
2119 cpu_register_physical_memory(s
->rtc_base
, 0xfff, iomemtype
);
2121 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save
, pxa2xx_rtc_load
, s
);
2123 /* Note that PM registers are in the same page with PWRI2C registers.
2124 * As a workaround we don't map PWRI2C into memory and we expect
2125 * PM handlers to call PWRI2C handlers when appropriate. */
2126 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600, s
->pic
[PXA2XX_PIC_I2C
], 1);
2127 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100, s
->pic
[PXA2XX_PIC_PWRI2C
], 0);
2129 s
->pm_base
= 0x40f00000;
2130 iomemtype
= cpu_register_io_memory(0, pxa2xx_pm_readfn
,
2131 pxa2xx_pm_writefn
, s
);
2132 cpu_register_physical_memory(s
->pm_base
, 0xfff, iomemtype
);
2133 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save
, pxa2xx_pm_load
, s
);
2135 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
2137 /* GPIO1 resets the processor */
2138 /* The handler can be overriden by board-specific code */
2139 pxa2xx_gpio_handler_set(s
->gpio
, 1, pxa2xx_reset
, s
);
2143 /* Initialise a PXA255 integrated chip (ARM based core). */
2144 struct pxa2xx_state_s
*pxa255_init(unsigned int sdram_size
,
2147 struct pxa2xx_state_s
*s
;
2148 struct pxa2xx_ssp_s
*ssp
;
2150 s
= (struct pxa2xx_state_s
*) qemu_mallocz(sizeof(struct pxa2xx_state_s
));
2152 s
->env
= cpu_init();
2153 cpu_arm_set_model(s
->env
, "pxa255");
2154 register_savevm("cpu", 0, 0, cpu_save
, cpu_load
, s
->env
);
2156 /* SDRAM & Internal Memory Storage */
2157 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
, sdram_size
,
2158 qemu_ram_alloc(sdram_size
) | IO_MEM_RAM
);
2159 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
, PXA2XX_INTERNAL_SIZE
,
2160 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE
) | IO_MEM_RAM
);
2162 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2164 s
->dma
= pxa255_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
2166 pxa25x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
]);
2168 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 85);
2170 s
->mmc
= pxa2xx_mmci_init(0x41100000, s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
2172 for (i
= 0; pxa255_serial
[i
].io_base
; i
++)
2174 serial_mm_init(pxa255_serial
[i
].io_base
, 2,
2175 s
->pic
[pxa255_serial
[i
].irqn
], serial_hds
[i
], 1);
2179 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
2180 s
->dma
, serial_hds
[i
]);
2183 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
], ds
);
2185 s
->cm_base
= 0x41300000;
2186 s
->cm_regs
[CCCR
>> 4] = 0x02000210; /* 416.0 MHz */
2187 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2188 iomemtype
= cpu_register_io_memory(0, pxa2xx_cm_readfn
,
2189 pxa2xx_cm_writefn
, s
);
2190 cpu_register_physical_memory(s
->cm_base
, 0xfff, iomemtype
);
2191 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save
, pxa2xx_cm_load
, s
);
2193 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2195 s
->mm_base
= 0x48000000;
2196 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2197 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2198 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2199 iomemtype
= cpu_register_io_memory(0, pxa2xx_mm_readfn
,
2200 pxa2xx_mm_writefn
, s
);
2201 cpu_register_physical_memory(s
->mm_base
, 0xfff, iomemtype
);
2202 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save
, pxa2xx_mm_load
, s
);
2204 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++);
2205 s
->ssp
= (struct pxa2xx_ssp_s
**)
2206 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
*) * i
);
2207 ssp
= (struct pxa2xx_ssp_s
*)
2208 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
) * i
);
2209 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++) {
2210 s
->ssp
[i
] = &ssp
[i
];
2211 ssp
[i
].base
= pxa255_ssp
[i
].io_base
;
2212 ssp
[i
].irq
= s
->pic
[pxa255_ssp
[i
].irqn
];
2214 iomemtype
= cpu_register_io_memory(0, pxa2xx_ssp_readfn
,
2215 pxa2xx_ssp_writefn
, &ssp
[i
]);
2216 cpu_register_physical_memory(ssp
[i
].base
, 0xfff, iomemtype
);
2217 register_savevm("pxa2xx_ssp", i
, 0,
2218 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
2222 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
2225 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2226 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2228 s
->rtc_base
= 0x40900000;
2229 iomemtype
= cpu_register_io_memory(0, pxa2xx_rtc_readfn
,
2230 pxa2xx_rtc_writefn
, s
);
2231 cpu_register_physical_memory(s
->rtc_base
, 0xfff, iomemtype
);
2233 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save
, pxa2xx_rtc_load
, s
);
2235 /* Note that PM registers are in the same page with PWRI2C registers.
2236 * As a workaround we don't map PWRI2C into memory and we expect
2237 * PM handlers to call PWRI2C handlers when appropriate. */
2238 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600, s
->pic
[PXA2XX_PIC_I2C
], 1);
2239 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100, s
->pic
[PXA2XX_PIC_PWRI2C
], 0);
2241 s
->pm_base
= 0x40f00000;
2242 iomemtype
= cpu_register_io_memory(0, pxa2xx_pm_readfn
,
2243 pxa2xx_pm_writefn
, s
);
2244 cpu_register_physical_memory(s
->pm_base
, 0xfff, iomemtype
);
2245 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save
, pxa2xx_pm_load
, s
);
2247 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
2249 /* GPIO1 resets the processor */
2250 /* The handler can be overriden by board-specific code */
2251 pxa2xx_gpio_handler_set(s
->gpio
, 1, pxa2xx_reset
, s
);