target-i386/helper2.c

   1 /*
   2  *  i386 helpers (without register variable usage)
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26 #include <assert.h>
  27 #include <sys/mman.h>
  28
  29 #include "cpu.h"
  30 #include "exec-all.h"
  31
  32 //#define DEBUG_MMU
  33
  34 CPUX86State *cpu_x86_init(void)
  35 {
  36     CPUX86State *env;
  37     int i;
  38     static int inited;
  39
  40     cpu_exec_init();
  41
  42     env = malloc(sizeof(CPUX86State));
  43     if (!env)
  44         return NULL;
  45     memset(env, 0, sizeof(CPUX86State));
  46     /* basic FPU init */
  47     for(i = 0;i < 8; i++)
  48         env->fptags[i] = 1;
  49     env->fpuc = 0x37f;
  50     /* flags setup : we activate the IRQs by default as in user mode */
  51     env->eflags = 0x2 | IF_MASK;
  52
  53     tlb_flush(env);
  54 #ifdef CONFIG_SOFTMMU
  55     env->hflags |= HF_SOFTMMU_MASK;
  56 #endif
  57     /* init various static tables */
  58     if (!inited) {
  59         inited = 1;
  60         optimize_flags_init();
  61     }
  62     return env;
  63 }
  64
  65 void cpu_x86_close(CPUX86State *env)
  66 {
  67     free(env);
  68 }
  69
  70 /***********************************************************/
  71 /* x86 debug */
  72
  73 static const char *cc_op_str[] = {
  74     "DYNAMIC",
  75     "EFLAGS",
  76     "MUL",
  77     "ADDB",
  78     "ADDW",
  79     "ADDL",
  80     "ADCB",
  81     "ADCW",
  82     "ADCL",
  83     "SUBB",
  84     "SUBW",
  85     "SUBL",
  86     "SBBB",
  87     "SBBW",
  88     "SBBL",
  89     "LOGICB",
  90     "LOGICW",
  91     "LOGICL",
  92     "INCB",
  93     "INCW",
  94     "INCL",
  95     "DECB",
  96     "DECW",
  97     "DECL",
  98     "SHLB",
  99     "SHLW",
 100     "SHLL",
 101     "SARB",
 102     "SARW",
 103     "SARL",
 104 };
 105
 106 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
 107 {
 108     int eflags;
 109     char cc_op_name[32];
 110
 111     eflags = env->eflags;
 112     fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
 113             "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
 114             "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c]\n",
 115             env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
 116             env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
 117             env->eip, eflags,
 118             eflags & DF_MASK ? 'D' : '-',
 119             eflags & CC_O ? 'O' : '-',
 120             eflags & CC_S ? 'S' : '-',
 121             eflags & CC_Z ? 'Z' : '-',
 122             eflags & CC_A ? 'A' : '-',
 123             eflags & CC_P ? 'P' : '-',
 124             eflags & CC_C ? 'C' : '-');
 125     fprintf(f, "CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x\n",
 126             env->segs[R_CS].selector,
 127             env->segs[R_SS].selector,
 128             env->segs[R_DS].selector,
 129             env->segs[R_ES].selector,
 130             env->segs[R_FS].selector,
 131             env->segs[R_GS].selector);
 132     if (flags & X86_DUMP_CCOP) {
 133         if ((unsigned)env->cc_op < CC_OP_NB)
 134             strcpy(cc_op_name, cc_op_str[env->cc_op]);
 135         else
 136             snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
 137         fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
 138                 env->cc_src, env->cc_dst, cc_op_name);
 139     }
 140     if (flags & X86_DUMP_FPU) {
 141         fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
 142                 (double)env->fpregs[0],
 143                 (double)env->fpregs[1],
 144                 (double)env->fpregs[2],
 145                 (double)env->fpregs[3]);
 146         fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
 147                 (double)env->fpregs[4],
 148                 (double)env->fpregs[5],
 149                 (double)env->fpregs[7],
 150                 (double)env->fpregs[8]);
 151     }
 152 }
 153
 154 /***********************************************************/
 155 /* x86 mmu */
 156 /* XXX: add PGE support */
 157
 158 /* called when cr3 or PG bit are modified */
 159 static int last_pg_state = -1;
 160 static int last_pe_state = 0;
 161 static uint32_t a20_mask;
 162 int a20_enabled;
 163
 164 int phys_ram_size;
 165 int phys_ram_fd;
 166 uint8_t *phys_ram_base;
 167
 168 void cpu_x86_set_a20(CPUX86State *env, int a20_state)
 169 {
 170     a20_state = (a20_state != 0);
 171     if (a20_state != a20_enabled) {
 172         /* when a20 is changed, all the MMU mappings are invalid, so
 173            we must flush everything */
 174         page_unmap();
 175         tlb_flush(env);
 176         a20_enabled = a20_state;
 177         if (a20_enabled)
 178             a20_mask = 0xffffffff;
 179         else
 180             a20_mask = 0xffefffff;
 181     }
 182 }
 183
 184 void cpu_x86_update_cr0(CPUX86State *env)
 185 {
 186     int pg_state, pe_state;
 187
 188 #ifdef DEBUG_MMU
 189     printf("CR0 update: CR0=0x%08x\n", env->cr[0]);
 190 #endif
 191     pg_state = env->cr[0] & CR0_PG_MASK;
 192     if (pg_state != last_pg_state) {
 193         page_unmap();
 194         tlb_flush(env);
 195         last_pg_state = pg_state;
 196     }
 197     pe_state = env->cr[0] & CR0_PE_MASK;
 198     if (last_pe_state != pe_state) {
 199         tb_flush();
 200         last_pe_state = pe_state;
 201     }
 202 }
 203
 204 void cpu_x86_update_cr3(CPUX86State *env)
 205 {
 206     if (env->cr[0] & CR0_PG_MASK) {
 207 #if defined(DEBUG_MMU)
 208         printf("CR3 update: CR3=%08x\n", env->cr[3]);
 209 #endif
 210         page_unmap();
 211         tlb_flush(env);
 212     }
 213 }
 214
 215 void cpu_x86_init_mmu(CPUX86State *env)
 216 {
 217     a20_enabled = 1;
 218     a20_mask = 0xffffffff;
 219
 220     last_pg_state = -1;
 221     cpu_x86_update_cr0(env);
 222 }
 223
 224 /* XXX: also flush 4MB pages */
 225 void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
 226 {
 227     int flags;
 228     unsigned long virt_addr;
 229
 230     tlb_flush_page(env, addr);
 231
 232     flags = page_get_flags(addr);
 233     if (flags & PAGE_VALID) {
 234         virt_addr = addr & ~0xfff;
 235 #if !defined(CONFIG_SOFTMMU)
 236         munmap((void *)virt_addr, 4096);
 237 #endif
 238         page_set_flags(virt_addr, virt_addr + 4096, 0);
 239     }
 240 }
 241
 242 /* return value:
 243    -1 = cannot handle fault
 244    0  = nothing more to do
 245    1  = generate PF fault
 246    2  = soft MMU activation required for this block
 247 */
 248 int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
 249                              int is_write, int is_user, int is_softmmu)
 250 {
 251     uint8_t *pde_ptr, *pte_ptr;
 252     uint32_t pde, pte, virt_addr;
 253     int error_code, is_dirty, prot, page_size, ret;
 254     unsigned long pd;
 255
 256 #ifdef DEBUG_MMU
 257     printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
 258            addr, is_write, is_user, env->eip);
 259 #endif
 260
 261     if (env->user_mode_only) {
 262         /* user mode only emulation */
 263         error_code = 0;
 264         goto do_fault;
 265     }
 266
 267     if (!(env->cr[0] & CR0_PG_MASK)) {
 268         pte = addr;
 269         virt_addr = addr & TARGET_PAGE_MASK;
 270         prot = PROT_READ | PROT_WRITE;
 271         page_size = 4096;
 272         goto do_mapping;
 273     }
 274
 275     /* page directory entry */
 276     pde_ptr = phys_ram_base +
 277         (((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & a20_mask);
 278     pde = ldl_raw(pde_ptr);
 279     if (!(pde & PG_PRESENT_MASK)) {
 280         error_code = 0;
 281         goto do_fault;
 282     }
 283     if (is_user) {
 284         if (!(pde & PG_USER_MASK))
 285             goto do_fault_protect;
 286         if (is_write && !(pde & PG_RW_MASK))
 287             goto do_fault_protect;
 288     } else {
 289         if ((env->cr[0] & CR0_WP_MASK) && (pde & PG_USER_MASK) &&
 290             is_write && !(pde & PG_RW_MASK))
 291             goto do_fault_protect;
 292     }
 293     /* if PSE bit is set, then we use a 4MB page */
 294     if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
 295         is_dirty = is_write && !(pde & PG_DIRTY_MASK);
 296         if (!(pde & PG_ACCESSED_MASK)) {
 297             pde |= PG_ACCESSED_MASK;
 298             if (is_dirty)
 299                 pde |= PG_DIRTY_MASK;
 300             stl_raw(pde_ptr, pde);
 301         }
 302
 303         pte = pde & ~0x003ff000; /* align to 4MB */
 304         page_size = 4096 * 1024;
 305         virt_addr = addr & ~0x003fffff;
 306     } else {
 307         if (!(pde & PG_ACCESSED_MASK)) {
 308             pde |= PG_ACCESSED_MASK;
 309             stl_raw(pde_ptr, pde);
 310         }
 311
 312         /* page directory entry */
 313         pte_ptr = phys_ram_base +
 314             (((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask);
 315         pte = ldl_raw(pte_ptr);
 316         if (!(pte & PG_PRESENT_MASK)) {
 317             error_code = 0;
 318             goto do_fault;
 319         }
 320         if (is_user) {
 321             if (!(pte & PG_USER_MASK))
 322                 goto do_fault_protect;
 323             if (is_write && !(pte & PG_RW_MASK))
 324                 goto do_fault_protect;
 325         } else {
 326             if ((env->cr[0] & CR0_WP_MASK) && (pte & PG_USER_MASK) &&
 327                 is_write && !(pte & PG_RW_MASK))
 328                 goto do_fault_protect;
 329         }
 330         is_dirty = is_write && !(pte & PG_DIRTY_MASK);
 331         if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
 332             pte |= PG_ACCESSED_MASK;
 333             if (is_dirty)
 334                 pte |= PG_DIRTY_MASK;
 335             stl_raw(pte_ptr, pte);
 336         }
 337         page_size = 4096;
 338         virt_addr = addr & ~0xfff;
 339     }
 340     /* the page can be put in the TLB */
 341     prot = PROT_READ;
 342     if (is_user) {
 343         if (pte & PG_RW_MASK)
 344             prot |= PROT_WRITE;
 345     } else {
 346         if (!(env->cr[0] & CR0_WP_MASK) || !(pte & PG_USER_MASK) ||
 347             (pte & PG_RW_MASK))
 348             prot |= PROT_WRITE;
 349     }
 350
 351  do_mapping:
 352     pte = pte & a20_mask;
 353 #if !defined(CONFIG_SOFTMMU)
 354     if (is_softmmu)
 355 #endif
 356     {
 357         unsigned long paddr, vaddr, address, addend, page_offset;
 358         int index;
 359
 360         /* software MMU case. Even if 4MB pages, we map only one 4KB
 361            page in the cache to avoid filling it too fast */
 362         page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
 363         paddr = (pte & TARGET_PAGE_MASK) + page_offset;
 364         vaddr = virt_addr + page_offset;
 365         index = (addr >> 12) & (CPU_TLB_SIZE - 1);
 366         pd = physpage_find(paddr);
 367         if (pd & 0xfff) {
 368             /* IO memory case */
 369             address = vaddr | pd;
 370             addend = paddr;
 371         } else {
 372             /* standard memory */
 373             address = vaddr;
 374             addend = (unsigned long)phys_ram_base + pd;
 375         }
 376         addend -= vaddr;
 377         env->tlb_read[is_user][index].address = address;
 378         env->tlb_read[is_user][index].addend = addend;
 379         if (prot & PROT_WRITE) {
 380             env->tlb_write[is_user][index].address = address;
 381             env->tlb_write[is_user][index].addend = addend;
 382         }
 383         page_set_flags(vaddr, vaddr + TARGET_PAGE_SIZE,
 384                        PAGE_VALID | PAGE_EXEC | prot);
 385         ret = 0;
 386     }
 387 #if !defined(CONFIG_SOFTMMU)
 388     else {
 389         ret = 0;
 390         /* XXX: incorrect for 4MB pages */
 391         pd = physpage_find(pte & ~0xfff);
 392         if ((pd & 0xfff) != 0) {
 393             /* IO access: no mapping is done as it will be handled by the
 394                soft MMU */
 395             if (!(env->hflags & HF_SOFTMMU_MASK))
 396                 ret = 2;
 397         } else {
 398             void *map_addr;
 399             map_addr = mmap((void *)virt_addr, page_size, prot,
 400                             MAP_SHARED | MAP_FIXED, phys_ram_fd, pd);
 401             if (map_addr == MAP_FAILED) {
 402                 fprintf(stderr,
 403                         "mmap failed when mapped physical address 0x%08x to virtual address 0x%08x\n",
 404                         pte & ~0xfff, virt_addr);
 405                 exit(1);
 406             }
 407 #ifdef DEBUG_MMU
 408             printf("mmaping 0x%08x to virt 0x%08x pse=%d\n",
 409                    pte & ~0xfff, virt_addr, (page_size != 4096));
 410 #endif
 411             page_set_flags(virt_addr, virt_addr + page_size,
 412                            PAGE_VALID | PAGE_EXEC | prot);
 413         }
 414     }
 415 #endif
 416     return ret;
 417  do_fault_protect:
 418     error_code = PG_ERROR_P_MASK;
 419  do_fault:
 420     env->cr[2] = addr;
 421     env->error_code = (is_write << PG_ERROR_W_BIT) | error_code;
 422     if (is_user)
 423         env->error_code |= PG_ERROR_U_MASK;
 424     return 1;
 425 }