target-ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if !defined (__CPU_PPC_H__)
  21 #define __CPU_PPC_H__
  22
  23 #include "config.h"
  24 #include <inttypes.h>
  25
  26 #if defined (TARGET_PPC64)
  27 typedef uint64_t ppc_gpr_t;
  28 #define TARGET_GPR_BITS  64
  29 #define TARGET_LONG_BITS 64
  30 #define REGX "%016" PRIx64
  31 #define TARGET_PAGE_BITS 12
  32 #elif defined(TARGET_PPCEMB)
  33 /* BookE have 36 bits physical address space */
  34 #define TARGET_PHYS_ADDR_BITS 64
  35 /* GPR are 64 bits: used by vector extension */
  36 typedef uint64_t ppc_gpr_t;
  37 #define TARGET_GPR_BITS  64
  38 #define TARGET_LONG_BITS 32
  39 #define REGX "%016" PRIx64
  40 #if defined(CONFIG_USER_ONLY)
  41 /* It looks like a lot of Linux programs assume page size
  42  * is 4kB long. This is evil, but we have to deal with it...
  43  */
  44 #define TARGET_PAGE_BITS 12
  45 #else
  46 /* Pages can be 1 kB small */
  47 #define TARGET_PAGE_BITS 10
  48 #endif
  49 #else
  50 #if (HOST_LONG_BITS >= 64)
  51 /* When using 64 bits temporary registers,
  52  * we can use 64 bits GPR with no extra cost
  53  * It's even an optimization as it will prevent
  54  * the compiler to do unuseful masking in the micro-ops.
  55  */
  56 typedef uint64_t ppc_gpr_t;
  57 #define TARGET_GPR_BITS  64
  58 #define REGX "%08" PRIx64
  59 #else
  60 typedef uint32_t ppc_gpr_t;
  61 #define TARGET_GPR_BITS  32
  62 #define REGX "%08" PRIx32
  63 #endif
  64 #define TARGET_LONG_BITS 32
  65 #define TARGET_PAGE_BITS 12
  66 #endif
  67
  68 #include "cpu-defs.h"
  69
  70 #define ADDRX TARGET_FMT_lx
  71 #define PADDRX TARGET_FMT_plx
  72
  73 #include <setjmp.h>
  74
  75 #include "softfloat.h"
  76
  77 #define TARGET_HAS_ICE 1
  78
  79 #if defined (TARGET_PPC64)
  80 #define ELF_MACHINE     EM_PPC64
  81 #else
  82 #define ELF_MACHINE     EM_PPC
  83 #endif
  84
  85 /*****************************************************************************/
  86 /* MMU model                                                                 */
  87 enum {
  88     POWERPC_MMU_UNKNOWN    = 0,
  89     /* Standard 32 bits PowerPC MMU                            */
  90     POWERPC_MMU_32B,
  91     /* PowerPC 6xx MMU with software TLB                       */
  92     POWERPC_MMU_SOFT_6xx,
  93     /* PowerPC 74xx MMU with software TLB                      */
  94     POWERPC_MMU_SOFT_74xx,
  95     /* PowerPC 4xx MMU with software TLB                       */
  96     POWERPC_MMU_SOFT_4xx,
  97     /* PowerPC 4xx MMU with software TLB and zones protections */
  98     POWERPC_MMU_SOFT_4xx_Z,
  99     /* PowerPC 4xx MMU in real mode only                       */
 100     POWERPC_MMU_REAL_4xx,
 101     /* BookE MMU model                                         */
 102     POWERPC_MMU_BOOKE,
 103     /* BookE FSL MMU model                                     */
 104     POWERPC_MMU_BOOKE_FSL,
 105 #if defined(TARGET_PPC64)
 106     /* 64 bits PowerPC MMU                                     */
 107     POWERPC_MMU_64B,
 108 #endif /* defined(TARGET_PPC64) */
 109 };
 110
 111 /*****************************************************************************/
 112 /* Exception model                                                           */
 113 enum {
 114     POWERPC_EXCP_UNKNOWN   = 0,
 115     /* Standard PowerPC exception model */
 116     POWERPC_EXCP_STD,
 117     /* PowerPC 40x exception model      */
 118     POWERPC_EXCP_40x,
 119     /* PowerPC 601 exception model      */
 120     POWERPC_EXCP_601,
 121     /* PowerPC 602 exception model      */
 122     POWERPC_EXCP_602,
 123     /* PowerPC 603 exception model      */
 124     POWERPC_EXCP_603,
 125     /* PowerPC 603e exception model     */
 126     POWERPC_EXCP_603E,
 127     /* PowerPC G2 exception model       */
 128     POWERPC_EXCP_G2,
 129     /* PowerPC 604 exception model      */
 130     POWERPC_EXCP_604,
 131     /* PowerPC 7x0 exception model      */
 132     POWERPC_EXCP_7x0,
 133     /* PowerPC 7x5 exception model      */
 134     POWERPC_EXCP_7x5,
 135     /* PowerPC 74xx exception model     */
 136     POWERPC_EXCP_74xx,
 137     /* BookE exception model            */
 138     POWERPC_EXCP_BOOKE,
 139 #if defined(TARGET_PPC64)
 140     /* PowerPC 970 exception model      */
 141     POWERPC_EXCP_970,
 142 #endif /* defined(TARGET_PPC64) */
 143 };
 144
 145 /*****************************************************************************/
 146 /* Exception vectors definitions                                             */
 147 enum {
 148     POWERPC_EXCP_NONE    = -1,
 149     /* The 64 first entries are used by the PowerPC embedded specification   */
 150     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
 151     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
 152     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
 153     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
 154     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
 155     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
 156     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
 157     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
 158     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 159     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 160     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 161     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 162     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 163     POWERPC_EXCP_DTLB     = 13, /* Data TLB error                            */
 164     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB error                     */
 165     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 166     /* Vectors 16 to 31 are reserved                                         */
 167 #if defined(TARGET_PPCEMB)
 168     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 169     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 170     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 171     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 172     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 173     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 174 #endif /* defined(TARGET_PPCEMB) */
 175     /* Vectors 38 to 63 are reserved                                         */
 176     /* Exceptions defined in the PowerPC server specification                */
 177     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 178 #if defined(TARGET_PPC64) /* PowerPC 64 */
 179     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 180     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 181 #endif /* defined(TARGET_PPC64) */
 182 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
 183     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 184 #endif /* defined(TARGET_PPC64H) */
 185     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 186 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
 187     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 188     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 189     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 190     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 191 #endif /* defined(TARGET_PPC64H) */
 192     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 193     /* 40x specific exceptions                                               */
 194     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 195     /* 601 specific exceptions                                               */
 196     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 197     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 198     /* 602 specific exceptions                                               */
 199     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 200     /* 602/603 specific exceptions                                           */
 201     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB error               */
 202     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 203     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 204     /* Exceptions available on most PowerPC                                  */
 205     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 206     POWERPC_EXCP_IABR     = 82, /* Instruction address breakpoint            */
 207     POWERPC_EXCP_SMI      = 83, /* System management interrupt               */
 208     POWERPC_EXCP_PERFM    = 84, /* Embedded performance monitor interrupt    */
 209     /* 7xx/74xx specific exceptions                                          */
 210     POWERPC_EXCP_THERM    = 85, /* Thermal interrupt                         */
 211     /* 74xx specific exceptions                                              */
 212     POWERPC_EXCP_VPUA     = 86, /* Vector assist exception                   */
 213     /* 970FX specific exceptions                                             */
 214     POWERPC_EXCP_SOFTP    = 87, /* Soft patch exception                      */
 215     POWERPC_EXCP_MAINT    = 88, /* Maintenance exception                     */
 216     /* EOL                                                                   */
 217     POWERPC_EXCP_NB       = 96,
 218     /* Qemu exceptions: used internally during code translation              */
 219     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 220     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 221     /* Qemu exceptions: special cases we want to stop translation            */
 222     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 223     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 224 };
 225
 226 /* Exceptions error codes                                                    */
 227 enum {
 228     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 229     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 230     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 231     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 232     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 233     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 234     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 235     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 236     /* FP exceptions                                                         */
 237     POWERPC_EXCP_FP            = 0x10,
 238     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 239     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 240     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 241     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 242     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 243     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 244     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 245     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 246     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 247     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 248     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 249     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 250     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 251     /* Invalid instruction                                                   */
 252     POWERPC_EXCP_INVAL         = 0x20,
 253     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 254     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 255     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 256     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 257     /* Privileged instruction                                                */
 258     POWERPC_EXCP_PRIV          = 0x30,
 259     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 260     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 261     /* Trap                                                                  */
 262     POWERPC_EXCP_TRAP          = 0x40,
 263 };
 264
 265 /*****************************************************************************/
 266 /* Input pins model                                                          */
 267 enum {
 268     PPC_FLAGS_INPUT_UNKNOWN = 0,
 269     /* PowerPC 6xx bus                  */
 270     PPC_FLAGS_INPUT_6xx,
 271     /* BookE bus                        */
 272     PPC_FLAGS_INPUT_BookE,
 273     /* PowerPC 405 bus                  */
 274     PPC_FLAGS_INPUT_405,
 275     /* PowerPC 970 bus                  */
 276     PPC_FLAGS_INPUT_970,
 277     /* PowerPC 401 bus                  */
 278     PPC_FLAGS_INPUT_401,
 279 };
 280
 281 #define PPC_INPUT(env) (env->bus_model)
 282
 283 /*****************************************************************************/
 284 typedef struct ppc_def_t ppc_def_t;
 285 typedef struct opc_handler_t opc_handler_t;
 286
 287 /*****************************************************************************/
 288 /* Types used to describe some PowerPC registers */
 289 typedef struct CPUPPCState CPUPPCState;
 290 typedef struct ppc_tb_t ppc_tb_t;
 291 typedef struct ppc_spr_t ppc_spr_t;
 292 typedef struct ppc_dcr_t ppc_dcr_t;
 293 typedef union ppc_avr_t ppc_avr_t;
 294 typedef union ppc_tlb_t ppc_tlb_t;
 295
 296 /* SPR access micro-ops generations callbacks */
 297 struct ppc_spr_t {
 298     void (*uea_read)(void *opaque, int spr_num);
 299     void (*uea_write)(void *opaque, int spr_num);
 300 #if !defined(CONFIG_USER_ONLY)
 301     void (*oea_read)(void *opaque, int spr_num);
 302     void (*oea_write)(void *opaque, int spr_num);
 303 #if defined(TARGET_PPC64H)
 304     void (*hea_read)(void *opaque, int spr_num);
 305     void (*hea_write)(void *opaque, int spr_num);
 306 #endif
 307 #endif
 308     const unsigned char *name;
 309 };
 310
 311 /* Altivec registers (128 bits) */
 312 union ppc_avr_t {
 313     uint8_t u8[16];
 314     uint16_t u16[8];
 315     uint32_t u32[4];
 316     uint64_t u64[2];
 317 };
 318
 319 /* Software TLB cache */
 320 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 321 struct ppc6xx_tlb_t {
 322     target_ulong pte0;
 323     target_ulong pte1;
 324     target_ulong EPN;
 325 };
 326
 327 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 328 struct ppcemb_tlb_t {
 329     target_phys_addr_t RPN;
 330     target_ulong EPN;
 331     target_ulong PID;
 332     target_ulong size;
 333     uint32_t prot;
 334     uint32_t attr; /* Storage attributes */
 335 };
 336
 337 union ppc_tlb_t {
 338     ppc6xx_tlb_t tlb6;
 339     ppcemb_tlb_t tlbe;
 340 };
 341
 342 /*****************************************************************************/
 343 /* Machine state register bits definition                                    */
 344 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 345 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 346 #define MSR_HV   60 /* hypervisor state                               hflags */
 347 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 348 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 349 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 350 #define MSR_VR   25 /* altivec available                            x hflags */
 351 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 352 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 353 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 354 #define MSR_KEY  19 /* key bit on 603e                                       */
 355 #define MSR_POW  18 /* Power management                                      */
 356 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 357 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 358 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 359 #define MSR_EE   15 /* External interrupt enable                             */
 360 #define MSR_PR   14 /* Problem state                                  hflags */
 361 #define MSR_FP   13 /* Floating point available                       hflags */
 362 #define MSR_ME   12 /* Machine check interrupt enable                        */
 363 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 364 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 365 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 366 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 367 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 368 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 369 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 370 #define MSR_AL   7  /* AL bit on POWER                                       */
 371 #define MSR_EP   6  /* Exception prefix on 601                               */
 372 #define MSR_IR   5  /* Instruction relocate                                  */
 373 #define MSR_DR   4  /* Data relocate                                         */
 374 #define MSR_PE   3  /* Protection enable on 403                              */
 375 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 376 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 377 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 378 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 379
 380 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 381 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 382 #define msr_hv   ((env->msr >> MSR_HV)   & 1)
 383 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 384 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 385 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 386 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
 387 #define msr_spe  ((env->msr >> MSR_SE)   & 1)
 388 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
 389 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
 390 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
 391 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 392 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 393 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 394 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 395 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 396 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
 397 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 398 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 399 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 400 #define msr_se   ((env->msr >> MSR_SE)   & 1)
 401 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 402 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
 403 #define msr_be   ((env->msr >> MSR_BE)   & 1)
 404 #define msr_de   ((env->msr >> MSR_DE)   & 1)
 405 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 406 #define msr_al   ((env->msr >> MSR_AL)   & 1)
 407 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 408 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 409 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 410 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
 411 #define msr_px   ((env->msr >> MSR_PX)   & 1)
 412 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 413 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
 414 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 415
 416 enum {
 417     POWERPC_FLAG_NONE = 0x00000000,
 418     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 419     POWERPC_FLAG_SPE  = 0x00000001,
 420     POWERPC_FLAG_VRE  = 0x00000002,
 421     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 422     POWERPC_FLAG_TGPR = 0x00000004,
 423     POWERPC_FLAG_CE   = 0x00000008,
 424     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 425     POWERPC_FLAG_SE   = 0x00000010,
 426     POWERPC_FLAG_DWE  = 0x00000020,
 427     POWERPC_FLAG_UBLE = 0x00000040,
 428     /* Flag for MSR bit 9 signification (BE/DE)                              */
 429     POWERPC_FLAG_BE   = 0x00000080,
 430     POWERPC_FLAG_DE   = 0x00000100,
 431     /* Flag for MSR but 2 signification (PX/PMM)                             */
 432     POWERPC_FLAG_PX   = 0x00000200,
 433     POWERPC_FLAG_PMM  = 0x00000400,
 434 };
 435
 436 /*****************************************************************************/
 437 /* Floating point status and control register                                */
 438 #define FPSCR_FX     31 /* Floating-point exception summary                  */
 439 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 440 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 441 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
 442 #define FPSCR_UX     27 /* Floating-point underflow exception                */
 443 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 444 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
 445 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 446 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 447 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 448 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 449 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 450 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 451 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 452 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 453 #define FPSCR_C      16 /* Floating-point result class descriptor            */
 454 #define FPSCR_FL     15 /* Floating-point less than or negative              */
 455 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
 456 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
 457 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 458 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
 459 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
 460 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 461 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 462 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 463 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 464 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 465 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 466 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 467 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 468 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 469 #define FPSCR_RN1    1
 470 #define FPSCR_RN     0  /* Floating-point rounding control                   */
 471 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 472 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 473 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 474 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 475 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 476 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 477 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 478 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 479 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 480 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 481 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 482 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 483 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 484 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 485 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 486 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 487 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 488 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 489 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 490 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 491 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 492 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 493 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 494 /* Invalid operation exception summary */
 495 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 496                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 497                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 498                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 499                                   (1 << FPSCR_VXCVI)))
 500 /* exception summary */
 501 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 502 /* enabled exception summary */
 503 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 504                    0x1F)
 505
 506 /*****************************************************************************/
 507 /* The whole PowerPC CPU context */
 508 #if defined(TARGET_PPC64H)
 509 #define NB_MMU_MODES 3
 510 #else
 511 #define NB_MMU_MODES 2
 512 #endif
 513
 514 struct CPUPPCState {
 515     /* First are the most commonly used resources
 516      * during translated code execution
 517      */
 518 #if TARGET_GPR_BITS > HOST_LONG_BITS
 519     /* temporary fixed-point registers
 520      * used to emulate 64 bits target on 32 bits hosts
 521      */
 522     ppc_gpr_t t0, t1, t2;
 523 #endif
 524     ppc_avr_t avr0, avr1, avr2;
 525
 526     /* general purpose registers */
 527     ppc_gpr_t gpr[32];
 528     /* LR */
 529     target_ulong lr;
 530     /* CTR */
 531     target_ulong ctr;
 532     /* condition register */
 533     uint8_t crf[8];
 534     /* XER */
 535     /* XXX: We use only 5 fields, but we want to keep the structure aligned */
 536     uint8_t xer[8];
 537     /* Reservation address */
 538     target_ulong reserve;
 539
 540     /* Those ones are used in supervisor mode only */
 541     /* machine state register */
 542     target_ulong msr;
 543     /* temporary general purpose registers */
 544     ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
 545
 546     /* Floating point execution context */
 547     /* temporary float registers */
 548     float64 ft0;
 549     float64 ft1;
 550     float64 ft2;
 551     float_status fp_status;
 552     /* floating point registers */
 553     float64 fpr[32];
 554     /* floating point status and control register */
 555     uint32_t fpscr;
 556
 557     CPU_COMMON
 558
 559     int halted; /* TRUE if the CPU is in suspend state */
 560
 561     int access_type; /* when a memory exception occurs, the access
 562                         type is stored here */
 563
 564     /* MMU context - only relevant for full system emulation */
 565 #if !defined(CONFIG_USER_ONLY)
 566 #if defined(TARGET_PPC64)
 567     /* Address space register */
 568     target_ulong asr;
 569     /* PowerPC 64 SLB area */
 570     int slb_nr;
 571 #endif
 572     /* segment registers */
 573     target_ulong sdr1;
 574     target_ulong sr[16];
 575     /* BATs */
 576     int nb_BATs;
 577     target_ulong DBAT[2][8];
 578     target_ulong IBAT[2][8];
 579     /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
 580     int nb_tlb;      /* Total number of TLB                                  */
 581     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
 582     int nb_ways;     /* Number of ways in the TLB set                        */
 583     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
 584     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
 585     int nb_pids;     /* Number of available PID registers                    */
 586     ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
 587     /* 403 dedicated access protection registers */
 588     target_ulong pb[4];
 589 #endif
 590
 591     /* Other registers */
 592     /* Special purpose registers */
 593     target_ulong spr[1024];
 594     ppc_spr_t spr_cb[1024];
 595     /* Altivec registers */
 596     ppc_avr_t avr[32];
 597     uint32_t vscr;
 598 #if defined(TARGET_PPCEMB)
 599     /* SPE registers */
 600     ppc_gpr_t spe_acc;
 601     float_status spe_status;
 602     uint32_t spe_fscr;
 603 #endif
 604
 605     /* Internal devices resources */
 606     /* Time base and decrementer */
 607     ppc_tb_t *tb_env;
 608     /* Device control registers */
 609     ppc_dcr_t *dcr_env;
 610
 611     int dcache_line_size;
 612     int icache_line_size;
 613
 614     /* Those resources are used during exception processing */
 615     /* CPU model definition */
 616     target_ulong msr_mask;
 617     uint8_t mmu_model;
 618     uint8_t excp_model;
 619     uint8_t bus_model;
 620     uint8_t pad;
 621     int bfd_mach;
 622     uint32_t flags;
 623
 624     int exception_index;
 625     int error_code;
 626     int interrupt_request;
 627     uint32_t pending_interrupts;
 628 #if !defined(CONFIG_USER_ONLY)
 629     /* This is the IRQ controller, which is implementation dependant
 630      * and only relevant when emulating a complete machine.
 631      */
 632     uint32_t irq_input_state;
 633     void **irq_inputs;
 634     /* Exception vectors */
 635     target_ulong excp_vectors[POWERPC_EXCP_NB];
 636     target_ulong excp_prefix;
 637     target_ulong ivor_mask;
 638     target_ulong ivpr_mask;
 639     target_ulong hreset_vector;
 640 #endif
 641
 642     /* Those resources are used only during code translation */
 643     /* Next instruction pointer */
 644     target_ulong nip;
 645
 646     /* opcode handlers */
 647     opc_handler_t *opcodes[0x40];
 648
 649     /* Those resources are used only in Qemu core */
 650     jmp_buf jmp_env;
 651     int user_mode_only; /* user mode only simulation */
 652     target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
 653     int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
 654
 655     /* Power management */
 656     int power_mode;
 657     int (*check_pow)(CPUPPCState *env);
 658
 659     /* temporary hack to handle OSI calls (only used if non NULL) */
 660     int (*osi_call)(struct CPUPPCState *env);
 661 };
 662
 663 /* Context used internally during MMU translations */
 664 typedef struct mmu_ctx_t mmu_ctx_t;
 665 struct mmu_ctx_t {
 666     target_phys_addr_t raddr;      /* Real address              */
 667     int prot;                      /* Protection bits           */
 668     target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
 669     target_ulong ptem;             /* Virtual segment ID | API  */
 670     int key;                       /* Access key                */
 671     int nx;                        /* Non-execute area          */
 672 };
 673
 674 /*****************************************************************************/
 675 CPUPPCState *cpu_ppc_init (void);
 676 int cpu_ppc_exec (CPUPPCState *s);
 677 void cpu_ppc_close (CPUPPCState *s);
 678 /* you can call this signal handler from your SIGBUS and SIGSEGV
 679    signal handlers to inform the virtual CPU of exceptions. non zero
 680    is returned if the signal was handled by the virtual CPU.  */
 681 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
 682                             void *puc);
 683
 684 void do_interrupt (CPUPPCState *env);
 685 void ppc_hw_interrupt (CPUPPCState *env);
 686 void cpu_loop_exit (void);
 687
 688 void dump_stack (CPUPPCState *env);
 689
 690 #if !defined(CONFIG_USER_ONLY)
 691 target_ulong do_load_ibatu (CPUPPCState *env, int nr);
 692 target_ulong do_load_ibatl (CPUPPCState *env, int nr);
 693 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
 694 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
 695 target_ulong do_load_dbatu (CPUPPCState *env, int nr);
 696 target_ulong do_load_dbatl (CPUPPCState *env, int nr);
 697 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
 698 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
 699 target_ulong do_load_sdr1 (CPUPPCState *env);
 700 void do_store_sdr1 (CPUPPCState *env, target_ulong value);
 701 #if defined(TARGET_PPC64)
 702 target_ulong ppc_load_asr (CPUPPCState *env);
 703 void ppc_store_asr (CPUPPCState *env, target_ulong value);
 704 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
 705 void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
 706 #endif /* defined(TARGET_PPC64) */
 707 #if 0 // Unused
 708 target_ulong do_load_sr (CPUPPCState *env, int srnum);
 709 #endif
 710 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
 711 #endif /* !defined(CONFIG_USER_ONLY) */
 712 target_ulong ppc_load_xer (CPUPPCState *env);
 713 void ppc_store_xer (CPUPPCState *env, target_ulong value);
 714 void ppc_store_msr (CPUPPCState *env, target_ulong value);
 715
 716 void cpu_ppc_reset (void *opaque);
 717 CPUPPCState *cpu_ppc_init (void);
 718 void cpu_ppc_close(CPUPPCState *env);
 719
 720 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
 721 int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
 722 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 723 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
 724
 725 /* Time-base and decrementer management */
 726 #ifndef NO_CPU_IO_DEFS
 727 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
 728 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
 729 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
 730 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
 731 uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
 732 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
 733 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
 734 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
 735 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
 736 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
 737 #if defined(TARGET_PPC64H)
 738 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
 739 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
 740 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
 741 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
 742 #endif
 743 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
 744 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
 745 #if !defined(CONFIG_USER_ONLY)
 746 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
 747 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
 748 target_ulong load_40x_pit (CPUPPCState *env);
 749 void store_40x_pit (CPUPPCState *env, target_ulong val);
 750 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
 751 void store_40x_sler (CPUPPCState *env, uint32_t val);
 752 void store_booke_tcr (CPUPPCState *env, target_ulong val);
 753 void store_booke_tsr (CPUPPCState *env, target_ulong val);
 754 void ppc_tlb_invalidate_all (CPUPPCState *env);
 755 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
 756 #if defined(TARGET_PPC64)
 757 void ppc_slb_invalidate_all (CPUPPCState *env);
 758 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
 759 #endif
 760 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
 761 #endif
 762 #endif
 763
 764 /* Device control registers */
 765 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
 766 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
 767
 768 #define CPUState CPUPPCState
 769 #define cpu_init cpu_ppc_init
 770 #define cpu_exec cpu_ppc_exec
 771 #define cpu_gen_code cpu_ppc_gen_code
 772 #define cpu_signal_handler cpu_ppc_signal_handler
 773 #define cpu_list ppc_cpu_list
 774
 775 /* MMU modes definitions */
 776 #define MMU_MODE0_SUFFIX _user
 777 #define MMU_MODE1_SUFFIX _kernel
 778 #if defined(TARGET_PPC64H)
 779 #define MMU_MODE2_SUFFIX _hypv
 780 #endif
 781 #define MMU_USER_IDX 0
 782 static inline int cpu_mmu_index (CPUState *env)
 783 {
 784     return env->mmu_idx;
 785 }
 786
 787 #include "cpu-all.h"
 788
 789 /*****************************************************************************/
 790 /* Registers definitions */
 791 #define XER_SO 31
 792 #define XER_OV 30
 793 #define XER_CA 29
 794 #define XER_CMP 8
 795 #define XER_BC  0
 796 #define xer_so  env->xer[4]
 797 #define xer_ov  env->xer[6]
 798 #define xer_ca  env->xer[2]
 799 #define xer_cmp env->xer[1]
 800 #define xer_bc  env->xer[0]
 801
 802 /* SPR definitions */
 803 #define SPR_MQ           (0x000)
 804 #define SPR_XER          (0x001)
 805 #define SPR_601_VRTCU    (0x004)
 806 #define SPR_601_VRTCL    (0x005)
 807 #define SPR_601_UDECR    (0x006)
 808 #define SPR_LR           (0x008)
 809 #define SPR_CTR          (0x009)
 810 #define SPR_DSISR        (0x012)
 811 #define SPR_DAR          (0x013) /* DAE for PowerPC 601 */
 812 #define SPR_601_RTCU     (0x014)
 813 #define SPR_601_RTCL     (0x015)
 814 #define SPR_DECR         (0x016)
 815 #define SPR_SDR1         (0x019)
 816 #define SPR_SRR0         (0x01A)
 817 #define SPR_SRR1         (0x01B)
 818 #define SPR_AMR          (0x01D)
 819 #define SPR_BOOKE_PID    (0x030)
 820 #define SPR_BOOKE_DECAR  (0x036)
 821 #define SPR_BOOKE_CSRR0  (0x03A)
 822 #define SPR_BOOKE_CSRR1  (0x03B)
 823 #define SPR_BOOKE_DEAR   (0x03D)
 824 #define SPR_BOOKE_ESR    (0x03E)
 825 #define SPR_BOOKE_IVPR   (0x03F)
 826 #define SPR_8xx_EIE      (0x050)
 827 #define SPR_8xx_EID      (0x051)
 828 #define SPR_8xx_NRE      (0x052)
 829 #define SPR_CTRL         (0x088)
 830 #define SPR_58x_CMPA     (0x090)
 831 #define SPR_58x_CMPB     (0x091)
 832 #define SPR_58x_CMPC     (0x092)
 833 #define SPR_58x_CMPD     (0x093)
 834 #define SPR_58x_ICR      (0x094)
 835 #define SPR_58x_DER      (0x094)
 836 #define SPR_58x_COUNTA   (0x096)
 837 #define SPR_58x_COUNTB   (0x097)
 838 #define SPR_UCTRL        (0x098)
 839 #define SPR_58x_CMPE     (0x098)
 840 #define SPR_58x_CMPF     (0x099)
 841 #define SPR_58x_CMPG     (0x09A)
 842 #define SPR_58x_CMPH     (0x09B)
 843 #define SPR_58x_LCTRL1   (0x09C)
 844 #define SPR_58x_LCTRL2   (0x09D)
 845 #define SPR_58x_ICTRL    (0x09E)
 846 #define SPR_58x_BAR      (0x09F)
 847 #define SPR_VRSAVE       (0x100)
 848 #define SPR_USPRG0       (0x100)
 849 #define SPR_USPRG1       (0x101)
 850 #define SPR_USPRG2       (0x102)
 851 #define SPR_USPRG3       (0x103)
 852 #define SPR_USPRG4       (0x104)
 853 #define SPR_USPRG5       (0x105)
 854 #define SPR_USPRG6       (0x106)
 855 #define SPR_USPRG7       (0x107)
 856 #define SPR_VTBL         (0x10C)
 857 #define SPR_VTBU         (0x10D)
 858 #define SPR_SPRG0        (0x110)
 859 #define SPR_SPRG1        (0x111)
 860 #define SPR_SPRG2        (0x112)
 861 #define SPR_SPRG3        (0x113)
 862 #define SPR_SPRG4        (0x114)
 863 #define SPR_SCOMC        (0x114)
 864 #define SPR_SPRG5        (0x115)
 865 #define SPR_SCOMD        (0x115)
 866 #define SPR_SPRG6        (0x116)
 867 #define SPR_SPRG7        (0x117)
 868 #define SPR_ASR          (0x118)
 869 #define SPR_EAR          (0x11A)
 870 #define SPR_TBL          (0x11C)
 871 #define SPR_TBU          (0x11D)
 872 #define SPR_TBU40        (0x11E)
 873 #define SPR_SVR          (0x11E)
 874 #define SPR_BOOKE_PIR    (0x11E)
 875 #define SPR_PVR          (0x11F)
 876 #define SPR_HSPRG0       (0x130)
 877 #define SPR_BOOKE_DBSR   (0x130)
 878 #define SPR_HSPRG1       (0x131)
 879 #define SPR_HDSISR       (0x132)
 880 #define SPR_HDAR         (0x133)
 881 #define SPR_BOOKE_DBCR0  (0x134)
 882 #define SPR_IBCR         (0x135)
 883 #define SPR_PURR         (0x135)
 884 #define SPR_BOOKE_DBCR1  (0x135)
 885 #define SPR_DBCR         (0x136)
 886 #define SPR_HDEC         (0x136)
 887 #define SPR_BOOKE_DBCR2  (0x136)
 888 #define SPR_HIOR         (0x137)
 889 #define SPR_MBAR         (0x137)
 890 #define SPR_RMOR         (0x138)
 891 #define SPR_BOOKE_IAC1   (0x138)
 892 #define SPR_HRMOR        (0x139)
 893 #define SPR_BOOKE_IAC2   (0x139)
 894 #define SPR_HSRR0        (0x13A)
 895 #define SPR_BOOKE_IAC3   (0x13A)
 896 #define SPR_HSRR1        (0x13B)
 897 #define SPR_BOOKE_IAC4   (0x13B)
 898 #define SPR_LPCR         (0x13C)
 899 #define SPR_BOOKE_DAC1   (0x13C)
 900 #define SPR_LPIDR        (0x13D)
 901 #define SPR_DABR2        (0x13D)
 902 #define SPR_BOOKE_DAC2   (0x13D)
 903 #define SPR_BOOKE_DVC1   (0x13E)
 904 #define SPR_BOOKE_DVC2   (0x13F)
 905 #define SPR_BOOKE_TSR    (0x150)
 906 #define SPR_BOOKE_TCR    (0x154)
 907 #define SPR_BOOKE_IVOR0  (0x190)
 908 #define SPR_BOOKE_IVOR1  (0x191)
 909 #define SPR_BOOKE_IVOR2  (0x192)
 910 #define SPR_BOOKE_IVOR3  (0x193)
 911 #define SPR_BOOKE_IVOR4  (0x194)
 912 #define SPR_BOOKE_IVOR5  (0x195)
 913 #define SPR_BOOKE_IVOR6  (0x196)
 914 #define SPR_BOOKE_IVOR7  (0x197)
 915 #define SPR_BOOKE_IVOR8  (0x198)
 916 #define SPR_BOOKE_IVOR9  (0x199)
 917 #define SPR_BOOKE_IVOR10 (0x19A)
 918 #define SPR_BOOKE_IVOR11 (0x19B)
 919 #define SPR_BOOKE_IVOR12 (0x19C)
 920 #define SPR_BOOKE_IVOR13 (0x19D)
 921 #define SPR_BOOKE_IVOR14 (0x19E)
 922 #define SPR_BOOKE_IVOR15 (0x19F)
 923 #define SPR_BOOKE_SPEFSCR (0x200)
 924 #define SPR_E500_BBEAR   (0x201)
 925 #define SPR_E500_BBTAR   (0x202)
 926 #define SPR_ATBL         (0x20E)
 927 #define SPR_ATBU         (0x20F)
 928 #define SPR_IBAT0U       (0x210)
 929 #define SPR_BOOKE_IVOR32 (0x210)
 930 #define SPR_IBAT0L       (0x211)
 931 #define SPR_BOOKE_IVOR33 (0x211)
 932 #define SPR_IBAT1U       (0x212)
 933 #define SPR_BOOKE_IVOR34 (0x212)
 934 #define SPR_IBAT1L       (0x213)
 935 #define SPR_BOOKE_IVOR35 (0x213)
 936 #define SPR_IBAT2U       (0x214)
 937 #define SPR_BOOKE_IVOR36 (0x214)
 938 #define SPR_IBAT2L       (0x215)
 939 #define SPR_E500_L1CFG0  (0x215)
 940 #define SPR_BOOKE_IVOR37 (0x215)
 941 #define SPR_IBAT3U       (0x216)
 942 #define SPR_E500_L1CFG1  (0x216)
 943 #define SPR_IBAT3L       (0x217)
 944 #define SPR_DBAT0U       (0x218)
 945 #define SPR_DBAT0L       (0x219)
 946 #define SPR_DBAT1U       (0x21A)
 947 #define SPR_DBAT1L       (0x21B)
 948 #define SPR_DBAT2U       (0x21C)
 949 #define SPR_DBAT2L       (0x21D)
 950 #define SPR_DBAT3U       (0x21E)
 951 #define SPR_DBAT3L       (0x21F)
 952 #define SPR_IBAT4U       (0x230)
 953 #define SPR_IBAT4L       (0x231)
 954 #define SPR_IBAT5U       (0x232)
 955 #define SPR_IBAT5L       (0x233)
 956 #define SPR_IBAT6U       (0x234)
 957 #define SPR_IBAT6L       (0x235)
 958 #define SPR_IBAT7U       (0x236)
 959 #define SPR_IBAT7L       (0x237)
 960 #define SPR_DBAT4U       (0x238)
 961 #define SPR_DBAT4L       (0x239)
 962 #define SPR_DBAT5U       (0x23A)
 963 #define SPR_BOOKE_MCSRR0 (0x23A)
 964 #define SPR_DBAT5L       (0x23B)
 965 #define SPR_BOOKE_MCSRR1 (0x23B)
 966 #define SPR_DBAT6U       (0x23C)
 967 #define SPR_BOOKE_MCSR   (0x23C)
 968 #define SPR_DBAT6L       (0x23D)
 969 #define SPR_E500_MCAR    (0x23D)
 970 #define SPR_DBAT7U       (0x23E)
 971 #define SPR_BOOKE_DSRR0  (0x23E)
 972 #define SPR_DBAT7L       (0x23F)
 973 #define SPR_BOOKE_DSRR1  (0x23F)
 974 #define SPR_BOOKE_SPRG8  (0x25C)
 975 #define SPR_BOOKE_SPRG9  (0x25D)
 976 #define SPR_BOOKE_MAS0   (0x270)
 977 #define SPR_BOOKE_MAS1   (0x271)
 978 #define SPR_BOOKE_MAS2   (0x272)
 979 #define SPR_BOOKE_MAS3   (0x273)
 980 #define SPR_BOOKE_MAS4   (0x274)
 981 #define SPR_BOOKE_MAS6   (0x276)
 982 #define SPR_BOOKE_PID1   (0x279)
 983 #define SPR_BOOKE_PID2   (0x27A)
 984 #define SPR_BOOKE_TLB0CFG (0x2B0)
 985 #define SPR_BOOKE_TLB1CFG (0x2B1)
 986 #define SPR_BOOKE_TLB2CFG (0x2B2)
 987 #define SPR_BOOKE_TLB3CFG (0x2B3)
 988 #define SPR_BOOKE_EPR    (0x2BE)
 989 #define SPR_PERF0        (0x300)
 990 #define SPR_PERF1        (0x301)
 991 #define SPR_PERF2        (0x302)
 992 #define SPR_PERF3        (0x303)
 993 #define SPR_PERF4        (0x304)
 994 #define SPR_PERF5        (0x305)
 995 #define SPR_PERF6        (0x306)
 996 #define SPR_PERF7        (0x307)
 997 #define SPR_PERF8        (0x308)
 998 #define SPR_PERF9        (0x309)
 999 #define SPR_PERFA        (0x30A)
1000 #define SPR_PERFB        (0x30B)
1001 #define SPR_PERFC        (0x30C)
1002 #define SPR_PERFD        (0x30D)
1003 #define SPR_PERFE        (0x30E)
1004 #define SPR_PERFF        (0x30F)
1005 #define SPR_UPERF0       (0x310)
1006 #define SPR_UPERF1       (0x311)
1007 #define SPR_UPERF2       (0x312)
1008 #define SPR_UPERF3       (0x313)
1009 #define SPR_UPERF4       (0x314)
1010 #define SPR_UPERF5       (0x315)
1011 #define SPR_UPERF6       (0x316)
1012 #define SPR_UPERF7       (0x317)
1013 #define SPR_UPERF8       (0x318)
1014 #define SPR_UPERF9       (0x319)
1015 #define SPR_UPERFA       (0x31A)
1016 #define SPR_UPERFB       (0x31B)
1017 #define SPR_UPERFC       (0x31C)
1018 #define SPR_UPERFD       (0x31D)
1019 #define SPR_UPERFE       (0x31E)
1020 #define SPR_UPERFF       (0x31F)
1021 #define SPR_440_INV0     (0x370)
1022 #define SPR_440_INV1     (0x371)
1023 #define SPR_440_INV2     (0x372)
1024 #define SPR_440_INV3     (0x373)
1025 #define SPR_440_ITV0     (0x374)
1026 #define SPR_440_ITV1     (0x375)
1027 #define SPR_440_ITV2     (0x376)
1028 #define SPR_440_ITV3     (0x377)
1029 #define SPR_440_CCR1     (0x378)
1030 #define SPR_DCRIPR       (0x37B)
1031 #define SPR_PPR          (0x380)
1032 #define SPR_440_DNV0     (0x390)
1033 #define SPR_440_DNV1     (0x391)
1034 #define SPR_440_DNV2     (0x392)
1035 #define SPR_440_DNV3     (0x393)
1036 #define SPR_440_DTV0     (0x394)
1037 #define SPR_440_DTV1     (0x395)
1038 #define SPR_440_DTV2     (0x396)
1039 #define SPR_440_DTV3     (0x397)
1040 #define SPR_440_DVLIM    (0x398)
1041 #define SPR_440_IVLIM    (0x399)
1042 #define SPR_440_RSTCFG   (0x39B)
1043 #define SPR_BOOKE_DCDBTRL (0x39C)
1044 #define SPR_BOOKE_DCDBTRH (0x39D)
1045 #define SPR_BOOKE_ICDBTRL (0x39E)
1046 #define SPR_BOOKE_ICDBTRH (0x39F)
1047 #define SPR_UMMCR2       (0x3A0)
1048 #define SPR_UPMC5        (0x3A1)
1049 #define SPR_UPMC6        (0x3A2)
1050 #define SPR_UBAMR        (0x3A7)
1051 #define SPR_UMMCR0       (0x3A8)
1052 #define SPR_UPMC1        (0x3A9)
1053 #define SPR_UPMC2        (0x3AA)
1054 #define SPR_USIAR        (0x3AB)
1055 #define SPR_UMMCR1       (0x3AC)
1056 #define SPR_UPMC3        (0x3AD)
1057 #define SPR_UPMC4        (0x3AE)
1058 #define SPR_USDA         (0x3AF)
1059 #define SPR_40x_ZPR      (0x3B0)
1060 #define SPR_BOOKE_MAS7   (0x3B0)
1061 #define SPR_620_PMR0     (0x3B0)
1062 #define SPR_MMCR2        (0x3B0)
1063 #define SPR_PMC5         (0x3B1)
1064 #define SPR_40x_PID      (0x3B1)
1065 #define SPR_620_PMR1     (0x3B1)
1066 #define SPR_PMC6         (0x3B2)
1067 #define SPR_440_MMUCR    (0x3B2)
1068 #define SPR_620_PMR2     (0x3B2)
1069 #define SPR_4xx_CCR0     (0x3B3)
1070 #define SPR_BOOKE_EPLC   (0x3B3)
1071 #define SPR_620_PMR3     (0x3B3)
1072 #define SPR_405_IAC3     (0x3B4)
1073 #define SPR_BOOKE_EPSC   (0x3B4)
1074 #define SPR_620_PMR4     (0x3B4)
1075 #define SPR_405_IAC4     (0x3B5)
1076 #define SPR_620_PMR5     (0x3B5)
1077 #define SPR_405_DVC1     (0x3B6)
1078 #define SPR_620_PMR6     (0x3B6)
1079 #define SPR_405_DVC2     (0x3B7)
1080 #define SPR_620_PMR7     (0x3B7)
1081 #define SPR_BAMR         (0x3B7)
1082 #define SPR_MMCR0        (0x3B8)
1083 #define SPR_620_PMR8     (0x3B8)
1084 #define SPR_PMC1         (0x3B9)
1085 #define SPR_40x_SGR      (0x3B9)
1086 #define SPR_620_PMR9     (0x3B9)
1087 #define SPR_PMC2         (0x3BA)
1088 #define SPR_40x_DCWR     (0x3BA)
1089 #define SPR_620_PMRA     (0x3BA)
1090 #define SPR_SIAR         (0x3BB)
1091 #define SPR_405_SLER     (0x3BB)
1092 #define SPR_620_PMRB     (0x3BB)
1093 #define SPR_MMCR1        (0x3BC)
1094 #define SPR_405_SU0R     (0x3BC)
1095 #define SPR_620_PMRC     (0x3BC)
1096 #define SPR_401_SKR      (0x3BC)
1097 #define SPR_PMC3         (0x3BD)
1098 #define SPR_405_DBCR1    (0x3BD)
1099 #define SPR_620_PMRD     (0x3BD)
1100 #define SPR_PMC4         (0x3BE)
1101 #define SPR_620_PMRE     (0x3BE)
1102 #define SPR_SDA          (0x3BF)
1103 #define SPR_620_PMRF     (0x3BF)
1104 #define SPR_403_VTBL     (0x3CC)
1105 #define SPR_403_VTBU     (0x3CD)
1106 #define SPR_DMISS        (0x3D0)
1107 #define SPR_DCMP         (0x3D1)
1108 #define SPR_HASH1        (0x3D2)
1109 #define SPR_HASH2        (0x3D3)
1110 #define SPR_BOOKE_ICDBDR (0x3D3)
1111 #define SPR_TLBMISS      (0x3D4)
1112 #define SPR_IMISS        (0x3D4)
1113 #define SPR_40x_ESR      (0x3D4)
1114 #define SPR_PTEHI        (0x3D5)
1115 #define SPR_ICMP         (0x3D5)
1116 #define SPR_40x_DEAR     (0x3D5)
1117 #define SPR_PTELO        (0x3D6)
1118 #define SPR_RPA          (0x3D6)
1119 #define SPR_40x_EVPR     (0x3D6)
1120 #define SPR_L3PM         (0x3D7)
1121 #define SPR_403_CDBCR    (0x3D7)
1122 #define SPR_L3OHCR       (0x3D8)
1123 #define SPR_TCR          (0x3D8)
1124 #define SPR_40x_TSR      (0x3D8)
1125 #define SPR_IBR          (0x3DA)
1126 #define SPR_40x_TCR      (0x3DA)
1127 #define SPR_ESASRR       (0x3DB)
1128 #define SPR_40x_PIT      (0x3DB)
1129 #define SPR_403_TBL      (0x3DC)
1130 #define SPR_403_TBU      (0x3DD)
1131 #define SPR_SEBR         (0x3DE)
1132 #define SPR_40x_SRR2     (0x3DE)
1133 #define SPR_SER          (0x3DF)
1134 #define SPR_40x_SRR3     (0x3DF)
1135 #define SPR_L3ITCR0      (0x3E8)
1136 #define SPR_L3ITCR1      (0x3E9)
1137 #define SPR_L3ITCR2      (0x3EA)
1138 #define SPR_L3ITCR3      (0x3EB)
1139 #define SPR_HID0         (0x3F0)
1140 #define SPR_40x_DBSR     (0x3F0)
1141 #define SPR_HID1         (0x3F1)
1142 #define SPR_IABR         (0x3F2)
1143 #define SPR_40x_DBCR0    (0x3F2)
1144 #define SPR_601_HID2     (0x3F2)
1145 #define SPR_E500_L1CSR0  (0x3F2)
1146 #define SPR_ICTRL        (0x3F3)
1147 #define SPR_HID2         (0x3F3)
1148 #define SPR_E500_L1CSR1  (0x3F3)
1149 #define SPR_440_DBDR     (0x3F3)
1150 #define SPR_LDSTDB       (0x3F4)
1151 #define SPR_40x_IAC1     (0x3F4)
1152 #define SPR_MMUCSR0      (0x3F4)
1153 #define SPR_DABR         (0x3F5)
1154 #define DABR_MASK (~(target_ulong)0x7)
1155 #define SPR_E500_BUCSR   (0x3F5)
1156 #define SPR_40x_IAC2     (0x3F5)
1157 #define SPR_601_HID5     (0x3F5)
1158 #define SPR_40x_DAC1     (0x3F6)
1159 #define SPR_MSSCR0       (0x3F6)
1160 #define SPR_970_HID5     (0x3F6)
1161 #define SPR_MSSSR0       (0x3F7)
1162 #define SPR_DABRX        (0x3F7)
1163 #define SPR_40x_DAC2     (0x3F7)
1164 #define SPR_MMUCFG       (0x3F7)
1165 #define SPR_LDSTCR       (0x3F8)
1166 #define SPR_L2PMCR       (0x3F8)
1167 #define SPR_750_HID2     (0x3F8)
1168 #define SPR_620_HID8     (0x3F8)
1169 #define SPR_L2CR         (0x3F9)
1170 #define SPR_620_HID9     (0x3F9)
1171 #define SPR_L3CR         (0x3FA)
1172 #define SPR_IABR2        (0x3FA)
1173 #define SPR_40x_DCCR     (0x3FA)
1174 #define SPR_ICTC         (0x3FB)
1175 #define SPR_40x_ICCR     (0x3FB)
1176 #define SPR_THRM1        (0x3FC)
1177 #define SPR_403_PBL1     (0x3FC)
1178 #define SPR_SP           (0x3FD)
1179 #define SPR_THRM2        (0x3FD)
1180 #define SPR_403_PBU1     (0x3FD)
1181 #define SPR_604_HID13    (0x3FD)
1182 #define SPR_LT           (0x3FE)
1183 #define SPR_THRM3        (0x3FE)
1184 #define SPR_FPECR        (0x3FE)
1185 #define SPR_403_PBL2     (0x3FE)
1186 #define SPR_PIR          (0x3FF)
1187 #define SPR_403_PBU2     (0x3FF)
1188 #define SPR_601_HID15    (0x3FF)
1189 #define SPR_604_HID15    (0x3FF)
1190 #define SPR_E500_SVR     (0x3FF)
1191
1192 /*****************************************************************************/
1193 /* Memory access type :
1194  * may be needed for precise access rights control and precise exceptions.
1195  */
1196 enum {
1197     /* 1 bit to define user level / supervisor access */
1198     ACCESS_USER  = 0x00,
1199     ACCESS_SUPER = 0x01,
1200     /* Type of instruction that generated the access */
1201     ACCESS_CODE  = 0x10, /* Code fetch access                */
1202     ACCESS_INT   = 0x20, /* Integer load/store access        */
1203     ACCESS_FLOAT = 0x30, /* floating point load/store access */
1204     ACCESS_RES   = 0x40, /* load/store with reservation      */
1205     ACCESS_EXT   = 0x50, /* external access                  */
1206     ACCESS_CACHE = 0x60, /* Cache manipulation               */
1207 };
1208
1209 /* Hardware interruption sources:
1210  * all those exception can be raised simulteaneously
1211  */
1212 /* Input pins definitions */
1213 enum {
1214     /* 6xx bus input pins */
1215     PPC6xx_INPUT_HRESET     = 0,
1216     PPC6xx_INPUT_SRESET     = 1,
1217     PPC6xx_INPUT_CKSTP_IN   = 2,
1218     PPC6xx_INPUT_MCP        = 3,
1219     PPC6xx_INPUT_SMI        = 4,
1220     PPC6xx_INPUT_INT        = 5,
1221     PPC6xx_INPUT_TBEN       = 6,
1222     PPC6xx_INPUT_WAKEUP     = 7,
1223     PPC6xx_INPUT_NB,
1224 };
1225
1226 enum {
1227     /* Embedded PowerPC input pins */
1228     PPCBookE_INPUT_HRESET     = 0,
1229     PPCBookE_INPUT_SRESET     = 1,
1230     PPCBookE_INPUT_CKSTP_IN   = 2,
1231     PPCBookE_INPUT_MCP        = 3,
1232     PPCBookE_INPUT_SMI        = 4,
1233     PPCBookE_INPUT_INT        = 5,
1234     PPCBookE_INPUT_CINT       = 6,
1235     PPCBookE_INPUT_NB,
1236 };
1237
1238 enum {
1239     /* PowerPC 40x input pins */
1240     PPC40x_INPUT_RESET_CORE = 0,
1241     PPC40x_INPUT_RESET_CHIP = 1,
1242     PPC40x_INPUT_RESET_SYS  = 2,
1243     PPC40x_INPUT_CINT       = 3,
1244     PPC40x_INPUT_INT        = 4,
1245     PPC40x_INPUT_HALT       = 5,
1246     PPC40x_INPUT_DEBUG      = 6,
1247     PPC40x_INPUT_NB,
1248 };
1249
1250 #if defined(TARGET_PPC64)
1251 enum {
1252     /* PowerPC 970 input pins */
1253     PPC970_INPUT_HRESET     = 0,
1254     PPC970_INPUT_SRESET     = 1,
1255     PPC970_INPUT_CKSTP      = 2,
1256     PPC970_INPUT_TBEN       = 3,
1257     PPC970_INPUT_MCP        = 4,
1258     PPC970_INPUT_INT        = 5,
1259     PPC970_INPUT_THINT      = 6,
1260 };
1261 #endif
1262
1263 /* Hardware exceptions definitions */
1264 enum {
1265     /* External hardware exception sources */
1266     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
1267     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
1268     PPC_INTERRUPT_MCK,            /* Machine check exception              */
1269     PPC_INTERRUPT_EXT,            /* External interrupt                   */
1270     PPC_INTERRUPT_SMI,            /* System management interrupt          */
1271     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
1272     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
1273     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
1274     /* Internal hardware exception sources */
1275     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
1276     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
1277     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
1278     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
1279     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
1280     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
1281     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
1282     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
1283 };
1284
1285 /*****************************************************************************/
1286
1287 #endif /* !defined (__CPU_PPC_H__) */