hw/ppc4xx_devs.c

   1 /*
   2  * QEMU PowerPC 4xx embedded processors shared devices emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 #include "ppc4xx.h"
  26
  27 extern int loglevel;
  28 extern FILE *logfile;
  29
  30 //#define DEBUG_MMIO
  31 #define DEBUG_UIC
  32
  33 /*****************************************************************************/
  34 /* Generic PowerPC 4xx processor instanciation */
  35 CPUState *ppc4xx_init (const unsigned char *cpu_model,
  36                        clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
  37                        uint32_t sysclk)
  38 {
  39     CPUState *env;
  40     ppc_def_t *def;
  41
  42     /* init CPUs */
  43     env = cpu_init();
  44     ppc_find_by_name(cpu_model, &def);
  45     if (def == NULL) {
  46         cpu_abort(env, "Unable to find PowerPC %s CPU definition\n",
  47                   cpu_model);
  48     }
  49     cpu_ppc_register(env, def);
  50     cpu_ppc_reset(env);
  51     cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
  52     cpu_clk->opaque = env;
  53     /* Set time-base frequency to sysclk */
  54     tb_clk->cb = ppc_emb_timers_init(env, sysclk);
  55     tb_clk->opaque = env;
  56     ppc_dcr_init(env, NULL, NULL);
  57     /* Register qemu callbacks */
  58     qemu_register_reset(&cpu_ppc_reset, env);
  59     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
  60
  61     return env;
  62 }
  63
  64 /*****************************************************************************/
  65 /* Fake device used to map multiple devices in a single memory page */
  66 #define MMIO_AREA_BITS 8
  67 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
  68 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
  69 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
  70 struct ppc4xx_mmio_t {
  71     target_phys_addr_t base;
  72     CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
  73     CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
  74     void *opaque[MMIO_AREA_NB];
  75 };
  76
  77 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
  78 {
  79 #ifdef DEBUG_UNASSIGNED
  80     ppc4xx_mmio_t *mmio;
  81
  82     mmio = opaque;
  83     printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
  84            addr, mmio->base);
  85 #endif
  86
  87     return 0;
  88 }
  89
  90 static void unassigned_mmio_writeb (void *opaque,
  91                                     target_phys_addr_t addr, uint32_t val)
  92 {
  93 #ifdef DEBUG_UNASSIGNED
  94     ppc4xx_mmio_t *mmio;
  95
  96     mmio = opaque;
  97     printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
  98            addr, val, mmio->base);
  99 #endif
 100 }
 101
 102 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
 103     unassigned_mmio_readb,
 104     unassigned_mmio_readb,
 105     unassigned_mmio_readb,
 106 };
 107
 108 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
 109     unassigned_mmio_writeb,
 110     unassigned_mmio_writeb,
 111     unassigned_mmio_writeb,
 112 };
 113
 114 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
 115                               target_phys_addr_t addr, int len)
 116 {
 117     CPUReadMemoryFunc **mem_read;
 118     uint32_t ret;
 119     int idx;
 120
 121     idx = MMIO_IDX(addr - mmio->base);
 122 #if defined(DEBUG_MMIO)
 123     printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
 124            mmio, len, addr, idx);
 125 #endif
 126     mem_read = mmio->mem_read[idx];
 127     ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
 128
 129     return ret;
 130 }
 131
 132 static void mmio_writelen (ppc4xx_mmio_t *mmio,
 133                            target_phys_addr_t addr, uint32_t value, int len)
 134 {
 135     CPUWriteMemoryFunc **mem_write;
 136     int idx;
 137
 138     idx = MMIO_IDX(addr - mmio->base);
 139 #if defined(DEBUG_MMIO)
 140     printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
 141            mmio, len, addr, idx, value);
 142 #endif
 143     mem_write = mmio->mem_write[idx];
 144     (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
 145 }
 146
 147 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
 148 {
 149 #if defined(DEBUG_MMIO)
 150     printf("%s: addr " PADDRX "\n", __func__, addr);
 151 #endif
 152
 153     return mmio_readlen(opaque, addr, 0);
 154 }
 155
 156 static void mmio_writeb (void *opaque,
 157                          target_phys_addr_t addr, uint32_t value)
 158 {
 159 #if defined(DEBUG_MMIO)
 160     printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
 161 #endif
 162     mmio_writelen(opaque, addr, value, 0);
 163 }
 164
 165 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
 166 {
 167 #if defined(DEBUG_MMIO)
 168     printf("%s: addr " PADDRX "\n", __func__, addr);
 169 #endif
 170
 171     return mmio_readlen(opaque, addr, 1);
 172 }
 173
 174 static void mmio_writew (void *opaque,
 175                          target_phys_addr_t addr, uint32_t value)
 176 {
 177 #if defined(DEBUG_MMIO)
 178     printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
 179 #endif
 180     mmio_writelen(opaque, addr, value, 1);
 181 }
 182
 183 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
 184 {
 185 #if defined(DEBUG_MMIO)
 186     printf("%s: addr " PADDRX "\n", __func__, addr);
 187 #endif
 188
 189     return mmio_readlen(opaque, addr, 2);
 190 }
 191
 192 static void mmio_writel (void *opaque,
 193                          target_phys_addr_t addr, uint32_t value)
 194 {
 195 #if defined(DEBUG_MMIO)
 196     printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
 197 #endif
 198     mmio_writelen(opaque, addr, value, 2);
 199 }
 200
 201 static CPUReadMemoryFunc *mmio_read[] = {
 202     &mmio_readb,
 203     &mmio_readw,
 204     &mmio_readl,
 205 };
 206
 207 static CPUWriteMemoryFunc *mmio_write[] = {
 208     &mmio_writeb,
 209     &mmio_writew,
 210     &mmio_writel,
 211 };
 212
 213 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
 214                           target_phys_addr_t offset, uint32_t len,
 215                           CPUReadMemoryFunc **mem_read,
 216                           CPUWriteMemoryFunc **mem_write, void *opaque)
 217 {
 218     uint32_t end;
 219     int idx, eidx;
 220
 221     if ((offset + len) > TARGET_PAGE_SIZE)
 222         return -1;
 223     idx = MMIO_IDX(offset);
 224     end = offset + len - 1;
 225     eidx = MMIO_IDX(end);
 226 #if defined(DEBUG_MMIO)
 227     printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
 228            end, idx, eidx);
 229 #endif
 230     for (; idx <= eidx; idx++) {
 231         mmio->mem_read[idx] = mem_read;
 232         mmio->mem_write[idx] = mem_write;
 233         mmio->opaque[idx] = opaque;
 234     }
 235
 236     return 0;
 237 }
 238
 239 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
 240 {
 241     ppc4xx_mmio_t *mmio;
 242     int mmio_memory;
 243
 244     mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
 245     if (mmio != NULL) {
 246         mmio->base = base;
 247         mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
 248 #if defined(DEBUG_MMIO)
 249         printf("%s: %p base %08x len %08x %d\n", __func__,
 250                mmio, base, TARGET_PAGE_SIZE, mmio_memory);
 251 #endif
 252         cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
 253         ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
 254                              unassigned_mmio_read, unassigned_mmio_write,
 255                              mmio);
 256     }
 257
 258     return mmio;
 259 }
 260
 261 /*****************************************************************************/
 262 /* "Universal" Interrupt controller */
 263 enum {
 264     DCR_UICSR  = 0x000,
 265     DCR_UICSRS = 0x001,
 266     DCR_UICER  = 0x002,
 267     DCR_UICCR  = 0x003,
 268     DCR_UICPR  = 0x004,
 269     DCR_UICTR  = 0x005,
 270     DCR_UICMSR = 0x006,
 271     DCR_UICVR  = 0x007,
 272     DCR_UICVCR = 0x008,
 273     DCR_UICMAX = 0x009,
 274 };
 275
 276 #define UIC_MAX_IRQ 32
 277 typedef struct ppcuic_t ppcuic_t;
 278 struct ppcuic_t {
 279     uint32_t dcr_base;
 280     int use_vectors;
 281     uint32_t uicsr;  /* Status register */
 282     uint32_t uicer;  /* Enable register */
 283     uint32_t uiccr;  /* Critical register */
 284     uint32_t uicpr;  /* Polarity register */
 285     uint32_t uictr;  /* Triggering register */
 286     uint32_t uicvcr; /* Vector configuration register */
 287     uint32_t uicvr;
 288     qemu_irq *irqs;
 289 };
 290
 291 static void ppcuic_trigger_irq (ppcuic_t *uic)
 292 {
 293     uint32_t ir, cr;
 294     int start, end, inc, i;
 295
 296     /* Trigger interrupt if any is pending */
 297     ir = uic->uicsr & uic->uicer & (~uic->uiccr);
 298     cr = uic->uicsr & uic->uicer & uic->uiccr;
 299 #ifdef DEBUG_UIC
 300     if (loglevel & CPU_LOG_INT) {
 301         fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
 302                 "   %08x ir %08x cr %08x\n", __func__,
 303                 uic->uicsr, uic->uicer, uic->uiccr,
 304                 uic->uicsr & uic->uicer, ir, cr);
 305     }
 306 #endif
 307     if (ir != 0x0000000) {
 308 #ifdef DEBUG_UIC
 309         if (loglevel & CPU_LOG_INT) {
 310             fprintf(logfile, "Raise UIC interrupt\n");
 311         }
 312 #endif
 313         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
 314     } else {
 315 #ifdef DEBUG_UIC
 316         if (loglevel & CPU_LOG_INT) {
 317             fprintf(logfile, "Lower UIC interrupt\n");
 318         }
 319 #endif
 320         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
 321     }
 322     /* Trigger critical interrupt if any is pending and update vector */
 323     if (cr != 0x0000000) {
 324         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
 325         if (uic->use_vectors) {
 326             /* Compute critical IRQ vector */
 327             if (uic->uicvcr & 1) {
 328                 start = 31;
 329                 end = 0;
 330                 inc = -1;
 331             } else {
 332                 start = 0;
 333                 end = 31;
 334                 inc = 1;
 335             }
 336             uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
 337             for (i = start; i <= end; i += inc) {
 338                 if (cr & (1 << i)) {
 339                     uic->uicvr += (i - start) * 512 * inc;
 340                     break;
 341                 }
 342             }
 343         }
 344 #ifdef DEBUG_UIC
 345         if (loglevel & CPU_LOG_INT) {
 346             fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
 347                     uic->uicvr);
 348         }
 349 #endif
 350     } else {
 351 #ifdef DEBUG_UIC
 352         if (loglevel & CPU_LOG_INT) {
 353             fprintf(logfile, "Lower UIC critical interrupt\n");
 354         }
 355 #endif
 356         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
 357         uic->uicvr = 0x00000000;
 358     }
 359 }
 360
 361 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
 362 {
 363     ppcuic_t *uic;
 364     uint32_t mask, sr;
 365
 366     uic = opaque;
 367     mask = 1 << irq_num;
 368 #ifdef DEBUG_UIC
 369     if (loglevel & CPU_LOG_INT) {
 370         fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
 371                 "%08x\n", __func__, irq_num, level,
 372                 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
 373     }
 374 #endif
 375     if (irq_num < 0 || irq_num > 31)
 376         return;
 377     sr = uic->uicsr;
 378     if (!(uic->uicpr & mask)) {
 379         /* Negatively asserted IRQ */
 380         level = level == 0 ? 1 : 0;
 381     }
 382     /* Update status register */
 383     if (uic->uictr & mask) {
 384         /* Edge sensitive interrupt */
 385         if (level == 1)
 386             uic->uicsr |= mask;
 387     } else {
 388         /* Level sensitive interrupt */
 389         if (level == 1)
 390             uic->uicsr |= mask;
 391         else
 392             uic->uicsr &= ~mask;
 393     }
 394 #ifdef DEBUG_UIC
 395     if (loglevel & CPU_LOG_INT) {
 396         fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
 397                 irq_num, level, uic->uicsr, sr);
 398     }
 399 #endif
 400     if (sr != uic->uicsr)
 401         ppcuic_trigger_irq(uic);
 402 }
 403
 404 static target_ulong dcr_read_uic (void *opaque, int dcrn)
 405 {
 406     ppcuic_t *uic;
 407     target_ulong ret;
 408
 409     uic = opaque;
 410     dcrn -= uic->dcr_base;
 411     switch (dcrn) {
 412     case DCR_UICSR:
 413     case DCR_UICSRS:
 414         ret = uic->uicsr;
 415         break;
 416     case DCR_UICER:
 417         ret = uic->uicer;
 418         break;
 419     case DCR_UICCR:
 420         ret = uic->uiccr;
 421         break;
 422     case DCR_UICPR:
 423         ret = uic->uicpr;
 424         break;
 425     case DCR_UICTR:
 426         ret = uic->uictr;
 427         break;
 428     case DCR_UICMSR:
 429         ret = uic->uicsr & uic->uicer;
 430         break;
 431     case DCR_UICVR:
 432         if (!uic->use_vectors)
 433             goto no_read;
 434         ret = uic->uicvr;
 435         break;
 436     case DCR_UICVCR:
 437         if (!uic->use_vectors)
 438             goto no_read;
 439         ret = uic->uicvcr;
 440         break;
 441     default:
 442     no_read:
 443         ret = 0x00000000;
 444         break;
 445     }
 446
 447     return ret;
 448 }
 449
 450 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
 451 {
 452     ppcuic_t *uic;
 453
 454     uic = opaque;
 455     dcrn -= uic->dcr_base;
 456 #ifdef DEBUG_UIC
 457     if (loglevel & CPU_LOG_INT) {
 458         fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
 459     }
 460 #endif
 461     switch (dcrn) {
 462     case DCR_UICSR:
 463         uic->uicsr &= ~val;
 464         ppcuic_trigger_irq(uic);
 465         break;
 466     case DCR_UICSRS:
 467         uic->uicsr |= val;
 468         ppcuic_trigger_irq(uic);
 469         break;
 470     case DCR_UICER:
 471         uic->uicer = val;
 472         ppcuic_trigger_irq(uic);
 473         break;
 474     case DCR_UICCR:
 475         uic->uiccr = val;
 476         ppcuic_trigger_irq(uic);
 477         break;
 478     case DCR_UICPR:
 479         uic->uicpr = val;
 480         ppcuic_trigger_irq(uic);
 481         break;
 482     case DCR_UICTR:
 483         uic->uictr = val;
 484         ppcuic_trigger_irq(uic);
 485         break;
 486     case DCR_UICMSR:
 487         break;
 488     case DCR_UICVR:
 489         break;
 490     case DCR_UICVCR:
 491         uic->uicvcr = val & 0xFFFFFFFD;
 492         ppcuic_trigger_irq(uic);
 493         break;
 494     }
 495 }
 496
 497 static void ppcuic_reset (void *opaque)
 498 {
 499     ppcuic_t *uic;
 500
 501     uic = opaque;
 502     uic->uiccr = 0x00000000;
 503     uic->uicer = 0x00000000;
 504     uic->uicpr = 0x00000000;
 505     uic->uicsr = 0x00000000;
 506     uic->uictr = 0x00000000;
 507     if (uic->use_vectors) {
 508         uic->uicvcr = 0x00000000;
 509         uic->uicvr = 0x0000000;
 510     }
 511 }
 512
 513 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
 514                        uint32_t dcr_base, int has_ssr, int has_vr)
 515 {
 516     ppcuic_t *uic;
 517     int i;
 518
 519     uic = qemu_mallocz(sizeof(ppcuic_t));
 520     if (uic != NULL) {
 521         uic->dcr_base = dcr_base;
 522         uic->irqs = irqs;
 523         if (has_vr)
 524             uic->use_vectors = 1;
 525         for (i = 0; i < DCR_UICMAX; i++) {
 526             ppc_dcr_register(env, dcr_base + i, uic,
 527                              &dcr_read_uic, &dcr_write_uic);
 528         }
 529         qemu_register_reset(ppcuic_reset, uic);
 530         ppcuic_reset(uic);
 531     }
 532
 533     return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
 534 }