SH4 delay slot code update, by Magnus Damm.
[qemu/qemu_0_9_1_stable.git] / hw / sh_intc.c
blob647f1cba9f521260249155aa018795bd4481766a
1 /*
2 * SuperH interrupt controller module
4 * Copyright (c) 2007 Magnus Damm
5 * Based on sh_timer.c and arm_timer.c by Paul Brook
6 * Copyright (c) 2005-2006 CodeSourcery.
8 * This code is licenced under the GPL.
9 */
11 #include <assert.h>
12 #include "sh_intc.h"
13 #include "hw.h"
14 #include "sh.h"
16 //#define DEBUG_INTC
18 #define INTC_A7(x) ((x) & 0x1fffffff)
19 #define INTC_ARRAY(x) (sizeof(x) / sizeof(x[0]))
21 #define INTC_MODE_NONE 0
22 #define INTC_MODE_DUAL_SET 1
23 #define INTC_MODE_DUAL_CLR 2
24 #define INTC_MODE_ENABLE_REG 3
25 #define INTC_MODE_MASK_REG 4
26 #define INTC_MODE_IS_PRIO 8
28 static unsigned int sh_intc_mode(unsigned long address,
29 unsigned long set_reg, unsigned long clr_reg)
31 if ((address != INTC_A7(set_reg)) &&
32 (address != INTC_A7(clr_reg)))
33 return INTC_MODE_NONE;
35 if (set_reg && clr_reg) {
36 if (address == INTC_A7(set_reg))
37 return INTC_MODE_DUAL_SET;
38 else
39 return INTC_MODE_DUAL_CLR;
42 if (set_reg)
43 return INTC_MODE_ENABLE_REG;
44 else
45 return INTC_MODE_MASK_REG;
48 static void sh_intc_locate(struct intc_desc *desc,
49 unsigned long address,
50 unsigned long **datap,
51 intc_enum **enums,
52 unsigned int *first,
53 unsigned int *width,
54 unsigned int *modep)
56 unsigned int i, mode;
58 /* this is slow but works for now */
60 if (desc->mask_regs) {
61 for (i = 0; i < desc->nr_mask_regs; i++) {
62 struct intc_mask_reg *mr = desc->mask_regs + i;
64 mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
65 if (mode == INTC_MODE_NONE)
66 continue;
68 *modep = mode;
69 *datap = &mr->value;
70 *enums = mr->enum_ids;
71 *first = mr->reg_width - 1;
72 *width = 1;
73 return;
77 if (desc->prio_regs) {
78 for (i = 0; i < desc->nr_prio_regs; i++) {
79 struct intc_prio_reg *pr = desc->prio_regs + i;
81 mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
82 if (mode == INTC_MODE_NONE)
83 continue;
85 *modep = mode | INTC_MODE_IS_PRIO;
86 *datap = &pr->value;
87 *enums = pr->enum_ids;
88 *first = (pr->reg_width / pr->field_width) - 1;
89 *width = pr->field_width;
90 return;
94 assert(0);
97 static void sh_intc_toggle(struct intc_desc *desc, intc_enum id,
98 int enable, int is_group)
100 struct intc_source *source = desc->sources + id;
101 int old = source->enable_count;
103 if (!id)
104 return;
106 if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
107 #ifdef DEBUG_INTC
108 printf("sh_intc: reserved interrupt source %d modified\n", id);
109 #endif
110 return;
113 if (source->vect) {
114 if (enable)
115 source->enable_count++;
116 else
117 source->enable_count--;
119 if (source->enable_count == source->enable_max) {
120 #ifdef DEBUG_INTC
121 printf("sh_intc: enabling interrupt source %d -> 0x%04x\n",
122 id, source->vect);
123 #endif
126 if (old == source->enable_max) {
127 #ifdef DEBUG_INTC
128 printf("sh_intc: disabling interrupt source %d -> 0x%04x\n",
129 id, source->vect);
130 #endif
133 #ifdef DEBUG_INTC
134 else {
135 printf("setting interrupt group %d to %d\n", id, !!enable);
137 #endif
139 if ((is_group || !source->vect) && source->next_enum_id) {
140 sh_intc_toggle(desc, source->next_enum_id, enable, 1);
143 #ifdef DEBUG_INTC
144 if (!source->vect) {
145 printf("setting interrupt group %d to %d - done\n", id, !!enable);
147 #endif
150 static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
152 struct intc_desc *desc = opaque;
153 intc_enum *enum_ids = NULL;
154 unsigned int first = 0;
155 unsigned int width = 0;
156 unsigned int mode = 0;
157 unsigned long *valuep;
159 #ifdef DEBUG_INTC
160 printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
161 #endif
163 sh_intc_locate(desc, (unsigned long)offset, &valuep,
164 &enum_ids, &first, &width, &mode);
165 return *valuep;
168 static void sh_intc_write(void *opaque, target_phys_addr_t offset,
169 uint32_t value)
171 struct intc_desc *desc = opaque;
172 intc_enum *enum_ids = NULL;
173 unsigned int first = 0;
174 unsigned int width = 0;
175 unsigned int mode = 0;
176 unsigned int k;
177 unsigned long *valuep;
178 unsigned long mask;
180 #ifdef DEBUG_INTC
181 printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
182 #endif
184 sh_intc_locate(desc, (unsigned long)offset, &valuep,
185 &enum_ids, &first, &width, &mode);
187 switch (mode) {
188 case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
189 case INTC_MODE_DUAL_SET: value |= *valuep; break;
190 case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
191 default: assert(0);
194 for (k = 0; k <= first; k++) {
195 mask = ((1 << width) - 1) << ((first - k) * width);
197 if ((*valuep & mask) == (value & mask))
198 continue;
199 #if 0
200 printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
201 k, first, enum_ids[k], (unsigned int)mask);
202 #endif
203 sh_intc_toggle(desc, enum_ids[k], value & mask, 0);
206 *valuep = value;
208 #ifdef DEBUG_INTC
209 printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
210 #endif
213 static CPUReadMemoryFunc *sh_intc_readfn[] = {
214 sh_intc_read,
215 sh_intc_read,
216 sh_intc_read
219 static CPUWriteMemoryFunc *sh_intc_writefn[] = {
220 sh_intc_write,
221 sh_intc_write,
222 sh_intc_write
225 struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
227 if (id)
228 return desc->sources + id;
230 return NULL;
233 static void sh_intc_register(struct intc_desc *desc,
234 unsigned long address)
236 if (address)
237 cpu_register_physical_memory(INTC_A7(address), 4, desc->iomemtype);
240 static void sh_intc_register_source(struct intc_desc *desc,
241 intc_enum source,
242 struct intc_group *groups,
243 int nr_groups)
245 unsigned int i, k;
246 struct intc_source *s;
248 if (desc->mask_regs) {
249 for (i = 0; i < desc->nr_mask_regs; i++) {
250 struct intc_mask_reg *mr = desc->mask_regs + i;
252 for (k = 0; k < INTC_ARRAY(mr->enum_ids); k++) {
253 if (mr->enum_ids[k] != source)
254 continue;
256 s = sh_intc_source(desc, mr->enum_ids[k]);
257 if (s)
258 s->enable_max++;
263 if (desc->prio_regs) {
264 for (i = 0; i < desc->nr_prio_regs; i++) {
265 struct intc_prio_reg *pr = desc->prio_regs + i;
267 for (k = 0; k < INTC_ARRAY(pr->enum_ids); k++) {
268 if (pr->enum_ids[k] != source)
269 continue;
271 s = sh_intc_source(desc, pr->enum_ids[k]);
272 if (s)
273 s->enable_max++;
278 if (groups) {
279 for (i = 0; i < nr_groups; i++) {
280 struct intc_group *gr = groups + i;
282 for (k = 0; k < INTC_ARRAY(gr->enum_ids); k++) {
283 if (gr->enum_ids[k] != source)
284 continue;
286 s = sh_intc_source(desc, gr->enum_ids[k]);
287 if (s)
288 s->enable_max++;
295 void sh_intc_register_sources(struct intc_desc *desc,
296 struct intc_vect *vectors,
297 int nr_vectors,
298 struct intc_group *groups,
299 int nr_groups)
301 unsigned int i, k;
302 struct intc_source *s;
304 for (i = 0; i < nr_vectors; i++) {
305 struct intc_vect *vect = vectors + i;
307 sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
308 s = sh_intc_source(desc, vect->enum_id);
309 if (s)
310 s->vect = vect->vect;
312 #ifdef DEBUG_INTC
313 printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
314 vect->enum_id, s->vect, s->enable_count, s->enable_max);
315 #endif
318 if (groups) {
319 for (i = 0; i < nr_groups; i++) {
320 struct intc_group *gr = groups + i;
322 s = sh_intc_source(desc, gr->enum_id);
323 s->next_enum_id = gr->enum_ids[0];
325 for (k = 1; k < INTC_ARRAY(gr->enum_ids); k++) {
326 if (!gr->enum_ids[k])
327 continue;
329 s = sh_intc_source(desc, gr->enum_ids[k - 1]);
330 s->next_enum_id = gr->enum_ids[k];
333 #ifdef DEBUG_INTC
334 printf("sh_intc: registered group %d (%d/%d)\n",
335 gr->enum_id, s->enable_count, s->enable_max);
336 #endif
341 int sh_intc_init(struct intc_desc *desc,
342 int nr_sources,
343 struct intc_mask_reg *mask_regs,
344 int nr_mask_regs,
345 struct intc_prio_reg *prio_regs,
346 int nr_prio_regs)
348 unsigned int i;
350 desc->nr_sources = nr_sources;
351 desc->mask_regs = mask_regs;
352 desc->nr_mask_regs = nr_mask_regs;
353 desc->prio_regs = prio_regs;
354 desc->nr_prio_regs = nr_prio_regs;
356 i = sizeof(struct intc_source) * nr_sources;
357 desc->sources = malloc(i);
358 if (!desc->sources)
359 return -1;
361 memset(desc->sources, 0, i);
363 desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn,
364 sh_intc_writefn, desc);
365 if (desc->mask_regs) {
366 for (i = 0; i < desc->nr_mask_regs; i++) {
367 struct intc_mask_reg *mr = desc->mask_regs + i;
369 sh_intc_register(desc, mr->set_reg);
370 sh_intc_register(desc, mr->clr_reg);
374 if (desc->prio_regs) {
375 for (i = 0; i < desc->nr_prio_regs; i++) {
376 struct intc_prio_reg *pr = desc->prio_regs + i;
378 sh_intc_register(desc, pr->set_reg);
379 sh_intc_register(desc, pr->clr_reg);
383 return 0;