hw/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 #define VERBOSE
  27 #define EMBED_STDVGA
  28 #undef DIRECT_VRAM
  29 #define HW_RECT_ACCEL
  30 #define HW_FILL_ACCEL
  31 #define HW_MOUSE_ACCEL
  32
  33 #ifdef EMBED_STDVGA
  34 # include "vga_int.h"
  35 #endif
  36
  37 struct vmsvga_state_s {
  38 #ifdef EMBED_STDVGA
  39     VGA_STATE_COMMON
  40 #endif
  41
  42     int width;
  43     int height;
  44     int invalidated;
  45     int depth;
  46     int bypp;
  47     int enable;
  48     int config;
  49     struct {
  50         int id;
  51         int x;
  52         int y;
  53         int on;
  54     } cursor;
  55
  56 #ifndef EMBED_STDVGA
  57     DisplayState *ds;
  58     int vram_size;
  59 #endif
  60     uint8_t *vram;
  61
  62     int index;
  63     int scratch_size;
  64     uint32_t *scratch;
  65     int new_width;
  66     int new_height;
  67     uint32_t guest;
  68     uint32_t svgaid;
  69     uint32_t wred;
  70     uint32_t wgreen;
  71     uint32_t wblue;
  72     int syncing;
  73     int fb_size;
  74
  75     union {
  76         uint32_t *fifo;
  77         struct __attribute__((__packed__)) {
  78             uint32_t min;
  79             uint32_t max;
  80             uint32_t next_cmd;
  81             uint32_t stop;
  82             /* Add registers here when adding capabilities.  */
  83             uint32_t fifo[0];
  84         } *cmd;
  85     };
  86
  87 #define REDRAW_FIFO_LEN 512
  88     struct vmsvga_rect_s {
  89         int x, y, w, h;
  90     } redraw_fifo[REDRAW_FIFO_LEN];
  91     int redraw_fifo_first, redraw_fifo_last;
  92 };
  93
  94 struct pci_vmsvga_state_s {
  95     PCIDevice card;
  96     struct vmsvga_state_s chip;
  97 };
  98
  99 #define SVGA_MAGIC              0x900000UL
 100 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
 101 #define SVGA_ID_0               SVGA_MAKE_ID(0)
 102 #define SVGA_ID_1               SVGA_MAKE_ID(1)
 103 #define SVGA_ID_2               SVGA_MAKE_ID(2)
 104
 105 #define SVGA_LEGACY_BASE_PORT   0x4560
 106 #define SVGA_INDEX_PORT         0x0
 107 #define SVGA_VALUE_PORT         0x1
 108 #define SVGA_BIOS_PORT          0x2
 109
 110 #define SVGA_VERSION_2
 111
 112 #ifdef SVGA_VERSION_2
 113 # define SVGA_ID                SVGA_ID_2
 114 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 115 # define SVGA_IO_MUL            1
 116 # define SVGA_FIFO_SIZE         0x10000
 117 # define SVGA_MEM_BASE          0xe0000000
 118 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 119 #else
 120 # define SVGA_ID                SVGA_ID_1
 121 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 122 # define SVGA_IO_MUL            4
 123 # define SVGA_FIFO_SIZE         0x10000
 124 # define SVGA_MEM_BASE          0xe0000000
 125 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 126 #endif
 127
 128 enum {
 129     /* ID 0, 1 and 2 registers */
 130     SVGA_REG_ID = 0,
 131     SVGA_REG_ENABLE = 1,
 132     SVGA_REG_WIDTH = 2,
 133     SVGA_REG_HEIGHT = 3,
 134     SVGA_REG_MAX_WIDTH = 4,
 135     SVGA_REG_MAX_HEIGHT = 5,
 136     SVGA_REG_DEPTH = 6,
 137     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 138     SVGA_REG_PSEUDOCOLOR = 8,
 139     SVGA_REG_RED_MASK = 9,
 140     SVGA_REG_GREEN_MASK = 10,
 141     SVGA_REG_BLUE_MASK = 11,
 142     SVGA_REG_BYTES_PER_LINE = 12,
 143     SVGA_REG_FB_START = 13,
 144     SVGA_REG_FB_OFFSET = 14,
 145     SVGA_REG_VRAM_SIZE = 15,
 146     SVGA_REG_FB_SIZE = 16,
 147
 148     /* ID 1 and 2 registers */
 149     SVGA_REG_CAPABILITIES = 17,
 150     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 151     SVGA_REG_MEM_SIZE = 19,
 152     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 153     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 154     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 155     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 156     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 157     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 158     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 159     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 160     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 161     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 162     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 163     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 164     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 165
 166     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 167     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 168     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 169 };
 170
 171 #define SVGA_CAP_NONE                   0
 172 #define SVGA_CAP_RECT_FILL              (1 << 0)
 173 #define SVGA_CAP_RECT_COPY              (1 << 1)
 174 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 175 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 176 #define SVGA_CAP_RASTER_OP              (1 << 4)
 177 #define SVGA_CAP_CURSOR                 (1 << 5)
 178 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 179 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 180 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 181 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 182 #define SVGA_CAP_GLYPH                  (1 << 10)
 183 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 184 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 185 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 186 #define SVGA_CAP_3D                     (1 << 14)
 187 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 188 #define SVGA_CAP_MULTIMON               (1 << 16)
 189 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 190
 191 /*
 192  * FIFO offsets (seen as an array of 32-bit words)
 193  */
 194 enum {
 195     /*
 196      * The original defined FIFO offsets
 197      */
 198     SVGA_FIFO_MIN = 0,
 199     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 200     SVGA_FIFO_NEXT_CMD,
 201     SVGA_FIFO_STOP,
 202
 203     /*
 204      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 205      */
 206     SVGA_FIFO_CAPABILITIES = 4,
 207     SVGA_FIFO_FLAGS,
 208     SVGA_FIFO_FENCE,
 209     SVGA_FIFO_3D_HWVERSION,
 210     SVGA_FIFO_PITCHLOCK,
 211 };
 212
 213 #define SVGA_FIFO_CAP_NONE              0
 214 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 215 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 216 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 217
 218 #define SVGA_FIFO_FLAG_NONE             0
 219 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 220
 221 /* These values can probably be changed arbitrarily.  */
 222 #define SVGA_SCRATCH_SIZE               0x8000
 223 #define SVGA_MAX_WIDTH                  2360
 224 #define SVGA_MAX_HEIGHT                 1770
 225
 226 #ifdef VERBOSE
 227 # define GUEST_OS_BASE          0x5001
 228 static const char *vmsvga_guest_id[] = {
 229     [0x00 ... 0x15] = "an unknown OS",
 230     [0x00] = "Dos",
 231     [0x01] = "Windows 3.1",
 232     [0x02] = "Windows 95",
 233     [0x03] = "Windows 98",
 234     [0x04] = "Windows ME",
 235     [0x05] = "Windows NT",
 236     [0x06] = "Windows 2000",
 237     [0x07] = "Linux",
 238     [0x08] = "OS/2",
 239     [0x0a] = "BSD",
 240     [0x0b] = "Whistler",
 241     [0x15] = "Windows 2003",
 242 };
 243 #endif
 244
 245 enum {
 246     SVGA_CMD_INVALID_CMD = 0,
 247     SVGA_CMD_UPDATE = 1,
 248     SVGA_CMD_RECT_FILL = 2,
 249     SVGA_CMD_RECT_COPY = 3,
 250     SVGA_CMD_DEFINE_BITMAP = 4,
 251     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 252     SVGA_CMD_DEFINE_PIXMAP = 6,
 253     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 254     SVGA_CMD_RECT_BITMAP_FILL = 8,
 255     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 256     SVGA_CMD_RECT_BITMAP_COPY = 10,
 257     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 258     SVGA_CMD_FREE_OBJECT = 12,
 259     SVGA_CMD_RECT_ROP_FILL = 13,
 260     SVGA_CMD_RECT_ROP_COPY = 14,
 261     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 262     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 263     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 264     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 265     SVGA_CMD_DEFINE_CURSOR = 19,
 266     SVGA_CMD_DISPLAY_CURSOR = 20,
 267     SVGA_CMD_MOVE_CURSOR = 21,
 268     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 269     SVGA_CMD_DRAW_GLYPH = 23,
 270     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 271     SVGA_CMD_UPDATE_VERBOSE = 25,
 272     SVGA_CMD_SURFACE_FILL = 26,
 273     SVGA_CMD_SURFACE_COPY = 27,
 274     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 275     SVGA_CMD_FRONT_ROP_FILL = 29,
 276     SVGA_CMD_FENCE = 30,
 277 };
 278
 279 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 280 enum {
 281     SVGA_CURSOR_ON_HIDE = 0,
 282     SVGA_CURSOR_ON_SHOW = 1,
 283     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 284     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 285 };
 286
 287 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 288                 int x, int y, int w, int h)
 289 {
 290 #ifndef DIRECT_VRAM
 291     int line = h;
 292     int bypl = s->bypp * s->width;
 293     int width = s->bypp * w;
 294     int start = s->bypp * x + bypl * y;
 295     uint8_t *src = s->vram + start;
 296     uint8_t *dst = s->ds->data + start;
 297
 298     for (; line > 0; line --, src += bypl, dst += bypl)
 299         memcpy(dst, src, width);
 300 #endif
 301
 302     dpy_update(s->ds, x, y, w, h);
 303 }
 304
 305 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
 306 {
 307 #ifndef DIRECT_VRAM
 308     memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height);
 309 #endif
 310
 311     dpy_update(s->ds, 0, 0, s->width, s->height);
 312 }
 313
 314 #ifdef DIRECT_VRAM
 315 # define vmsvga_update_rect_delayed     vmsvga_update_rect
 316 #else
 317 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 318                 int x, int y, int w, int h)
 319 {
 320     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
 321     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 322     rect->x = x;
 323     rect->y = y;
 324     rect->w = w;
 325     rect->h = h;
 326 }
 327 #endif
 328
 329 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 330 {
 331     struct vmsvga_rect_s *rect;
 332     if (s->invalidated) {
 333         s->redraw_fifo_first = s->redraw_fifo_last;
 334         return;
 335     }
 336     /* Overlapping region updates can be optimised out here - if someone
 337      * knows a smart algorithm to do that, please share.  */
 338     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 339         rect = &s->redraw_fifo[s->redraw_fifo_first ++];
 340         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 341         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 342     }
 343 }
 344
 345 #ifdef HW_RECT_ACCEL
 346 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 347                 int x0, int y0, int x1, int y1, int w, int h)
 348 {
 349 # ifdef DIRECT_VRAM
 350     uint8_t *vram = s->ds->data;
 351 # else
 352     uint8_t *vram = s->vram;
 353 # endif
 354     int bypl = s->bypp * s->width;
 355     int width = s->bypp * w;
 356     int line = h;
 357     uint8_t *ptr[2];
 358
 359 # ifdef DIRECT_VRAM
 360     if (s->ds->dpy_copy)
 361         s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h);
 362     else
 363 # endif
 364     {
 365         if (y1 > y0) {
 366             ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
 367             ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
 368             for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
 369                 memmove(ptr[1], ptr[0], width);
 370         } else {
 371             ptr[0] = vram + s->bypp * x0 + bypl * y0;
 372             ptr[1] = vram + s->bypp * x1 + bypl * y1;
 373             for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
 374                 memmove(ptr[1], ptr[0], width);
 375         }
 376     }
 377
 378     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 379 }
 380 #endif
 381
 382 #ifdef HW_FILL_ACCEL
 383 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 384                 uint32_t c, int x, int y, int w, int h)
 385 {
 386 # ifdef DIRECT_VRAM
 387     uint8_t *vram = s->ds->data;
 388 # else
 389     uint8_t *vram = s->vram;
 390 # endif
 391     int bypp = s->bypp;
 392     int bypl = bypp * s->width;
 393     int width = bypp * w;
 394     int line = h;
 395     int column;
 396     uint8_t *fst = vram + bypp * x + bypl * y;
 397     uint8_t *dst;
 398     uint8_t *src;
 399     uint8_t col[4];
 400
 401 # ifdef DIRECT_VRAM
 402     if (s->ds->dpy_fill)
 403         s->ds->dpy_fill(s->ds, x, y, w, h, c);
 404     else
 405 # endif
 406     {
 407         col[0] = c;
 408         col[1] = c >> 8;
 409         col[2] = c >> 16;
 410         col[3] = c >> 24;
 411
 412         if (line --) {
 413             dst = fst;
 414             src = col;
 415             for (column = width; column > 0; column --) {
 416                 *(dst ++) = *(src ++);
 417                 if (src - col == bypp)
 418                     src = col;
 419             }
 420             dst = fst;
 421             for (; line > 0; line --) {
 422                 dst += bypl;
 423                 memcpy(dst, fst, width);
 424             }
 425         }
 426     }
 427
 428     vmsvga_update_rect_delayed(s, x, y, w, h);
 429 }
 430 #endif
 431
 432 struct vmsvga_cursor_definition_s {
 433     int width;
 434     int height;
 435     int id;
 436     int bpp;
 437     int hot_x;
 438     int hot_y;
 439     uint32_t mask[1024];
 440     uint32_t image[1024];
 441 };
 442
 443 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 444 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 445
 446 #ifdef HW_MOUSE_ACCEL
 447 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 448                 struct vmsvga_cursor_definition_s *c)
 449 {
 450     int i;
 451     for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
 452         c->mask[i] = ~c->mask[i];
 453
 454     if (s->ds->cursor_define)
 455         s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
 456                         (uint8_t *) c->image, (uint8_t *) c->mask);
 457 }
 458 #endif
 459
 460 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
 461 {
 462     if (!s->config || !s->enable)
 463         return 1;
 464     return (s->cmd->next_cmd == s->cmd->stop);
 465 }
 466
 467 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 468 {
 469     uint32_t cmd = s->fifo[s->cmd->stop >> 2];
 470     s->cmd->stop += 4;
 471     if (s->cmd->stop >= s->cmd->max)
 472         s->cmd->stop = s->cmd->min;
 473     return cmd;
 474 }
 475
 476 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 477 {
 478     uint32_t cmd, colour;
 479     int args = 0;
 480     int x, y, dx, dy, width, height;
 481     struct vmsvga_cursor_definition_s cursor;
 482     while (!vmsvga_fifo_empty(s))
 483         switch (cmd = vmsvga_fifo_read(s)) {
 484         case SVGA_CMD_UPDATE:
 485         case SVGA_CMD_UPDATE_VERBOSE:
 486             x = vmsvga_fifo_read(s);
 487             y = vmsvga_fifo_read(s);
 488             width = vmsvga_fifo_read(s);
 489             height = vmsvga_fifo_read(s);
 490             vmsvga_update_rect_delayed(s, x, y, width, height);
 491             break;
 492
 493         case SVGA_CMD_RECT_FILL:
 494             colour = vmsvga_fifo_read(s);
 495             x = vmsvga_fifo_read(s);
 496             y = vmsvga_fifo_read(s);
 497             width = vmsvga_fifo_read(s);
 498             height = vmsvga_fifo_read(s);
 499 #ifdef HW_FILL_ACCEL
 500             vmsvga_fill_rect(s, colour, x, y, width, height);
 501             break;
 502 #else
 503             goto badcmd;
 504 #endif
 505
 506         case SVGA_CMD_RECT_COPY:
 507             x = vmsvga_fifo_read(s);
 508             y = vmsvga_fifo_read(s);
 509             dx = vmsvga_fifo_read(s);
 510             dy = vmsvga_fifo_read(s);
 511             width = vmsvga_fifo_read(s);
 512             height = vmsvga_fifo_read(s);
 513 #ifdef HW_RECT_ACCEL
 514             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 515             break;
 516 #else
 517             goto badcmd;
 518 #endif
 519
 520         case SVGA_CMD_DEFINE_CURSOR:
 521             cursor.id = vmsvga_fifo_read(s);
 522             cursor.hot_x = vmsvga_fifo_read(s);
 523             cursor.hot_y = vmsvga_fifo_read(s);
 524             cursor.width = x = vmsvga_fifo_read(s);
 525             cursor.height = y = vmsvga_fifo_read(s);
 526             vmsvga_fifo_read(s);
 527             cursor.bpp = vmsvga_fifo_read(s);
 528             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
 529                 cursor.mask[args] = vmsvga_fifo_read(s);
 530             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
 531                 cursor.image[args] = vmsvga_fifo_read(s);
 532 #ifdef HW_MOUSE_ACCEL
 533             vmsvga_cursor_define(s, &cursor);
 534             break;
 535 #else
 536             args = 0;
 537             goto badcmd;
 538 #endif
 539
 540         /*
 541          * Other commands that we at least know the number of arguments
 542          * for so we can avoid FIFO desync if driver uses them illegally.
 543          */
 544         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 545             vmsvga_fifo_read(s);
 546             vmsvga_fifo_read(s);
 547             vmsvga_fifo_read(s);
 548             x = vmsvga_fifo_read(s);
 549             y = vmsvga_fifo_read(s);
 550             args = x * y;
 551             goto badcmd;
 552         case SVGA_CMD_RECT_ROP_FILL:
 553             args = 6;
 554             goto badcmd;
 555         case SVGA_CMD_RECT_ROP_COPY:
 556             args = 7;
 557             goto badcmd;
 558         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 559             vmsvga_fifo_read(s);
 560             vmsvga_fifo_read(s);
 561             args = 7 + (vmsvga_fifo_read(s) >> 2);
 562             goto badcmd;
 563         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 564             args = 12;
 565             goto badcmd;
 566
 567         /*
 568          * Other commands that are not listed as depending on any
 569          * CAPABILITIES bits, but are not described in the README either.
 570          */
 571         case SVGA_CMD_SURFACE_FILL:
 572         case SVGA_CMD_SURFACE_COPY:
 573         case SVGA_CMD_FRONT_ROP_FILL:
 574         case SVGA_CMD_FENCE:
 575         case SVGA_CMD_INVALID_CMD:
 576             break; /* Nop */
 577
 578         default:
 579         badcmd:
 580             while (args --)
 581                 vmsvga_fifo_read(s);
 582             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 583                             __FUNCTION__, cmd);
 584             break;
 585         }
 586
 587     s->syncing = 0;
 588 }
 589
 590 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 591 {
 592     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 593     return s->index;
 594 }
 595
 596 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 597 {
 598     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 599     s->index = index;
 600 }
 601
 602 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 603 {
 604     uint32_t caps;
 605     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 606     switch (s->index) {
 607     case SVGA_REG_ID:
 608         return s->svgaid;
 609
 610     case SVGA_REG_ENABLE:
 611         return s->enable;
 612
 613     case SVGA_REG_WIDTH:
 614         return s->width;
 615
 616     case SVGA_REG_HEIGHT:
 617         return s->height;
 618
 619     case SVGA_REG_MAX_WIDTH:
 620         return SVGA_MAX_WIDTH;
 621
 622     case SVGA_REG_MAX_HEIGHT:
 623         return SVGA_MAX_HEIGHT;
 624
 625     case SVGA_REG_DEPTH:
 626         return s->depth;
 627
 628     case SVGA_REG_BITS_PER_PIXEL:
 629         return (s->depth + 7) & ~7;
 630
 631     case SVGA_REG_PSEUDOCOLOR:
 632         return 0x0;
 633
 634     case SVGA_REG_RED_MASK:
 635         return s->wred;
 636     case SVGA_REG_GREEN_MASK:
 637         return s->wgreen;
 638     case SVGA_REG_BLUE_MASK:
 639         return s->wblue;
 640
 641     case SVGA_REG_BYTES_PER_LINE:
 642         return ((s->depth + 7) >> 3) * s->new_width;
 643
 644     case SVGA_REG_FB_START:
 645         return SVGA_MEM_BASE;
 646
 647     case SVGA_REG_FB_OFFSET:
 648         return 0x0;
 649
 650     case SVGA_REG_VRAM_SIZE:
 651         return s->vram_size - SVGA_FIFO_SIZE;
 652
 653     case SVGA_REG_FB_SIZE:
 654         return s->fb_size;
 655
 656     case SVGA_REG_CAPABILITIES:
 657         caps = SVGA_CAP_NONE;
 658 #ifdef HW_RECT_ACCEL
 659         caps |= SVGA_CAP_RECT_COPY;
 660 #endif
 661 #ifdef HW_FILL_ACCEL
 662         caps |= SVGA_CAP_RECT_FILL;
 663 #endif
 664 #ifdef HW_MOUSE_ACCEL
 665         if (s->ds->mouse_set)
 666             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 667                     SVGA_CAP_CURSOR_BYPASS;
 668 #endif
 669         return caps;
 670
 671     case SVGA_REG_MEM_START:
 672         return SVGA_MEM_BASE + s->vram_size - SVGA_FIFO_SIZE;
 673
 674     case SVGA_REG_MEM_SIZE:
 675         return SVGA_FIFO_SIZE;
 676
 677     case SVGA_REG_CONFIG_DONE:
 678         return s->config;
 679
 680     case SVGA_REG_SYNC:
 681     case SVGA_REG_BUSY:
 682         return s->syncing;
 683
 684     case SVGA_REG_GUEST_ID:
 685         return s->guest;
 686
 687     case SVGA_REG_CURSOR_ID:
 688         return s->cursor.id;
 689
 690     case SVGA_REG_CURSOR_X:
 691         return s->cursor.x;
 692
 693     case SVGA_REG_CURSOR_Y:
 694         return s->cursor.x;
 695
 696     case SVGA_REG_CURSOR_ON:
 697         return s->cursor.on;
 698
 699     case SVGA_REG_HOST_BITS_PER_PIXEL:
 700         return (s->depth + 7) & ~7;
 701
 702     case SVGA_REG_SCRATCH_SIZE:
 703         return s->scratch_size;
 704
 705     case SVGA_REG_MEM_REGS:
 706     case SVGA_REG_NUM_DISPLAYS:
 707     case SVGA_REG_PITCHLOCK:
 708     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 709         return 0;
 710
 711     default:
 712         if (s->index >= SVGA_SCRATCH_BASE &&
 713                 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
 714             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 715         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 716     }
 717
 718     return 0;
 719 }
 720
 721 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 722 {
 723     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 724     switch (s->index) {
 725     case SVGA_REG_ID:
 726         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
 727             s->svgaid = value;
 728         break;
 729
 730     case SVGA_REG_ENABLE:
 731         s->enable = value;
 732         s->config &= !!value;
 733         s->width = -1;
 734         s->height = -1;
 735         s->invalidated = 1;
 736 #ifdef EMBED_STDVGA
 737         s->invalidate(opaque);
 738 #endif
 739         if (s->enable)
 740             s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
 741         break;
 742
 743     case SVGA_REG_WIDTH:
 744         s->new_width = value;
 745         s->invalidated = 1;
 746         break;
 747
 748     case SVGA_REG_HEIGHT:
 749         s->new_height = value;
 750         s->invalidated = 1;
 751         break;
 752
 753     case SVGA_REG_DEPTH:
 754     case SVGA_REG_BITS_PER_PIXEL:
 755         if (value != s->depth) {
 756             printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
 757             s->config = 0;
 758         }
 759         break;
 760
 761     case SVGA_REG_CONFIG_DONE:
 762         if (value) {
 763             s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
 764             /* Check range and alignment.  */
 765             if ((s->cmd->min | s->cmd->max |
 766                         s->cmd->next_cmd | s->cmd->stop) & 3)
 767                 break;
 768             if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
 769                 break;
 770             if (s->cmd->max > SVGA_FIFO_SIZE)
 771                 break;
 772             if (s->cmd->max < s->cmd->min + 10 * 1024)
 773                 break;
 774         }
 775         s->config = !!value;
 776         break;
 777
 778     case SVGA_REG_SYNC:
 779         s->syncing = 1;
 780         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 781         break;
 782
 783     case SVGA_REG_GUEST_ID:
 784         s->guest = value;
 785 #ifdef VERBOSE
 786         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 787                 sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id))
 788             printf("%s: guest runs %s.\n", __FUNCTION__,
 789                             vmsvga_guest_id[value - GUEST_OS_BASE]);
 790 #endif
 791         break;
 792
 793     case SVGA_REG_CURSOR_ID:
 794         s->cursor.id = value;
 795         break;
 796
 797     case SVGA_REG_CURSOR_X:
 798         s->cursor.x = value;
 799         break;
 800
 801     case SVGA_REG_CURSOR_Y:
 802         s->cursor.y = value;
 803         break;
 804
 805     case SVGA_REG_CURSOR_ON:
 806         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 807         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 808 #ifdef HW_MOUSE_ACCEL
 809         if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
 810             s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
 811 #endif
 812         break;
 813
 814     case SVGA_REG_MEM_REGS:
 815     case SVGA_REG_NUM_DISPLAYS:
 816     case SVGA_REG_PITCHLOCK:
 817     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 818         break;
 819
 820     default:
 821         if (s->index >= SVGA_SCRATCH_BASE &&
 822                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 823             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 824             break;
 825         }
 826         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 827     }
 828 }
 829
 830 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 831 {
 832     printf("%s: what are we supposed to return?\n", __FUNCTION__);
 833     return 0xcafe;
 834 }
 835
 836 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 837 {
 838     printf("%s: what are we supposed to do with (%08x)?\n",
 839                     __FUNCTION__, data);
 840 }
 841
 842 static inline void vmsvga_size(struct vmsvga_state_s *s)
 843 {
 844     if (s->new_width != s->width || s->new_height != s->height) {
 845         s->width = s->new_width;
 846         s->height = s->new_height;
 847         dpy_resize(s->ds, s->width, s->height);
 848         s->invalidated = 1;
 849     }
 850 }
 851
 852 static void vmsvga_update_display(void *opaque)
 853 {
 854     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 855     if (!s->enable) {
 856 #ifdef EMBED_STDVGA
 857         s->update(opaque);
 858 #endif
 859         return;
 860     }
 861
 862     vmsvga_size(s);
 863
 864     vmsvga_fifo_run(s);
 865     vmsvga_update_rect_flush(s);
 866
 867     /*
 868      * Is it more efficient to look at vram VGA-dirty bits or wait
 869      * for the driver to issue SVGA_CMD_UPDATE?
 870      */
 871     if (s->invalidated) {
 872         s->invalidated = 0;
 873         vmsvga_update_screen(s);
 874     }
 875 }
 876
 877 static void vmsvga_reset(struct vmsvga_state_s *s)
 878 {
 879     s->index = 0;
 880     s->enable = 0;
 881     s->config = 0;
 882     s->width = -1;
 883     s->height = -1;
 884     s->svgaid = SVGA_ID;
 885     s->depth = s->ds->depth ? s->ds->depth : 24;
 886     s->bypp = (s->depth + 7) >> 3;
 887     s->cursor.on = 0;
 888     s->redraw_fifo_first = 0;
 889     s->redraw_fifo_last = 0;
 890     switch (s->depth) {
 891     case 8:
 892         s->wred   = 0x00000007;
 893         s->wgreen = 0x00000038;
 894         s->wblue  = 0x000000c0;
 895         break;
 896     case 15:
 897         s->wred   = 0x0000001f;
 898         s->wgreen = 0x000003e0;
 899         s->wblue  = 0x00007c00;
 900         break;
 901     case 16:
 902         s->wred   = 0x0000001f;
 903         s->wgreen = 0x000007e0;
 904         s->wblue  = 0x0000f800;
 905         break;
 906     case 24:
 907         s->wred   = 0x00ff0000;
 908         s->wgreen = 0x0000ff00;
 909         s->wblue  = 0x000000ff;
 910         break;
 911     case 32:
 912         s->wred   = 0x00ff0000;
 913         s->wgreen = 0x0000ff00;
 914         s->wblue  = 0x000000ff;
 915         break;
 916     }
 917     s->syncing = 0;
 918 }
 919
 920 static void vmsvga_invalidate_display(void *opaque)
 921 {
 922     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 923     if (!s->enable) {
 924 #ifdef EMBED_STDVGA
 925         s->invalidate(opaque);
 926 #endif
 927         return;
 928     }
 929
 930     s->invalidated = 1;
 931 }
 932
 933 /* save the vga display in a PPM image even if no display is
 934    available */
 935 static void vmsvga_screen_dump(void *opaque, const char *filename)
 936 {
 937     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 938     if (!s->enable) {
 939 #ifdef EMBED_STDVGA
 940         s->screen_dump(opaque, filename);
 941 #endif
 942         return;
 943     }
 944
 945     if (s->depth == 32) {
 946         ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
 947     }
 948 }
 949
 950 #ifdef DIRECT_VRAM
 951 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
 952 {
 953     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 954     addr -= SVGA_MEM_BASE;
 955     if (addr < s->fb_size)
 956         return *(uint8_t *) (s->ds->data + addr);
 957     else
 958         return *(uint8_t *) (s->vram + addr);
 959 }
 960
 961 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
 962 {
 963     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 964     addr -= SVGA_MEM_BASE;
 965     if (addr < s->fb_size)
 966         return *(uint16_t *) (s->ds->data + addr);
 967     else
 968         return *(uint16_t *) (s->vram + addr);
 969 }
 970
 971 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
 972 {
 973     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 974     addr -= SVGA_MEM_BASE;
 975     if (addr < s->fb_size)
 976         return *(uint32_t *) (s->ds->data + addr);
 977     else
 978         return *(uint32_t *) (s->vram + addr);
 979 }
 980
 981 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
 982                 uint32_t value)
 983 {
 984     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 985     addr -= SVGA_MEM_BASE;
 986     if (addr < s->fb_size)
 987         *(uint8_t *) (s->ds->data + addr) = value;
 988     else
 989         *(uint8_t *) (s->vram + addr) = value;
 990 }
 991
 992 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
 993                 uint32_t value)
 994 {
 995     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 996     addr -= SVGA_MEM_BASE;
 997     if (addr < s->fb_size)
 998         *(uint16_t *) (s->ds->data + addr) = value;
 999     else
1000         *(uint16_t *) (s->vram + addr) = value;
1001 }
1002
1003 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1004                 uint32_t value)
1005 {
1006     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1007     addr -= SVGA_MEM_BASE;
1008     if (addr < s->fb_size)
1009         *(uint32_t *) (s->ds->data + addr) = value;
1010     else
1011         *(uint32_t *) (s->vram + addr) = value;
1012 }
1013
1014 static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1015     vmsvga_vram_readb,
1016     vmsvga_vram_readw,
1017     vmsvga_vram_readl,
1018 };
1019
1020 static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1021     vmsvga_vram_writeb,
1022     vmsvga_vram_writew,
1023     vmsvga_vram_writel,
1024 };
1025 #endif
1026
1027 static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1028 {
1029     qemu_put_be32s(f, &s->depth);
1030     qemu_put_be32s(f, &s->enable);
1031     qemu_put_be32s(f, &s->config);
1032     qemu_put_be32s(f, &s->cursor.id);
1033     qemu_put_be32s(f, &s->cursor.x);
1034     qemu_put_be32s(f, &s->cursor.y);
1035     qemu_put_be32s(f, &s->cursor.on);
1036     qemu_put_be32s(f, &s->index);
1037     qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1038     qemu_put_be32s(f, &s->new_width);
1039     qemu_put_be32s(f, &s->new_height);
1040     qemu_put_be32s(f, &s->guest);
1041     qemu_put_be32s(f, &s->svgaid);
1042     qemu_put_be32s(f, &s->syncing);
1043     qemu_put_be32s(f, &s->fb_size);
1044 }
1045
1046 static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1047 {
1048     int depth;
1049     qemu_get_be32s(f, &depth);
1050     qemu_get_be32s(f, &s->enable);
1051     qemu_get_be32s(f, &s->config);
1052     qemu_get_be32s(f, &s->cursor.id);
1053     qemu_get_be32s(f, &s->cursor.x);
1054     qemu_get_be32s(f, &s->cursor.y);
1055     qemu_get_be32s(f, &s->cursor.on);
1056     qemu_get_be32s(f, &s->index);
1057     qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1058     qemu_get_be32s(f, &s->new_width);
1059     qemu_get_be32s(f, &s->new_height);
1060     qemu_get_be32s(f, &s->guest);
1061     qemu_get_be32s(f, &s->svgaid);
1062     qemu_get_be32s(f, &s->syncing);
1063     qemu_get_be32s(f, &s->fb_size);
1064
1065     if (s->enable && depth != s->depth) {
1066         printf("%s: need colour depth of %i bits to resume operation.\n",
1067                         __FUNCTION__, depth);
1068         return -EINVAL;
1069     }
1070
1071     s->invalidated = 1;
1072     if (s->config)
1073         s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1074
1075     return 0;
1076 }
1077
1078 static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1079                 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1080                 int vga_ram_size)
1081 {
1082     int iomemtype;
1083     s->ds = ds;
1084     s->vram = vga_ram_base;
1085     s->vram_size = vga_ram_size;
1086
1087     s->scratch_size = SVGA_SCRATCH_SIZE;
1088     s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1089
1090     vmsvga_reset(s);
1091
1092 #ifdef DIRECT_VRAM
1093     iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1094                     vmsvga_vram_write, s);
1095 #else
1096     iomemtype = vga_ram_offset | IO_MEM_RAM;
1097 #endif
1098     cpu_register_physical_memory(SVGA_MEM_BASE, vga_ram_size,
1099                     iomemtype);
1100
1101     register_ioport_read(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_INDEX_PORT,
1102                     1, 4, vmsvga_index_read, s);
1103     register_ioport_write(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_INDEX_PORT,
1104                     1, 4, vmsvga_index_write, s);
1105     register_ioport_read(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_VALUE_PORT,
1106                     1, 4, vmsvga_value_read, s);
1107     register_ioport_write(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_VALUE_PORT,
1108                     1, 4, vmsvga_value_write, s);
1109     register_ioport_read(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_BIOS_PORT,
1110                     1, 4, vmsvga_bios_read, s);
1111     register_ioport_write(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_BIOS_PORT,
1112                     1, 4, vmsvga_bios_write, s);
1113
1114     graphic_console_init(ds, vmsvga_update_display,
1115                     vmsvga_invalidate_display, vmsvga_screen_dump, s);
1116
1117 #ifdef EMBED_STDVGA
1118     vga_common_init((VGAState *) s, ds,
1119                     vga_ram_base, vga_ram_offset, vga_ram_size);
1120     vga_init((VGAState *) s);
1121 #endif
1122 }
1123
1124 static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1125 {
1126     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1127     pci_device_save(&s->card, f);
1128     vmsvga_save(&s->chip, f);
1129 }
1130
1131 static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1132 {
1133     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1134     int ret;
1135
1136     ret = pci_device_load(&s->card, f);
1137     if (ret < 0)
1138         return ret;
1139
1140     ret = vmsvga_load(&s->chip, f);
1141     if (ret < 0)
1142         return ret;
1143
1144     return 0;
1145 }
1146
1147 #define PCI_VENDOR_ID_VMWARE            0x15ad
1148 #define PCI_DEVICE_ID_VMWARE_SVGA2      0x0405
1149 #define PCI_DEVICE_ID_VMWARE_SVGA       0x0710
1150 #define PCI_DEVICE_ID_VMWARE_NET        0x0720
1151 #define PCI_DEVICE_ID_VMWARE_SCSI       0x0730
1152 #define PCI_DEVICE_ID_VMWARE_IDE        0x1729
1153 #define PCI_CLASS_BASE_DISPLAY          0x03
1154 #define PCI_CLASS_SUB_VGA               0x00
1155 #define PCI_CLASS_HEADERTYPE_00h        0x00
1156
1157 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1158                      unsigned long vga_ram_offset, int vga_ram_size)
1159 {
1160     struct pci_vmsvga_state_s *s;
1161
1162     /* Setup PCI configuration */
1163     s = (struct pci_vmsvga_state_s *)
1164         pci_register_device(bus, "QEMUware SVGA",
1165                 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1166     s->card.config[PCI_VENDOR_ID]       = PCI_VENDOR_ID_VMWARE & 0xff;
1167     s->card.config[PCI_VENDOR_ID + 1]   = PCI_VENDOR_ID_VMWARE >> 8;
1168     s->card.config[PCI_DEVICE_ID]       = SVGA_PCI_DEVICE_ID & 0xff;
1169     s->card.config[PCI_DEVICE_ID + 1]   = SVGA_PCI_DEVICE_ID >> 8;
1170     s->card.config[PCI_COMMAND]         = 0x07;         /* I/O + Memory */
1171     s->card.config[PCI_CLASS_DEVICE]    = PCI_CLASS_SUB_VGA;
1172     s->card.config[0x0b]                = PCI_CLASS_BASE_DISPLAY;
1173     s->card.config[0x0c]                = 0x08;         /* Cache line size */
1174     s->card.config[0x0d]                = 0x40;         /* Latency timer */
1175     s->card.config[0x0e]                = PCI_CLASS_HEADERTYPE_00h;
1176     s->card.config[0x10]                = ((SVGA_IO_BASE >>  0) & 0xff) | 1;
1177     s->card.config[0x11]                =  (SVGA_IO_BASE >>  8) & 0xff;
1178     s->card.config[0x12]                =  (SVGA_IO_BASE >> 16) & 0xff;
1179     s->card.config[0x13]                =  (SVGA_IO_BASE >> 24) & 0xff;
1180     s->card.config[0x18]                = (SVGA_MEM_BASE >>  0) & 0xff;
1181     s->card.config[0x19]                = (SVGA_MEM_BASE >>  8) & 0xff;
1182     s->card.config[0x1a]                = (SVGA_MEM_BASE >> 16) & 0xff;
1183     s->card.config[0x1b]                = (SVGA_MEM_BASE >> 24) & 0xff;
1184     s->card.config[0x2c]                = PCI_VENDOR_ID_VMWARE & 0xff;
1185     s->card.config[0x2d]                = PCI_VENDOR_ID_VMWARE >> 8;
1186     s->card.config[0x2e]                = SVGA_PCI_DEVICE_ID & 0xff;
1187     s->card.config[0x2f]                = SVGA_PCI_DEVICE_ID >> 8;
1188     s->card.config[0x3c]                = 0xff;         /* End */
1189
1190     vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1191
1192     register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1193 }