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We must reset the PowerPC CPU _after_ registering it, as hardware reset
[qemu/qemu_0_9_1_stable.git] / hw / ppc405_uc.c
blob8a31475ed1569b82a25bf1fc0016b5d5365de164
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25 #include "ppc405.h"
26
27 extern int loglevel;
28 extern FILE *logfile;
29
30 //#define DEBUG_MMIO
31 #define DEBUG_OPBA
32 #define DEBUG_SDRAM
33 #define DEBUG_GPIO
34 #define DEBUG_SERIAL
35 #define DEBUG_OCM
36 //#define DEBUG_I2C
37 #define DEBUG_GPT
38 #define DEBUG_MAL
39 #define DEBUG_UIC
40 #define DEBUG_CLOCKS
41 //#define DEBUG_UNASSIGNED
42
43 /*****************************************************************************/
44 /* Generic PowerPC 405 processor instanciation */
45 CPUState *ppc405_init (const unsigned char *cpu_model,
46 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
47 uint32_t sysclk)
48 {
49 CPUState *env;
50 ppc_def_t *def;
51
52 /* init CPUs */
53 env = cpu_init();
54 ppc_find_by_name(cpu_model, &def);
55 if (def == NULL) {
56 cpu_abort(env, "Unable to find PowerPC %s CPU definition\n",
57 cpu_model);
58 }
59 cpu_ppc_register(env, def);
60 cpu_ppc_reset(env);
61 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
62 cpu_clk->opaque = env;
63 /* Set time-base frequency to sysclk */
64 tb_clk->cb = ppc_emb_timers_init(env, sysclk);
65 tb_clk->opaque = env;
66 ppc_dcr_init(env, NULL, NULL);
67 /* Register Qemu callbacks */
68 qemu_register_reset(&cpu_ppc_reset, env);
69 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
70
71 return env;
72 }
73
74 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
75 uint32_t flags)
76 {
77 ram_addr_t bdloc;
78 int i, n;
79
80 /* We put the bd structure at the top of memory */
81 if (bd->bi_memsize >= 0x01000000UL)
82 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
83 else
84 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
85 stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
86 stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
87 stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
88 stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
89 stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
90 stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
91 stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
92 stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
93 stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
94 for (i = 0; i < 6; i++)
95 stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
96 stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
97 stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
98 stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
99 stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
100 for (i = 0; i < 4; i++)
101 stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
102 for (i = 0; i < 32; i++)
103 stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
104 stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
105 stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
106 for (i = 0; i < 6; i++)
107 stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
108 n = 0x6A;
109 if (flags & 0x00000001) {
110 for (i = 0; i < 6; i++)
111 stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
112 }
113 stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);
114 n += 4;
115 for (i = 0; i < 2; i++) {
116 stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);
117 n += 4;
118 }
119
120 return bdloc;
121 }
122
123 /*****************************************************************************/
124 /* Shared peripherals */
125
126 /*****************************************************************************/
127 /* Fake device used to map multiple devices in a single memory page */
128 #define MMIO_AREA_BITS 8
129 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
130 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
131 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
132 struct ppc4xx_mmio_t {
133 target_phys_addr_t base;
134 CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
135 CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
136 void *opaque[MMIO_AREA_NB];
137 };
138
139 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
140 {
141 #ifdef DEBUG_UNASSIGNED
142 ppc4xx_mmio_t *mmio;
143
144 mmio = opaque;
145 printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
146 addr, mmio->base);
147 #endif
148
149 return 0;
150 }
151
152 static void unassigned_mmio_writeb (void *opaque,
153 target_phys_addr_t addr, uint32_t val)
154 {
155 #ifdef DEBUG_UNASSIGNED
156 ppc4xx_mmio_t *mmio;
157
158 mmio = opaque;
159 printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
160 addr, val, mmio->base);
161 #endif
162 }
163
164 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
165 unassigned_mmio_readb,
166 unassigned_mmio_readb,
167 unassigned_mmio_readb,
168 };
169
170 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
171 unassigned_mmio_writeb,
172 unassigned_mmio_writeb,
173 unassigned_mmio_writeb,
174 };
175
176 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
177 target_phys_addr_t addr, int len)
178 {
179 CPUReadMemoryFunc **mem_read;
180 uint32_t ret;
181 int idx;
182
183 idx = MMIO_IDX(addr - mmio->base);
184 #if defined(DEBUG_MMIO)
185 printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
186 mmio, len, addr, idx);
187 #endif
188 mem_read = mmio->mem_read[idx];
189 ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
190
191 return ret;
192 }
193
194 static void mmio_writelen (ppc4xx_mmio_t *mmio,
195 target_phys_addr_t addr, uint32_t value, int len)
196 {
197 CPUWriteMemoryFunc **mem_write;
198 int idx;
199
200 idx = MMIO_IDX(addr - mmio->base);
201 #if defined(DEBUG_MMIO)
202 printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
203 mmio, len, addr, idx, value);
204 #endif
205 mem_write = mmio->mem_write[idx];
206 (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
207 }
208
209 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
210 {
211 #if defined(DEBUG_MMIO)
212 printf("%s: addr " PADDRX "\n", __func__, addr);
213 #endif
214
215 return mmio_readlen(opaque, addr, 0);
216 }
217
218 static void mmio_writeb (void *opaque,
219 target_phys_addr_t addr, uint32_t value)
220 {
221 #if defined(DEBUG_MMIO)
222 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
223 #endif
224 mmio_writelen(opaque, addr, value, 0);
225 }
226
227 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
228 {
229 #if defined(DEBUG_MMIO)
230 printf("%s: addr " PADDRX "\n", __func__, addr);
231 #endif
232
233 return mmio_readlen(opaque, addr, 1);
234 }
235
236 static void mmio_writew (void *opaque,
237 target_phys_addr_t addr, uint32_t value)
238 {
239 #if defined(DEBUG_MMIO)
240 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
241 #endif
242 mmio_writelen(opaque, addr, value, 1);
243 }
244
245 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
246 {
247 #if defined(DEBUG_MMIO)
248 printf("%s: addr " PADDRX "\n", __func__, addr);
249 #endif
250
251 return mmio_readlen(opaque, addr, 2);
252 }
253
254 static void mmio_writel (void *opaque,
255 target_phys_addr_t addr, uint32_t value)
256 {
257 #if defined(DEBUG_MMIO)
258 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
259 #endif
260 mmio_writelen(opaque, addr, value, 2);
261 }
262
263 static CPUReadMemoryFunc *mmio_read[] = {
264 &mmio_readb,
265 &mmio_readw,
266 &mmio_readl,
267 };
268
269 static CPUWriteMemoryFunc *mmio_write[] = {
270 &mmio_writeb,
271 &mmio_writew,
272 &mmio_writel,
273 };
274
275 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
276 target_phys_addr_t offset, uint32_t len,
277 CPUReadMemoryFunc **mem_read,
278 CPUWriteMemoryFunc **mem_write, void *opaque)
279 {
280 uint32_t end;
281 int idx, eidx;
282
283 if ((offset + len) > TARGET_PAGE_SIZE)
284 return -1;
285 idx = MMIO_IDX(offset);
286 end = offset + len - 1;
287 eidx = MMIO_IDX(end);
288 #if defined(DEBUG_MMIO)
289 printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
290 end, idx, eidx);
291 #endif
292 for (; idx <= eidx; idx++) {
293 mmio->mem_read[idx] = mem_read;
294 mmio->mem_write[idx] = mem_write;
295 mmio->opaque[idx] = opaque;
296 }
297
298 return 0;
299 }
300
301 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
302 {
303 ppc4xx_mmio_t *mmio;
304 int mmio_memory;
305
306 mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
307 if (mmio != NULL) {
308 mmio->base = base;
309 mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
310 #if defined(DEBUG_MMIO)
311 printf("%s: %p base %08x len %08x %d\n", __func__,
312 mmio, base, TARGET_PAGE_SIZE, mmio_memory);
313 #endif
314 cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
315 ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
316 unassigned_mmio_read, unassigned_mmio_write,
317 mmio);
318 }
319
320 return mmio;
321 }
322
323 /*****************************************************************************/
324 /* Peripheral local bus arbitrer */
325 enum {
326 PLB0_BESR = 0x084,
327 PLB0_BEAR = 0x086,
328 PLB0_ACR = 0x087,
329 };
330
331 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
332 struct ppc4xx_plb_t {
333 uint32_t acr;
334 uint32_t bear;
335 uint32_t besr;
336 };
337
338 static target_ulong dcr_read_plb (void *opaque, int dcrn)
339 {
340 ppc4xx_plb_t *plb;
341 target_ulong ret;
342
343 plb = opaque;
344 switch (dcrn) {
345 case PLB0_ACR:
346 ret = plb->acr;
347 break;
348 case PLB0_BEAR:
349 ret = plb->bear;
350 break;
351 case PLB0_BESR:
352 ret = plb->besr;
353 break;
354 default:
355 /* Avoid gcc warning */
356 ret = 0;
357 break;
358 }
359
360 return ret;
361 }
362
363 static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
364 {
365 ppc4xx_plb_t *plb;
366
367 plb = opaque;
368 switch (dcrn) {
369 case PLB0_ACR:
370 /* We don't care about the actual parameters written as
371 * we don't manage any priorities on the bus
372 */
373 plb->acr = val & 0xF8000000;
374 break;
375 case PLB0_BEAR:
376 /* Read only */
377 break;
378 case PLB0_BESR:
379 /* Write-clear */
380 plb->besr &= ~val;
381 break;
382 }
383 }
384
385 static void ppc4xx_plb_reset (void *opaque)
386 {
387 ppc4xx_plb_t *plb;
388
389 plb = opaque;
390 plb->acr = 0x00000000;
391 plb->bear = 0x00000000;
392 plb->besr = 0x00000000;
393 }
394
395 void ppc4xx_plb_init (CPUState *env)
396 {
397 ppc4xx_plb_t *plb;
398
399 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
400 if (plb != NULL) {
401 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
402 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
403 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
404 ppc4xx_plb_reset(plb);
405 qemu_register_reset(ppc4xx_plb_reset, plb);
406 }
407 }
408
409 /*****************************************************************************/
410 /* PLB to OPB bridge */
411 enum {
412 POB0_BESR0 = 0x0A0,
413 POB0_BESR1 = 0x0A2,
414 POB0_BEAR = 0x0A4,
415 };
416
417 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
418 struct ppc4xx_pob_t {
419 uint32_t bear;
420 uint32_t besr[2];
421 };
422
423 static target_ulong dcr_read_pob (void *opaque, int dcrn)
424 {
425 ppc4xx_pob_t *pob;
426 target_ulong ret;
427
428 pob = opaque;
429 switch (dcrn) {
430 case POB0_BEAR:
431 ret = pob->bear;
432 break;
433 case POB0_BESR0:
434 case POB0_BESR1:
435 ret = pob->besr[dcrn - POB0_BESR0];
436 break;
437 default:
438 /* Avoid gcc warning */
439 ret = 0;
440 break;
441 }
442
443 return ret;
444 }
445
446 static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
447 {
448 ppc4xx_pob_t *pob;
449
450 pob = opaque;
451 switch (dcrn) {
452 case POB0_BEAR:
453 /* Read only */
454 break;
455 case POB0_BESR0:
456 case POB0_BESR1:
457 /* Write-clear */
458 pob->besr[dcrn - POB0_BESR0] &= ~val;
459 break;
460 }
461 }
462
463 static void ppc4xx_pob_reset (void *opaque)
464 {
465 ppc4xx_pob_t *pob;
466
467 pob = opaque;
468 /* No error */
469 pob->bear = 0x00000000;
470 pob->besr[0] = 0x0000000;
471 pob->besr[1] = 0x0000000;
472 }
473
474 void ppc4xx_pob_init (CPUState *env)
475 {
476 ppc4xx_pob_t *pob;
477
478 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
479 if (pob != NULL) {
480 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
481 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
482 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
483 qemu_register_reset(ppc4xx_pob_reset, pob);
484 ppc4xx_pob_reset(env);
485 }
486 }
487
488 /*****************************************************************************/
489 /* OPB arbitrer */
490 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
491 struct ppc4xx_opba_t {
492 target_phys_addr_t base;
493 uint8_t cr;
494 uint8_t pr;
495 };
496
497 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
498 {
499 ppc4xx_opba_t *opba;
500 uint32_t ret;
501
502 #ifdef DEBUG_OPBA
503 printf("%s: addr " PADDRX "\n", __func__, addr);
504 #endif
505 opba = opaque;
506 switch (addr - opba->base) {
507 case 0x00:
508 ret = opba->cr;
509 break;
510 case 0x01:
511 ret = opba->pr;
512 break;
513 default:
514 ret = 0x00;
515 break;
516 }
517
518 return ret;
519 }
520
521 static void opba_writeb (void *opaque,
522 target_phys_addr_t addr, uint32_t value)
523 {
524 ppc4xx_opba_t *opba;
525
526 #ifdef DEBUG_OPBA
527 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
528 #endif
529 opba = opaque;
530 switch (addr - opba->base) {
531 case 0x00:
532 opba->cr = value & 0xF8;
533 break;
534 case 0x01:
535 opba->pr = value & 0xFF;
536 break;
537 default:
538 break;
539 }
540 }
541
542 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
543 {
544 uint32_t ret;
545
546 #ifdef DEBUG_OPBA
547 printf("%s: addr " PADDRX "\n", __func__, addr);
548 #endif
549 ret = opba_readb(opaque, addr) << 8;
550 ret |= opba_readb(opaque, addr + 1);
551
552 return ret;
553 }
554
555 static void opba_writew (void *opaque,
556 target_phys_addr_t addr, uint32_t value)
557 {
558 #ifdef DEBUG_OPBA
559 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
560 #endif
561 opba_writeb(opaque, addr, value >> 8);
562 opba_writeb(opaque, addr + 1, value);
563 }
564
565 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
566 {
567 uint32_t ret;
568
569 #ifdef DEBUG_OPBA
570 printf("%s: addr " PADDRX "\n", __func__, addr);
571 #endif
572 ret = opba_readb(opaque, addr) << 24;
573 ret |= opba_readb(opaque, addr + 1) << 16;
574
575 return ret;
576 }
577
578 static void opba_writel (void *opaque,
579 target_phys_addr_t addr, uint32_t value)
580 {
581 #ifdef DEBUG_OPBA
582 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
583 #endif
584 opba_writeb(opaque, addr, value >> 24);
585 opba_writeb(opaque, addr + 1, value >> 16);
586 }
587
588 static CPUReadMemoryFunc *opba_read[] = {
589 &opba_readb,
590 &opba_readw,
591 &opba_readl,
592 };
593
594 static CPUWriteMemoryFunc *opba_write[] = {
595 &opba_writeb,
596 &opba_writew,
597 &opba_writel,
598 };
599
600 static void ppc4xx_opba_reset (void *opaque)
601 {
602 ppc4xx_opba_t *opba;
603
604 opba = opaque;
605 opba->cr = 0x00; /* No dynamic priorities - park disabled */
606 opba->pr = 0x11;
607 }
608
609 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
610 target_phys_addr_t offset)
611 {
612 ppc4xx_opba_t *opba;
613
614 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
615 if (opba != NULL) {
616 opba->base = offset;
617 #ifdef DEBUG_OPBA
618 printf("%s: offset=" PADDRX "\n", __func__, offset);
619 #endif
620 ppc4xx_mmio_register(env, mmio, offset, 0x002,
621 opba_read, opba_write, opba);
622 qemu_register_reset(ppc4xx_opba_reset, opba);
623 ppc4xx_opba_reset(opba);
624 }
625 }
626
627 /*****************************************************************************/
628 /* "Universal" Interrupt controller */
629 enum {
630 DCR_UICSR = 0x000,
631 DCR_UICSRS = 0x001,
632 DCR_UICER = 0x002,
633 DCR_UICCR = 0x003,
634 DCR_UICPR = 0x004,
635 DCR_UICTR = 0x005,
636 DCR_UICMSR = 0x006,
637 DCR_UICVR = 0x007,
638 DCR_UICVCR = 0x008,
639 DCR_UICMAX = 0x009,
640 };
641
642 #define UIC_MAX_IRQ 32
643 typedef struct ppcuic_t ppcuic_t;
644 struct ppcuic_t {
645 uint32_t dcr_base;
646 int use_vectors;
647 uint32_t uicsr; /* Status register */
648 uint32_t uicer; /* Enable register */
649 uint32_t uiccr; /* Critical register */
650 uint32_t uicpr; /* Polarity register */
651 uint32_t uictr; /* Triggering register */
652 uint32_t uicvcr; /* Vector configuration register */
653 uint32_t uicvr;
654 qemu_irq *irqs;
655 };
656
657 static void ppcuic_trigger_irq (ppcuic_t *uic)
658 {
659 uint32_t ir, cr;
660 int start, end, inc, i;
661
662 /* Trigger interrupt if any is pending */
663 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
664 cr = uic->uicsr & uic->uicer & uic->uiccr;
665 #ifdef DEBUG_UIC
666 if (loglevel & CPU_LOG_INT) {
667 fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
668 " %08x ir %08x cr %08x\n", __func__,
669 uic->uicsr, uic->uicer, uic->uiccr,
670 uic->uicsr & uic->uicer, ir, cr);
671 }
672 #endif
673 if (ir != 0x0000000) {
674 #ifdef DEBUG_UIC
675 if (loglevel & CPU_LOG_INT) {
676 fprintf(logfile, "Raise UIC interrupt\n");
677 }
678 #endif
679 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
680 } else {
681 #ifdef DEBUG_UIC
682 if (loglevel & CPU_LOG_INT) {
683 fprintf(logfile, "Lower UIC interrupt\n");
684 }
685 #endif
686 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
687 }
688 /* Trigger critical interrupt if any is pending and update vector */
689 if (cr != 0x0000000) {
690 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
691 if (uic->use_vectors) {
692 /* Compute critical IRQ vector */
693 if (uic->uicvcr & 1) {
694 start = 31;
695 end = 0;
696 inc = -1;
697 } else {
698 start = 0;
699 end = 31;
700 inc = 1;
701 }
702 uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
703 for (i = start; i <= end; i += inc) {
704 if (cr & (1 << i)) {
705 uic->uicvr += (i - start) * 512 * inc;
706 break;
707 }
708 }
709 }
710 #ifdef DEBUG_UIC
711 if (loglevel & CPU_LOG_INT) {
712 fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
713 uic->uicvr);
714 }
715 #endif
716 } else {
717 #ifdef DEBUG_UIC
718 if (loglevel & CPU_LOG_INT) {
719 fprintf(logfile, "Lower UIC critical interrupt\n");
720 }
721 #endif
722 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
723 uic->uicvr = 0x00000000;
724 }
725 }
726
727 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
728 {
729 ppcuic_t *uic;
730 uint32_t mask, sr;
731
732 uic = opaque;
733 mask = 1 << irq_num;
734 #ifdef DEBUG_UIC
735 if (loglevel & CPU_LOG_INT) {
736 fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
737 "%08x\n", __func__, irq_num, level,
738 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
739 }
740 #endif
741 if (irq_num < 0 || irq_num > 31)
742 return;
743 sr = uic->uicsr;
744 if (!(uic->uicpr & mask)) {
745 /* Negatively asserted IRQ */
746 level = level == 0 ? 1 : 0;
747 }
748 /* Update status register */
749 if (uic->uictr & mask) {
750 /* Edge sensitive interrupt */
751 if (level == 1)
752 uic->uicsr |= mask;
753 } else {
754 /* Level sensitive interrupt */
755 if (level == 1)
756 uic->uicsr |= mask;
757 else
758 uic->uicsr &= ~mask;
759 }
760 #ifdef DEBUG_UIC
761 if (loglevel & CPU_LOG_INT) {
762 fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
763 irq_num, level, uic->uicsr, sr);
764 }
765 #endif
766 if (sr != uic->uicsr)
767 ppcuic_trigger_irq(uic);
768 }
769
770 static target_ulong dcr_read_uic (void *opaque, int dcrn)
771 {
772 ppcuic_t *uic;
773 target_ulong ret;
774
775 uic = opaque;
776 dcrn -= uic->dcr_base;
777 switch (dcrn) {
778 case DCR_UICSR:
779 case DCR_UICSRS:
780 ret = uic->uicsr;
781 break;
782 case DCR_UICER:
783 ret = uic->uicer;
784 break;
785 case DCR_UICCR:
786 ret = uic->uiccr;
787 break;
788 case DCR_UICPR:
789 ret = uic->uicpr;
790 break;
791 case DCR_UICTR:
792 ret = uic->uictr;
793 break;
794 case DCR_UICMSR:
795 ret = uic->uicsr & uic->uicer;
796 break;
797 case DCR_UICVR:
798 if (!uic->use_vectors)
799 goto no_read;
800 ret = uic->uicvr;
801 break;
802 case DCR_UICVCR:
803 if (!uic->use_vectors)
804 goto no_read;
805 ret = uic->uicvcr;
806 break;
807 default:
808 no_read:
809 ret = 0x00000000;
810 break;
811 }
812
813 return ret;
814 }
815
816 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
817 {
818 ppcuic_t *uic;
819
820 uic = opaque;
821 dcrn -= uic->dcr_base;
822 #ifdef DEBUG_UIC
823 if (loglevel & CPU_LOG_INT) {
824 fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
825 }
826 #endif
827 switch (dcrn) {
828 case DCR_UICSR:
829 uic->uicsr &= ~val;
830 ppcuic_trigger_irq(uic);
831 break;
832 case DCR_UICSRS:
833 uic->uicsr |= val;
834 ppcuic_trigger_irq(uic);
835 break;
836 case DCR_UICER:
837 uic->uicer = val;
838 ppcuic_trigger_irq(uic);
839 break;
840 case DCR_UICCR:
841 uic->uiccr = val;
842 ppcuic_trigger_irq(uic);
843 break;
844 case DCR_UICPR:
845 uic->uicpr = val;
846 ppcuic_trigger_irq(uic);
847 break;
848 case DCR_UICTR:
849 uic->uictr = val;
850 ppcuic_trigger_irq(uic);
851 break;
852 case DCR_UICMSR:
853 break;
854 case DCR_UICVR:
855 break;
856 case DCR_UICVCR:
857 uic->uicvcr = val & 0xFFFFFFFD;
858 ppcuic_trigger_irq(uic);
859 break;
860 }
861 }
862
863 static void ppcuic_reset (void *opaque)
864 {
865 ppcuic_t *uic;
866
867 uic = opaque;
868 uic->uiccr = 0x00000000;
869 uic->uicer = 0x00000000;
870 uic->uicpr = 0x00000000;
871 uic->uicsr = 0x00000000;
872 uic->uictr = 0x00000000;
873 if (uic->use_vectors) {
874 uic->uicvcr = 0x00000000;
875 uic->uicvr = 0x0000000;
876 }
877 }
878
879 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
880 uint32_t dcr_base, int has_ssr, int has_vr)
881 {
882 ppcuic_t *uic;
883 int i;
884
885 uic = qemu_mallocz(sizeof(ppcuic_t));
886 if (uic != NULL) {
887 uic->dcr_base = dcr_base;
888 uic->irqs = irqs;
889 if (has_vr)
890 uic->use_vectors = 1;
891 for (i = 0; i < DCR_UICMAX; i++) {
892 ppc_dcr_register(env, dcr_base + i, uic,
893 &dcr_read_uic, &dcr_write_uic);
894 }
895 qemu_register_reset(ppcuic_reset, uic);
896 ppcuic_reset(uic);
897 }
898
899 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
900 }
901
902 /*****************************************************************************/
903 /* Code decompression controller */
904 /* XXX: TODO */
905
906 /*****************************************************************************/
907 /* SDRAM controller */
908 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
909 struct ppc4xx_sdram_t {
910 uint32_t addr;
911 int nbanks;
912 target_phys_addr_t ram_bases[4];
913 target_phys_addr_t ram_sizes[4];
914 uint32_t besr0;
915 uint32_t besr1;
916 uint32_t bear;
917 uint32_t cfg;
918 uint32_t status;
919 uint32_t rtr;
920 uint32_t pmit;
921 uint32_t bcr[4];
922 uint32_t tr;
923 uint32_t ecccfg;
924 uint32_t eccesr;
925 qemu_irq irq;
926 };
927
928 enum {
929 SDRAM0_CFGADDR = 0x010,
930 SDRAM0_CFGDATA = 0x011,
931 };
932
933 static uint32_t sdram_bcr (target_phys_addr_t ram_base,
934 target_phys_addr_t ram_size)
935 {
936 uint32_t bcr;
937
938 switch (ram_size) {
939 case (4 * 1024 * 1024):
940 bcr = 0x00000000;
941 break;
942 case (8 * 1024 * 1024):
943 bcr = 0x00020000;
944 break;
945 case (16 * 1024 * 1024):
946 bcr = 0x00040000;
947 break;
948 case (32 * 1024 * 1024):
949 bcr = 0x00060000;
950 break;
951 case (64 * 1024 * 1024):
952 bcr = 0x00080000;
953 break;
954 case (128 * 1024 * 1024):
955 bcr = 0x000A0000;
956 break;
957 case (256 * 1024 * 1024):
958 bcr = 0x000C0000;
959 break;
960 default:
961 printf("%s: invalid RAM size " TARGET_FMT_plx "\n",
962 __func__, ram_size);
963 return 0x00000000;
964 }
965 bcr |= ram_base & 0xFF800000;
966 bcr |= 1;
967
968 return bcr;
969 }
970
971 static inline target_phys_addr_t sdram_base (uint32_t bcr)
972 {
973 return bcr & 0xFF800000;
974 }
975
976 static target_ulong sdram_size (uint32_t bcr)
977 {
978 target_ulong size;
979 int sh;
980
981 sh = (bcr >> 17) & 0x7;
982 if (sh == 7)
983 size = -1;
984 else
985 size = (4 * 1024 * 1024) << sh;
986
987 return size;
988 }
989
990 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
991 {
992 if (*bcrp & 0x00000001) {
993 /* Unmap RAM */
994 #ifdef DEBUG_SDRAM
995 printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
996 __func__, sdram_base(*bcrp), sdram_size(*bcrp));
997 #endif
998 cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
999 IO_MEM_UNASSIGNED);
1000 }
1001 *bcrp = bcr & 0xFFDEE001;
1002 if (enabled && (bcr & 0x00000001)) {
1003 #ifdef DEBUG_SDRAM
1004 printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
1005 __func__, sdram_base(bcr), sdram_size(bcr));
1006 #endif
1007 cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
1008 sdram_base(bcr) | IO_MEM_RAM);
1009 }
1010 }
1011
1012 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
1013 {
1014 int i;
1015
1016 for (i = 0; i < sdram->nbanks; i++) {
1017 if (sdram->ram_sizes[i] != 0) {
1018 sdram_set_bcr(&sdram->bcr[i],
1019 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
1020 1);
1021 } else {
1022 sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
1023 }
1024 }
1025 }
1026
1027 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
1028 {
1029 int i;
1030
1031 for (i = 0; i < sdram->nbanks; i++) {
1032 #ifdef DEBUG_SDRAM
1033 printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
1034 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
1035 #endif
1036 cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
1037 sdram_size(sdram->bcr[i]),
1038 IO_MEM_UNASSIGNED);
1039 }
1040 }
1041
1042 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
1043 {
1044 ppc4xx_sdram_t *sdram;
1045 target_ulong ret;
1046
1047 sdram = opaque;
1048 switch (dcrn) {
1049 case SDRAM0_CFGADDR:
1050 ret = sdram->addr;
1051 break;
1052 case SDRAM0_CFGDATA:
1053 switch (sdram->addr) {
1054 case 0x00: /* SDRAM_BESR0 */
1055 ret = sdram->besr0;
1056 break;
1057 case 0x08: /* SDRAM_BESR1 */
1058 ret = sdram->besr1;
1059 break;
1060 case 0x10: /* SDRAM_BEAR */
1061 ret = sdram->bear;
1062 break;
1063 case 0x20: /* SDRAM_CFG */
1064 ret = sdram->cfg;
1065 break;
1066 case 0x24: /* SDRAM_STATUS */
1067 ret = sdram->status;
1068 break;
1069 case 0x30: /* SDRAM_RTR */
1070 ret = sdram->rtr;
1071 break;
1072 case 0x34: /* SDRAM_PMIT */
1073 ret = sdram->pmit;
1074 break;
1075 case 0x40: /* SDRAM_B0CR */
1076 ret = sdram->bcr[0];
1077 break;
1078 case 0x44: /* SDRAM_B1CR */
1079 ret = sdram->bcr[1];
1080 break;
1081 case 0x48: /* SDRAM_B2CR */
1082 ret = sdram->bcr[2];
1083 break;
1084 case 0x4C: /* SDRAM_B3CR */
1085 ret = sdram->bcr[3];
1086 break;
1087 case 0x80: /* SDRAM_TR */
1088 ret = -1; /* ? */
1089 break;
1090 case 0x94: /* SDRAM_ECCCFG */
1091 ret = sdram->ecccfg;
1092 break;
1093 case 0x98: /* SDRAM_ECCESR */
1094 ret = sdram->eccesr;
1095 break;
1096 default: /* Error */
1097 ret = -1;
1098 break;
1099 }
1100 break;
1101 default:
1102 /* Avoid gcc warning */
1103 ret = 0x00000000;
1104 break;
1105 }
1106
1107 return ret;
1108 }
1109
1110 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
1111 {
1112 ppc4xx_sdram_t *sdram;
1113
1114 sdram = opaque;
1115 switch (dcrn) {
1116 case SDRAM0_CFGADDR:
1117 sdram->addr = val;
1118 break;
1119 case SDRAM0_CFGDATA:
1120 switch (sdram->addr) {
1121 case 0x00: /* SDRAM_BESR0 */
1122 sdram->besr0 &= ~val;
1123 break;
1124 case 0x08: /* SDRAM_BESR1 */
1125 sdram->besr1 &= ~val;
1126 break;
1127 case 0x10: /* SDRAM_BEAR */
1128 sdram->bear = val;
1129 break;
1130 case 0x20: /* SDRAM_CFG */
1131 val &= 0xFFE00000;
1132 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
1133 #ifdef DEBUG_SDRAM
1134 printf("%s: enable SDRAM controller\n", __func__);
1135 #endif
1136 /* validate all RAM mappings */
1137 sdram_map_bcr(sdram);
1138 sdram->status &= ~0x80000000;
1139 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
1140 #ifdef DEBUG_SDRAM
1141 printf("%s: disable SDRAM controller\n", __func__);
1142 #endif
1143 /* invalidate all RAM mappings */
1144 sdram_unmap_bcr(sdram);
1145 sdram->status |= 0x80000000;
1146 }
1147 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
1148 sdram->status |= 0x40000000;
1149 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
1150 sdram->status &= ~0x40000000;
1151 sdram->cfg = val;
1152 break;
1153 case 0x24: /* SDRAM_STATUS */
1154 /* Read-only register */
1155 break;
1156 case 0x30: /* SDRAM_RTR */
1157 sdram->rtr = val & 0x3FF80000;
1158 break;
1159 case 0x34: /* SDRAM_PMIT */
1160 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
1161 break;
1162 case 0x40: /* SDRAM_B0CR */
1163 sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
1164 break;
1165 case 0x44: /* SDRAM_B1CR */
1166 sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
1167 break;
1168 case 0x48: /* SDRAM_B2CR */
1169 sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
1170 break;
1171 case 0x4C: /* SDRAM_B3CR */
1172 sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
1173 break;
1174 case 0x80: /* SDRAM_TR */
1175 sdram->tr = val & 0x018FC01F;
1176 break;
1177 case 0x94: /* SDRAM_ECCCFG */
1178 sdram->ecccfg = val & 0x00F00000;
1179 break;
1180 case 0x98: /* SDRAM_ECCESR */
1181 val &= 0xFFF0F000;
1182 if (sdram->eccesr == 0 && val != 0)
1183 qemu_irq_raise(sdram->irq);
1184 else if (sdram->eccesr != 0 && val == 0)
1185 qemu_irq_lower(sdram->irq);
1186 sdram->eccesr = val;
1187 break;
1188 default: /* Error */
1189 break;
1190 }
1191 break;
1192 }
1193 }
1194
1195 static void sdram_reset (void *opaque)
1196 {
1197 ppc4xx_sdram_t *sdram;
1198
1199 sdram = opaque;
1200 sdram->addr = 0x00000000;
1201 sdram->bear = 0x00000000;
1202 sdram->besr0 = 0x00000000; /* No error */
1203 sdram->besr1 = 0x00000000; /* No error */
1204 sdram->cfg = 0x00000000;
1205 sdram->ecccfg = 0x00000000; /* No ECC */
1206 sdram->eccesr = 0x00000000; /* No error */
1207 sdram->pmit = 0x07C00000;
1208 sdram->rtr = 0x05F00000;
1209 sdram->tr = 0x00854009;
1210 /* We pre-initialize RAM banks */
1211 sdram->status = 0x00000000;
1212 sdram->cfg = 0x00800000;
1213 sdram_unmap_bcr(sdram);
1214 }
1215
1216 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1217 target_phys_addr_t *ram_bases,
1218 target_phys_addr_t *ram_sizes,
1219 int do_init)
1220 {
1221 ppc4xx_sdram_t *sdram;
1222
1223 sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
1224 if (sdram != NULL) {
1225 sdram->irq = irq;
1226 sdram->nbanks = nbanks;
1227 memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
1228 memcpy(sdram->ram_bases, ram_bases,
1229 nbanks * sizeof(target_phys_addr_t));
1230 memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
1231 memcpy(sdram->ram_sizes, ram_sizes,
1232 nbanks * sizeof(target_phys_addr_t));
1233 sdram_reset(sdram);
1234 qemu_register_reset(&sdram_reset, sdram);
1235 ppc_dcr_register(env, SDRAM0_CFGADDR,
1236 sdram, &dcr_read_sdram, &dcr_write_sdram);
1237 ppc_dcr_register(env, SDRAM0_CFGDATA,
1238 sdram, &dcr_read_sdram, &dcr_write_sdram);
1239 if (do_init)
1240 sdram_map_bcr(sdram);
1241 }
1242 }
1243
1244 /*****************************************************************************/
1245 /* Peripheral controller */
1246 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
1247 struct ppc4xx_ebc_t {
1248 uint32_t addr;
1249 uint32_t bcr[8];
1250 uint32_t bap[8];
1251 uint32_t bear;
1252 uint32_t besr0;
1253 uint32_t besr1;
1254 uint32_t cfg;
1255 };
1256
1257 enum {
1258 EBC0_CFGADDR = 0x012,
1259 EBC0_CFGDATA = 0x013,
1260 };
1261
1262 static target_ulong dcr_read_ebc (void *opaque, int dcrn)
1263 {
1264 ppc4xx_ebc_t *ebc;
1265 target_ulong ret;
1266
1267 ebc = opaque;
1268 switch (dcrn) {
1269 case EBC0_CFGADDR:
1270 ret = ebc->addr;
1271 break;
1272 case EBC0_CFGDATA:
1273 switch (ebc->addr) {
1274 case 0x00: /* B0CR */
1275 ret = ebc->bcr[0];
1276 break;
1277 case 0x01: /* B1CR */
1278 ret = ebc->bcr[1];
1279 break;
1280 case 0x02: /* B2CR */
1281 ret = ebc->bcr[2];
1282 break;
1283 case 0x03: /* B3CR */
1284 ret = ebc->bcr[3];
1285 break;
1286 case 0x04: /* B4CR */
1287 ret = ebc->bcr[4];
1288 break;
1289 case 0x05: /* B5CR */
1290 ret = ebc->bcr[5];
1291 break;
1292 case 0x06: /* B6CR */
1293 ret = ebc->bcr[6];
1294 break;
1295 case 0x07: /* B7CR */
1296 ret = ebc->bcr[7];
1297 break;
1298 case 0x10: /* B0AP */
1299 ret = ebc->bap[0];
1300 break;
1301 case 0x11: /* B1AP */
1302 ret = ebc->bap[1];
1303 break;
1304 case 0x12: /* B2AP */
1305 ret = ebc->bap[2];
1306 break;
1307 case 0x13: /* B3AP */
1308 ret = ebc->bap[3];
1309 break;
1310 case 0x14: /* B4AP */
1311 ret = ebc->bap[4];
1312 break;
1313 case 0x15: /* B5AP */
1314 ret = ebc->bap[5];
1315 break;
1316 case 0x16: /* B6AP */
1317 ret = ebc->bap[6];
1318 break;
1319 case 0x17: /* B7AP */
1320 ret = ebc->bap[7];
1321 break;
1322 case 0x20: /* BEAR */
1323 ret = ebc->bear;
1324 break;
1325 case 0x21: /* BESR0 */
1326 ret = ebc->besr0;
1327 break;
1328 case 0x22: /* BESR1 */
1329 ret = ebc->besr1;
1330 break;
1331 case 0x23: /* CFG */
1332 ret = ebc->cfg;
1333 break;
1334 default:
1335 ret = 0x00000000;
1336 break;
1337 }
1338 default:
1339 ret = 0x00000000;
1340 break;
1341 }
1342
1343 return ret;
1344 }
1345
1346 static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
1347 {
1348 ppc4xx_ebc_t *ebc;
1349
1350 ebc = opaque;
1351 switch (dcrn) {
1352 case EBC0_CFGADDR:
1353 ebc->addr = val;
1354 break;
1355 case EBC0_CFGDATA:
1356 switch (ebc->addr) {
1357 case 0x00: /* B0CR */
1358 break;
1359 case 0x01: /* B1CR */
1360 break;
1361 case 0x02: /* B2CR */
1362 break;
1363 case 0x03: /* B3CR */
1364 break;
1365 case 0x04: /* B4CR */
1366 break;
1367 case 0x05: /* B5CR */
1368 break;
1369 case 0x06: /* B6CR */
1370 break;
1371 case 0x07: /* B7CR */
1372 break;
1373 case 0x10: /* B0AP */
1374 break;
1375 case 0x11: /* B1AP */
1376 break;
1377 case 0x12: /* B2AP */
1378 break;
1379 case 0x13: /* B3AP */
1380 break;
1381 case 0x14: /* B4AP */
1382 break;
1383 case 0x15: /* B5AP */
1384 break;
1385 case 0x16: /* B6AP */
1386 break;
1387 case 0x17: /* B7AP */
1388 break;
1389 case 0x20: /* BEAR */
1390 break;
1391 case 0x21: /* BESR0 */
1392 break;
1393 case 0x22: /* BESR1 */
1394 break;
1395 case 0x23: /* CFG */
1396 break;
1397 default:
1398 break;
1399 }
1400 break;
1401 default:
1402 break;
1403 }
1404 }
1405
1406 static void ebc_reset (void *opaque)
1407 {
1408 ppc4xx_ebc_t *ebc;
1409 int i;
1410
1411 ebc = opaque;
1412 ebc->addr = 0x00000000;
1413 ebc->bap[0] = 0x7F8FFE80;
1414 ebc->bcr[0] = 0xFFE28000;
1415 for (i = 0; i < 8; i++) {
1416 ebc->bap[i] = 0x00000000;
1417 ebc->bcr[i] = 0x00000000;
1418 }
1419 ebc->besr0 = 0x00000000;
1420 ebc->besr1 = 0x00000000;
1421 ebc->cfg = 0x80400000;
1422 }
1423
1424 void ppc405_ebc_init (CPUState *env)
1425 {
1426 ppc4xx_ebc_t *ebc;
1427
1428 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
1429 if (ebc != NULL) {
1430 ebc_reset(ebc);
1431 qemu_register_reset(&ebc_reset, ebc);
1432 ppc_dcr_register(env, EBC0_CFGADDR,
1433 ebc, &dcr_read_ebc, &dcr_write_ebc);
1434 ppc_dcr_register(env, EBC0_CFGDATA,
1435 ebc, &dcr_read_ebc, &dcr_write_ebc);
1436 }
1437 }
1438
1439 /*****************************************************************************/
1440 /* DMA controller */
1441 enum {
1442 DMA0_CR0 = 0x100,
1443 DMA0_CT0 = 0x101,
1444 DMA0_DA0 = 0x102,
1445 DMA0_SA0 = 0x103,
1446 DMA0_SG0 = 0x104,
1447 DMA0_CR1 = 0x108,
1448 DMA0_CT1 = 0x109,
1449 DMA0_DA1 = 0x10A,
1450 DMA0_SA1 = 0x10B,
1451 DMA0_SG1 = 0x10C,
1452 DMA0_CR2 = 0x110,
1453 DMA0_CT2 = 0x111,
1454 DMA0_DA2 = 0x112,
1455 DMA0_SA2 = 0x113,
1456 DMA0_SG2 = 0x114,
1457 DMA0_CR3 = 0x118,
1458 DMA0_CT3 = 0x119,
1459 DMA0_DA3 = 0x11A,
1460 DMA0_SA3 = 0x11B,
1461 DMA0_SG3 = 0x11C,
1462 DMA0_SR = 0x120,
1463 DMA0_SGC = 0x123,
1464 DMA0_SLP = 0x125,
1465 DMA0_POL = 0x126,
1466 };
1467
1468 typedef struct ppc405_dma_t ppc405_dma_t;
1469 struct ppc405_dma_t {
1470 qemu_irq irqs[4];
1471 uint32_t cr[4];
1472 uint32_t ct[4];
1473 uint32_t da[4];
1474 uint32_t sa[4];
1475 uint32_t sg[4];
1476 uint32_t sr;
1477 uint32_t sgc;
1478 uint32_t slp;
1479 uint32_t pol;
1480 };
1481
1482 static target_ulong dcr_read_dma (void *opaque, int dcrn)
1483 {
1484 ppc405_dma_t *dma;
1485
1486 dma = opaque;
1487
1488 return 0;
1489 }
1490
1491 static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
1492 {
1493 ppc405_dma_t *dma;
1494
1495 dma = opaque;
1496 }
1497
1498 static void ppc405_dma_reset (void *opaque)
1499 {
1500 ppc405_dma_t *dma;
1501 int i;
1502
1503 dma = opaque;
1504 for (i = 0; i < 4; i++) {
1505 dma->cr[i] = 0x00000000;
1506 dma->ct[i] = 0x00000000;
1507 dma->da[i] = 0x00000000;
1508 dma->sa[i] = 0x00000000;
1509 dma->sg[i] = 0x00000000;
1510 }
1511 dma->sr = 0x00000000;
1512 dma->sgc = 0x00000000;
1513 dma->slp = 0x7C000000;
1514 dma->pol = 0x00000000;
1515 }
1516
1517 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
1518 {
1519 ppc405_dma_t *dma;
1520
1521 dma = qemu_mallocz(sizeof(ppc405_dma_t));
1522 if (dma != NULL) {
1523 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
1524 ppc405_dma_reset(dma);
1525 qemu_register_reset(&ppc405_dma_reset, dma);
1526 ppc_dcr_register(env, DMA0_CR0,
1527 dma, &dcr_read_dma, &dcr_write_dma);
1528 ppc_dcr_register(env, DMA0_CT0,
1529 dma, &dcr_read_dma, &dcr_write_dma);
1530 ppc_dcr_register(env, DMA0_DA0,
1531 dma, &dcr_read_dma, &dcr_write_dma);
1532 ppc_dcr_register(env, DMA0_SA0,
1533 dma, &dcr_read_dma, &dcr_write_dma);
1534 ppc_dcr_register(env, DMA0_SG0,
1535 dma, &dcr_read_dma, &dcr_write_dma);
1536 ppc_dcr_register(env, DMA0_CR1,
1537 dma, &dcr_read_dma, &dcr_write_dma);
1538 ppc_dcr_register(env, DMA0_CT1,
1539 dma, &dcr_read_dma, &dcr_write_dma);
1540 ppc_dcr_register(env, DMA0_DA1,
1541 dma, &dcr_read_dma, &dcr_write_dma);
1542 ppc_dcr_register(env, DMA0_SA1,
1543 dma, &dcr_read_dma, &dcr_write_dma);
1544 ppc_dcr_register(env, DMA0_SG1,
1545 dma, &dcr_read_dma, &dcr_write_dma);
1546 ppc_dcr_register(env, DMA0_CR2,
1547 dma, &dcr_read_dma, &dcr_write_dma);
1548 ppc_dcr_register(env, DMA0_CT2,
1549 dma, &dcr_read_dma, &dcr_write_dma);
1550 ppc_dcr_register(env, DMA0_DA2,
1551 dma, &dcr_read_dma, &dcr_write_dma);
1552 ppc_dcr_register(env, DMA0_SA2,
1553 dma, &dcr_read_dma, &dcr_write_dma);
1554 ppc_dcr_register(env, DMA0_SG2,
1555 dma, &dcr_read_dma, &dcr_write_dma);
1556 ppc_dcr_register(env, DMA0_CR3,
1557 dma, &dcr_read_dma, &dcr_write_dma);
1558 ppc_dcr_register(env, DMA0_CT3,
1559 dma, &dcr_read_dma, &dcr_write_dma);
1560 ppc_dcr_register(env, DMA0_DA3,
1561 dma, &dcr_read_dma, &dcr_write_dma);
1562 ppc_dcr_register(env, DMA0_SA3,
1563 dma, &dcr_read_dma, &dcr_write_dma);
1564 ppc_dcr_register(env, DMA0_SG3,
1565 dma, &dcr_read_dma, &dcr_write_dma);
1566 ppc_dcr_register(env, DMA0_SR,
1567 dma, &dcr_read_dma, &dcr_write_dma);
1568 ppc_dcr_register(env, DMA0_SGC,
1569 dma, &dcr_read_dma, &dcr_write_dma);
1570 ppc_dcr_register(env, DMA0_SLP,
1571 dma, &dcr_read_dma, &dcr_write_dma);
1572 ppc_dcr_register(env, DMA0_POL,
1573 dma, &dcr_read_dma, &dcr_write_dma);
1574 }
1575 }
1576
1577 /*****************************************************************************/
1578 /* GPIO */
1579 typedef struct ppc405_gpio_t ppc405_gpio_t;
1580 struct ppc405_gpio_t {
1581 target_phys_addr_t base;
1582 uint32_t or;
1583 uint32_t tcr;
1584 uint32_t osrh;
1585 uint32_t osrl;
1586 uint32_t tsrh;
1587 uint32_t tsrl;
1588 uint32_t odr;
1589 uint32_t ir;
1590 uint32_t rr1;
1591 uint32_t isr1h;
1592 uint32_t isr1l;
1593 };
1594
1595 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
1596 {
1597 ppc405_gpio_t *gpio;
1598
1599 gpio = opaque;
1600 #ifdef DEBUG_GPIO
1601 printf("%s: addr " PADDRX "\n", __func__, addr);
1602 #endif
1603
1604 return 0;
1605 }
1606
1607 static void ppc405_gpio_writeb (void *opaque,
1608 target_phys_addr_t addr, uint32_t value)
1609 {
1610 ppc405_gpio_t *gpio;
1611
1612 gpio = opaque;
1613 #ifdef DEBUG_GPIO
1614 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1615 #endif
1616 }
1617
1618 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
1619 {
1620 ppc405_gpio_t *gpio;
1621
1622 gpio = opaque;
1623 #ifdef DEBUG_GPIO
1624 printf("%s: addr " PADDRX "\n", __func__, addr);
1625 #endif
1626
1627 return 0;
1628 }
1629
1630 static void ppc405_gpio_writew (void *opaque,
1631 target_phys_addr_t addr, uint32_t value)
1632 {
1633 ppc405_gpio_t *gpio;
1634
1635 gpio = opaque;
1636 #ifdef DEBUG_GPIO
1637 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1638 #endif
1639 }
1640
1641 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
1642 {
1643 ppc405_gpio_t *gpio;
1644
1645 gpio = opaque;
1646 #ifdef DEBUG_GPIO
1647 printf("%s: addr " PADDRX "\n", __func__, addr);
1648 #endif
1649
1650 return 0;
1651 }
1652
1653 static void ppc405_gpio_writel (void *opaque,
1654 target_phys_addr_t addr, uint32_t value)
1655 {
1656 ppc405_gpio_t *gpio;
1657
1658 gpio = opaque;
1659 #ifdef DEBUG_GPIO
1660 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1661 #endif
1662 }
1663
1664 static CPUReadMemoryFunc *ppc405_gpio_read[] = {
1665 &ppc405_gpio_readb,
1666 &ppc405_gpio_readw,
1667 &ppc405_gpio_readl,
1668 };
1669
1670 static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
1671 &ppc405_gpio_writeb,
1672 &ppc405_gpio_writew,
1673 &ppc405_gpio_writel,
1674 };
1675
1676 static void ppc405_gpio_reset (void *opaque)
1677 {
1678 ppc405_gpio_t *gpio;
1679
1680 gpio = opaque;
1681 }
1682
1683 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
1684 target_phys_addr_t offset)
1685 {
1686 ppc405_gpio_t *gpio;
1687
1688 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
1689 if (gpio != NULL) {
1690 gpio->base = offset;
1691 ppc405_gpio_reset(gpio);
1692 qemu_register_reset(&ppc405_gpio_reset, gpio);
1693 #ifdef DEBUG_GPIO
1694 printf("%s: offset=" PADDRX "\n", __func__, offset);
1695 #endif
1696 ppc4xx_mmio_register(env, mmio, offset, 0x038,
1697 ppc405_gpio_read, ppc405_gpio_write, gpio);
1698 }
1699 }
1700
1701 /*****************************************************************************/
1702 /* Serial ports */
1703 static CPUReadMemoryFunc *serial_mm_read[] = {
1704 &serial_mm_readb,
1705 &serial_mm_readw,
1706 &serial_mm_readl,
1707 };
1708
1709 static CPUWriteMemoryFunc *serial_mm_write[] = {
1710 &serial_mm_writeb,
1711 &serial_mm_writew,
1712 &serial_mm_writel,
1713 };
1714
1715 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1716 target_phys_addr_t offset, qemu_irq irq,
1717 CharDriverState *chr)
1718 {
1719 void *serial;
1720
1721 #ifdef DEBUG_SERIAL
1722 printf("%s: offset=" PADDRX "\n", __func__, offset);
1723 #endif
1724 serial = serial_mm_init(offset, 0, irq, chr, 0);
1725 ppc4xx_mmio_register(env, mmio, offset, 0x008,
1726 serial_mm_read, serial_mm_write, serial);
1727 }
1728
1729 /*****************************************************************************/
1730 /* On Chip Memory */
1731 enum {
1732 OCM0_ISARC = 0x018,
1733 OCM0_ISACNTL = 0x019,
1734 OCM0_DSARC = 0x01A,
1735 OCM0_DSACNTL = 0x01B,
1736 };
1737
1738 typedef struct ppc405_ocm_t ppc405_ocm_t;
1739 struct ppc405_ocm_t {
1740 target_ulong offset;
1741 uint32_t isarc;
1742 uint32_t isacntl;
1743 uint32_t dsarc;
1744 uint32_t dsacntl;
1745 };
1746
1747 static void ocm_update_mappings (ppc405_ocm_t *ocm,
1748 uint32_t isarc, uint32_t isacntl,
1749 uint32_t dsarc, uint32_t dsacntl)
1750 {
1751 #ifdef DEBUG_OCM
1752 printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
1753 isarc, isacntl, dsarc, dsacntl,
1754 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
1755 #endif
1756 if (ocm->isarc != isarc ||
1757 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
1758 if (ocm->isacntl & 0x80000000) {
1759 /* Unmap previously assigned memory region */
1760 printf("OCM unmap ISA %08x\n", ocm->isarc);
1761 cpu_register_physical_memory(ocm->isarc, 0x04000000,
1762 IO_MEM_UNASSIGNED);
1763 }
1764 if (isacntl & 0x80000000) {
1765 /* Map new instruction memory region */
1766 #ifdef DEBUG_OCM
1767 printf("OCM map ISA %08x\n", isarc);
1768 #endif
1769 cpu_register_physical_memory(isarc, 0x04000000,
1770 ocm->offset | IO_MEM_RAM);
1771 }
1772 }
1773 if (ocm->dsarc != dsarc ||
1774 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
1775 if (ocm->dsacntl & 0x80000000) {
1776 /* Beware not to unmap the region we just mapped */
1777 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
1778 /* Unmap previously assigned memory region */
1779 #ifdef DEBUG_OCM
1780 printf("OCM unmap DSA %08x\n", ocm->dsarc);
1781 #endif
1782 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
1783 IO_MEM_UNASSIGNED);
1784 }
1785 }
1786 if (dsacntl & 0x80000000) {
1787 /* Beware not to remap the region we just mapped */
1788 if (!(isacntl & 0x80000000) || dsarc != isarc) {
1789 /* Map new data memory region */
1790 #ifdef DEBUG_OCM
1791 printf("OCM map DSA %08x\n", dsarc);
1792 #endif
1793 cpu_register_physical_memory(dsarc, 0x04000000,
1794 ocm->offset | IO_MEM_RAM);
1795 }
1796 }
1797 }
1798 }
1799
1800 static target_ulong dcr_read_ocm (void *opaque, int dcrn)
1801 {
1802 ppc405_ocm_t *ocm;
1803 target_ulong ret;
1804
1805 ocm = opaque;
1806 switch (dcrn) {
1807 case OCM0_ISARC:
1808 ret = ocm->isarc;
1809 break;
1810 case OCM0_ISACNTL:
1811 ret = ocm->isacntl;
1812 break;
1813 case OCM0_DSARC:
1814 ret = ocm->dsarc;
1815 break;
1816 case OCM0_DSACNTL:
1817 ret = ocm->dsacntl;
1818 break;
1819 default:
1820 ret = 0;
1821 break;
1822 }
1823
1824 return ret;
1825 }
1826
1827 static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
1828 {
1829 ppc405_ocm_t *ocm;
1830 uint32_t isarc, dsarc, isacntl, dsacntl;
1831
1832 ocm = opaque;
1833 isarc = ocm->isarc;
1834 dsarc = ocm->dsarc;
1835 isacntl = ocm->isacntl;
1836 dsacntl = ocm->dsacntl;
1837 switch (dcrn) {
1838 case OCM0_ISARC:
1839 isarc = val & 0xFC000000;
1840 break;
1841 case OCM0_ISACNTL:
1842 isacntl = val & 0xC0000000;
1843 break;
1844 case OCM0_DSARC:
1845 isarc = val & 0xFC000000;
1846 break;
1847 case OCM0_DSACNTL:
1848 isacntl = val & 0xC0000000;
1849 break;
1850 }
1851 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1852 ocm->isarc = isarc;
1853 ocm->dsarc = dsarc;
1854 ocm->isacntl = isacntl;
1855 ocm->dsacntl = dsacntl;
1856 }
1857
1858 static void ocm_reset (void *opaque)
1859 {
1860 ppc405_ocm_t *ocm;
1861 uint32_t isarc, dsarc, isacntl, dsacntl;
1862
1863 ocm = opaque;
1864 isarc = 0x00000000;
1865 isacntl = 0x00000000;
1866 dsarc = 0x00000000;
1867 dsacntl = 0x00000000;
1868 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1869 ocm->isarc = isarc;
1870 ocm->dsarc = dsarc;
1871 ocm->isacntl = isacntl;
1872 ocm->dsacntl = dsacntl;
1873 }
1874
1875 void ppc405_ocm_init (CPUState *env, unsigned long offset)
1876 {
1877 ppc405_ocm_t *ocm;
1878
1879 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
1880 if (ocm != NULL) {
1881 ocm->offset = offset;
1882 ocm_reset(ocm);
1883 qemu_register_reset(&ocm_reset, ocm);
1884 ppc_dcr_register(env, OCM0_ISARC,
1885 ocm, &dcr_read_ocm, &dcr_write_ocm);
1886 ppc_dcr_register(env, OCM0_ISACNTL,
1887 ocm, &dcr_read_ocm, &dcr_write_ocm);
1888 ppc_dcr_register(env, OCM0_DSARC,
1889 ocm, &dcr_read_ocm, &dcr_write_ocm);
1890 ppc_dcr_register(env, OCM0_DSACNTL,
1891 ocm, &dcr_read_ocm, &dcr_write_ocm);
1892 }
1893 }
1894
1895 /*****************************************************************************/
1896 /* I2C controller */
1897 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
1898 struct ppc4xx_i2c_t {
1899 target_phys_addr_t base;
1900 qemu_irq irq;
1901 uint8_t mdata;
1902 uint8_t lmadr;
1903 uint8_t hmadr;
1904 uint8_t cntl;
1905 uint8_t mdcntl;
1906 uint8_t sts;
1907 uint8_t extsts;
1908 uint8_t sdata;
1909 uint8_t lsadr;
1910 uint8_t hsadr;
1911 uint8_t clkdiv;
1912 uint8_t intrmsk;
1913 uint8_t xfrcnt;
1914 uint8_t xtcntlss;
1915 uint8_t directcntl;
1916 };
1917
1918 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1919 {
1920 ppc4xx_i2c_t *i2c;
1921 uint32_t ret;
1922
1923 #ifdef DEBUG_I2C
1924 printf("%s: addr " PADDRX "\n", __func__, addr);
1925 #endif
1926 i2c = opaque;
1927 switch (addr - i2c->base) {
1928 case 0x00:
1929 // i2c_readbyte(&i2c->mdata);
1930 ret = i2c->mdata;
1931 break;
1932 case 0x02:
1933 ret = i2c->sdata;
1934 break;
1935 case 0x04:
1936 ret = i2c->lmadr;
1937 break;
1938 case 0x05:
1939 ret = i2c->hmadr;
1940 break;
1941 case 0x06:
1942 ret = i2c->cntl;
1943 break;
1944 case 0x07:
1945 ret = i2c->mdcntl;
1946 break;
1947 case 0x08:
1948 ret = i2c->sts;
1949 break;
1950 case 0x09:
1951 ret = i2c->extsts;
1952 break;
1953 case 0x0A:
1954 ret = i2c->lsadr;
1955 break;
1956 case 0x0B:
1957 ret = i2c->hsadr;
1958 break;
1959 case 0x0C:
1960 ret = i2c->clkdiv;
1961 break;
1962 case 0x0D:
1963 ret = i2c->intrmsk;
1964 break;
1965 case 0x0E:
1966 ret = i2c->xfrcnt;
1967 break;
1968 case 0x0F:
1969 ret = i2c->xtcntlss;
1970 break;
1971 case 0x10:
1972 ret = i2c->directcntl;
1973 break;
1974 default:
1975 ret = 0x00;
1976 break;
1977 }
1978 #ifdef DEBUG_I2C
1979 printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret);
1980 #endif
1981
1982 return ret;
1983 }
1984
1985 static void ppc4xx_i2c_writeb (void *opaque,
1986 target_phys_addr_t addr, uint32_t value)
1987 {
1988 ppc4xx_i2c_t *i2c;
1989
1990 #ifdef DEBUG_I2C
1991 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1992 #endif
1993 i2c = opaque;
1994 switch (addr - i2c->base) {
1995 case 0x00:
1996 i2c->mdata = value;
1997 // i2c_sendbyte(&i2c->mdata);
1998 break;
1999 case 0x02:
2000 i2c->sdata = value;
2001 break;
2002 case 0x04:
2003 i2c->lmadr = value;
2004 break;
2005 case 0x05:
2006 i2c->hmadr = value;
2007 break;
2008 case 0x06:
2009 i2c->cntl = value;
2010 break;
2011 case 0x07:
2012 i2c->mdcntl = value & 0xDF;
2013 break;
2014 case 0x08:
2015 i2c->sts &= ~(value & 0x0A);
2016 break;
2017 case 0x09:
2018 i2c->extsts &= ~(value & 0x8F);
2019 break;
2020 case 0x0A:
2021 i2c->lsadr = value;
2022 break;
2023 case 0x0B:
2024 i2c->hsadr = value;
2025 break;
2026 case 0x0C:
2027 i2c->clkdiv = value;
2028 break;
2029 case 0x0D:
2030 i2c->intrmsk = value;
2031 break;
2032 case 0x0E:
2033 i2c->xfrcnt = value & 0x77;
2034 break;
2035 case 0x0F:
2036 i2c->xtcntlss = value;
2037 break;
2038 case 0x10:
2039 i2c->directcntl = value & 0x7;
2040 break;
2041 }
2042 }
2043
2044 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
2045 {
2046 uint32_t ret;
2047
2048 #ifdef DEBUG_I2C
2049 printf("%s: addr " PADDRX "\n", __func__, addr);
2050 #endif
2051 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
2052 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
2053
2054 return ret;
2055 }
2056
2057 static void ppc4xx_i2c_writew (void *opaque,
2058 target_phys_addr_t addr, uint32_t value)
2059 {
2060 #ifdef DEBUG_I2C
2061 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2062 #endif
2063 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
2064 ppc4xx_i2c_writeb(opaque, addr + 1, value);
2065 }
2066
2067 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
2068 {
2069 uint32_t ret;
2070
2071 #ifdef DEBUG_I2C
2072 printf("%s: addr " PADDRX "\n", __func__, addr);
2073 #endif
2074 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
2075 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
2076 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
2077 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
2078
2079 return ret;
2080 }
2081
2082 static void ppc4xx_i2c_writel (void *opaque,
2083 target_phys_addr_t addr, uint32_t value)
2084 {
2085 #ifdef DEBUG_I2C
2086 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2087 #endif
2088 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
2089 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
2090 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
2091 ppc4xx_i2c_writeb(opaque, addr + 3, value);
2092 }
2093
2094 static CPUReadMemoryFunc *i2c_read[] = {
2095 &ppc4xx_i2c_readb,
2096 &ppc4xx_i2c_readw,
2097 &ppc4xx_i2c_readl,
2098 };
2099
2100 static CPUWriteMemoryFunc *i2c_write[] = {
2101 &ppc4xx_i2c_writeb,
2102 &ppc4xx_i2c_writew,
2103 &ppc4xx_i2c_writel,
2104 };
2105
2106 static void ppc4xx_i2c_reset (void *opaque)
2107 {
2108 ppc4xx_i2c_t *i2c;
2109
2110 i2c = opaque;
2111 i2c->mdata = 0x00;
2112 i2c->sdata = 0x00;
2113 i2c->cntl = 0x00;
2114 i2c->mdcntl = 0x00;
2115 i2c->sts = 0x00;
2116 i2c->extsts = 0x00;
2117 i2c->clkdiv = 0x00;
2118 i2c->xfrcnt = 0x00;
2119 i2c->directcntl = 0x0F;
2120 }
2121
2122 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
2123 target_phys_addr_t offset, qemu_irq irq)
2124 {
2125 ppc4xx_i2c_t *i2c;
2126
2127 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
2128 if (i2c != NULL) {
2129 i2c->base = offset;
2130 i2c->irq = irq;
2131 ppc4xx_i2c_reset(i2c);
2132 #ifdef DEBUG_I2C
2133 printf("%s: offset=" PADDRX "\n", __func__, offset);
2134 #endif
2135 ppc4xx_mmio_register(env, mmio, offset, 0x011,
2136 i2c_read, i2c_write, i2c);
2137 qemu_register_reset(ppc4xx_i2c_reset, i2c);
2138 }
2139 }
2140
2141 /*****************************************************************************/
2142 /* General purpose timers */
2143 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
2144 struct ppc4xx_gpt_t {
2145 target_phys_addr_t base;
2146 int64_t tb_offset;
2147 uint32_t tb_freq;
2148 struct QEMUTimer *timer;
2149 qemu_irq irqs[5];
2150 uint32_t oe;
2151 uint32_t ol;
2152 uint32_t im;
2153 uint32_t is;
2154 uint32_t ie;
2155 uint32_t comp[5];
2156 uint32_t mask[5];
2157 };
2158
2159 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
2160 {
2161 #ifdef DEBUG_GPT
2162 printf("%s: addr " PADDRX "\n", __func__, addr);
2163 #endif
2164 /* XXX: generate a bus fault */
2165 return -1;
2166 }
2167
2168 static void ppc4xx_gpt_writeb (void *opaque,
2169 target_phys_addr_t addr, uint32_t value)
2170 {
2171 #ifdef DEBUG_I2C
2172 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2173 #endif
2174 /* XXX: generate a bus fault */
2175 }
2176
2177 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
2178 {
2179 #ifdef DEBUG_GPT
2180 printf("%s: addr " PADDRX "\n", __func__, addr);
2181 #endif
2182 /* XXX: generate a bus fault */
2183 return -1;
2184 }
2185
2186 static void ppc4xx_gpt_writew (void *opaque,
2187 target_phys_addr_t addr, uint32_t value)
2188 {
2189 #ifdef DEBUG_I2C
2190 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2191 #endif
2192 /* XXX: generate a bus fault */
2193 }
2194
2195 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
2196 {
2197 /* XXX: TODO */
2198 return 0;
2199 }
2200
2201 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
2202 {
2203 /* XXX: TODO */
2204 }
2205
2206 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
2207 {
2208 uint32_t mask;
2209 int i;
2210
2211 mask = 0x80000000;
2212 for (i = 0; i < 5; i++) {
2213 if (gpt->oe & mask) {
2214 /* Output is enabled */
2215 if (ppc4xx_gpt_compare(gpt, i)) {
2216 /* Comparison is OK */
2217 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
2218 } else {
2219 /* Comparison is KO */
2220 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
2221 }
2222 }
2223 mask = mask >> 1;
2224 }
2225 }
2226
2227 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
2228 {
2229 uint32_t mask;
2230 int i;
2231
2232 mask = 0x00008000;
2233 for (i = 0; i < 5; i++) {
2234 if (gpt->is & gpt->im & mask)
2235 qemu_irq_raise(gpt->irqs[i]);
2236 else
2237 qemu_irq_lower(gpt->irqs[i]);
2238 mask = mask >> 1;
2239 }
2240 }
2241
2242 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
2243 {
2244 /* XXX: TODO */
2245 }
2246
2247 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
2248 {
2249 ppc4xx_gpt_t *gpt;
2250 uint32_t ret;
2251 int idx;
2252
2253 #ifdef DEBUG_GPT
2254 printf("%s: addr " PADDRX "\n", __func__, addr);
2255 #endif
2256 gpt = opaque;
2257 switch (addr - gpt->base) {
2258 case 0x00:
2259 /* Time base counter */
2260 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
2261 gpt->tb_freq, ticks_per_sec);
2262 break;
2263 case 0x10:
2264 /* Output enable */
2265 ret = gpt->oe;
2266 break;
2267 case 0x14:
2268 /* Output level */
2269 ret = gpt->ol;
2270 break;
2271 case 0x18:
2272 /* Interrupt mask */
2273 ret = gpt->im;
2274 break;
2275 case 0x1C:
2276 case 0x20:
2277 /* Interrupt status */
2278 ret = gpt->is;
2279 break;
2280 case 0x24:
2281 /* Interrupt enable */
2282 ret = gpt->ie;
2283 break;
2284 case 0x80 ... 0x90:
2285 /* Compare timer */
2286 idx = ((addr - gpt->base) - 0x80) >> 2;
2287 ret = gpt->comp[idx];
2288 break;
2289 case 0xC0 ... 0xD0:
2290 /* Compare mask */
2291 idx = ((addr - gpt->base) - 0xC0) >> 2;
2292 ret = gpt->mask[idx];
2293 break;
2294 default:
2295 ret = -1;
2296 break;
2297 }
2298
2299 return ret;
2300 }
2301
2302 static void ppc4xx_gpt_writel (void *opaque,
2303 target_phys_addr_t addr, uint32_t value)
2304 {
2305 ppc4xx_gpt_t *gpt;
2306 int idx;
2307
2308 #ifdef DEBUG_I2C
2309 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2310 #endif
2311 gpt = opaque;
2312 switch (addr - gpt->base) {
2313 case 0x00:
2314 /* Time base counter */
2315 gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
2316 - qemu_get_clock(vm_clock);
2317 ppc4xx_gpt_compute_timer(gpt);
2318 break;
2319 case 0x10:
2320 /* Output enable */
2321 gpt->oe = value & 0xF8000000;
2322 ppc4xx_gpt_set_outputs(gpt);
2323 break;
2324 case 0x14:
2325 /* Output level */
2326 gpt->ol = value & 0xF8000000;
2327 ppc4xx_gpt_set_outputs(gpt);
2328 break;
2329 case 0x18:
2330 /* Interrupt mask */
2331 gpt->im = value & 0x0000F800;
2332 break;
2333 case 0x1C:
2334 /* Interrupt status set */
2335 gpt->is |= value & 0x0000F800;
2336 ppc4xx_gpt_set_irqs(gpt);
2337 break;
2338 case 0x20:
2339 /* Interrupt status clear */
2340 gpt->is &= ~(value & 0x0000F800);
2341 ppc4xx_gpt_set_irqs(gpt);
2342 break;
2343 case 0x24:
2344 /* Interrupt enable */
2345 gpt->ie = value & 0x0000F800;
2346 ppc4xx_gpt_set_irqs(gpt);
2347 break;
2348 case 0x80 ... 0x90:
2349 /* Compare timer */
2350 idx = ((addr - gpt->base) - 0x80) >> 2;
2351 gpt->comp[idx] = value & 0xF8000000;
2352 ppc4xx_gpt_compute_timer(gpt);
2353 break;
2354 case 0xC0 ... 0xD0:
2355 /* Compare mask */
2356 idx = ((addr - gpt->base) - 0xC0) >> 2;
2357 gpt->mask[idx] = value & 0xF8000000;
2358 ppc4xx_gpt_compute_timer(gpt);
2359 break;
2360 }
2361 }
2362
2363 static CPUReadMemoryFunc *gpt_read[] = {
2364 &ppc4xx_gpt_readb,
2365 &ppc4xx_gpt_readw,
2366 &ppc4xx_gpt_readl,
2367 };
2368
2369 static CPUWriteMemoryFunc *gpt_write[] = {
2370 &ppc4xx_gpt_writeb,
2371 &ppc4xx_gpt_writew,
2372 &ppc4xx_gpt_writel,
2373 };
2374
2375 static void ppc4xx_gpt_cb (void *opaque)
2376 {
2377 ppc4xx_gpt_t *gpt;
2378
2379 gpt = opaque;
2380 ppc4xx_gpt_set_irqs(gpt);
2381 ppc4xx_gpt_set_outputs(gpt);
2382 ppc4xx_gpt_compute_timer(gpt);
2383 }
2384
2385 static void ppc4xx_gpt_reset (void *opaque)
2386 {
2387 ppc4xx_gpt_t *gpt;
2388 int i;
2389
2390 gpt = opaque;
2391 qemu_del_timer(gpt->timer);
2392 gpt->oe = 0x00000000;
2393 gpt->ol = 0x00000000;
2394 gpt->im = 0x00000000;
2395 gpt->is = 0x00000000;
2396 gpt->ie = 0x00000000;
2397 for (i = 0; i < 5; i++) {
2398 gpt->comp[i] = 0x00000000;
2399 gpt->mask[i] = 0x00000000;
2400 }
2401 }
2402
2403 void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
2404 target_phys_addr_t offset, qemu_irq irqs[5])
2405 {
2406 ppc4xx_gpt_t *gpt;
2407 int i;
2408
2409 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
2410 if (gpt != NULL) {
2411 gpt->base = offset;
2412 for (i = 0; i < 5; i++)
2413 gpt->irqs[i] = irqs[i];
2414 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
2415 ppc4xx_gpt_reset(gpt);
2416 #ifdef DEBUG_GPT
2417 printf("%s: offset=" PADDRX "\n", __func__, offset);
2418 #endif
2419 ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
2420 gpt_read, gpt_write, gpt);
2421 qemu_register_reset(ppc4xx_gpt_reset, gpt);
2422 }
2423 }
2424
2425 /*****************************************************************************/
2426 /* MAL */
2427 enum {
2428 MAL0_CFG = 0x180,
2429 MAL0_ESR = 0x181,
2430 MAL0_IER = 0x182,
2431 MAL0_TXCASR = 0x184,
2432 MAL0_TXCARR = 0x185,
2433 MAL0_TXEOBISR = 0x186,
2434 MAL0_TXDEIR = 0x187,
2435 MAL0_RXCASR = 0x190,
2436 MAL0_RXCARR = 0x191,
2437 MAL0_RXEOBISR = 0x192,
2438 MAL0_RXDEIR = 0x193,
2439 MAL0_TXCTP0R = 0x1A0,
2440 MAL0_TXCTP1R = 0x1A1,
2441 MAL0_TXCTP2R = 0x1A2,
2442 MAL0_TXCTP3R = 0x1A3,
2443 MAL0_RXCTP0R = 0x1C0,
2444 MAL0_RXCTP1R = 0x1C1,
2445 MAL0_RCBS0 = 0x1E0,
2446 MAL0_RCBS1 = 0x1E1,
2447 };
2448
2449 typedef struct ppc40x_mal_t ppc40x_mal_t;
2450 struct ppc40x_mal_t {
2451 qemu_irq irqs[4];
2452 uint32_t cfg;
2453 uint32_t esr;
2454 uint32_t ier;
2455 uint32_t txcasr;
2456 uint32_t txcarr;
2457 uint32_t txeobisr;
2458 uint32_t txdeir;
2459 uint32_t rxcasr;
2460 uint32_t rxcarr;
2461 uint32_t rxeobisr;
2462 uint32_t rxdeir;
2463 uint32_t txctpr[4];
2464 uint32_t rxctpr[2];
2465 uint32_t rcbs[2];
2466 };
2467
2468 static void ppc40x_mal_reset (void *opaque);
2469
2470 static target_ulong dcr_read_mal (void *opaque, int dcrn)
2471 {
2472 ppc40x_mal_t *mal;
2473 target_ulong ret;
2474
2475 mal = opaque;
2476 switch (dcrn) {
2477 case MAL0_CFG:
2478 ret = mal->cfg;
2479 break;
2480 case MAL0_ESR:
2481 ret = mal->esr;
2482 break;
2483 case MAL0_IER:
2484 ret = mal->ier;
2485 break;
2486 case MAL0_TXCASR:
2487 ret = mal->txcasr;
2488 break;
2489 case MAL0_TXCARR:
2490 ret = mal->txcarr;
2491 break;
2492 case MAL0_TXEOBISR:
2493 ret = mal->txeobisr;
2494 break;
2495 case MAL0_TXDEIR:
2496 ret = mal->txdeir;
2497 break;
2498 case MAL0_RXCASR:
2499 ret = mal->rxcasr;
2500 break;
2501 case MAL0_RXCARR:
2502 ret = mal->rxcarr;
2503 break;
2504 case MAL0_RXEOBISR:
2505 ret = mal->rxeobisr;
2506 break;
2507 case MAL0_RXDEIR:
2508 ret = mal->rxdeir;
2509 break;
2510 case MAL0_TXCTP0R:
2511 ret = mal->txctpr[0];
2512 break;
2513 case MAL0_TXCTP1R:
2514 ret = mal->txctpr[1];
2515 break;
2516 case MAL0_TXCTP2R:
2517 ret = mal->txctpr[2];
2518 break;
2519 case MAL0_TXCTP3R:
2520 ret = mal->txctpr[3];
2521 break;
2522 case MAL0_RXCTP0R:
2523 ret = mal->rxctpr[0];
2524 break;
2525 case MAL0_RXCTP1R:
2526 ret = mal->rxctpr[1];
2527 break;
2528 case MAL0_RCBS0:
2529 ret = mal->rcbs[0];
2530 break;
2531 case MAL0_RCBS1:
2532 ret = mal->rcbs[1];
2533 break;
2534 default:
2535 ret = 0;
2536 break;
2537 }
2538
2539 return ret;
2540 }
2541
2542 static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
2543 {
2544 ppc40x_mal_t *mal;
2545 int idx;
2546
2547 mal = opaque;
2548 switch (dcrn) {
2549 case MAL0_CFG:
2550 if (val & 0x80000000)
2551 ppc40x_mal_reset(mal);
2552 mal->cfg = val & 0x00FFC087;
2553 break;
2554 case MAL0_ESR:
2555 /* Read/clear */
2556 mal->esr &= ~val;
2557 break;
2558 case MAL0_IER:
2559 mal->ier = val & 0x0000001F;
2560 break;
2561 case MAL0_TXCASR:
2562 mal->txcasr = val & 0xF0000000;
2563 break;
2564 case MAL0_TXCARR:
2565 mal->txcarr = val & 0xF0000000;
2566 break;
2567 case MAL0_TXEOBISR:
2568 /* Read/clear */
2569 mal->txeobisr &= ~val;
2570 break;
2571 case MAL0_TXDEIR:
2572 /* Read/clear */
2573 mal->txdeir &= ~val;
2574 break;
2575 case MAL0_RXCASR:
2576 mal->rxcasr = val & 0xC0000000;
2577 break;
2578 case MAL0_RXCARR:
2579 mal->rxcarr = val & 0xC0000000;
2580 break;
2581 case MAL0_RXEOBISR:
2582 /* Read/clear */
2583 mal->rxeobisr &= ~val;
2584 break;
2585 case MAL0_RXDEIR:
2586 /* Read/clear */
2587 mal->rxdeir &= ~val;
2588 break;
2589 case MAL0_TXCTP0R:
2590 idx = 0;
2591 goto update_tx_ptr;
2592 case MAL0_TXCTP1R:
2593 idx = 1;
2594 goto update_tx_ptr;
2595 case MAL0_TXCTP2R:
2596 idx = 2;
2597 goto update_tx_ptr;
2598 case MAL0_TXCTP3R:
2599 idx = 3;
2600 update_tx_ptr:
2601 mal->txctpr[idx] = val;
2602 break;
2603 case MAL0_RXCTP0R:
2604 idx = 0;
2605 goto update_rx_ptr;
2606 case MAL0_RXCTP1R:
2607 idx = 1;
2608 update_rx_ptr:
2609 mal->rxctpr[idx] = val;
2610 break;
2611 case MAL0_RCBS0:
2612 idx = 0;
2613 goto update_rx_size;
2614 case MAL0_RCBS1:
2615 idx = 1;
2616 update_rx_size:
2617 mal->rcbs[idx] = val & 0x000000FF;
2618 break;
2619 }
2620 }
2621
2622 static void ppc40x_mal_reset (void *opaque)
2623 {
2624 ppc40x_mal_t *mal;
2625
2626 mal = opaque;
2627 mal->cfg = 0x0007C000;
2628 mal->esr = 0x00000000;
2629 mal->ier = 0x00000000;
2630 mal->rxcasr = 0x00000000;
2631 mal->rxdeir = 0x00000000;
2632 mal->rxeobisr = 0x00000000;
2633 mal->txcasr = 0x00000000;
2634 mal->txdeir = 0x00000000;
2635 mal->txeobisr = 0x00000000;
2636 }
2637
2638 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
2639 {
2640 ppc40x_mal_t *mal;
2641 int i;
2642
2643 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
2644 if (mal != NULL) {
2645 for (i = 0; i < 4; i++)
2646 mal->irqs[i] = irqs[i];
2647 ppc40x_mal_reset(mal);
2648 qemu_register_reset(&ppc40x_mal_reset, mal);
2649 ppc_dcr_register(env, MAL0_CFG,
2650 mal, &dcr_read_mal, &dcr_write_mal);
2651 ppc_dcr_register(env, MAL0_ESR,
2652 mal, &dcr_read_mal, &dcr_write_mal);
2653 ppc_dcr_register(env, MAL0_IER,
2654 mal, &dcr_read_mal, &dcr_write_mal);
2655 ppc_dcr_register(env, MAL0_TXCASR,
2656 mal, &dcr_read_mal, &dcr_write_mal);
2657 ppc_dcr_register(env, MAL0_TXCARR,
2658 mal, &dcr_read_mal, &dcr_write_mal);
2659 ppc_dcr_register(env, MAL0_TXEOBISR,
2660 mal, &dcr_read_mal, &dcr_write_mal);
2661 ppc_dcr_register(env, MAL0_TXDEIR,
2662 mal, &dcr_read_mal, &dcr_write_mal);
2663 ppc_dcr_register(env, MAL0_RXCASR,
2664 mal, &dcr_read_mal, &dcr_write_mal);
2665 ppc_dcr_register(env, MAL0_RXCARR,
2666 mal, &dcr_read_mal, &dcr_write_mal);
2667 ppc_dcr_register(env, MAL0_RXEOBISR,
2668 mal, &dcr_read_mal, &dcr_write_mal);
2669 ppc_dcr_register(env, MAL0_RXDEIR,
2670 mal, &dcr_read_mal, &dcr_write_mal);
2671 ppc_dcr_register(env, MAL0_TXCTP0R,
2672 mal, &dcr_read_mal, &dcr_write_mal);
2673 ppc_dcr_register(env, MAL0_TXCTP1R,
2674 mal, &dcr_read_mal, &dcr_write_mal);
2675 ppc_dcr_register(env, MAL0_TXCTP2R,
2676 mal, &dcr_read_mal, &dcr_write_mal);
2677 ppc_dcr_register(env, MAL0_TXCTP3R,
2678 mal, &dcr_read_mal, &dcr_write_mal);
2679 ppc_dcr_register(env, MAL0_RXCTP0R,
2680 mal, &dcr_read_mal, &dcr_write_mal);
2681 ppc_dcr_register(env, MAL0_RXCTP1R,
2682 mal, &dcr_read_mal, &dcr_write_mal);
2683 ppc_dcr_register(env, MAL0_RCBS0,
2684 mal, &dcr_read_mal, &dcr_write_mal);
2685 ppc_dcr_register(env, MAL0_RCBS1,
2686 mal, &dcr_read_mal, &dcr_write_mal);
2687 }
2688 }
2689
2690 /*****************************************************************************/
2691 /* SPR */
2692 void ppc40x_core_reset (CPUState *env)
2693 {
2694 target_ulong dbsr;
2695
2696 printf("Reset PowerPC core\n");
2697 cpu_ppc_reset(env);
2698 dbsr = env->spr[SPR_40x_DBSR];
2699 dbsr &= ~0x00000300;
2700 dbsr |= 0x00000100;
2701 env->spr[SPR_40x_DBSR] = dbsr;
2702 cpu_loop_exit();
2703 }
2704
2705 void ppc40x_chip_reset (CPUState *env)
2706 {
2707 target_ulong dbsr;
2708
2709 printf("Reset PowerPC chip\n");
2710 cpu_ppc_reset(env);
2711 /* XXX: TODO reset all internal peripherals */
2712 dbsr = env->spr[SPR_40x_DBSR];
2713 dbsr &= ~0x00000300;
2714 dbsr |= 0x00000200;
2715 env->spr[SPR_40x_DBSR] = dbsr;
2716 cpu_loop_exit();
2717 }
2718
2719 void ppc40x_system_reset (CPUState *env)
2720 {
2721 printf("Reset PowerPC system\n");
2722 qemu_system_reset_request();
2723 }
2724
2725 void store_40x_dbcr0 (CPUState *env, uint32_t val)
2726 {
2727 switch ((val >> 28) & 0x3) {
2728 case 0x0:
2729 /* No action */
2730 break;
2731 case 0x1:
2732 /* Core reset */
2733 ppc40x_core_reset(env);
2734 break;
2735 case 0x2:
2736 /* Chip reset */
2737 ppc40x_chip_reset(env);
2738 break;
2739 case 0x3:
2740 /* System reset */
2741 ppc40x_system_reset(env);
2742 break;
2743 }
2744 }
2745
2746 /*****************************************************************************/
2747 /* PowerPC 405CR */
2748 enum {
2749 PPC405CR_CPC0_PLLMR = 0x0B0,
2750 PPC405CR_CPC0_CR0 = 0x0B1,
2751 PPC405CR_CPC0_CR1 = 0x0B2,
2752 PPC405CR_CPC0_PSR = 0x0B4,
2753 PPC405CR_CPC0_JTAGID = 0x0B5,
2754 PPC405CR_CPC0_ER = 0x0B9,
2755 PPC405CR_CPC0_FR = 0x0BA,
2756 PPC405CR_CPC0_SR = 0x0BB,
2757 };
2758
2759 enum {
2760 PPC405CR_CPU_CLK = 0,
2761 PPC405CR_TMR_CLK = 1,
2762 PPC405CR_PLB_CLK = 2,
2763 PPC405CR_SDRAM_CLK = 3,
2764 PPC405CR_OPB_CLK = 4,
2765 PPC405CR_EXT_CLK = 5,
2766 PPC405CR_UART_CLK = 6,
2767 PPC405CR_CLK_NB = 7,
2768 };
2769
2770 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
2771 struct ppc405cr_cpc_t {
2772 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2773 uint32_t sysclk;
2774 uint32_t psr;
2775 uint32_t cr0;
2776 uint32_t cr1;
2777 uint32_t jtagid;
2778 uint32_t pllmr;
2779 uint32_t er;
2780 uint32_t fr;
2781 };
2782
2783 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
2784 {
2785 uint64_t VCO_out, PLL_out;
2786 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
2787 int M, D0, D1, D2;
2788
2789 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
2790 if (cpc->pllmr & 0x80000000) {
2791 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
2792 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
2793 M = D0 * D1 * D2;
2794 VCO_out = cpc->sysclk * M;
2795 if (VCO_out < 400000000 || VCO_out > 800000000) {
2796 /* PLL cannot lock */
2797 cpc->pllmr &= ~0x80000000;
2798 goto bypass_pll;
2799 }
2800 PLL_out = VCO_out / D2;
2801 } else {
2802 /* Bypass PLL */
2803 bypass_pll:
2804 M = D0;
2805 PLL_out = cpc->sysclk * M;
2806 }
2807 CPU_clk = PLL_out;
2808 if (cpc->cr1 & 0x00800000)
2809 TMR_clk = cpc->sysclk; /* Should have a separate clock */
2810 else
2811 TMR_clk = CPU_clk;
2812 PLB_clk = CPU_clk / D0;
2813 SDRAM_clk = PLB_clk;
2814 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
2815 OPB_clk = PLB_clk / D0;
2816 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
2817 EXT_clk = PLB_clk / D0;
2818 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
2819 UART_clk = CPU_clk / D0;
2820 /* Setup CPU clocks */
2821 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
2822 /* Setup time-base clock */
2823 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
2824 /* Setup PLB clock */
2825 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
2826 /* Setup SDRAM clock */
2827 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
2828 /* Setup OPB clock */
2829 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
2830 /* Setup external clock */
2831 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
2832 /* Setup UART clock */
2833 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
2834 }
2835
2836 static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
2837 {
2838 ppc405cr_cpc_t *cpc;
2839 target_ulong ret;
2840
2841 cpc = opaque;
2842 switch (dcrn) {
2843 case PPC405CR_CPC0_PLLMR:
2844 ret = cpc->pllmr;
2845 break;
2846 case PPC405CR_CPC0_CR0:
2847 ret = cpc->cr0;
2848 break;
2849 case PPC405CR_CPC0_CR1:
2850 ret = cpc->cr1;
2851 break;
2852 case PPC405CR_CPC0_PSR:
2853 ret = cpc->psr;
2854 break;
2855 case PPC405CR_CPC0_JTAGID:
2856 ret = cpc->jtagid;
2857 break;
2858 case PPC405CR_CPC0_ER:
2859 ret = cpc->er;
2860 break;
2861 case PPC405CR_CPC0_FR:
2862 ret = cpc->fr;
2863 break;
2864 case PPC405CR_CPC0_SR:
2865 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
2866 break;
2867 default:
2868 /* Avoid gcc warning */
2869 ret = 0;
2870 break;
2871 }
2872
2873 return ret;
2874 }
2875
2876 static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
2877 {
2878 ppc405cr_cpc_t *cpc;
2879
2880 cpc = opaque;
2881 switch (dcrn) {
2882 case PPC405CR_CPC0_PLLMR:
2883 cpc->pllmr = val & 0xFFF77C3F;
2884 break;
2885 case PPC405CR_CPC0_CR0:
2886 cpc->cr0 = val & 0x0FFFFFFE;
2887 break;
2888 case PPC405CR_CPC0_CR1:
2889 cpc->cr1 = val & 0x00800000;
2890 break;
2891 case PPC405CR_CPC0_PSR:
2892 /* Read-only */
2893 break;
2894 case PPC405CR_CPC0_JTAGID:
2895 /* Read-only */
2896 break;
2897 case PPC405CR_CPC0_ER:
2898 cpc->er = val & 0xBFFC0000;
2899 break;
2900 case PPC405CR_CPC0_FR:
2901 cpc->fr = val & 0xBFFC0000;
2902 break;
2903 case PPC405CR_CPC0_SR:
2904 /* Read-only */
2905 break;
2906 }
2907 }
2908
2909 static void ppc405cr_cpc_reset (void *opaque)
2910 {
2911 ppc405cr_cpc_t *cpc;
2912 int D;
2913
2914 cpc = opaque;
2915 /* Compute PLLMR value from PSR settings */
2916 cpc->pllmr = 0x80000000;
2917 /* PFWD */
2918 switch ((cpc->psr >> 30) & 3) {
2919 case 0:
2920 /* Bypass */
2921 cpc->pllmr &= ~0x80000000;
2922 break;
2923 case 1:
2924 /* Divide by 3 */
2925 cpc->pllmr |= 5 << 16;
2926 break;
2927 case 2:
2928 /* Divide by 4 */
2929 cpc->pllmr |= 4 << 16;
2930 break;
2931 case 3:
2932 /* Divide by 6 */
2933 cpc->pllmr |= 2 << 16;
2934 break;
2935 }
2936 /* PFBD */
2937 D = (cpc->psr >> 28) & 3;
2938 cpc->pllmr |= (D + 1) << 20;
2939 /* PT */
2940 D = (cpc->psr >> 25) & 7;
2941 switch (D) {
2942 case 0x2:
2943 cpc->pllmr |= 0x13;
2944 break;
2945 case 0x4:
2946 cpc->pllmr |= 0x15;
2947 break;
2948 case 0x5:
2949 cpc->pllmr |= 0x16;
2950 break;
2951 default:
2952 break;
2953 }
2954 /* PDC */
2955 D = (cpc->psr >> 23) & 3;
2956 cpc->pllmr |= D << 26;
2957 /* ODP */
2958 D = (cpc->psr >> 21) & 3;
2959 cpc->pllmr |= D << 10;
2960 /* EBPD */
2961 D = (cpc->psr >> 17) & 3;
2962 cpc->pllmr |= D << 24;
2963 cpc->cr0 = 0x0000003C;
2964 cpc->cr1 = 0x2B0D8800;
2965 cpc->er = 0x00000000;
2966 cpc->fr = 0x00000000;
2967 ppc405cr_clk_setup(cpc);
2968 }
2969
2970 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2971 {
2972 int D;
2973
2974 /* XXX: this should be read from IO pins */
2975 cpc->psr = 0x00000000; /* 8 bits ROM */
2976 /* PFWD */
2977 D = 0x2; /* Divide by 4 */
2978 cpc->psr |= D << 30;
2979 /* PFBD */
2980 D = 0x1; /* Divide by 2 */
2981 cpc->psr |= D << 28;
2982 /* PDC */
2983 D = 0x1; /* Divide by 2 */
2984 cpc->psr |= D << 23;
2985 /* PT */
2986 D = 0x5; /* M = 16 */
2987 cpc->psr |= D << 25;
2988 /* ODP */
2989 D = 0x1; /* Divide by 2 */
2990 cpc->psr |= D << 21;
2991 /* EBDP */
2992 D = 0x2; /* Divide by 4 */
2993 cpc->psr |= D << 17;
2994 }
2995
2996 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2997 uint32_t sysclk)
2998 {
2999 ppc405cr_cpc_t *cpc;
3000
3001 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
3002 if (cpc != NULL) {
3003 memcpy(cpc->clk_setup, clk_setup,
3004 PPC405CR_CLK_NB * sizeof(clk_setup_t));
3005 cpc->sysclk = sysclk;
3006 cpc->jtagid = 0x42051049;
3007 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
3008 &dcr_read_crcpc, &dcr_write_crcpc);
3009 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
3010 &dcr_read_crcpc, &dcr_write_crcpc);
3011 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
3012 &dcr_read_crcpc, &dcr_write_crcpc);
3013 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
3014 &dcr_read_crcpc, &dcr_write_crcpc);
3015 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
3016 &dcr_read_crcpc, &dcr_write_crcpc);
3017 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
3018 &dcr_read_crcpc, &dcr_write_crcpc);
3019 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
3020 &dcr_read_crcpc, &dcr_write_crcpc);
3021 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
3022 &dcr_read_crcpc, &dcr_write_crcpc);
3023 ppc405cr_clk_init(cpc);
3024 qemu_register_reset(ppc405cr_cpc_reset, cpc);
3025 ppc405cr_cpc_reset(cpc);
3026 }
3027 }
3028
3029 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
3030 target_phys_addr_t ram_sizes[4],
3031 uint32_t sysclk, qemu_irq **picp,
3032 ram_addr_t *offsetp, int do_init)
3033 {
3034 clk_setup_t clk_setup[PPC405CR_CLK_NB];
3035 qemu_irq dma_irqs[4];
3036 CPUState *env;
3037 ppc4xx_mmio_t *mmio;
3038 qemu_irq *pic, *irqs;
3039 ram_addr_t offset;
3040 int i;
3041
3042 memset(clk_setup, 0, sizeof(clk_setup));
3043 env = ppc405_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
3044 &clk_setup[PPC405CR_TMR_CLK], sysclk);
3045 /* Memory mapped devices registers */
3046 mmio = ppc4xx_mmio_init(env, 0xEF600000);
3047 /* PLB arbitrer */
3048 ppc4xx_plb_init(env);
3049 /* PLB to OPB bridge */
3050 ppc4xx_pob_init(env);
3051 /* OBP arbitrer */
3052 ppc4xx_opba_init(env, mmio, 0x600);
3053 /* Universal interrupt controller */
3054 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
3055 irqs[PPCUIC_OUTPUT_INT] =
3056 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
3057 irqs[PPCUIC_OUTPUT_CINT] =
3058 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
3059 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
3060 *picp = pic;
3061 /* SDRAM controller */
3062 ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
3063 offset = 0;
3064 for (i = 0; i < 4; i++)
3065 offset += ram_sizes[i];
3066 /* External bus controller */
3067 ppc405_ebc_init(env);
3068 /* DMA controller */
3069 dma_irqs[0] = pic[26];
3070 dma_irqs[1] = pic[25];
3071 dma_irqs[2] = pic[24];
3072 dma_irqs[3] = pic[23];
3073 ppc405_dma_init(env, dma_irqs);
3074 /* Serial ports */
3075 if (serial_hds[0] != NULL) {
3076 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
3077 }
3078 if (serial_hds[1] != NULL) {
3079 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
3080 }
3081 /* IIC controller */
3082 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
3083 /* GPIO */
3084 ppc405_gpio_init(env, mmio, 0x700);
3085 /* CPU control */
3086 ppc405cr_cpc_init(env, clk_setup, sysclk);
3087 *offsetp = offset;
3088
3089 return env;
3090 }
3091
3092 /*****************************************************************************/
3093 /* PowerPC 405EP */
3094 /* CPU control */
3095 enum {
3096 PPC405EP_CPC0_PLLMR0 = 0x0F0,
3097 PPC405EP_CPC0_BOOT = 0x0F1,
3098 PPC405EP_CPC0_EPCTL = 0x0F3,
3099 PPC405EP_CPC0_PLLMR1 = 0x0F4,
3100 PPC405EP_CPC0_UCR = 0x0F5,
3101 PPC405EP_CPC0_SRR = 0x0F6,
3102 PPC405EP_CPC0_JTAGID = 0x0F7,
3103 PPC405EP_CPC0_PCI = 0x0F9,
3104 #if 0
3105 PPC405EP_CPC0_ER = xxx,
3106 PPC405EP_CPC0_FR = xxx,
3107 PPC405EP_CPC0_SR = xxx,
3108 #endif
3109 };
3110
3111 enum {
3112 PPC405EP_CPU_CLK = 0,
3113 PPC405EP_PLB_CLK = 1,
3114 PPC405EP_OPB_CLK = 2,
3115 PPC405EP_EBC_CLK = 3,
3116 PPC405EP_MAL_CLK = 4,
3117 PPC405EP_PCI_CLK = 5,
3118 PPC405EP_UART0_CLK = 6,
3119 PPC405EP_UART1_CLK = 7,
3120 PPC405EP_CLK_NB = 8,
3121 };
3122
3123 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
3124 struct ppc405ep_cpc_t {
3125 uint32_t sysclk;
3126 clk_setup_t clk_setup[PPC405EP_CLK_NB];
3127 uint32_t boot;
3128 uint32_t epctl;
3129 uint32_t pllmr[2];
3130 uint32_t ucr;
3131 uint32_t srr;
3132 uint32_t jtagid;
3133 uint32_t pci;
3134 /* Clock and power management */
3135 uint32_t er;
3136 uint32_t fr;
3137 uint32_t sr;
3138 };
3139
3140 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
3141 {
3142 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
3143 uint32_t UART0_clk, UART1_clk;
3144 uint64_t VCO_out, PLL_out;
3145 int M, D;
3146
3147 VCO_out = 0;
3148 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
3149 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
3150 // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
3151 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
3152 // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
3153 VCO_out = cpc->sysclk * M * D;
3154 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
3155 /* Error - unlock the PLL */
3156 printf("VCO out of range %" PRIu64 "\n", VCO_out);
3157 #if 0
3158 cpc->pllmr[1] &= ~0x80000000;
3159 goto pll_bypass;
3160 #endif
3161 }
3162 PLL_out = VCO_out / D;
3163 /* Pretend the PLL is locked */
3164 cpc->boot |= 0x00000001;
3165 } else {
3166 #if 0
3167 pll_bypass:
3168 #endif
3169 PLL_out = cpc->sysclk;
3170 if (cpc->pllmr[1] & 0x40000000) {
3171 /* Pretend the PLL is not locked */
3172 cpc->boot &= ~0x00000001;
3173 }
3174 }
3175 /* Now, compute all other clocks */
3176 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
3177 #ifdef DEBUG_CLOCKS
3178 // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
3179 #endif
3180 CPU_clk = PLL_out / D;
3181 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
3182 #ifdef DEBUG_CLOCKS
3183 // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
3184 #endif
3185 PLB_clk = CPU_clk / D;
3186 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
3187 #ifdef DEBUG_CLOCKS
3188 // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
3189 #endif
3190 OPB_clk = PLB_clk / D;
3191 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
3192 #ifdef DEBUG_CLOCKS
3193 // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
3194 #endif
3195 EBC_clk = PLB_clk / D;
3196 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
3197 #ifdef DEBUG_CLOCKS
3198 // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
3199 #endif
3200 MAL_clk = PLB_clk / D;
3201 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
3202 #ifdef DEBUG_CLOCKS
3203 // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
3204 #endif
3205 PCI_clk = PLB_clk / D;
3206 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
3207 #ifdef DEBUG_CLOCKS
3208 // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
3209 #endif
3210 UART0_clk = PLL_out / D;
3211 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
3212 #ifdef DEBUG_CLOCKS
3213 // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
3214 #endif
3215 UART1_clk = PLL_out / D;
3216 #ifdef DEBUG_CLOCKS
3217 printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
3218 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
3219 printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
3220 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
3221 UART0_clk, UART1_clk);
3222 printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb,
3223 cpc->clk_setup[PPC405EP_CPU_CLK].opaque);
3224 #endif
3225 /* Setup CPU clocks */
3226 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
3227 /* Setup PLB clock */
3228 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
3229 /* Setup OPB clock */
3230 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
3231 /* Setup external clock */
3232 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
3233 /* Setup MAL clock */
3234 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
3235 /* Setup PCI clock */
3236 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
3237 /* Setup UART0 clock */
3238 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
3239 /* Setup UART1 clock */
3240 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
3241 }
3242
3243 static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
3244 {
3245 ppc405ep_cpc_t *cpc;
3246 target_ulong ret;
3247
3248 cpc = opaque;
3249 switch (dcrn) {
3250 case PPC405EP_CPC0_BOOT:
3251 ret = cpc->boot;
3252 break;
3253 case PPC405EP_CPC0_EPCTL:
3254 ret = cpc->epctl;
3255 break;
3256 case PPC405EP_CPC0_PLLMR0:
3257 ret = cpc->pllmr[0];
3258 break;
3259 case PPC405EP_CPC0_PLLMR1:
3260 ret = cpc->pllmr[1];
3261 break;
3262 case PPC405EP_CPC0_UCR:
3263 ret = cpc->ucr;
3264 break;
3265 case PPC405EP_CPC0_SRR:
3266 ret = cpc->srr;
3267 break;
3268 case PPC405EP_CPC0_JTAGID:
3269 ret = cpc->jtagid;
3270 break;
3271 case PPC405EP_CPC0_PCI:
3272 ret = cpc->pci;
3273 break;
3274 default:
3275 /* Avoid gcc warning */
3276 ret = 0;
3277 break;
3278 }
3279
3280 return ret;
3281 }
3282
3283 static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
3284 {
3285 ppc405ep_cpc_t *cpc;
3286
3287 cpc = opaque;
3288 switch (dcrn) {
3289 case PPC405EP_CPC0_BOOT:
3290 /* Read-only register */
3291 break;
3292 case PPC405EP_CPC0_EPCTL:
3293 /* Don't care for now */
3294 cpc->epctl = val & 0xC00000F3;
3295 break;
3296 case PPC405EP_CPC0_PLLMR0:
3297 cpc->pllmr[0] = val & 0x00633333;
3298 ppc405ep_compute_clocks(cpc);
3299 break;
3300 case PPC405EP_CPC0_PLLMR1:
3301 cpc->pllmr[1] = val & 0xC0F73FFF;
3302 ppc405ep_compute_clocks(cpc);
3303 break;
3304 case PPC405EP_CPC0_UCR:
3305 /* UART control - don't care for now */
3306 cpc->ucr = val & 0x003F7F7F;
3307 break;
3308 case PPC405EP_CPC0_SRR:
3309 cpc->srr = val;
3310 break;
3311 case PPC405EP_CPC0_JTAGID:
3312 /* Read-only */
3313 break;
3314 case PPC405EP_CPC0_PCI:
3315 cpc->pci = val;
3316 break;
3317 }
3318 }
3319
3320 static void ppc405ep_cpc_reset (void *opaque)
3321 {
3322 ppc405ep_cpc_t *cpc = opaque;
3323
3324 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
3325 cpc->epctl = 0x00000000;
3326 cpc->pllmr[0] = 0x00011010;
3327 cpc->pllmr[1] = 0x40000000;
3328 cpc->ucr = 0x00000000;
3329 cpc->srr = 0x00040000;
3330 cpc->pci = 0x00000000;
3331 cpc->er = 0x00000000;
3332 cpc->fr = 0x00000000;
3333 cpc->sr = 0x00000000;
3334 ppc405ep_compute_clocks(cpc);
3335 }
3336
3337 /* XXX: sysclk should be between 25 and 100 MHz */
3338 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
3339 uint32_t sysclk)
3340 {
3341 ppc405ep_cpc_t *cpc;
3342
3343 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
3344 if (cpc != NULL) {
3345 memcpy(cpc->clk_setup, clk_setup,
3346 PPC405EP_CLK_NB * sizeof(clk_setup_t));
3347 cpc->jtagid = 0x20267049;
3348 cpc->sysclk = sysclk;
3349 ppc405ep_cpc_reset(cpc);
3350 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
3351 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
3352 &dcr_read_epcpc, &dcr_write_epcpc);
3353 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
3354 &dcr_read_epcpc, &dcr_write_epcpc);
3355 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
3356 &dcr_read_epcpc, &dcr_write_epcpc);
3357 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
3358 &dcr_read_epcpc, &dcr_write_epcpc);
3359 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
3360 &dcr_read_epcpc, &dcr_write_epcpc);
3361 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
3362 &dcr_read_epcpc, &dcr_write_epcpc);
3363 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
3364 &dcr_read_epcpc, &dcr_write_epcpc);
3365 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
3366 &dcr_read_epcpc, &dcr_write_epcpc);
3367 #if 0
3368 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
3369 &dcr_read_epcpc, &dcr_write_epcpc);
3370 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
3371 &dcr_read_epcpc, &dcr_write_epcpc);
3372 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
3373 &dcr_read_epcpc, &dcr_write_epcpc);
3374 #endif
3375 }
3376 }
3377
3378 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
3379 target_phys_addr_t ram_sizes[2],
3380 uint32_t sysclk, qemu_irq **picp,
3381 ram_addr_t *offsetp, int do_init)
3382 {
3383 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
3384 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
3385 CPUState *env;
3386 ppc4xx_mmio_t *mmio;
3387 qemu_irq *pic, *irqs;
3388 ram_addr_t offset;
3389 int i;
3390
3391 memset(clk_setup, 0, sizeof(clk_setup));
3392 /* init CPUs */
3393 env = ppc405_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
3394 &tlb_clk_setup, sysclk);
3395 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
3396 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
3397 /* Internal devices init */
3398 /* Memory mapped devices registers */
3399 mmio = ppc4xx_mmio_init(env, 0xEF600000);
3400 /* PLB arbitrer */
3401 ppc4xx_plb_init(env);
3402 /* PLB to OPB bridge */
3403 ppc4xx_pob_init(env);
3404 /* OBP arbitrer */
3405 ppc4xx_opba_init(env, mmio, 0x600);
3406 /* Universal interrupt controller */
3407 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
3408 irqs[PPCUIC_OUTPUT_INT] =
3409 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
3410 irqs[PPCUIC_OUTPUT_CINT] =
3411 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
3412 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
3413 *picp = pic;
3414 /* SDRAM controller */
3415 ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
3416 offset = 0;
3417 for (i = 0; i < 2; i++)
3418 offset += ram_sizes[i];
3419 /* External bus controller */
3420 ppc405_ebc_init(env);
3421 /* DMA controller */
3422 dma_irqs[0] = pic[26];
3423 dma_irqs[1] = pic[25];
3424 dma_irqs[2] = pic[24];
3425 dma_irqs[3] = pic[23];
3426 ppc405_dma_init(env, dma_irqs);
3427 /* IIC controller */
3428 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
3429 /* GPIO */
3430 ppc405_gpio_init(env, mmio, 0x700);
3431 /* Serial ports */
3432 if (serial_hds[0] != NULL) {
3433 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
3434 }
3435 if (serial_hds[1] != NULL) {
3436 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
3437 }
3438 /* OCM */
3439 ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
3440 offset += 4096;
3441 /* GPT */
3442 gpt_irqs[0] = pic[12];
3443 gpt_irqs[1] = pic[11];
3444 gpt_irqs[2] = pic[10];
3445 gpt_irqs[3] = pic[9];
3446 gpt_irqs[4] = pic[8];
3447 ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
3448 /* PCI */
3449 /* Uses pic[28], pic[15], pic[13] */
3450 /* MAL */
3451 mal_irqs[0] = pic[20];
3452 mal_irqs[1] = pic[19];
3453 mal_irqs[2] = pic[18];
3454 mal_irqs[3] = pic[17];
3455 ppc405_mal_init(env, mal_irqs);
3456 /* Ethernet */
3457 /* Uses pic[22], pic[16], pic[14] */
3458 /* CPU control */
3459 ppc405ep_cpc_init(env, clk_setup, sysclk);
3460 *offsetp = offset;
3461
3462 return env;
3463 }
Stable branch of Qemu 0.9.1