target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "cpu-defs.h"
  24
  25 #define R_EAX 0
  26 #define R_ECX 1
  27 #define R_EDX 2
  28 #define R_EBX 3
  29 #define R_ESP 4
  30 #define R_EBP 5
  31 #define R_ESI 6
  32 #define R_EDI 7
  33
  34 #define R_AL 0
  35 #define R_CL 1
  36 #define R_DL 2
  37 #define R_BL 3
  38 #define R_AH 4
  39 #define R_CH 5
  40 #define R_DH 6
  41 #define R_BH 7
  42
  43 #define R_ES 0
  44 #define R_CS 1
  45 #define R_SS 2
  46 #define R_DS 3
  47 #define R_FS 4
  48 #define R_GS 5
  49
  50 /* segment descriptor fields */
  51 #define DESC_G_MASK     (1 << 23)
  52 #define DESC_B_SHIFT    22
  53 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  54 #define DESC_AVL_MASK   (1 << 20)
  55 #define DESC_P_MASK     (1 << 15)
  56 #define DESC_DPL_SHIFT  13
  57 #define DESC_S_MASK     (1 << 12)
  58 #define DESC_TYPE_SHIFT 8
  59 #define DESC_A_MASK     (1 << 8)
  60
  61 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  62 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  63 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  64
  65 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  66 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  67
  68 #define DESC_TSS_BUSY_MASK (1 << 9)
  69
  70 /* eflags masks */
  71 #define CC_C    0x0001
  72 #define CC_P    0x0004
  73 #define CC_A    0x0010
  74 #define CC_Z    0x0040
  75 #define CC_S    0x0080
  76 #define CC_O    0x0800
  77
  78 #define TF_SHIFT   8
  79 #define IOPL_SHIFT 12
  80 #define VM_SHIFT   17
  81
  82 #define TF_MASK                 0x00000100
  83 #define IF_MASK                 0x00000200
  84 #define DF_MASK                 0x00000400
  85 #define IOPL_MASK               0x00003000
  86 #define NT_MASK                 0x00004000
  87 #define RF_MASK                 0x00010000
  88 #define VM_MASK                 0x00020000
  89 #define AC_MASK                 0x00040000
  90 #define VIF_MASK                0x00080000
  91 #define VIP_MASK                0x00100000
  92 #define ID_MASK                 0x00200000
  93
  94 /* hidden flags - used internally by qemu to represent additionnal cpu
  95    states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
  96    using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
  97    with eflags. */
  98 /* current cpl */
  99 #define HF_CPL_SHIFT         0
 100 /* true if soft mmu is being used */
 101 #define HF_SOFTMMU_SHIFT     2
 102 /* true if hardware interrupts must be disabled for next instruction */
 103 #define HF_INHIBIT_IRQ_SHIFT 3
 104 /* 16 or 32 segments */
 105 #define HF_CS32_SHIFT        4
 106 #define HF_SS32_SHIFT        5
 107 /* zero base for DS, ES and SS */
 108 #define HF_ADDSEG_SHIFT      6
 109
 110 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 111 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 112 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 113 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 114 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 115 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 116
 117 #define CR0_PE_MASK  (1 << 0)
 118 #define CR0_TS_MASK  (1 << 3)
 119 #define CR0_WP_MASK  (1 << 16)
 120 #define CR0_AM_MASK  (1 << 18)
 121 #define CR0_PG_MASK  (1 << 31)
 122
 123 #define CR4_VME_MASK  (1 << 0)
 124 #define CR4_PVI_MASK  (1 << 1)
 125 #define CR4_TSD_MASK  (1 << 2)
 126 #define CR4_DE_MASK   (1 << 3)
 127 #define CR4_PSE_MASK  (1 << 4)
 128
 129 #define PG_PRESENT_BIT  0
 130 #define PG_RW_BIT       1
 131 #define PG_USER_BIT     2
 132 #define PG_PWT_BIT      3
 133 #define PG_PCD_BIT      4
 134 #define PG_ACCESSED_BIT 5
 135 #define PG_DIRTY_BIT    6
 136 #define PG_PSE_BIT      7
 137 #define PG_GLOBAL_BIT   8
 138
 139 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 140 #define PG_RW_MASK       (1 << PG_RW_BIT)
 141 #define PG_USER_MASK     (1 << PG_USER_BIT)
 142 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 143 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 144 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 145 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 146 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 147 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 148
 149 #define PG_ERROR_W_BIT     1
 150
 151 #define PG_ERROR_P_MASK    0x01
 152 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 153 #define PG_ERROR_U_MASK    0x04
 154 #define PG_ERROR_RSVD_MASK 0x08
 155
 156 #define MSR_IA32_APICBASE               0x1b
 157 #define MSR_IA32_APICBASE_BSP           (1<<8)
 158 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 159 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 160
 161 #define MSR_IA32_SYSENTER_CS            0x174
 162 #define MSR_IA32_SYSENTER_ESP           0x175
 163 #define MSR_IA32_SYSENTER_EIP           0x176
 164
 165 #define EXCP00_DIVZ     0
 166 #define EXCP01_SSTP     1
 167 #define EXCP02_NMI      2
 168 #define EXCP03_INT3     3
 169 #define EXCP04_INTO     4
 170 #define EXCP05_BOUND    5
 171 #define EXCP06_ILLOP    6
 172 #define EXCP07_PREX     7
 173 #define EXCP08_DBLE     8
 174 #define EXCP09_XERR     9
 175 #define EXCP0A_TSS      10
 176 #define EXCP0B_NOSEG    11
 177 #define EXCP0C_STACK    12
 178 #define EXCP0D_GPF      13
 179 #define EXCP0E_PAGE     14
 180 #define EXCP10_COPR     16
 181 #define EXCP11_ALGN     17
 182 #define EXCP12_MCHK     18
 183
 184 enum {
 185     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 186     CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
 187
 188     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 189     CC_OP_MULW,
 190     CC_OP_MULL,
 191
 192     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 193     CC_OP_ADDW,
 194     CC_OP_ADDL,
 195
 196     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 197     CC_OP_ADCW,
 198     CC_OP_ADCL,
 199
 200     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 201     CC_OP_SUBW,
 202     CC_OP_SUBL,
 203
 204     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 205     CC_OP_SBBW,
 206     CC_OP_SBBL,
 207
 208     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 209     CC_OP_LOGICW,
 210     CC_OP_LOGICL,
 211
 212     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 213     CC_OP_INCW,
 214     CC_OP_INCL,
 215
 216     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 217     CC_OP_DECW,
 218     CC_OP_DECL,
 219
 220     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 221     CC_OP_SHLW,
 222     CC_OP_SHLL,
 223
 224     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 225     CC_OP_SARW,
 226     CC_OP_SARL,
 227
 228     CC_OP_NB,
 229 };
 230
 231 #ifdef __i386__
 232 #define USE_X86LDOUBLE
 233 #endif
 234
 235 #ifdef USE_X86LDOUBLE
 236 typedef long double CPU86_LDouble;
 237 #else
 238 typedef double CPU86_LDouble;
 239 #endif
 240
 241 typedef struct SegmentCache {
 242     uint32_t selector;
 243     uint8_t *base;
 244     uint32_t limit;
 245     uint32_t flags;
 246 } SegmentCache;
 247
 248 typedef struct CPUX86State {
 249     /* standard registers */
 250     uint32_t regs[8];
 251     uint32_t eip;
 252     uint32_t eflags; /* eflags register. During CPU emulation, CC
 253                         flags and DF are set to zero because they are
 254                         stored elsewhere */
 255
 256     /* emulator internal eflags handling */
 257     uint32_t cc_src;
 258     uint32_t cc_dst;
 259     uint32_t cc_op;
 260     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 261     uint32_t hflags; /* hidden flags, see HF_xxx constants */
 262
 263     /* FPU state */
 264     unsigned int fpstt; /* top of stack index */
 265     unsigned int fpus;
 266     unsigned int fpuc;
 267     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 268     CPU86_LDouble fpregs[8];
 269
 270     /* emulator internal variables */
 271     CPU86_LDouble ft0;
 272     union {
 273         float f;
 274         double d;
 275         int i32;
 276         int64_t i64;
 277     } fp_convert;
 278
 279     /* segments */
 280     SegmentCache segs[6]; /* selector values */
 281     SegmentCache ldt;
 282     SegmentCache tr;
 283     SegmentCache gdt; /* only base and limit are used */
 284     SegmentCache idt; /* only base and limit are used */
 285
 286     /* sysenter registers */
 287     uint32_t sysenter_cs;
 288     uint32_t sysenter_esp;
 289     uint32_t sysenter_eip;
 290
 291     /* exception/interrupt handling */
 292     jmp_buf jmp_env;
 293     int exception_index;
 294     int error_code;
 295     int exception_is_int;
 296     int exception_next_eip;
 297     struct TranslationBlock *current_tb; /* currently executing TB */
 298     uint32_t cr[5]; /* NOTE: cr1 is unused */
 299     uint32_t dr[8]; /* debug registers */
 300     int interrupt_request;
 301     int user_mode_only; /* user mode only simulation */
 302
 303     /* soft mmu support */
 304     /* 0 = kernel, 1 = user */
 305     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
 306     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
 307
 308     /* ice debug support */
 309     uint32_t breakpoints[MAX_BREAKPOINTS];
 310     int nb_breakpoints;
 311     int singlestep_enabled;
 312
 313     /* user data */
 314     void *opaque;
 315 } CPUX86State;
 316
 317 #ifndef IN_OP_I386
 318 void cpu_x86_outb(CPUX86State *env, int addr, int val);
 319 void cpu_x86_outw(CPUX86State *env, int addr, int val);
 320 void cpu_x86_outl(CPUX86State *env, int addr, int val);
 321 int cpu_x86_inb(CPUX86State *env, int addr);
 322 int cpu_x86_inw(CPUX86State *env, int addr);
 323 int cpu_x86_inl(CPUX86State *env, int addr);
 324 #endif
 325
 326 CPUX86State *cpu_x86_init(void);
 327 int cpu_x86_exec(CPUX86State *s);
 328 void cpu_x86_close(CPUX86State *s);
 329 int cpu_x86_get_pic_interrupt(CPUX86State *s);
 330
 331 /* this function must always be used to load data in the segment
 332    cache: it synchronizes the hflags with the segment cache values */
 333 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 334                                           int seg_reg, unsigned int selector,
 335                                           uint8_t *base, unsigned int limit,
 336                                           unsigned int flags)
 337 {
 338     SegmentCache *sc;
 339     unsigned int new_hflags;
 340
 341     sc = &env->segs[seg_reg];
 342     sc->selector = selector;
 343     sc->base = base;
 344     sc->limit = limit;
 345     sc->flags = flags;
 346
 347     /* update the hidden flags */
 348     new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 349         >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 350     new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
 351         >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 352     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 353         /* XXX: try to avoid this test. The problem comes from the
 354            fact that is real mode or vm86 mode we only modify the
 355            'base' and 'selector' fields of the segment cache to go
 356            faster. A solution may be to force addseg to one in
 357            translate-i386.c. */
 358         new_hflags |= HF_ADDSEG_MASK;
 359     } else {
 360         new_hflags |= (((unsigned long)env->segs[R_DS].base |
 361                         (unsigned long)env->segs[R_ES].base |
 362                         (unsigned long)env->segs[R_SS].base) != 0) <<
 363             HF_ADDSEG_SHIFT;
 364     }
 365     env->hflags = (env->hflags &
 366                    ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 367 }
 368
 369 /* wrapper, just in case memory mappings must be changed */
 370 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 371 {
 372 #if HF_CPL_MASK == 3
 373     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 374 #else
 375 #error HF_CPL_MASK is hardcoded
 376 #endif
 377 }
 378
 379 /* the following helpers are only usable in user mode simulation as
 380    they can trigger unexpected exceptions */
 381 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 382 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
 383 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
 384
 385 /* you can call this signal handler from your SIGBUS and SIGSEGV
 386    signal handlers to inform the virtual CPU of exceptions. non zero
 387    is returned if the signal was handled by the virtual CPU.  */
 388 struct siginfo;
 389 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
 390                            void *puc);
 391
 392 /* MMU defines */
 393 void cpu_x86_init_mmu(CPUX86State *env);
 394 extern int phys_ram_size;
 395 extern int phys_ram_fd;
 396 extern uint8_t *phys_ram_base;
 397 extern int a20_enabled;
 398
 399 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 400
 401 /* used to debug */
 402 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 403 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 404 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
 405
 406 #define TARGET_PAGE_BITS 12
 407 #include "cpu-all.h"
 408
 409 #endif /* CPU_I386_H */