hw/usb-ohci.c

   1 /*
   2  * QEMU USB OHCI Emulation
   3  * Copyright (c) 2004 Gianni Tedesco
   4  * Copyright (c) 2006 CodeSourcery
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  * TODO:
  22  *  o Isochronous transfers
  23  *  o Allocate bandwidth in frames properly
  24  *  o Disable timers when nothing needs to be done, or remove timer usage
  25  *    all together.
  26  *  o Handle unrecoverable errors properly
  27  *  o BIOS work to boot from USB storage
  28 */
  29
  30 #include "vl.h"
  31
  32 //#define DEBUG_OHCI
  33 /* Dump packet contents.  */
  34 //#define DEBUG_PACKET
  35 /* This causes frames to occur 1000x slower */
  36 //#define OHCI_TIME_WARP 1
  37
  38 #ifdef DEBUG_OHCI
  39 #define dprintf printf
  40 #else
  41 #define dprintf(...)
  42 #endif
  43
  44 /* Number of Downstream Ports on the root hub.  */
  45
  46 #define OHCI_MAX_PORTS 15
  47
  48 static int64_t usb_frame_time;
  49 static int64_t usb_bit_time;
  50
  51 typedef struct OHCIPort {
  52     USBPort port;
  53     uint32_t ctrl;
  54 } OHCIPort;
  55
  56 enum ohci_type {
  57     OHCI_TYPE_PCI,
  58     OHCI_TYPE_PXA
  59 };
  60
  61 typedef struct {
  62     qemu_irq irq;
  63     enum ohci_type type;
  64     target_phys_addr_t mem_base;
  65     int mem;
  66     int num_ports;
  67     const char *name;
  68
  69     QEMUTimer *eof_timer;
  70     int64_t sof_time;
  71
  72     /* OHCI state */
  73     /* Control partition */
  74     uint32_t ctl, status;
  75     uint32_t intr_status;
  76     uint32_t intr;
  77
  78     /* memory pointer partition */
  79     uint32_t hcca;
  80     uint32_t ctrl_head, ctrl_cur;
  81     uint32_t bulk_head, bulk_cur;
  82     uint32_t per_cur;
  83     uint32_t done;
  84     int done_count;
  85
  86     /* Frame counter partition */
  87     uint32_t fsmps:15;
  88     uint32_t fit:1;
  89     uint32_t fi:14;
  90     uint32_t frt:1;
  91     uint16_t frame_number;
  92     uint16_t padding;
  93     uint32_t pstart;
  94     uint32_t lst;
  95
  96     /* Root Hub partition */
  97     uint32_t rhdesc_a, rhdesc_b;
  98     uint32_t rhstatus;
  99     OHCIPort rhport[OHCI_MAX_PORTS];
 100
 101     /* PXA27x Non-OHCI events */
 102     uint32_t hstatus;
 103     uint32_t hmask;
 104     uint32_t hreset;
 105     uint32_t htest;
 106
 107     /* Active packets.  */
 108     uint32_t old_ctl;
 109     USBPacket usb_packet;
 110     uint8_t usb_buf[8192];
 111     uint32_t async_td;
 112     int async_complete;
 113
 114 } OHCIState;
 115
 116 /* Host Controller Communications Area */
 117 struct ohci_hcca {
 118     uint32_t intr[32];
 119     uint16_t frame, pad;
 120     uint32_t done;
 121 };
 122
 123 static void ohci_bus_stop(OHCIState *ohci);
 124
 125 /* Bitfields for the first word of an Endpoint Desciptor.  */
 126 #define OHCI_ED_FA_SHIFT  0
 127 #define OHCI_ED_FA_MASK   (0x7f<<OHCI_ED_FA_SHIFT)
 128 #define OHCI_ED_EN_SHIFT  7
 129 #define OHCI_ED_EN_MASK   (0xf<<OHCI_ED_EN_SHIFT)
 130 #define OHCI_ED_D_SHIFT   11
 131 #define OHCI_ED_D_MASK    (3<<OHCI_ED_D_SHIFT)
 132 #define OHCI_ED_S         (1<<13)
 133 #define OHCI_ED_K         (1<<14)
 134 #define OHCI_ED_F         (1<<15)
 135 #define OHCI_ED_MPS_SHIFT 7
 136 #define OHCI_ED_MPS_MASK  (0xf<<OHCI_ED_FA_SHIFT)
 137
 138 /* Flags in the head field of an Endpoint Desciptor.  */
 139 #define OHCI_ED_H         1
 140 #define OHCI_ED_C         2
 141
 142 /* Bitfields for the first word of a Transfer Desciptor.  */
 143 #define OHCI_TD_R         (1<<18)
 144 #define OHCI_TD_DP_SHIFT  19
 145 #define OHCI_TD_DP_MASK   (3<<OHCI_TD_DP_SHIFT)
 146 #define OHCI_TD_DI_SHIFT  21
 147 #define OHCI_TD_DI_MASK   (7<<OHCI_TD_DI_SHIFT)
 148 #define OHCI_TD_T0        (1<<24)
 149 #define OHCI_TD_T1        (1<<24)
 150 #define OHCI_TD_EC_SHIFT  26
 151 #define OHCI_TD_EC_MASK   (3<<OHCI_TD_EC_SHIFT)
 152 #define OHCI_TD_CC_SHIFT  28
 153 #define OHCI_TD_CC_MASK   (0xf<<OHCI_TD_CC_SHIFT)
 154
 155 #define OHCI_DPTR_MASK    0xfffffff0
 156
 157 #define OHCI_BM(val, field) \
 158   (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
 159
 160 #define OHCI_SET_BM(val, field, newval) do { \
 161     val &= ~OHCI_##field##_MASK; \
 162     val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
 163     } while(0)
 164
 165 /* endpoint descriptor */
 166 struct ohci_ed {
 167     uint32_t flags;
 168     uint32_t tail;
 169     uint32_t head;
 170     uint32_t next;
 171 };
 172
 173 /* General transfer descriptor */
 174 struct ohci_td {
 175     uint32_t flags;
 176     uint32_t cbp;
 177     uint32_t next;
 178     uint32_t be;
 179 };
 180
 181 #define USB_HZ                      12000000
 182
 183 /* OHCI Local stuff */
 184 #define OHCI_CTL_CBSR         ((1<<0)|(1<<1))
 185 #define OHCI_CTL_PLE          (1<<2)
 186 #define OHCI_CTL_IE           (1<<3)
 187 #define OHCI_CTL_CLE          (1<<4)
 188 #define OHCI_CTL_BLE          (1<<5)
 189 #define OHCI_CTL_HCFS         ((1<<6)|(1<<7))
 190 #define  OHCI_USB_RESET       0x00
 191 #define  OHCI_USB_RESUME      0x40
 192 #define  OHCI_USB_OPERATIONAL 0x80
 193 #define  OHCI_USB_SUSPEND     0xc0
 194 #define OHCI_CTL_IR           (1<<8)
 195 #define OHCI_CTL_RWC          (1<<9)
 196 #define OHCI_CTL_RWE          (1<<10)
 197
 198 #define OHCI_STATUS_HCR       (1<<0)
 199 #define OHCI_STATUS_CLF       (1<<1)
 200 #define OHCI_STATUS_BLF       (1<<2)
 201 #define OHCI_STATUS_OCR       (1<<3)
 202 #define OHCI_STATUS_SOC       ((1<<6)|(1<<7))
 203
 204 #define OHCI_INTR_SO          (1<<0) /* Scheduling overrun */
 205 #define OHCI_INTR_WD          (1<<1) /* HcDoneHead writeback */
 206 #define OHCI_INTR_SF          (1<<2) /* Start of frame */
 207 #define OHCI_INTR_RD          (1<<3) /* Resume detect */
 208 #define OHCI_INTR_UE          (1<<4) /* Unrecoverable error */
 209 #define OHCI_INTR_FNO         (1<<5) /* Frame number overflow */
 210 #define OHCI_INTR_RHSC        (1<<6) /* Root hub status change */
 211 #define OHCI_INTR_OC          (1<<30) /* Ownership change */
 212 #define OHCI_INTR_MIE         (1<<31) /* Master Interrupt Enable */
 213
 214 #define OHCI_HCCA_SIZE        0x100
 215 #define OHCI_HCCA_MASK        0xffffff00
 216
 217 #define OHCI_EDPTR_MASK       0xfffffff0
 218
 219 #define OHCI_FMI_FI           0x00003fff
 220 #define OHCI_FMI_FSMPS        0xffff0000
 221 #define OHCI_FMI_FIT          0x80000000
 222
 223 #define OHCI_FR_RT            (1<<31)
 224
 225 #define OHCI_LS_THRESH        0x628
 226
 227 #define OHCI_RHA_RW_MASK      0x00000000 /* Mask of supported features.  */
 228 #define OHCI_RHA_PSM          (1<<8)
 229 #define OHCI_RHA_NPS          (1<<9)
 230 #define OHCI_RHA_DT           (1<<10)
 231 #define OHCI_RHA_OCPM         (1<<11)
 232 #define OHCI_RHA_NOCP         (1<<12)
 233 #define OHCI_RHA_POTPGT_MASK  0xff000000
 234
 235 #define OHCI_RHS_LPS          (1<<0)
 236 #define OHCI_RHS_OCI          (1<<1)
 237 #define OHCI_RHS_DRWE         (1<<15)
 238 #define OHCI_RHS_LPSC         (1<<16)
 239 #define OHCI_RHS_OCIC         (1<<17)
 240 #define OHCI_RHS_CRWE         (1<<31)
 241
 242 #define OHCI_PORT_CCS         (1<<0)
 243 #define OHCI_PORT_PES         (1<<1)
 244 #define OHCI_PORT_PSS         (1<<2)
 245 #define OHCI_PORT_POCI        (1<<3)
 246 #define OHCI_PORT_PRS         (1<<4)
 247 #define OHCI_PORT_PPS         (1<<8)
 248 #define OHCI_PORT_LSDA        (1<<9)
 249 #define OHCI_PORT_CSC         (1<<16)
 250 #define OHCI_PORT_PESC        (1<<17)
 251 #define OHCI_PORT_PSSC        (1<<18)
 252 #define OHCI_PORT_OCIC        (1<<19)
 253 #define OHCI_PORT_PRSC        (1<<20)
 254 #define OHCI_PORT_WTC         (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
 255                                |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
 256
 257 #define OHCI_TD_DIR_SETUP     0x0
 258 #define OHCI_TD_DIR_OUT       0x1
 259 #define OHCI_TD_DIR_IN        0x2
 260 #define OHCI_TD_DIR_RESERVED  0x3
 261
 262 #define OHCI_CC_NOERROR             0x0
 263 #define OHCI_CC_CRC                 0x1
 264 #define OHCI_CC_BITSTUFFING         0x2
 265 #define OHCI_CC_DATATOGGLEMISMATCH  0x3
 266 #define OHCI_CC_STALL               0x4
 267 #define OHCI_CC_DEVICENOTRESPONDING 0x5
 268 #define OHCI_CC_PIDCHECKFAILURE     0x6
 269 #define OHCI_CC_UNDEXPETEDPID       0x7
 270 #define OHCI_CC_DATAOVERRUN         0x8
 271 #define OHCI_CC_DATAUNDERRUN        0x9
 272 #define OHCI_CC_BUFFEROVERRUN       0xc
 273 #define OHCI_CC_BUFFERUNDERRUN      0xd
 274
 275 #define OHCI_HRESET_FSBIR       (1 << 0)
 276
 277 /* Update IRQ levels */
 278 static inline void ohci_intr_update(OHCIState *ohci)
 279 {
 280     int level = 0;
 281
 282     if ((ohci->intr & OHCI_INTR_MIE) &&
 283         (ohci->intr_status & ohci->intr))
 284         level = 1;
 285
 286     qemu_set_irq(ohci->irq, level);
 287 }
 288
 289 /* Set an interrupt */
 290 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
 291 {
 292     ohci->intr_status |= intr;
 293     ohci_intr_update(ohci);
 294 }
 295
 296 /* Attach or detach a device on a root hub port.  */
 297 static void ohci_attach(USBPort *port1, USBDevice *dev)
 298 {
 299     OHCIState *s = port1->opaque;
 300     OHCIPort *port = &s->rhport[port1->index];
 301     uint32_t old_state = port->ctrl;
 302
 303     if (dev) {
 304         if (port->port.dev) {
 305             usb_attach(port1, NULL);
 306         }
 307         /* set connect status */
 308         port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
 309
 310         /* update speed */
 311         if (dev->speed == USB_SPEED_LOW)
 312             port->ctrl |= OHCI_PORT_LSDA;
 313         else
 314             port->ctrl &= ~OHCI_PORT_LSDA;
 315         port->port.dev = dev;
 316
 317         /* notify of remote-wakeup */
 318         if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND)
 319             ohci_set_interrupt(s, OHCI_INTR_RD);
 320
 321         /* send the attach message */
 322         usb_send_msg(dev, USB_MSG_ATTACH);
 323         dprintf("usb-ohci: Attached port %d\n", port1->index);
 324     } else {
 325         /* set connect status */
 326         if (port->ctrl & OHCI_PORT_CCS) {
 327             port->ctrl &= ~OHCI_PORT_CCS;
 328             port->ctrl |= OHCI_PORT_CSC;
 329         }
 330         /* disable port */
 331         if (port->ctrl & OHCI_PORT_PES) {
 332             port->ctrl &= ~OHCI_PORT_PES;
 333             port->ctrl |= OHCI_PORT_PESC;
 334         }
 335         dev = port->port.dev;
 336         if (dev) {
 337             /* send the detach message */
 338             usb_send_msg(dev, USB_MSG_DETACH);
 339         }
 340         port->port.dev = NULL;
 341         dprintf("usb-ohci: Detached port %d\n", port1->index);
 342     }
 343
 344     if (old_state != port->ctrl)
 345         ohci_set_interrupt(s, OHCI_INTR_RHSC);
 346 }
 347
 348 /* Reset the controller */
 349 static void ohci_reset(void *opaque)
 350 {
 351     OHCIState *ohci = opaque;
 352     OHCIPort *port;
 353     int i;
 354
 355     ohci_bus_stop(ohci);
 356     ohci->ctl = 0;
 357     ohci->old_ctl = 0;
 358     ohci->status = 0;
 359     ohci->intr_status = 0;
 360     ohci->intr = OHCI_INTR_MIE;
 361
 362     ohci->hcca = 0;
 363     ohci->ctrl_head = ohci->ctrl_cur = 0;
 364     ohci->bulk_head = ohci->bulk_cur = 0;
 365     ohci->per_cur = 0;
 366     ohci->done = 0;
 367     ohci->done_count = 7;
 368
 369     /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
 370      * I took the value linux sets ...
 371      */
 372     ohci->fsmps = 0x2778;
 373     ohci->fi = 0x2edf;
 374     ohci->fit = 0;
 375     ohci->frt = 0;
 376     ohci->frame_number = 0;
 377     ohci->pstart = 0;
 378     ohci->lst = OHCI_LS_THRESH;
 379
 380     ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
 381     ohci->rhdesc_b = 0x0; /* Impl. specific */
 382     ohci->rhstatus = 0;
 383
 384     for (i = 0; i < ohci->num_ports; i++)
 385       {
 386         port = &ohci->rhport[i];
 387         port->ctrl = 0;
 388         if (port->port.dev)
 389             ohci_attach(&port->port, port->port.dev);
 390       }
 391     if (ohci->async_td) {
 392         usb_cancel_packet(&ohci->usb_packet);
 393         ohci->async_td = 0;
 394     }
 395     dprintf("usb-ohci: Reset %s\n", ohci->name);
 396 }
 397
 398 /* Get an array of dwords from main memory */
 399 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
 400 {
 401     int i;
 402
 403     for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
 404         cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
 405         *buf = le32_to_cpu(*buf);
 406     }
 407
 408     return 1;
 409 }
 410
 411 /* Put an array of dwords in to main memory */
 412 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
 413 {
 414     int i;
 415
 416     for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
 417         uint32_t tmp = cpu_to_le32(*buf);
 418         cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
 419     }
 420
 421     return 1;
 422 }
 423
 424 static inline int ohci_read_ed(uint32_t addr, struct ohci_ed *ed)
 425 {
 426     return get_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2);
 427 }
 428
 429 static inline int ohci_read_td(uint32_t addr, struct ohci_td *td)
 430 {
 431     return get_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2);
 432 }
 433
 434 static inline int ohci_put_ed(uint32_t addr, struct ohci_ed *ed)
 435 {
 436     return put_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2);
 437 }
 438
 439 static inline int ohci_put_td(uint32_t addr, struct ohci_td *td)
 440 {
 441     return put_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2);
 442 }
 443
 444 /* Read/Write the contents of a TD from/to main memory.  */
 445 static void ohci_copy_td(struct ohci_td *td, uint8_t *buf, int len, int write)
 446 {
 447     uint32_t ptr;
 448     uint32_t n;
 449
 450     ptr = td->cbp;
 451     n = 0x1000 - (ptr & 0xfff);
 452     if (n > len)
 453         n = len;
 454     cpu_physical_memory_rw(ptr, buf, n, write);
 455     if (n == len)
 456         return;
 457     ptr = td->be & ~0xfffu;
 458     buf += n;
 459     cpu_physical_memory_rw(ptr, buf, len - n, write);
 460 }
 461
 462 static void ohci_process_lists(OHCIState *ohci);
 463
 464 static void ohci_async_complete_packet(USBPacket * packet, void *opaque)
 465 {
 466     OHCIState *ohci = opaque;
 467 #ifdef DEBUG_PACKET
 468     dprintf("Async packet complete\n");
 469 #endif
 470     ohci->async_complete = 1;
 471     ohci_process_lists(ohci);
 472 }
 473
 474 /* Service a transport descriptor.
 475    Returns nonzero to terminate processing of this endpoint.  */
 476
 477 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
 478 {
 479     int dir;
 480     size_t len = 0;
 481     char *str = NULL;
 482     int pid;
 483     int ret;
 484     int i;
 485     USBDevice *dev;
 486     struct ohci_td td;
 487     uint32_t addr;
 488     int flag_r;
 489     int completion;
 490
 491     addr = ed->head & OHCI_DPTR_MASK;
 492     /* See if this TD has already been submitted to the device.  */
 493     completion = (addr == ohci->async_td);
 494     if (completion && !ohci->async_complete) {
 495 #ifdef DEBUG_PACKET
 496         dprintf("Skipping async TD\n");
 497 #endif
 498         return 1;
 499     }
 500     if (!ohci_read_td(addr, &td)) {
 501         fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
 502         return 0;
 503     }
 504
 505     dir = OHCI_BM(ed->flags, ED_D);
 506     switch (dir) {
 507     case OHCI_TD_DIR_OUT:
 508     case OHCI_TD_DIR_IN:
 509         /* Same value.  */
 510         break;
 511     default:
 512         dir = OHCI_BM(td.flags, TD_DP);
 513         break;
 514     }
 515
 516     switch (dir) {
 517     case OHCI_TD_DIR_IN:
 518         str = "in";
 519         pid = USB_TOKEN_IN;
 520         break;
 521     case OHCI_TD_DIR_OUT:
 522         str = "out";
 523         pid = USB_TOKEN_OUT;
 524         break;
 525     case OHCI_TD_DIR_SETUP:
 526         str = "setup";
 527         pid = USB_TOKEN_SETUP;
 528         break;
 529     default:
 530         fprintf(stderr, "usb-ohci: Bad direction\n");
 531         return 1;
 532     }
 533     if (td.cbp && td.be) {
 534         if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
 535             len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
 536         } else {
 537             len = (td.be - td.cbp) + 1;
 538         }
 539
 540         if (len && dir != OHCI_TD_DIR_IN && !completion) {
 541             ohci_copy_td(&td, ohci->usb_buf, len, 0);
 542         }
 543     }
 544
 545     flag_r = (td.flags & OHCI_TD_R) != 0;
 546 #ifdef DEBUG_PACKET
 547     dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
 548             addr, len, str, flag_r, td.cbp, td.be);
 549
 550     if (len >= 0 && dir != OHCI_TD_DIR_IN) {
 551         dprintf("  data:");
 552         for (i = 0; i < len; i++)
 553             printf(" %.2x", ohci->usb_buf[i]);
 554         dprintf("\n");
 555     }
 556 #endif
 557     if (completion) {
 558         ret = ohci->usb_packet.len;
 559         ohci->async_td = 0;
 560         ohci->async_complete = 0;
 561     } else {
 562         ret = USB_RET_NODEV;
 563         for (i = 0; i < ohci->num_ports; i++) {
 564             dev = ohci->rhport[i].port.dev;
 565             if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
 566                 continue;
 567
 568             if (ohci->async_td) {
 569                 /* ??? The hardware should allow one active packet per
 570                    endpoint.  We only allow one active packet per controller.
 571                    This should be sufficient as long as devices respond in a
 572                    timely manner.
 573                  */
 574 #ifdef DEBUG_PACKET
 575                 dprintf("Too many pending packets\n");
 576 #endif
 577                 return 1;
 578             }
 579             ohci->usb_packet.pid = pid;
 580             ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
 581             ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
 582             ohci->usb_packet.data = ohci->usb_buf;
 583             ohci->usb_packet.len = len;
 584             ohci->usb_packet.complete_cb = ohci_async_complete_packet;
 585             ohci->usb_packet.complete_opaque = ohci;
 586             ret = dev->handle_packet(dev, &ohci->usb_packet);
 587             if (ret != USB_RET_NODEV)
 588                 break;
 589         }
 590 #ifdef DEBUG_PACKET
 591         dprintf("ret=%d\n", ret);
 592 #endif
 593         if (ret == USB_RET_ASYNC) {
 594             ohci->async_td = addr;
 595             return 1;
 596         }
 597     }
 598     if (ret >= 0) {
 599         if (dir == OHCI_TD_DIR_IN) {
 600             ohci_copy_td(&td, ohci->usb_buf, ret, 1);
 601 #ifdef DEBUG_PACKET
 602             dprintf("  data:");
 603             for (i = 0; i < ret; i++)
 604                 printf(" %.2x", ohci->usb_buf[i]);
 605             dprintf("\n");
 606 #endif
 607         } else {
 608             ret = len;
 609         }
 610     }
 611
 612     /* Writeback */
 613     if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
 614         /* Transmission succeeded.  */
 615         if (ret == len) {
 616             td.cbp = 0;
 617         } else {
 618             td.cbp += ret;
 619             if ((td.cbp & 0xfff) + ret > 0xfff) {
 620                 td.cbp &= 0xfff;
 621                 td.cbp |= td.be & ~0xfff;
 622             }
 623         }
 624         td.flags |= OHCI_TD_T1;
 625         td.flags ^= OHCI_TD_T0;
 626         OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
 627         OHCI_SET_BM(td.flags, TD_EC, 0);
 628
 629         ed->head &= ~OHCI_ED_C;
 630         if (td.flags & OHCI_TD_T0)
 631             ed->head |= OHCI_ED_C;
 632     } else {
 633         if (ret >= 0) {
 634             dprintf("usb-ohci: Underrun\n");
 635             OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
 636         } else {
 637             switch (ret) {
 638             case USB_RET_NODEV:
 639                 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
 640             case USB_RET_NAK:
 641                 dprintf("usb-ohci: got NAK\n");
 642                 return 1;
 643             case USB_RET_STALL:
 644                 dprintf("usb-ohci: got STALL\n");
 645                 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
 646                 break;
 647             case USB_RET_BABBLE:
 648                 dprintf("usb-ohci: got BABBLE\n");
 649                 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
 650                 break;
 651             default:
 652                 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
 653                 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
 654                 OHCI_SET_BM(td.flags, TD_EC, 3);
 655                 break;
 656             }
 657         }
 658         ed->head |= OHCI_ED_H;
 659     }
 660
 661     /* Retire this TD */
 662     ed->head &= ~OHCI_DPTR_MASK;
 663     ed->head |= td.next & OHCI_DPTR_MASK;
 664     td.next = ohci->done;
 665     ohci->done = addr;
 666     i = OHCI_BM(td.flags, TD_DI);
 667     if (i < ohci->done_count)
 668         ohci->done_count = i;
 669     ohci_put_td(addr, &td);
 670     return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
 671 }
 672
 673 /* Service an endpoint list.  Returns nonzero if active TD were found.  */
 674 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head)
 675 {
 676     struct ohci_ed ed;
 677     uint32_t next_ed;
 678     uint32_t cur;
 679     int active;
 680
 681     active = 0;
 682
 683     if (head == 0)
 684         return 0;
 685
 686     for (cur = head; cur; cur = next_ed) {
 687         if (!ohci_read_ed(cur, &ed)) {
 688             fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
 689             return 0;
 690         }
 691
 692         next_ed = ed.next & OHCI_DPTR_MASK;
 693
 694         if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
 695             uint32_t addr;
 696             /* Cancel pending packets for ED that have been paused.  */
 697             addr = ed.head & OHCI_DPTR_MASK;
 698             if (ohci->async_td && addr == ohci->async_td) {
 699                 usb_cancel_packet(&ohci->usb_packet);
 700                 ohci->async_td = 0;
 701             }
 702             continue;
 703         }
 704
 705         /* Skip isochronous endpoints.  */
 706         if (ed.flags & OHCI_ED_F)
 707           continue;
 708
 709         while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
 710 #ifdef DEBUG_PACKET
 711             dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
 712                     "h=%u c=%u\n  head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
 713                     OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
 714                     OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
 715                     (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
 716                     OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
 717                     (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
 718                     ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
 719 #endif
 720             active = 1;
 721
 722             if (ohci_service_td(ohci, &ed))
 723                 break;
 724         }
 725
 726         ohci_put_ed(cur, &ed);
 727     }
 728
 729     return active;
 730 }
 731
 732 /* Generate a SOF event, and set a timer for EOF */
 733 static void ohci_sof(OHCIState *ohci)
 734 {
 735     ohci->sof_time = qemu_get_clock(vm_clock);
 736     qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
 737     ohci_set_interrupt(ohci, OHCI_INTR_SF);
 738 }
 739
 740 /* Process Control and Bulk lists.  */
 741 static void ohci_process_lists(OHCIState *ohci)
 742 {
 743     if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
 744         if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
 745           dprintf("usb-ohci: head %x, cur %x\n", ohci->ctrl_head, ohci->ctrl_cur);
 746         if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) {
 747             ohci->ctrl_cur = 0;
 748             ohci->status &= ~OHCI_STATUS_CLF;
 749         }
 750     }
 751
 752     if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
 753         if (!ohci_service_ed_list(ohci, ohci->bulk_head)) {
 754             ohci->bulk_cur = 0;
 755             ohci->status &= ~OHCI_STATUS_BLF;
 756         }
 757     }
 758 }
 759
 760 /* Do frame processing on frame boundary */
 761 static void ohci_frame_boundary(void *opaque)
 762 {
 763     OHCIState *ohci = opaque;
 764     struct ohci_hcca hcca;
 765
 766     cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 0);
 767
 768     /* Process all the lists at the end of the frame */
 769     if (ohci->ctl & OHCI_CTL_PLE) {
 770         int n;
 771
 772         n = ohci->frame_number & 0x1f;
 773         ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]));
 774     }
 775
 776     /* Cancel all pending packets if either of the lists has been disabled.  */
 777     if (ohci->async_td &&
 778         ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
 779         usb_cancel_packet(&ohci->usb_packet);
 780         ohci->async_td = 0;
 781     }
 782     ohci->old_ctl = ohci->ctl;
 783     ohci_process_lists(ohci);
 784
 785     /* Frame boundary, so do EOF stuf here */
 786     ohci->frt = ohci->fit;
 787
 788     /* XXX: endianness */
 789     ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
 790     hcca.frame = cpu_to_le32(ohci->frame_number);
 791
 792     if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
 793         if (!ohci->done)
 794             abort();
 795         if (ohci->intr & ohci->intr_status)
 796             ohci->done |= 1;
 797         hcca.done = cpu_to_le32(ohci->done);
 798         ohci->done = 0;
 799         ohci->done_count = 7;
 800         ohci_set_interrupt(ohci, OHCI_INTR_WD);
 801     }
 802
 803     if (ohci->done_count != 7 && ohci->done_count != 0)
 804         ohci->done_count--;
 805
 806     /* Do SOF stuff here */
 807     ohci_sof(ohci);
 808
 809     /* Writeback HCCA */
 810     cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 1);
 811 }
 812
 813 /* Start sending SOF tokens across the USB bus, lists are processed in
 814  * next frame
 815  */
 816 static int ohci_bus_start(OHCIState *ohci)
 817 {
 818     ohci->eof_timer = qemu_new_timer(vm_clock,
 819                     ohci_frame_boundary,
 820                     ohci);
 821
 822     if (ohci->eof_timer == NULL) {
 823         fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name);
 824         /* TODO: Signal unrecoverable error */
 825         return 0;
 826     }
 827
 828     dprintf("usb-ohci: %s: USB Operational\n", ohci->name);
 829
 830     ohci_sof(ohci);
 831
 832     return 1;
 833 }
 834
 835 /* Stop sending SOF tokens on the bus */
 836 static void ohci_bus_stop(OHCIState *ohci)
 837 {
 838     if (ohci->eof_timer)
 839         qemu_del_timer(ohci->eof_timer);
 840     ohci->eof_timer = NULL;
 841 }
 842
 843 /* Sets a flag in a port status register but only set it if the port is
 844  * connected, if not set ConnectStatusChange flag. If flag is enabled
 845  * return 1.
 846  */
 847 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
 848 {
 849     int ret = 1;
 850
 851     /* writing a 0 has no effect */
 852     if (val == 0)
 853         return 0;
 854
 855     /* If CurrentConnectStatus is cleared we set
 856      * ConnectStatusChange
 857      */
 858     if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
 859         ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
 860         if (ohci->rhstatus & OHCI_RHS_DRWE) {
 861             /* TODO: CSC is a wakeup event */
 862         }
 863         return 0;
 864     }
 865
 866     if (ohci->rhport[i].ctrl & val)
 867         ret = 0;
 868
 869     /* set the bit */
 870     ohci->rhport[i].ctrl |= val;
 871
 872     return ret;
 873 }
 874
 875 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
 876 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
 877 {
 878     val &= OHCI_FMI_FI;
 879
 880     if (val != ohci->fi) {
 881         dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
 882             ohci->name, ohci->fi, ohci->fi);
 883     }
 884
 885     ohci->fi = val;
 886 }
 887
 888 static void ohci_port_power(OHCIState *ohci, int i, int p)
 889 {
 890     if (p) {
 891         ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
 892     } else {
 893         ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
 894                     OHCI_PORT_CCS|
 895                     OHCI_PORT_PSS|
 896                     OHCI_PORT_PRS);
 897     }
 898 }
 899
 900 /* Set HcControlRegister */
 901 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
 902 {
 903     uint32_t old_state;
 904     uint32_t new_state;
 905
 906     old_state = ohci->ctl & OHCI_CTL_HCFS;
 907     ohci->ctl = val;
 908     new_state = ohci->ctl & OHCI_CTL_HCFS;
 909
 910     /* no state change */
 911     if (old_state == new_state)
 912         return;
 913
 914     switch (new_state) {
 915     case OHCI_USB_OPERATIONAL:
 916         ohci_bus_start(ohci);
 917         break;
 918     case OHCI_USB_SUSPEND:
 919         ohci_bus_stop(ohci);
 920         dprintf("usb-ohci: %s: USB Suspended\n", ohci->name);
 921         break;
 922     case OHCI_USB_RESUME:
 923         dprintf("usb-ohci: %s: USB Resume\n", ohci->name);
 924         break;
 925     case OHCI_USB_RESET:
 926         ohci_reset(ohci);
 927         dprintf("usb-ohci: %s: USB Reset\n", ohci->name);
 928         break;
 929     }
 930 }
 931
 932 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
 933 {
 934     uint16_t fr;
 935     int64_t tks;
 936
 937     if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
 938         return (ohci->frt << 31);
 939
 940     /* Being in USB operational state guarnatees sof_time was
 941      * set already.
 942      */
 943     tks = qemu_get_clock(vm_clock) - ohci->sof_time;
 944
 945     /* avoid muldiv if possible */
 946     if (tks >= usb_frame_time)
 947         return (ohci->frt << 31);
 948
 949     tks = muldiv64(1, tks, usb_bit_time);
 950     fr = (uint16_t)(ohci->fi - tks);
 951
 952     return (ohci->frt << 31) | fr;
 953 }
 954
 955
 956 /* Set root hub status */
 957 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
 958 {
 959     uint32_t old_state;
 960
 961     old_state = ohci->rhstatus;
 962
 963     /* write 1 to clear OCIC */
 964     if (val & OHCI_RHS_OCIC)
 965         ohci->rhstatus &= ~OHCI_RHS_OCIC;
 966
 967     if (val & OHCI_RHS_LPS) {
 968         int i;
 969
 970         for (i = 0; i < ohci->num_ports; i++)
 971             ohci_port_power(ohci, i, 0);
 972         dprintf("usb-ohci: powered down all ports\n");
 973     }
 974
 975     if (val & OHCI_RHS_LPSC) {
 976         int i;
 977
 978         for (i = 0; i < ohci->num_ports; i++)
 979             ohci_port_power(ohci, i, 1);
 980         dprintf("usb-ohci: powered up all ports\n");
 981     }
 982
 983     if (val & OHCI_RHS_DRWE)
 984         ohci->rhstatus |= OHCI_RHS_DRWE;
 985
 986     if (val & OHCI_RHS_CRWE)
 987         ohci->rhstatus &= ~OHCI_RHS_DRWE;
 988
 989     if (old_state != ohci->rhstatus)
 990         ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
 991 }
 992
 993 /* Set root hub port status */
 994 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
 995 {
 996     uint32_t old_state;
 997     OHCIPort *port;
 998
 999     port = &ohci->rhport[portnum];
1000     old_state = port->ctrl;
1001
1002     /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1003     if (val & OHCI_PORT_WTC)
1004         port->ctrl &= ~(val & OHCI_PORT_WTC);
1005
1006     if (val & OHCI_PORT_CCS)
1007         port->ctrl &= ~OHCI_PORT_PES;
1008
1009     ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1010
1011     if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
1012         dprintf("usb-ohci: port %d: SUSPEND\n", portnum);
1013
1014     if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1015         dprintf("usb-ohci: port %d: RESET\n", portnum);
1016         usb_send_msg(port->port.dev, USB_MSG_RESET);
1017         port->ctrl &= ~OHCI_PORT_PRS;
1018         /* ??? Should this also set OHCI_PORT_PESC.  */
1019         port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1020     }
1021
1022     /* Invert order here to ensure in ambiguous case, device is
1023      * powered up...
1024      */
1025     if (val & OHCI_PORT_LSDA)
1026         ohci_port_power(ohci, portnum, 0);
1027     if (val & OHCI_PORT_PPS)
1028         ohci_port_power(ohci, portnum, 1);
1029
1030     if (old_state != port->ctrl)
1031         ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1032
1033     return;
1034 }
1035
1036 static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1037 {
1038     OHCIState *ohci = ptr;
1039
1040     addr -= ohci->mem_base;
1041
1042     /* Only aligned reads are allowed on OHCI */
1043     if (addr & 3) {
1044         fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1045         return 0xffffffff;
1046     }
1047
1048     if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1049         /* HcRhPortStatus */
1050         return ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1051     }
1052
1053     switch (addr >> 2) {
1054     case 0: /* HcRevision */
1055         return 0x10;
1056
1057     case 1: /* HcControl */
1058         return ohci->ctl;
1059
1060     case 2: /* HcCommandStatus */
1061         return ohci->status;
1062
1063     case 3: /* HcInterruptStatus */
1064         return ohci->intr_status;
1065
1066     case 4: /* HcInterruptEnable */
1067     case 5: /* HcInterruptDisable */
1068         return ohci->intr;
1069
1070     case 6: /* HcHCCA */
1071         return ohci->hcca;
1072
1073     case 7: /* HcPeriodCurrentED */
1074         return ohci->per_cur;
1075
1076     case 8: /* HcControlHeadED */
1077         return ohci->ctrl_head;
1078
1079     case 9: /* HcControlCurrentED */
1080         return ohci->ctrl_cur;
1081
1082     case 10: /* HcBulkHeadED */
1083         return ohci->bulk_head;
1084
1085     case 11: /* HcBulkCurrentED */
1086         return ohci->bulk_cur;
1087
1088     case 12: /* HcDoneHead */
1089         return ohci->done;
1090
1091     case 13: /* HcFmInterval */
1092         return (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1093
1094     case 14: /* HcFmRemaining */
1095         return ohci_get_frame_remaining(ohci);
1096
1097     case 15: /* HcFmNumber */
1098         return ohci->frame_number;
1099
1100     case 16: /* HcPeriodicStart */
1101         return ohci->pstart;
1102
1103     case 17: /* HcLSThreshold */
1104         return ohci->lst;
1105
1106     case 18: /* HcRhDescriptorA */
1107         return ohci->rhdesc_a;
1108
1109     case 19: /* HcRhDescriptorB */
1110         return ohci->rhdesc_b;
1111
1112     case 20: /* HcRhStatus */
1113         return ohci->rhstatus;
1114
1115     /* PXA27x specific registers */
1116     case 24: /* HcStatus */
1117         return ohci->hstatus & ohci->hmask;
1118
1119     case 25: /* HcHReset */
1120         return ohci->hreset;
1121
1122     case 26: /* HcHInterruptEnable */
1123         return ohci->hmask;
1124
1125     case 27: /* HcHInterruptTest */
1126         return ohci->htest;
1127
1128     default:
1129         fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1130         return 0xffffffff;
1131     }
1132 }
1133
1134 static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1135 {
1136     OHCIState *ohci = ptr;
1137
1138     addr -= ohci->mem_base;
1139
1140     /* Only aligned reads are allowed on OHCI */
1141     if (addr & 3) {
1142         fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1143         return;
1144     }
1145
1146     if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1147         /* HcRhPortStatus */
1148         ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1149         return;
1150     }
1151
1152     switch (addr >> 2) {
1153     case 1: /* HcControl */
1154         ohci_set_ctl(ohci, val);
1155         break;
1156
1157     case 2: /* HcCommandStatus */
1158         /* SOC is read-only */
1159         val = (val & ~OHCI_STATUS_SOC);
1160
1161         /* Bits written as '0' remain unchanged in the register */
1162         ohci->status |= val;
1163
1164         if (ohci->status & OHCI_STATUS_HCR)
1165             ohci_reset(ohci);
1166         break;
1167
1168     case 3: /* HcInterruptStatus */
1169         ohci->intr_status &= ~val;
1170         ohci_intr_update(ohci);
1171         break;
1172
1173     case 4: /* HcInterruptEnable */
1174         ohci->intr |= val;
1175         ohci_intr_update(ohci);
1176         break;
1177
1178     case 5: /* HcInterruptDisable */
1179         ohci->intr &= ~val;
1180         ohci_intr_update(ohci);
1181         break;
1182
1183     case 6: /* HcHCCA */
1184         ohci->hcca = val & OHCI_HCCA_MASK;
1185         break;
1186
1187     case 8: /* HcControlHeadED */
1188         ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1189         break;
1190
1191     case 9: /* HcControlCurrentED */
1192         ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1193         break;
1194
1195     case 10: /* HcBulkHeadED */
1196         ohci->bulk_head = val & OHCI_EDPTR_MASK;
1197         break;
1198
1199     case 11: /* HcBulkCurrentED */
1200         ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1201         break;
1202
1203     case 13: /* HcFmInterval */
1204         ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1205         ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1206         ohci_set_frame_interval(ohci, val);
1207         break;
1208
1209     case 16: /* HcPeriodicStart */
1210         ohci->pstart = val & 0xffff;
1211         break;
1212
1213     case 17: /* HcLSThreshold */
1214         ohci->lst = val & 0xffff;
1215         break;
1216
1217     case 18: /* HcRhDescriptorA */
1218         ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1219         ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1220         break;
1221
1222     case 19: /* HcRhDescriptorB */
1223         break;
1224
1225     case 20: /* HcRhStatus */
1226         ohci_set_hub_status(ohci, val);
1227         break;
1228
1229     /* PXA27x specific registers */
1230     case 24: /* HcStatus */
1231         ohci->hstatus &= ~(val & ohci->hmask);
1232
1233     case 25: /* HcHReset */
1234         ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1235         if (val & OHCI_HRESET_FSBIR)
1236             ohci_reset(ohci);
1237         break;
1238
1239     case 26: /* HcHInterruptEnable */
1240         ohci->hmask = val;
1241         break;
1242
1243     case 27: /* HcHInterruptTest */
1244         ohci->htest = val;
1245         break;
1246
1247     default:
1248         fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1249         break;
1250     }
1251 }
1252
1253 /* Only dword reads are defined on OHCI register space */
1254 static CPUReadMemoryFunc *ohci_readfn[3]={
1255     ohci_mem_read,
1256     ohci_mem_read,
1257     ohci_mem_read
1258 };
1259
1260 /* Only dword writes are defined on OHCI register space */
1261 static CPUWriteMemoryFunc *ohci_writefn[3]={
1262     ohci_mem_write,
1263     ohci_mem_write,
1264     ohci_mem_write
1265 };
1266
1267 static void usb_ohci_init(OHCIState *ohci, int num_ports, int devfn,
1268             qemu_irq irq, enum ohci_type type, const char *name)
1269 {
1270     int i;
1271
1272     if (usb_frame_time == 0) {
1273 #if OHCI_TIME_WARP
1274         usb_frame_time = ticks_per_sec;
1275         usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ/1000);
1276 #else
1277         usb_frame_time = muldiv64(1, ticks_per_sec, 1000);
1278         if (ticks_per_sec >= USB_HZ) {
1279             usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ);
1280         } else {
1281             usb_bit_time = 1;
1282         }
1283 #endif
1284         dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
1285                 usb_frame_time, usb_bit_time);
1286     }
1287
1288     ohci->mem = cpu_register_io_memory(0, ohci_readfn, ohci_writefn, ohci);
1289     ohci->name = name;
1290
1291     ohci->irq = irq;
1292     ohci->type = type;
1293
1294     ohci->num_ports = num_ports;
1295     for (i = 0; i < num_ports; i++) {
1296         qemu_register_usb_port(&ohci->rhport[i].port, ohci, i, ohci_attach);
1297     }
1298
1299     ohci->async_td = 0;
1300     qemu_register_reset(ohci_reset, ohci);
1301     ohci_reset(ohci);
1302 }
1303
1304 typedef struct {
1305     PCIDevice pci_dev;
1306     OHCIState state;
1307 } OHCIPCIState;
1308
1309 static void ohci_mapfunc(PCIDevice *pci_dev, int i,
1310             uint32_t addr, uint32_t size, int type)
1311 {
1312     OHCIPCIState *ohci = (OHCIPCIState *)pci_dev;
1313     ohci->state.mem_base = addr;
1314     cpu_register_physical_memory(addr, size, ohci->state.mem);
1315 }
1316
1317 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn)
1318 {
1319     OHCIPCIState *ohci;
1320     int vid = 0x106b;
1321     int did = 0x003f;
1322
1323     ohci = (OHCIPCIState *)pci_register_device(bus, "OHCI USB", sizeof(*ohci),
1324                                                devfn, NULL, NULL);
1325     if (ohci == NULL) {
1326         fprintf(stderr, "usb-ohci: Failed to register PCI device\n");
1327         return;
1328     }
1329
1330     ohci->pci_dev.config[0x00] = vid & 0xff;
1331     ohci->pci_dev.config[0x01] = (vid >> 8) & 0xff;
1332     ohci->pci_dev.config[0x02] = did & 0xff;
1333     ohci->pci_dev.config[0x03] = (did >> 8) & 0xff;
1334     ohci->pci_dev.config[0x09] = 0x10; /* OHCI */
1335     ohci->pci_dev.config[0x0a] = 0x3;
1336     ohci->pci_dev.config[0x0b] = 0xc;
1337     ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1338
1339     usb_ohci_init(&ohci->state, num_ports, devfn, ohci->pci_dev.irq[0],
1340                   OHCI_TYPE_PCI, ohci->pci_dev.name);
1341
1342     pci_register_io_region((struct PCIDevice *)ohci, 0, 256,
1343                            PCI_ADDRESS_SPACE_MEM, ohci_mapfunc);
1344 }
1345
1346 void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
1347                        qemu_irq irq)
1348 {
1349     OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
1350
1351     usb_ohci_init(ohci, num_ports, devfn, irq,
1352                   OHCI_TYPE_PXA, "OHCI USB");
1353     ohci->mem_base = base;
1354
1355     cpu_register_physical_memory(ohci->mem_base, 0x1000, ohci->mem);
1356 }