2 * QEMU SCI/SCIF serial port emulation
4 * Copyright (c) 2007 Magnus Damm
6 * Based on serial.c - QEMU 16450 UART emulation
7 * Copyright (c) 2003-2004 Fabrice Bellard
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 //#define DEBUG_SERIAL
32 #define SH_SERIAL_FLAG_TEND (1 << 0)
33 #define SH_SERIAL_FLAG_TDE (1 << 1)
34 #define SH_SERIAL_FLAG_RDF (1 << 2)
35 #define SH_SERIAL_FLAG_BRK (1 << 3)
36 #define SH_SERIAL_FLAG_DR (1 << 4)
42 uint8_t dr
; /* ftdr / tdr */
43 uint8_t sr
; /* fsr / ssr */
47 uint8_t rx_fifo
[16]; /* frdr / rdr */
50 target_phys_addr_t base
;
58 static void sh_serial_ioport_write(void *opaque
, uint32_t offs
, uint32_t val
)
60 sh_serial_state
*s
= opaque
;
64 printf("sh_serial: write base=0x%08lx offs=0x%02x val=0x%02x\n",
65 (unsigned long) s
->base
, offs
, val
);
69 s
->smr
= val
& ((s
->feat
& SH_SERIAL_FEAT_SCIF
) ? 0x7b : 0xff);
75 s
->scr
= val
& ((s
->feat
& SH_SERIAL_FEAT_SCIF
) ? 0xfb : 0xff);
76 if (!(val
& (1 << 5)))
77 s
->flags
|= SH_SERIAL_FLAG_TEND
;
79 case 0x0c: /* FTDR / TDR */
82 qemu_chr_write(s
->chr
, &ch
, 1);
85 s
->flags
&= ~SH_SERIAL_FLAG_TDE
;
88 case 0x14: /* FRDR / RDR */
93 if (s
->feat
& SH_SERIAL_FEAT_SCIF
) {
96 if (!(val
& (1 << 6)))
97 s
->flags
&= ~SH_SERIAL_FLAG_TEND
;
98 if (!(val
& (1 << 5)))
99 s
->flags
&= ~SH_SERIAL_FLAG_TDE
;
100 if (!(val
& (1 << 4)))
101 s
->flags
&= ~SH_SERIAL_FLAG_BRK
;
102 if (!(val
& (1 << 1)))
103 s
->flags
&= ~SH_SERIAL_FLAG_RDF
;
104 if (!(val
& (1 << 0)))
105 s
->flags
&= ~SH_SERIAL_FLAG_DR
;
110 case 0x20: /* SPTR */
133 fprintf(stderr
, "sh_serial: unsupported write to 0x%02x\n", offs
);
137 static uint32_t sh_serial_ioport_read(void *opaque
, uint32_t offs
)
139 sh_serial_state
*s
= opaque
;
158 if (s
->feat
& SH_SERIAL_FEAT_SCIF
) {
162 if (s
->flags
& SH_SERIAL_FLAG_TEND
)
164 if (s
->flags
& SH_SERIAL_FLAG_TDE
)
166 if (s
->flags
& SH_SERIAL_FLAG_BRK
)
168 if (s
->flags
& SH_SERIAL_FLAG_RDF
)
170 if (s
->flags
& SH_SERIAL_FLAG_DR
)
173 if (s
->scr
& (1 << 5))
174 s
->flags
|= SH_SERIAL_FLAG_TDE
| SH_SERIAL_FLAG_TEND
;
209 printf("sh_serial: read base=0x%08lx offs=0x%02x val=0x%x\n",
210 (unsigned long) s
->base
, offs
, ret
);
213 if (ret
& ~((1 << 16) - 1)) {
214 fprintf(stderr
, "sh_serial: unsupported read from 0x%02x\n", offs
);
221 static int sh_serial_can_receive(sh_serial_state
*s
)
226 static void sh_serial_receive_byte(sh_serial_state
*s
, int ch
)
230 static void sh_serial_receive_break(sh_serial_state
*s
)
234 static int sh_serial_can_receive1(void *opaque
)
236 sh_serial_state
*s
= opaque
;
237 return sh_serial_can_receive(s
);
240 static void sh_serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
242 sh_serial_state
*s
= opaque
;
243 sh_serial_receive_byte(s
, buf
[0]);
246 static void sh_serial_event(void *opaque
, int event
)
248 sh_serial_state
*s
= opaque
;
249 if (event
== CHR_EVENT_BREAK
)
250 sh_serial_receive_break(s
);
253 uint32_t sh_serial_read (void *opaque
, target_phys_addr_t addr
)
255 sh_serial_state
*s
= opaque
;
256 return sh_serial_ioport_read(s
, addr
- s
->base
);
259 void sh_serial_write (void *opaque
,
260 target_phys_addr_t addr
, uint32_t value
)
262 sh_serial_state
*s
= opaque
;
263 sh_serial_ioport_write(s
, addr
- s
->base
, value
);
266 static CPUReadMemoryFunc
*sh_serial_readfn
[] = {
272 static CPUWriteMemoryFunc
*sh_serial_writefn
[] = {
278 void sh_serial_init (target_phys_addr_t base
, int feat
,
279 uint32_t freq
, CharDriverState
*chr
)
284 s
= qemu_mallocz(sizeof(sh_serial_state
));
290 s
->flags
= SH_SERIAL_FLAG_TEND
| SH_SERIAL_FLAG_TDE
;
297 if (feat
& SH_SERIAL_FEAT_SCIF
) {
306 s_io_memory
= cpu_register_io_memory(0, sh_serial_readfn
,
307 sh_serial_writefn
, s
);
308 cpu_register_physical_memory(base
, 0x28, s_io_memory
);
313 qemu_chr_add_handlers(chr
, sh_serial_can_receive1
, sh_serial_receive1
,