2 * Intel XScale PXA255/270 processor support.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
7 * This code is licenced under the GPL.
13 target_phys_addr_t io_base
;
16 { 0x40100000, PXA2XX_PIC_FFUART
},
17 { 0x40200000, PXA2XX_PIC_BTUART
},
18 { 0x40700000, PXA2XX_PIC_STUART
},
19 { 0x41600000, PXA25X_PIC_HWUART
},
21 }, pxa270_serial
[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART
},
23 { 0x40200000, PXA2XX_PIC_BTUART
},
24 { 0x40700000, PXA2XX_PIC_STUART
},
29 target_phys_addr_t io_base
;
32 { 0x41000000, PXA2XX_PIC_SSP
},
35 { 0x41000000, PXA2XX_PIC_SSP
},
36 { 0x41400000, PXA25X_PIC_NSSP
},
39 { 0x41000000, PXA2XX_PIC_SSP
},
40 { 0x41400000, PXA25X_PIC_NSSP
},
41 { 0x41500000, PXA26X_PIC_ASSP
},
44 { 0x41000000, PXA2XX_PIC_SSP
},
45 { 0x41700000, PXA27X_PIC_SSP2
},
46 { 0x41900000, PXA2XX_PIC_SSP3
},
50 #define PMCR 0x00 /* Power Manager Control register */
51 #define PSSR 0x04 /* Power Manager Sleep Status register */
52 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
53 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
54 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
55 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
56 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
57 #define PCFR 0x1c /* Power Manager General Configuration register */
58 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
59 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
60 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
61 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
62 #define RCSR 0x30 /* Reset Controller Status register */
63 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
64 #define PTSR 0x38 /* Power Manager Standby Configuration register */
65 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
66 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
67 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
68 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
69 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
70 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
72 static uint32_t pxa2xx_pm_read(void *opaque
, target_phys_addr_t addr
)
74 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
82 return s
->pm_regs
[addr
>> 2];
85 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
91 static void pxa2xx_pm_write(void *opaque
, target_phys_addr_t addr
,
94 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
99 s
->pm_regs
[addr
>> 2] &= 0x15 & ~(value
& 0x2a);
100 s
->pm_regs
[addr
>> 2] |= value
& 0x15;
103 case PSSR
: /* Read-clean registers */
106 s
->pm_regs
[addr
>> 2] &= ~value
;
109 default: /* Read-write registers */
110 if (addr
>= PMCR
&& addr
<= PCMD31
&& !(addr
& 3)) {
111 s
->pm_regs
[addr
>> 2] = value
;
115 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
120 static CPUReadMemoryFunc
*pxa2xx_pm_readfn
[] = {
126 static CPUWriteMemoryFunc
*pxa2xx_pm_writefn
[] = {
132 static void pxa2xx_pm_save(QEMUFile
*f
, void *opaque
)
134 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
137 for (i
= 0; i
< 0x40; i
++)
138 qemu_put_be32s(f
, &s
->pm_regs
[i
]);
141 static int pxa2xx_pm_load(QEMUFile
*f
, void *opaque
, int version_id
)
143 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
146 for (i
= 0; i
< 0x40; i
++)
147 qemu_get_be32s(f
, &s
->pm_regs
[i
]);
152 #define CCCR 0x00 /* Core Clock Configuration register */
153 #define CKEN 0x04 /* Clock Enable register */
154 #define OSCC 0x08 /* Oscillator Configuration register */
155 #define CCSR 0x0c /* Core Clock Status register */
157 static uint32_t pxa2xx_cm_read(void *opaque
, target_phys_addr_t addr
)
159 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
166 return s
->cm_regs
[addr
>> 2];
169 return s
->cm_regs
[CCCR
>> 2] | (3 << 28);
172 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
178 static void pxa2xx_cm_write(void *opaque
, target_phys_addr_t addr
,
181 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
187 s
->cm_regs
[addr
>> 2] = value
;
191 s
->cm_regs
[addr
>> 2] &= ~0x6c;
192 s
->cm_regs
[addr
>> 2] |= value
& 0x6e;
193 if ((value
>> 1) & 1) /* OON */
194 s
->cm_regs
[addr
>> 2] |= 1 << 0; /* Oscillator is now stable */
198 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
203 static CPUReadMemoryFunc
*pxa2xx_cm_readfn
[] = {
209 static CPUWriteMemoryFunc
*pxa2xx_cm_writefn
[] = {
215 static void pxa2xx_cm_save(QEMUFile
*f
, void *opaque
)
217 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
220 for (i
= 0; i
< 4; i
++)
221 qemu_put_be32s(f
, &s
->cm_regs
[i
]);
222 qemu_put_be32s(f
, &s
->clkcfg
);
223 qemu_put_be32s(f
, &s
->pmnc
);
226 static int pxa2xx_cm_load(QEMUFile
*f
, void *opaque
, int version_id
)
228 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
231 for (i
= 0; i
< 4; i
++)
232 qemu_get_be32s(f
, &s
->cm_regs
[i
]);
233 qemu_get_be32s(f
, &s
->clkcfg
);
234 qemu_get_be32s(f
, &s
->pmnc
);
239 static uint32_t pxa2xx_clkpwr_read(void *opaque
, int op2
, int reg
, int crm
)
241 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
244 case 6: /* Clock Configuration register */
247 case 7: /* Power Mode register */
251 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
257 static void pxa2xx_clkpwr_write(void *opaque
, int op2
, int reg
, int crm
,
260 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
261 static const char *pwrmode
[8] = {
262 "Normal", "Idle", "Deep-idle", "Standby",
263 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
267 case 6: /* Clock Configuration register */
268 s
->clkcfg
= value
& 0xf;
270 printf("%s: CPU frequency change attempt\n", __FUNCTION__
);
273 case 7: /* Power Mode register */
275 printf("%s: CPU voltage change attempt\n", __FUNCTION__
);
283 if (!(s
->cm_regs
[CCCR
>> 2] & (1 << 31))) { /* CPDIS */
284 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
291 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
292 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
296 s
->env
->uncached_cpsr
=
297 ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
298 s
->env
->cp15
.c1_sys
= 0;
299 s
->env
->cp15
.c1_coproc
= 0;
300 s
->env
->cp15
.c2_base
= 0;
302 s
->pm_regs
[PSSR
>> 2] |= 0x8; /* Set STS */
303 s
->pm_regs
[RCSR
>> 2] |= 0x8; /* Set GPR */
306 * The scratch-pad register is almost universally used
307 * for storing the return address on suspend. For the
308 * lack of a resuming bootloader, perform a jump
309 * directly to that address.
311 memset(s
->env
->regs
, 0, 4 * 15);
312 s
->env
->regs
[15] = s
->pm_regs
[PSPR
>> 2];
315 buffer
= 0xe59ff000; /* ldr pc, [pc, #0] */
316 cpu_physical_memory_write(0, &buffer
, 4);
317 buffer
= s
->pm_regs
[PSPR
>> 2];
318 cpu_physical_memory_write(8, &buffer
, 4);
322 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
328 printf("%s: machine entered %s mode\n", __FUNCTION__
,
334 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
339 /* Performace Monitoring Registers */
340 #define CPPMNC 0 /* Performance Monitor Control register */
341 #define CPCCNT 1 /* Clock Counter register */
342 #define CPINTEN 4 /* Interrupt Enable register */
343 #define CPFLAG 5 /* Overflow Flag register */
344 #define CPEVTSEL 8 /* Event Selection register */
346 #define CPPMN0 0 /* Performance Count register 0 */
347 #define CPPMN1 1 /* Performance Count register 1 */
348 #define CPPMN2 2 /* Performance Count register 2 */
349 #define CPPMN3 3 /* Performance Count register 3 */
351 static uint32_t pxa2xx_perf_read(void *opaque
, int op2
, int reg
, int crm
)
353 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
360 return qemu_get_clock(vm_clock
);
369 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
375 static void pxa2xx_perf_write(void *opaque
, int op2
, int reg
, int crm
,
378 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
392 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
397 static uint32_t pxa2xx_cp14_read(void *opaque
, int op2
, int reg
, int crm
)
401 return pxa2xx_clkpwr_read(opaque
, op2
, reg
, crm
);
403 return pxa2xx_perf_read(opaque
, op2
, reg
, crm
);
414 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
420 static void pxa2xx_cp14_write(void *opaque
, int op2
, int reg
, int crm
,
425 pxa2xx_clkpwr_write(opaque
, op2
, reg
, crm
, value
);
428 pxa2xx_perf_write(opaque
, op2
, reg
, crm
, value
);
440 printf("%s: Bad register 0x%x\n", __FUNCTION__
, reg
);
445 #define MDCNFG 0x00 /* SDRAM Configuration register */
446 #define MDREFR 0x04 /* SDRAM Refresh Control register */
447 #define MSC0 0x08 /* Static Memory Control register 0 */
448 #define MSC1 0x0c /* Static Memory Control register 1 */
449 #define MSC2 0x10 /* Static Memory Control register 2 */
450 #define MECR 0x14 /* Expansion Memory Bus Config register */
451 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
452 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
453 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
454 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
455 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
456 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
457 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
458 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
459 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
460 #define ARB_CNTL 0x48 /* Arbiter Control register */
461 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
462 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
463 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
464 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
465 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
466 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
467 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
469 static uint32_t pxa2xx_mm_read(void *opaque
, target_phys_addr_t addr
)
471 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
475 case MDCNFG
... SA1110
:
477 return s
->mm_regs
[addr
>> 2];
480 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
486 static void pxa2xx_mm_write(void *opaque
, target_phys_addr_t addr
,
489 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
493 case MDCNFG
... SA1110
:
494 if ((addr
& 3) == 0) {
495 s
->mm_regs
[addr
>> 2] = value
;
500 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
505 static CPUReadMemoryFunc
*pxa2xx_mm_readfn
[] = {
511 static CPUWriteMemoryFunc
*pxa2xx_mm_writefn
[] = {
517 static void pxa2xx_mm_save(QEMUFile
*f
, void *opaque
)
519 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
522 for (i
= 0; i
< 0x1a; i
++)
523 qemu_put_be32s(f
, &s
->mm_regs
[i
]);
526 static int pxa2xx_mm_load(QEMUFile
*f
, void *opaque
, int version_id
)
528 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
531 for (i
= 0; i
< 0x1a; i
++)
532 qemu_get_be32s(f
, &s
->mm_regs
[i
]);
537 /* Synchronous Serial Ports */
538 struct pxa2xx_ssp_s
{
539 target_phys_addr_t base
;
552 uint32_t rx_fifo
[16];
556 uint32_t (*readfn
)(void *opaque
);
557 void (*writefn
)(void *opaque
, uint32_t value
);
561 #define SSCR0 0x00 /* SSP Control register 0 */
562 #define SSCR1 0x04 /* SSP Control register 1 */
563 #define SSSR 0x08 /* SSP Status register */
564 #define SSITR 0x0c /* SSP Interrupt Test register */
565 #define SSDR 0x10 /* SSP Data register */
566 #define SSTO 0x28 /* SSP Time-Out register */
567 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
568 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
569 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
570 #define SSTSS 0x38 /* SSP Time Slot Status register */
571 #define SSACD 0x3c /* SSP Audio Clock Divider register */
573 /* Bitfields for above registers */
574 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
575 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
576 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
577 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
578 #define SSCR0_SSE (1 << 7)
579 #define SSCR0_RIM (1 << 22)
580 #define SSCR0_TIM (1 << 23)
581 #define SSCR0_MOD (1 << 31)
582 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
583 #define SSCR1_RIE (1 << 0)
584 #define SSCR1_TIE (1 << 1)
585 #define SSCR1_LBM (1 << 2)
586 #define SSCR1_MWDS (1 << 5)
587 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
588 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
589 #define SSCR1_EFWR (1 << 14)
590 #define SSCR1_PINTE (1 << 18)
591 #define SSCR1_TINTE (1 << 19)
592 #define SSCR1_RSRE (1 << 20)
593 #define SSCR1_TSRE (1 << 21)
594 #define SSCR1_EBCEI (1 << 29)
595 #define SSITR_INT (7 << 5)
596 #define SSSR_TNF (1 << 2)
597 #define SSSR_RNE (1 << 3)
598 #define SSSR_TFS (1 << 5)
599 #define SSSR_RFS (1 << 6)
600 #define SSSR_ROR (1 << 7)
601 #define SSSR_PINT (1 << 18)
602 #define SSSR_TINT (1 << 19)
603 #define SSSR_EOC (1 << 20)
604 #define SSSR_TUR (1 << 21)
605 #define SSSR_BCE (1 << 23)
606 #define SSSR_RW 0x00bc0080
608 static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s
*s
)
612 level
|= s
->ssitr
& SSITR_INT
;
613 level
|= (s
->sssr
& SSSR_BCE
) && (s
->sscr
[1] & SSCR1_EBCEI
);
614 level
|= (s
->sssr
& SSSR_TUR
) && !(s
->sscr
[0] & SSCR0_TIM
);
615 level
|= (s
->sssr
& SSSR_EOC
) && (s
->sssr
& (SSSR_TINT
| SSSR_PINT
));
616 level
|= (s
->sssr
& SSSR_TINT
) && (s
->sscr
[1] & SSCR1_TINTE
);
617 level
|= (s
->sssr
& SSSR_PINT
) && (s
->sscr
[1] & SSCR1_PINTE
);
618 level
|= (s
->sssr
& SSSR_ROR
) && !(s
->sscr
[0] & SSCR0_RIM
);
619 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
620 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
621 qemu_set_irq(s
->irq
, !!level
);
624 static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s
*s
)
626 s
->sssr
&= ~(0xf << 12); /* Clear RFL */
627 s
->sssr
&= ~(0xf << 8); /* Clear TFL */
628 s
->sssr
&= ~SSSR_TNF
;
630 s
->sssr
|= ((s
->rx_level
- 1) & 0xf) << 12;
631 if (s
->rx_level
>= SSCR1_RFT(s
->sscr
[1]))
634 s
->sssr
&= ~SSSR_RFS
;
635 if (0 <= SSCR1_TFT(s
->sscr
[1]))
638 s
->sssr
&= ~SSSR_TFS
;
642 s
->sssr
&= ~SSSR_RNE
;
646 pxa2xx_ssp_int_update(s
);
649 static uint32_t pxa2xx_ssp_read(void *opaque
, target_phys_addr_t addr
)
651 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
667 return s
->sssr
| s
->ssitr
;
671 if (s
->rx_level
< 1) {
672 printf("%s: SSP Rx Underrun\n", __FUNCTION__
);
676 retval
= s
->rx_fifo
[s
->rx_start
++];
678 pxa2xx_ssp_fifo_update(s
);
689 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
695 static void pxa2xx_ssp_write(void *opaque
, target_phys_addr_t addr
,
698 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
703 s
->sscr
[0] = value
& 0xc7ffffff;
704 s
->enable
= value
& SSCR0_SSE
;
705 if (value
& SSCR0_MOD
)
706 printf("%s: Attempt to use network mode\n", __FUNCTION__
);
707 if (s
->enable
&& SSCR0_DSS(value
) < 4)
708 printf("%s: Wrong data size: %i bits\n", __FUNCTION__
,
710 if (!(value
& SSCR0_SSE
)) {
715 pxa2xx_ssp_fifo_update(s
);
720 if (value
& (SSCR1_LBM
| SSCR1_EFWR
))
721 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__
);
722 pxa2xx_ssp_fifo_update(s
);
734 s
->ssitr
= value
& SSITR_INT
;
735 pxa2xx_ssp_int_update(s
);
739 s
->sssr
&= ~(value
& SSSR_RW
);
740 pxa2xx_ssp_int_update(s
);
744 if (SSCR0_UWIRE(s
->sscr
[0])) {
745 if (s
->sscr
[1] & SSCR1_MWDS
)
750 /* Note how 32bits overflow does no harm here */
751 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
753 /* Data goes from here to the Tx FIFO and is shifted out from
754 * there directly to the slave, no need to buffer it.
758 s
->writefn(s
->opaque
, value
);
760 if (s
->rx_level
< 0x10) {
762 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] =
763 s
->readfn(s
->opaque
);
765 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0xf] = 0x0;
769 pxa2xx_ssp_fifo_update(s
);
785 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
790 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s
*port
,
791 uint32_t (*readfn
)(void *opaque
),
792 void (*writefn
)(void *opaque
, uint32_t value
), void *opaque
)
795 printf("%s: no such SSP\n", __FUNCTION__
);
799 port
->opaque
= opaque
;
800 port
->readfn
= readfn
;
801 port
->writefn
= writefn
;
804 static CPUReadMemoryFunc
*pxa2xx_ssp_readfn
[] = {
810 static CPUWriteMemoryFunc
*pxa2xx_ssp_writefn
[] = {
816 static void pxa2xx_ssp_save(QEMUFile
*f
, void *opaque
)
818 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
821 qemu_put_be32(f
, s
->enable
);
823 qemu_put_be32s(f
, &s
->sscr
[0]);
824 qemu_put_be32s(f
, &s
->sscr
[1]);
825 qemu_put_be32s(f
, &s
->sspsp
);
826 qemu_put_be32s(f
, &s
->ssto
);
827 qemu_put_be32s(f
, &s
->ssitr
);
828 qemu_put_be32s(f
, &s
->sssr
);
829 qemu_put_8s(f
, &s
->sstsa
);
830 qemu_put_8s(f
, &s
->ssrsa
);
831 qemu_put_8s(f
, &s
->ssacd
);
833 qemu_put_byte(f
, s
->rx_level
);
834 for (i
= 0; i
< s
->rx_level
; i
++)
835 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 0xf]);
838 static int pxa2xx_ssp_load(QEMUFile
*f
, void *opaque
, int version_id
)
840 struct pxa2xx_ssp_s
*s
= (struct pxa2xx_ssp_s
*) opaque
;
843 s
->enable
= qemu_get_be32(f
);
845 qemu_get_be32s(f
, &s
->sscr
[0]);
846 qemu_get_be32s(f
, &s
->sscr
[1]);
847 qemu_get_be32s(f
, &s
->sspsp
);
848 qemu_get_be32s(f
, &s
->ssto
);
849 qemu_get_be32s(f
, &s
->ssitr
);
850 qemu_get_be32s(f
, &s
->sssr
);
851 qemu_get_8s(f
, &s
->sstsa
);
852 qemu_get_8s(f
, &s
->ssrsa
);
853 qemu_get_8s(f
, &s
->ssacd
);
855 s
->rx_level
= qemu_get_byte(f
);
857 for (i
= 0; i
< s
->rx_level
; i
++)
858 s
->rx_fifo
[i
] = qemu_get_byte(f
);
863 /* Real-Time Clock */
864 #define RCNR 0x00 /* RTC Counter register */
865 #define RTAR 0x04 /* RTC Alarm register */
866 #define RTSR 0x08 /* RTC Status register */
867 #define RTTR 0x0c /* RTC Timer Trim register */
868 #define RDCR 0x10 /* RTC Day Counter register */
869 #define RYCR 0x14 /* RTC Year Counter register */
870 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
871 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
872 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
873 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
874 #define SWCR 0x28 /* RTC Stopwatch Counter register */
875 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
876 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
877 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
878 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
880 static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s
*s
)
882 qemu_set_irq(s
->pic
[PXA2XX_PIC_RTCALARM
], !!(s
->rtsr
& 0x2553));
885 static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s
*s
)
887 int64_t rt
= qemu_get_clock(rt_clock
);
888 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
889 (1000 * ((s
->rttr
& 0xffff) + 1));
890 s
->last_rdcr
+= ((rt
- s
->last_hz
) << 15) /
891 (1000 * ((s
->rttr
& 0xffff) + 1));
895 static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s
*s
)
897 int64_t rt
= qemu_get_clock(rt_clock
);
898 if (s
->rtsr
& (1 << 12))
899 s
->last_swcr
+= (rt
- s
->last_sw
) / 10;
903 static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s
*s
)
905 int64_t rt
= qemu_get_clock(rt_clock
);
906 if (s
->rtsr
& (1 << 15))
907 s
->last_swcr
+= rt
- s
->last_pi
;
911 static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s
*s
,
914 if ((rtsr
& (1 << 2)) && !(rtsr
& (1 << 0)))
915 qemu_mod_timer(s
->rtc_hz
, s
->last_hz
+
916 (((s
->rtar
- s
->last_rcnr
) * 1000 *
917 ((s
->rttr
& 0xffff) + 1)) >> 15));
919 qemu_del_timer(s
->rtc_hz
);
921 if ((rtsr
& (1 << 5)) && !(rtsr
& (1 << 4)))
922 qemu_mod_timer(s
->rtc_rdal1
, s
->last_hz
+
923 (((s
->rdar1
- s
->last_rdcr
) * 1000 *
924 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
926 qemu_del_timer(s
->rtc_rdal1
);
928 if ((rtsr
& (1 << 7)) && !(rtsr
& (1 << 6)))
929 qemu_mod_timer(s
->rtc_rdal2
, s
->last_hz
+
930 (((s
->rdar2
- s
->last_rdcr
) * 1000 *
931 ((s
->rttr
& 0xffff) + 1)) >> 15)); /* TODO: fixup */
933 qemu_del_timer(s
->rtc_rdal2
);
935 if ((rtsr
& 0x1200) == 0x1200 && !(rtsr
& (1 << 8)))
936 qemu_mod_timer(s
->rtc_swal1
, s
->last_sw
+
937 (s
->swar1
- s
->last_swcr
) * 10); /* TODO: fixup */
939 qemu_del_timer(s
->rtc_swal1
);
941 if ((rtsr
& 0x1800) == 0x1800 && !(rtsr
& (1 << 10)))
942 qemu_mod_timer(s
->rtc_swal2
, s
->last_sw
+
943 (s
->swar2
- s
->last_swcr
) * 10); /* TODO: fixup */
945 qemu_del_timer(s
->rtc_swal2
);
947 if ((rtsr
& 0xc000) == 0xc000 && !(rtsr
& (1 << 13)))
948 qemu_mod_timer(s
->rtc_pi
, s
->last_pi
+
949 (s
->piar
& 0xffff) - s
->last_rtcpicr
);
951 qemu_del_timer(s
->rtc_pi
);
954 static inline void pxa2xx_rtc_hz_tick(void *opaque
)
956 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
958 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
959 pxa2xx_rtc_int_update(s
);
962 static inline void pxa2xx_rtc_rdal1_tick(void *opaque
)
964 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
966 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
967 pxa2xx_rtc_int_update(s
);
970 static inline void pxa2xx_rtc_rdal2_tick(void *opaque
)
972 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
974 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
975 pxa2xx_rtc_int_update(s
);
978 static inline void pxa2xx_rtc_swal1_tick(void *opaque
)
980 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
982 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
983 pxa2xx_rtc_int_update(s
);
986 static inline void pxa2xx_rtc_swal2_tick(void *opaque
)
988 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
989 s
->rtsr
|= (1 << 10);
990 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
991 pxa2xx_rtc_int_update(s
);
994 static inline void pxa2xx_rtc_pi_tick(void *opaque
)
996 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
997 s
->rtsr
|= (1 << 13);
998 pxa2xx_rtc_piupdate(s
);
1000 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1001 pxa2xx_rtc_int_update(s
);
1004 static uint32_t pxa2xx_rtc_read(void *opaque
, target_phys_addr_t addr
)
1006 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1007 addr
-= s
->rtc_base
;
1031 return s
->last_rcnr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
1032 (1000 * ((s
->rttr
& 0xffff) + 1));
1034 return s
->last_rdcr
+ ((qemu_get_clock(rt_clock
) - s
->last_hz
) << 15) /
1035 (1000 * ((s
->rttr
& 0xffff) + 1));
1037 return s
->last_rycr
;
1039 if (s
->rtsr
& (1 << 12))
1040 return s
->last_swcr
+ (qemu_get_clock(rt_clock
) - s
->last_sw
) / 10;
1042 return s
->last_swcr
;
1044 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1050 static void pxa2xx_rtc_write(void *opaque
, target_phys_addr_t addr
,
1053 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1054 addr
-= s
->rtc_base
;
1058 if (!(s
->rttr
& (1 << 31))) {
1059 pxa2xx_rtc_hzupdate(s
);
1061 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1066 if ((s
->rtsr
^ value
) & (1 << 15))
1067 pxa2xx_rtc_piupdate(s
);
1069 if ((s
->rtsr
^ value
) & (1 << 12))
1070 pxa2xx_rtc_swupdate(s
);
1072 if (((s
->rtsr
^ value
) & 0x4aac) | (value
& ~0xdaac))
1073 pxa2xx_rtc_alarm_update(s
, value
);
1075 s
->rtsr
= (value
& 0xdaac) | (s
->rtsr
& ~(value
& ~0xdaac));
1076 pxa2xx_rtc_int_update(s
);
1081 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1086 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1091 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1096 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1101 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1105 pxa2xx_rtc_swupdate(s
);
1108 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1113 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1118 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1122 pxa2xx_rtc_hzupdate(s
);
1123 s
->last_rcnr
= value
;
1124 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1128 pxa2xx_rtc_hzupdate(s
);
1129 s
->last_rdcr
= value
;
1130 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1134 s
->last_rycr
= value
;
1138 pxa2xx_rtc_swupdate(s
);
1139 s
->last_swcr
= value
;
1140 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1144 pxa2xx_rtc_piupdate(s
);
1145 s
->last_rtcpicr
= value
& 0xffff;
1146 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1150 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1154 static CPUReadMemoryFunc
*pxa2xx_rtc_readfn
[] = {
1160 static CPUWriteMemoryFunc
*pxa2xx_rtc_writefn
[] = {
1166 static void pxa2xx_rtc_init(struct pxa2xx_state_s
*s
)
1179 tm
= localtime(&ti
);
1180 wom
= ((tm
->tm_mday
- 1) / 7) + 1;
1182 s
->last_rcnr
= (uint32_t) ti
;
1183 s
->last_rdcr
= (wom
<< 20) | ((tm
->tm_wday
+ 1) << 17) |
1184 (tm
->tm_hour
<< 12) | (tm
->tm_min
<< 6) | tm
->tm_sec
;
1185 s
->last_rycr
= ((tm
->tm_year
+ 1900) << 9) |
1186 ((tm
->tm_mon
+ 1) << 5) | tm
->tm_mday
;
1187 s
->last_swcr
= (tm
->tm_hour
<< 19) |
1188 (tm
->tm_min
<< 13) | (tm
->tm_sec
<< 7);
1189 s
->last_rtcpicr
= 0;
1190 s
->last_hz
= s
->last_sw
= s
->last_pi
= qemu_get_clock(rt_clock
);
1192 s
->rtc_hz
= qemu_new_timer(rt_clock
, pxa2xx_rtc_hz_tick
, s
);
1193 s
->rtc_rdal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal1_tick
, s
);
1194 s
->rtc_rdal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_rdal2_tick
, s
);
1195 s
->rtc_swal1
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal1_tick
, s
);
1196 s
->rtc_swal2
= qemu_new_timer(rt_clock
, pxa2xx_rtc_swal2_tick
, s
);
1197 s
->rtc_pi
= qemu_new_timer(rt_clock
, pxa2xx_rtc_pi_tick
, s
);
1200 static void pxa2xx_rtc_save(QEMUFile
*f
, void *opaque
)
1202 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1204 pxa2xx_rtc_hzupdate(s
);
1205 pxa2xx_rtc_piupdate(s
);
1206 pxa2xx_rtc_swupdate(s
);
1208 qemu_put_be32s(f
, &s
->rttr
);
1209 qemu_put_be32s(f
, &s
->rtsr
);
1210 qemu_put_be32s(f
, &s
->rtar
);
1211 qemu_put_be32s(f
, &s
->rdar1
);
1212 qemu_put_be32s(f
, &s
->rdar2
);
1213 qemu_put_be32s(f
, &s
->ryar1
);
1214 qemu_put_be32s(f
, &s
->ryar2
);
1215 qemu_put_be32s(f
, &s
->swar1
);
1216 qemu_put_be32s(f
, &s
->swar2
);
1217 qemu_put_be32s(f
, &s
->piar
);
1218 qemu_put_be32s(f
, &s
->last_rcnr
);
1219 qemu_put_be32s(f
, &s
->last_rdcr
);
1220 qemu_put_be32s(f
, &s
->last_rycr
);
1221 qemu_put_be32s(f
, &s
->last_swcr
);
1222 qemu_put_be32s(f
, &s
->last_rtcpicr
);
1223 qemu_put_be64s(f
, &s
->last_hz
);
1224 qemu_put_be64s(f
, &s
->last_sw
);
1225 qemu_put_be64s(f
, &s
->last_pi
);
1228 static int pxa2xx_rtc_load(QEMUFile
*f
, void *opaque
, int version_id
)
1230 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
1232 qemu_get_be32s(f
, &s
->rttr
);
1233 qemu_get_be32s(f
, &s
->rtsr
);
1234 qemu_get_be32s(f
, &s
->rtar
);
1235 qemu_get_be32s(f
, &s
->rdar1
);
1236 qemu_get_be32s(f
, &s
->rdar2
);
1237 qemu_get_be32s(f
, &s
->ryar1
);
1238 qemu_get_be32s(f
, &s
->ryar2
);
1239 qemu_get_be32s(f
, &s
->swar1
);
1240 qemu_get_be32s(f
, &s
->swar2
);
1241 qemu_get_be32s(f
, &s
->piar
);
1242 qemu_get_be32s(f
, &s
->last_rcnr
);
1243 qemu_get_be32s(f
, &s
->last_rdcr
);
1244 qemu_get_be32s(f
, &s
->last_rycr
);
1245 qemu_get_be32s(f
, &s
->last_swcr
);
1246 qemu_get_be32s(f
, &s
->last_rtcpicr
);
1247 qemu_get_be64s(f
, &s
->last_hz
);
1248 qemu_get_be64s(f
, &s
->last_sw
);
1249 qemu_get_be64s(f
, &s
->last_pi
);
1251 pxa2xx_rtc_alarm_update(s
, s
->rtsr
);
1257 struct pxa2xx_i2c_s
{
1260 target_phys_addr_t base
;
1269 #define IBMR 0x80 /* I2C Bus Monitor register */
1270 #define IDBR 0x88 /* I2C Data Buffer register */
1271 #define ICR 0x90 /* I2C Control register */
1272 #define ISR 0x98 /* I2C Status register */
1273 #define ISAR 0xa0 /* I2C Slave Address register */
1275 static void pxa2xx_i2c_update(struct pxa2xx_i2c_s
*s
)
1278 level
|= s
->status
& s
->control
& (1 << 10); /* BED */
1279 level
|= (s
->status
& (1 << 7)) && (s
->control
& (1 << 9)); /* IRF */
1280 level
|= (s
->status
& (1 << 6)) && (s
->control
& (1 << 8)); /* ITE */
1281 level
|= s
->status
& (1 << 9); /* SAD */
1282 qemu_set_irq(s
->irq
, !!level
);
1285 /* These are only stubs now. */
1286 static void pxa2xx_i2c_event(i2c_slave
*i2c
, enum i2c_event event
)
1288 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) i2c
;
1291 case I2C_START_SEND
:
1292 s
->status
|= (1 << 9); /* set SAD */
1293 s
->status
&= ~(1 << 0); /* clear RWM */
1295 case I2C_START_RECV
:
1296 s
->status
|= (1 << 9); /* set SAD */
1297 s
->status
|= 1 << 0; /* set RWM */
1300 s
->status
|= (1 << 4); /* set SSD */
1303 s
->status
|= 1 << 1; /* set ACKNAK */
1306 pxa2xx_i2c_update(s
);
1309 static int pxa2xx_i2c_rx(i2c_slave
*i2c
)
1311 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) i2c
;
1312 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1315 if (s
->status
& (1 << 0)) { /* RWM */
1316 s
->status
|= 1 << 6; /* set ITE */
1318 pxa2xx_i2c_update(s
);
1323 static int pxa2xx_i2c_tx(i2c_slave
*i2c
, uint8_t data
)
1325 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) i2c
;
1326 if ((s
->control
& (1 << 14)) || !(s
->control
& (1 << 6)))
1329 if (!(s
->status
& (1 << 0))) { /* RWM */
1330 s
->status
|= 1 << 7; /* set IRF */
1333 pxa2xx_i2c_update(s
);
1338 static uint32_t pxa2xx_i2c_read(void *opaque
, target_phys_addr_t addr
)
1340 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1347 return s
->status
| (i2c_bus_busy(s
->bus
) << 2);
1349 return s
->slave
.address
;
1353 if (s
->status
& (1 << 2))
1354 s
->ibmr
^= 3; /* Fake SCL and SDA pin changes */
1359 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1365 static void pxa2xx_i2c_write(void *opaque
, target_phys_addr_t addr
,
1368 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1374 s
->control
= value
& 0xfff7;
1375 if ((value
& (1 << 3)) && (value
& (1 << 6))) { /* TB and IUE */
1376 /* TODO: slave mode */
1377 if (value
& (1 << 0)) { /* START condition */
1379 s
->status
|= 1 << 0; /* set RWM */
1381 s
->status
&= ~(1 << 0); /* clear RWM */
1382 ack
= !i2c_start_transfer(s
->bus
, s
->data
>> 1, s
->data
& 1);
1384 if (s
->status
& (1 << 0)) { /* RWM */
1385 s
->data
= i2c_recv(s
->bus
);
1386 if (value
& (1 << 2)) /* ACKNAK */
1390 ack
= !i2c_send(s
->bus
, s
->data
);
1393 if (value
& (1 << 1)) /* STOP condition */
1394 i2c_end_transfer(s
->bus
);
1397 if (value
& (1 << 0)) /* START condition */
1398 s
->status
|= 1 << 6; /* set ITE */
1400 if (s
->status
& (1 << 0)) /* RWM */
1401 s
->status
|= 1 << 7; /* set IRF */
1403 s
->status
|= 1 << 6; /* set ITE */
1404 s
->status
&= ~(1 << 1); /* clear ACKNAK */
1406 s
->status
|= 1 << 6; /* set ITE */
1407 s
->status
|= 1 << 10; /* set BED */
1408 s
->status
|= 1 << 1; /* set ACKNAK */
1411 if (!(value
& (1 << 3)) && (value
& (1 << 6))) /* !TB and IUE */
1412 if (value
& (1 << 4)) /* MA */
1413 i2c_end_transfer(s
->bus
);
1414 pxa2xx_i2c_update(s
);
1418 s
->status
&= ~(value
& 0x07f0);
1419 pxa2xx_i2c_update(s
);
1423 i2c_set_slave_address(&s
->slave
, value
& 0x7f);
1427 s
->data
= value
& 0xff;
1431 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1435 static CPUReadMemoryFunc
*pxa2xx_i2c_readfn
[] = {
1441 static CPUWriteMemoryFunc
*pxa2xx_i2c_writefn
[] = {
1447 static void pxa2xx_i2c_save(QEMUFile
*f
, void *opaque
)
1449 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1451 qemu_put_be16s(f
, &s
->control
);
1452 qemu_put_be16s(f
, &s
->status
);
1453 qemu_put_8s(f
, &s
->ibmr
);
1454 qemu_put_8s(f
, &s
->data
);
1456 i2c_bus_save(f
, s
->bus
);
1457 i2c_slave_save(f
, &s
->slave
);
1460 static int pxa2xx_i2c_load(QEMUFile
*f
, void *opaque
, int version_id
)
1462 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*) opaque
;
1464 qemu_get_be16s(f
, &s
->control
);
1465 qemu_get_be16s(f
, &s
->status
);
1466 qemu_get_8s(f
, &s
->ibmr
);
1467 qemu_get_8s(f
, &s
->data
);
1469 i2c_bus_load(f
, s
->bus
);
1470 i2c_slave_load(f
, &s
->slave
);
1474 struct pxa2xx_i2c_s
*pxa2xx_i2c_init(target_phys_addr_t base
,
1475 qemu_irq irq
, uint32_t page_size
)
1478 struct pxa2xx_i2c_s
*s
= (struct pxa2xx_i2c_s
*)
1479 i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s
));
1483 s
->slave
.event
= pxa2xx_i2c_event
;
1484 s
->slave
.recv
= pxa2xx_i2c_rx
;
1485 s
->slave
.send
= pxa2xx_i2c_tx
;
1486 s
->bus
= i2c_init_bus();
1488 iomemtype
= cpu_register_io_memory(0, pxa2xx_i2c_readfn
,
1489 pxa2xx_i2c_writefn
, s
);
1490 cpu_register_physical_memory(s
->base
& ~page_size
, page_size
, iomemtype
);
1492 register_savevm("pxa2xx_i2c", base
, 0,
1493 pxa2xx_i2c_save
, pxa2xx_i2c_load
, s
);
1498 i2c_bus
*pxa2xx_i2c_bus(struct pxa2xx_i2c_s
*s
)
1503 /* PXA Inter-IC Sound Controller */
1504 static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s
*i2s
)
1510 i2s
->control
[0] = 0x00;
1511 i2s
->control
[1] = 0x00;
1516 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1517 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1518 #define SACR_DREC(val) (val & (1 << 3))
1519 #define SACR_DPRL(val) (val & (1 << 4))
1521 static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s
*i2s
)
1524 rfs
= SACR_RFTH(i2s
->control
[0]) < i2s
->rx_len
&&
1525 !SACR_DREC(i2s
->control
[1]);
1526 tfs
= (i2s
->tx_len
|| i2s
->fifo_len
< SACR_TFTH(i2s
->control
[0])) &&
1527 i2s
->enable
&& !SACR_DPRL(i2s
->control
[1]);
1529 pxa2xx_dma_request(i2s
->dma
, PXA2XX_RX_RQ_I2S
, rfs
);
1530 pxa2xx_dma_request(i2s
->dma
, PXA2XX_TX_RQ_I2S
, tfs
);
1532 i2s
->status
&= 0xe0;
1533 if (i2s
->fifo_len
< 16 || !i2s
->enable
)
1534 i2s
->status
|= 1 << 0; /* TNF */
1536 i2s
->status
|= 1 << 1; /* RNE */
1538 i2s
->status
|= 1 << 2; /* BSY */
1540 i2s
->status
|= 1 << 3; /* TFS */
1542 i2s
->status
|= 1 << 4; /* RFS */
1543 if (!(i2s
->tx_len
&& i2s
->enable
))
1544 i2s
->status
|= i2s
->fifo_len
<< 8; /* TFL */
1545 i2s
->status
|= MAX(i2s
->rx_len
, 0xf) << 12; /* RFL */
1547 qemu_set_irq(i2s
->irq
, i2s
->status
& i2s
->mask
);
1550 #define SACR0 0x00 /* Serial Audio Global Control register */
1551 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1552 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1553 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1554 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1555 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1556 #define SADR 0x80 /* Serial Audio Data register */
1558 static uint32_t pxa2xx_i2s_read(void *opaque
, target_phys_addr_t addr
)
1560 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1565 return s
->control
[0];
1567 return s
->control
[1];
1577 if (s
->rx_len
> 0) {
1579 pxa2xx_i2s_update(s
);
1580 return s
->codec_in(s
->opaque
);
1584 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1590 static void pxa2xx_i2s_write(void *opaque
, target_phys_addr_t addr
,
1593 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1599 if (value
& (1 << 3)) /* RST */
1600 pxa2xx_i2s_reset(s
);
1601 s
->control
[0] = value
& 0xff3d;
1602 if (!s
->enable
&& (value
& 1) && s
->tx_len
) { /* ENB */
1603 for (sample
= s
->fifo
; s
->fifo_len
> 0; s
->fifo_len
--, sample
++)
1604 s
->codec_out(s
->opaque
, *sample
);
1605 s
->status
&= ~(1 << 7); /* I2SOFF */
1607 if (value
& (1 << 4)) /* EFWR */
1608 printf("%s: Attempt to use special function\n", __FUNCTION__
);
1609 s
->enable
= ((value
^ 4) & 5) == 5; /* ENB && !RST*/
1610 pxa2xx_i2s_update(s
);
1613 s
->control
[1] = value
& 0x0039;
1614 if (value
& (1 << 5)) /* ENLBF */
1615 printf("%s: Attempt to use loopback function\n", __FUNCTION__
);
1616 if (value
& (1 << 4)) /* DPRL */
1618 pxa2xx_i2s_update(s
);
1621 s
->mask
= value
& 0x0078;
1622 pxa2xx_i2s_update(s
);
1625 s
->status
&= ~(value
& (3 << 5));
1626 pxa2xx_i2s_update(s
);
1629 s
->clk
= value
& 0x007f;
1632 if (s
->tx_len
&& s
->enable
) {
1634 pxa2xx_i2s_update(s
);
1635 s
->codec_out(s
->opaque
, value
);
1636 } else if (s
->fifo_len
< 16) {
1637 s
->fifo
[s
->fifo_len
++] = value
;
1638 pxa2xx_i2s_update(s
);
1642 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1646 static CPUReadMemoryFunc
*pxa2xx_i2s_readfn
[] = {
1652 static CPUWriteMemoryFunc
*pxa2xx_i2s_writefn
[] = {
1658 static void pxa2xx_i2s_save(QEMUFile
*f
, void *opaque
)
1660 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1662 qemu_put_be32s(f
, &s
->control
[0]);
1663 qemu_put_be32s(f
, &s
->control
[1]);
1664 qemu_put_be32s(f
, &s
->status
);
1665 qemu_put_be32s(f
, &s
->mask
);
1666 qemu_put_be32s(f
, &s
->clk
);
1668 qemu_put_be32(f
, s
->enable
);
1669 qemu_put_be32(f
, s
->rx_len
);
1670 qemu_put_be32(f
, s
->tx_len
);
1671 qemu_put_be32(f
, s
->fifo_len
);
1674 static int pxa2xx_i2s_load(QEMUFile
*f
, void *opaque
, int version_id
)
1676 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1678 qemu_get_be32s(f
, &s
->control
[0]);
1679 qemu_get_be32s(f
, &s
->control
[1]);
1680 qemu_get_be32s(f
, &s
->status
);
1681 qemu_get_be32s(f
, &s
->mask
);
1682 qemu_get_be32s(f
, &s
->clk
);
1684 s
->enable
= qemu_get_be32(f
);
1685 s
->rx_len
= qemu_get_be32(f
);
1686 s
->tx_len
= qemu_get_be32(f
);
1687 s
->fifo_len
= qemu_get_be32(f
);
1692 static void pxa2xx_i2s_data_req(void *opaque
, int tx
, int rx
)
1694 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*) opaque
;
1697 /* Signal FIFO errors */
1698 if (s
->enable
&& s
->tx_len
)
1699 s
->status
|= 1 << 5; /* TUR */
1700 if (s
->enable
&& s
->rx_len
)
1701 s
->status
|= 1 << 6; /* ROR */
1703 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1704 * handle the cases where it makes a difference. */
1705 s
->tx_len
= tx
- s
->fifo_len
;
1707 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1709 for (sample
= s
->fifo
; s
->fifo_len
; s
->fifo_len
--, sample
++)
1710 s
->codec_out(s
->opaque
, *sample
);
1711 pxa2xx_i2s_update(s
);
1714 static struct pxa2xx_i2s_s
*pxa2xx_i2s_init(target_phys_addr_t base
,
1715 qemu_irq irq
, struct pxa2xx_dma_state_s
*dma
)
1718 struct pxa2xx_i2s_s
*s
= (struct pxa2xx_i2s_s
*)
1719 qemu_mallocz(sizeof(struct pxa2xx_i2s_s
));
1724 s
->data_req
= pxa2xx_i2s_data_req
;
1726 pxa2xx_i2s_reset(s
);
1728 iomemtype
= cpu_register_io_memory(0, pxa2xx_i2s_readfn
,
1729 pxa2xx_i2s_writefn
, s
);
1730 cpu_register_physical_memory(s
->base
& 0xfff00000, 0x100000, iomemtype
);
1732 register_savevm("pxa2xx_i2s", base
, 0,
1733 pxa2xx_i2s_save
, pxa2xx_i2s_load
, s
);
1738 /* PXA Fast Infra-red Communications Port */
1739 struct pxa2xx_fir_s
{
1740 target_phys_addr_t base
;
1742 struct pxa2xx_dma_state_s
*dma
;
1744 CharDriverState
*chr
;
1751 uint8_t rx_fifo
[64];
1754 static void pxa2xx_fir_reset(struct pxa2xx_fir_s
*s
)
1756 s
->control
[0] = 0x00;
1757 s
->control
[1] = 0x00;
1758 s
->control
[2] = 0x00;
1759 s
->status
[0] = 0x00;
1760 s
->status
[1] = 0x00;
1764 static inline void pxa2xx_fir_update(struct pxa2xx_fir_s
*s
)
1766 static const int tresh
[4] = { 8, 16, 32, 0 };
1768 if ((s
->control
[0] & (1 << 4)) && /* RXE */
1769 s
->rx_len
>= tresh
[s
->control
[2] & 3]) /* TRIG */
1770 s
->status
[0] |= 1 << 4; /* RFS */
1772 s
->status
[0] &= ~(1 << 4); /* RFS */
1773 if (s
->control
[0] & (1 << 3)) /* TXE */
1774 s
->status
[0] |= 1 << 3; /* TFS */
1776 s
->status
[0] &= ~(1 << 3); /* TFS */
1778 s
->status
[1] |= 1 << 2; /* RNE */
1780 s
->status
[1] &= ~(1 << 2); /* RNE */
1781 if (s
->control
[0] & (1 << 4)) /* RXE */
1782 s
->status
[1] |= 1 << 0; /* RSY */
1784 s
->status
[1] &= ~(1 << 0); /* RSY */
1786 intr
|= (s
->control
[0] & (1 << 5)) && /* RIE */
1787 (s
->status
[0] & (1 << 4)); /* RFS */
1788 intr
|= (s
->control
[0] & (1 << 6)) && /* TIE */
1789 (s
->status
[0] & (1 << 3)); /* TFS */
1790 intr
|= (s
->control
[2] & (1 << 4)) && /* TRAIL */
1791 (s
->status
[0] & (1 << 6)); /* EOC */
1792 intr
|= (s
->control
[0] & (1 << 2)) && /* TUS */
1793 (s
->status
[0] & (1 << 1)); /* TUR */
1794 intr
|= s
->status
[0] & 0x25; /* FRE, RAB, EIF */
1796 pxa2xx_dma_request(s
->dma
, PXA2XX_RX_RQ_ICP
, (s
->status
[0] >> 4) & 1);
1797 pxa2xx_dma_request(s
->dma
, PXA2XX_TX_RQ_ICP
, (s
->status
[0] >> 3) & 1);
1799 qemu_set_irq(s
->irq
, intr
&& s
->enable
);
1802 #define ICCR0 0x00 /* FICP Control register 0 */
1803 #define ICCR1 0x04 /* FICP Control register 1 */
1804 #define ICCR2 0x08 /* FICP Control register 2 */
1805 #define ICDR 0x0c /* FICP Data register */
1806 #define ICSR0 0x14 /* FICP Status register 0 */
1807 #define ICSR1 0x18 /* FICP Status register 1 */
1808 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1810 static uint32_t pxa2xx_fir_read(void *opaque
, target_phys_addr_t addr
)
1812 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1818 return s
->control
[0];
1820 return s
->control
[1];
1822 return s
->control
[2];
1824 s
->status
[0] &= ~0x01;
1825 s
->status
[1] &= ~0x72;
1828 ret
= s
->rx_fifo
[s
->rx_start
++];
1830 pxa2xx_fir_update(s
);
1833 printf("%s: Rx FIFO underrun.\n", __FUNCTION__
);
1836 return s
->status
[0];
1838 return s
->status
[1] | (1 << 3); /* TNF */
1842 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1848 static void pxa2xx_fir_write(void *opaque
, target_phys_addr_t addr
,
1851 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1857 s
->control
[0] = value
;
1858 if (!(value
& (1 << 4))) /* RXE */
1859 s
->rx_len
= s
->rx_start
= 0;
1860 if (!(value
& (1 << 3))) /* TXE */
1862 s
->enable
= value
& 1; /* ITR */
1865 pxa2xx_fir_update(s
);
1868 s
->control
[1] = value
;
1871 s
->control
[2] = value
& 0x3f;
1872 pxa2xx_fir_update(s
);
1875 if (s
->control
[2] & (1 << 2)) /* TXP */
1879 if (s
->chr
&& s
->enable
&& (s
->control
[0] & (1 << 3))) /* TXE */
1880 qemu_chr_write(s
->chr
, &ch
, 1);
1883 s
->status
[0] &= ~(value
& 0x66);
1884 pxa2xx_fir_update(s
);
1889 printf("%s: Bad register " REG_FMT
"\n", __FUNCTION__
, addr
);
1893 static CPUReadMemoryFunc
*pxa2xx_fir_readfn
[] = {
1899 static CPUWriteMemoryFunc
*pxa2xx_fir_writefn
[] = {
1905 static int pxa2xx_fir_is_empty(void *opaque
)
1907 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1908 return (s
->rx_len
< 64);
1911 static void pxa2xx_fir_rx(void *opaque
, const uint8_t *buf
, int size
)
1913 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1914 if (!(s
->control
[0] & (1 << 4))) /* RXE */
1918 s
->status
[1] |= 1 << 4; /* EOF */
1919 if (s
->rx_len
>= 64) {
1920 s
->status
[1] |= 1 << 6; /* ROR */
1924 if (s
->control
[2] & (1 << 3)) /* RXP */
1925 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = *(buf
++);
1927 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
++) & 63] = ~*(buf
++);
1930 pxa2xx_fir_update(s
);
1933 static void pxa2xx_fir_event(void *opaque
, int event
)
1937 static void pxa2xx_fir_save(QEMUFile
*f
, void *opaque
)
1939 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1942 qemu_put_be32(f
, s
->enable
);
1944 qemu_put_8s(f
, &s
->control
[0]);
1945 qemu_put_8s(f
, &s
->control
[1]);
1946 qemu_put_8s(f
, &s
->control
[2]);
1947 qemu_put_8s(f
, &s
->status
[0]);
1948 qemu_put_8s(f
, &s
->status
[1]);
1950 qemu_put_byte(f
, s
->rx_len
);
1951 for (i
= 0; i
< s
->rx_len
; i
++)
1952 qemu_put_byte(f
, s
->rx_fifo
[(s
->rx_start
+ i
) & 63]);
1955 static int pxa2xx_fir_load(QEMUFile
*f
, void *opaque
, int version_id
)
1957 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*) opaque
;
1960 s
->enable
= qemu_get_be32(f
);
1962 qemu_get_8s(f
, &s
->control
[0]);
1963 qemu_get_8s(f
, &s
->control
[1]);
1964 qemu_get_8s(f
, &s
->control
[2]);
1965 qemu_get_8s(f
, &s
->status
[0]);
1966 qemu_get_8s(f
, &s
->status
[1]);
1968 s
->rx_len
= qemu_get_byte(f
);
1970 for (i
= 0; i
< s
->rx_len
; i
++)
1971 s
->rx_fifo
[i
] = qemu_get_byte(f
);
1976 static struct pxa2xx_fir_s
*pxa2xx_fir_init(target_phys_addr_t base
,
1977 qemu_irq irq
, struct pxa2xx_dma_state_s
*dma
,
1978 CharDriverState
*chr
)
1981 struct pxa2xx_fir_s
*s
= (struct pxa2xx_fir_s
*)
1982 qemu_mallocz(sizeof(struct pxa2xx_fir_s
));
1989 pxa2xx_fir_reset(s
);
1991 iomemtype
= cpu_register_io_memory(0, pxa2xx_fir_readfn
,
1992 pxa2xx_fir_writefn
, s
);
1993 cpu_register_physical_memory(s
->base
, 0x1000, iomemtype
);
1996 qemu_chr_add_handlers(chr
, pxa2xx_fir_is_empty
,
1997 pxa2xx_fir_rx
, pxa2xx_fir_event
, s
);
1999 register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save
, pxa2xx_fir_load
, s
);
2004 void pxa2xx_reset(int line
, int level
, void *opaque
)
2006 struct pxa2xx_state_s
*s
= (struct pxa2xx_state_s
*) opaque
;
2007 if (level
&& (s
->pm_regs
[PCFR
>> 2] & 0x10)) { /* GPR_EN */
2009 /* TODO: reset peripherals */
2013 /* Initialise a PXA270 integrated chip (ARM based core). */
2014 struct pxa2xx_state_s
*pxa270_init(unsigned int sdram_size
,
2015 DisplayState
*ds
, const char *revision
)
2017 struct pxa2xx_state_s
*s
;
2018 struct pxa2xx_ssp_s
*ssp
;
2020 s
= (struct pxa2xx_state_s
*) qemu_mallocz(sizeof(struct pxa2xx_state_s
));
2022 if (revision
&& strncmp(revision
, "pxa27", 5)) {
2023 fprintf(stderr
, "Machine requires a PXA27x processor.\n");
2027 s
->env
= cpu_init();
2028 cpu_arm_set_model(s
->env
, revision
?: "pxa270");
2029 register_savevm("cpu", 0, 0, cpu_save
, cpu_load
, s
->env
);
2031 /* SDRAM & Internal Memory Storage */
2032 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
,
2033 sdram_size
, qemu_ram_alloc(sdram_size
) | IO_MEM_RAM
);
2034 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
,
2035 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM
);
2037 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2039 s
->dma
= pxa27x_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
2041 pxa27x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
],
2042 s
->pic
[PXA27X_PIC_OST_4_11
]);
2044 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 121);
2046 s
->mmc
= pxa2xx_mmci_init(0x41100000, s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
2048 for (i
= 0; pxa270_serial
[i
].io_base
; i
++)
2050 serial_mm_init(pxa270_serial
[i
].io_base
, 2,
2051 s
->pic
[pxa270_serial
[i
].irqn
], serial_hds
[i
], 1);
2055 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
2056 s
->dma
, serial_hds
[i
]);
2059 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
], ds
);
2061 s
->cm_base
= 0x41300000;
2062 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2063 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2064 iomemtype
= cpu_register_io_memory(0, pxa2xx_cm_readfn
,
2065 pxa2xx_cm_writefn
, s
);
2066 cpu_register_physical_memory(s
->cm_base
, 0x1000, iomemtype
);
2067 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save
, pxa2xx_cm_load
, s
);
2069 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2071 s
->mm_base
= 0x48000000;
2072 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2073 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2074 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2075 iomemtype
= cpu_register_io_memory(0, pxa2xx_mm_readfn
,
2076 pxa2xx_mm_writefn
, s
);
2077 cpu_register_physical_memory(s
->mm_base
, 0x1000, iomemtype
);
2078 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save
, pxa2xx_mm_load
, s
);
2080 s
->pm_base
= 0x40f00000;
2081 iomemtype
= cpu_register_io_memory(0, pxa2xx_pm_readfn
,
2082 pxa2xx_pm_writefn
, s
);
2083 cpu_register_physical_memory(s
->pm_base
, 0x100, iomemtype
);
2084 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save
, pxa2xx_pm_load
, s
);
2086 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++);
2087 s
->ssp
= (struct pxa2xx_ssp_s
**)
2088 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
*) * i
);
2089 ssp
= (struct pxa2xx_ssp_s
*)
2090 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
) * i
);
2091 for (i
= 0; pxa27x_ssp
[i
].io_base
; i
++) {
2092 s
->ssp
[i
] = &ssp
[i
];
2093 ssp
[i
].base
= pxa27x_ssp
[i
].io_base
;
2094 ssp
[i
].irq
= s
->pic
[pxa27x_ssp
[i
].irqn
];
2096 iomemtype
= cpu_register_io_memory(0, pxa2xx_ssp_readfn
,
2097 pxa2xx_ssp_writefn
, &ssp
[i
]);
2098 cpu_register_physical_memory(ssp
[i
].base
, 0x1000, iomemtype
);
2099 register_savevm("pxa2xx_ssp", i
, 0,
2100 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
2104 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
2107 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2108 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2110 s
->rtc_base
= 0x40900000;
2111 iomemtype
= cpu_register_io_memory(0, pxa2xx_rtc_readfn
,
2112 pxa2xx_rtc_writefn
, s
);
2113 cpu_register_physical_memory(s
->rtc_base
, 0x1000, iomemtype
);
2115 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save
, pxa2xx_rtc_load
, s
);
2117 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600, s
->pic
[PXA2XX_PIC_I2C
], 0xffff);
2118 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100, s
->pic
[PXA2XX_PIC_PWRI2C
], 0xff);
2120 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
2122 /* GPIO1 resets the processor */
2123 /* The handler can be overridden by board-specific code */
2124 pxa2xx_gpio_handler_set(s
->gpio
, 1, pxa2xx_reset
, s
);
2128 /* Initialise a PXA255 integrated chip (ARM based core). */
2129 struct pxa2xx_state_s
*pxa255_init(unsigned int sdram_size
,
2132 struct pxa2xx_state_s
*s
;
2133 struct pxa2xx_ssp_s
*ssp
;
2135 s
= (struct pxa2xx_state_s
*) qemu_mallocz(sizeof(struct pxa2xx_state_s
));
2137 s
->env
= cpu_init();
2138 cpu_arm_set_model(s
->env
, "pxa255");
2139 register_savevm("cpu", 0, 0, cpu_save
, cpu_load
, s
->env
);
2141 /* SDRAM & Internal Memory Storage */
2142 cpu_register_physical_memory(PXA2XX_SDRAM_BASE
, sdram_size
,
2143 qemu_ram_alloc(sdram_size
) | IO_MEM_RAM
);
2144 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE
, PXA2XX_INTERNAL_SIZE
,
2145 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE
) | IO_MEM_RAM
);
2147 s
->pic
= pxa2xx_pic_init(0x40d00000, s
->env
);
2149 s
->dma
= pxa255_dma_init(0x40000000, s
->pic
[PXA2XX_PIC_DMA
]);
2151 pxa25x_timer_init(0x40a00000, &s
->pic
[PXA2XX_PIC_OST_0
]);
2153 s
->gpio
= pxa2xx_gpio_init(0x40e00000, s
->env
, s
->pic
, 85);
2155 s
->mmc
= pxa2xx_mmci_init(0x41100000, s
->pic
[PXA2XX_PIC_MMC
], s
->dma
);
2157 for (i
= 0; pxa255_serial
[i
].io_base
; i
++)
2159 serial_mm_init(pxa255_serial
[i
].io_base
, 2,
2160 s
->pic
[pxa255_serial
[i
].irqn
], serial_hds
[i
], 1);
2164 s
->fir
= pxa2xx_fir_init(0x40800000, s
->pic
[PXA2XX_PIC_ICP
],
2165 s
->dma
, serial_hds
[i
]);
2168 s
->lcd
= pxa2xx_lcdc_init(0x44000000, s
->pic
[PXA2XX_PIC_LCD
], ds
);
2170 s
->cm_base
= 0x41300000;
2171 s
->cm_regs
[CCCR
>> 2] = 0x02000210; /* 416.0 MHz */
2172 s
->clkcfg
= 0x00000009; /* Turbo mode active */
2173 iomemtype
= cpu_register_io_memory(0, pxa2xx_cm_readfn
,
2174 pxa2xx_cm_writefn
, s
);
2175 cpu_register_physical_memory(s
->cm_base
, 0x1000, iomemtype
);
2176 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save
, pxa2xx_cm_load
, s
);
2178 cpu_arm_set_cp_io(s
->env
, 14, pxa2xx_cp14_read
, pxa2xx_cp14_write
, s
);
2180 s
->mm_base
= 0x48000000;
2181 s
->mm_regs
[MDMRS
>> 2] = 0x00020002;
2182 s
->mm_regs
[MDREFR
>> 2] = 0x03ca4000;
2183 s
->mm_regs
[MECR
>> 2] = 0x00000001; /* Two PC Card sockets */
2184 iomemtype
= cpu_register_io_memory(0, pxa2xx_mm_readfn
,
2185 pxa2xx_mm_writefn
, s
);
2186 cpu_register_physical_memory(s
->mm_base
, 0x1000, iomemtype
);
2187 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save
, pxa2xx_mm_load
, s
);
2189 s
->pm_base
= 0x40f00000;
2190 iomemtype
= cpu_register_io_memory(0, pxa2xx_pm_readfn
,
2191 pxa2xx_pm_writefn
, s
);
2192 cpu_register_physical_memory(s
->pm_base
, 0x100, iomemtype
);
2193 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save
, pxa2xx_pm_load
, s
);
2195 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++);
2196 s
->ssp
= (struct pxa2xx_ssp_s
**)
2197 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
*) * i
);
2198 ssp
= (struct pxa2xx_ssp_s
*)
2199 qemu_mallocz(sizeof(struct pxa2xx_ssp_s
) * i
);
2200 for (i
= 0; pxa255_ssp
[i
].io_base
; i
++) {
2201 s
->ssp
[i
] = &ssp
[i
];
2202 ssp
[i
].base
= pxa255_ssp
[i
].io_base
;
2203 ssp
[i
].irq
= s
->pic
[pxa255_ssp
[i
].irqn
];
2205 iomemtype
= cpu_register_io_memory(0, pxa2xx_ssp_readfn
,
2206 pxa2xx_ssp_writefn
, &ssp
[i
]);
2207 cpu_register_physical_memory(ssp
[i
].base
, 0x1000, iomemtype
);
2208 register_savevm("pxa2xx_ssp", i
, 0,
2209 pxa2xx_ssp_save
, pxa2xx_ssp_load
, s
);
2213 usb_ohci_init_pxa(0x4c000000, 3, -1, s
->pic
[PXA2XX_PIC_USBH1
]);
2216 s
->pcmcia
[0] = pxa2xx_pcmcia_init(0x20000000);
2217 s
->pcmcia
[1] = pxa2xx_pcmcia_init(0x30000000);
2219 s
->rtc_base
= 0x40900000;
2220 iomemtype
= cpu_register_io_memory(0, pxa2xx_rtc_readfn
,
2221 pxa2xx_rtc_writefn
, s
);
2222 cpu_register_physical_memory(s
->rtc_base
, 0x1000, iomemtype
);
2224 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save
, pxa2xx_rtc_load
, s
);
2226 s
->i2c
[0] = pxa2xx_i2c_init(0x40301600, s
->pic
[PXA2XX_PIC_I2C
], 0xffff);
2227 s
->i2c
[1] = pxa2xx_i2c_init(0x40f00100, s
->pic
[PXA2XX_PIC_PWRI2C
], 0xff);
2229 s
->i2s
= pxa2xx_i2s_init(0x40400000, s
->pic
[PXA2XX_PIC_I2S
], s
->dma
);
2231 /* GPIO1 resets the processor */
2232 /* The handler can be overridden by board-specific code */
2233 pxa2xx_gpio_handler_set(s
->gpio
, 1, pxa2xx_reset
, s
);