hw/prep_pci.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "vl.h"
  26 typedef uint32_t pci_addr_t;
  27 #include "pci_host.h"
  28
  29 typedef PCIHostState PREPPCIState;
  30
  31 static void pci_prep_addr_writel(void* opaque, uint32_t addr, uint32_t val)
  32 {
  33     PREPPCIState *s = opaque;
  34     s->config_reg = val;
  35 }
  36
  37 static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr)
  38 {
  39     PREPPCIState *s = opaque;
  40     return s->config_reg;
  41 }
  42
  43 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
  44 {
  45     int i;
  46
  47     for(i = 0; i < 11; i++) {
  48         if ((addr & (1 << (11 + i))) != 0)
  49             break;
  50     }
  51     return (addr & 0x7ff) |  (i << 11);
  52 }
  53
  54 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
  55 {
  56     PREPPCIState *s = opaque;
  57     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
  58 }
  59
  60 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
  61 {
  62     PREPPCIState *s = opaque;
  63 #ifdef TARGET_WORDS_BIGENDIAN
  64     val = bswap16(val);
  65 #endif
  66     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
  67 }
  68
  69 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
  70 {
  71     PREPPCIState *s = opaque;
  72 #ifdef TARGET_WORDS_BIGENDIAN
  73     val = bswap32(val);
  74 #endif
  75     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
  76 }
  77
  78 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
  79 {
  80     PREPPCIState *s = opaque;
  81     uint32_t val;
  82     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
  83     return val;
  84 }
  85
  86 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
  87 {
  88     PREPPCIState *s = opaque;
  89     uint32_t val;
  90     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
  91 #ifdef TARGET_WORDS_BIGENDIAN
  92     val = bswap16(val);
  93 #endif
  94     return val;
  95 }
  96
  97 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
  98 {
  99     PREPPCIState *s = opaque;
 100     uint32_t val;
 101     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
 102 #ifdef TARGET_WORDS_BIGENDIAN
 103     val = bswap32(val);
 104 #endif
 105     return val;
 106 }
 107
 108 static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
 109     &PPC_PCIIO_writeb,
 110     &PPC_PCIIO_writew,
 111     &PPC_PCIIO_writel,
 112 };
 113
 114 static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
 115     &PPC_PCIIO_readb,
 116     &PPC_PCIIO_readw,
 117     &PPC_PCIIO_readl,
 118 };
 119
 120 /* Don't know if this matches real hardware, but it agrees with OHW.  */
 121 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
 122 {
 123     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 124 }
 125
 126 static void prep_set_irq(qemu_irq *pic, int irq_num, int level)
 127 {
 128     qemu_set_irq(pic[irq_num ? 11 : 9], level);
 129 }
 130
 131 PCIBus *pci_prep_init(qemu_irq *pic)
 132 {
 133     PREPPCIState *s;
 134     PCIDevice *d;
 135     int PPC_io_memory;
 136
 137     s = qemu_mallocz(sizeof(PREPPCIState));
 138     s->bus = pci_register_bus(prep_set_irq, prep_map_irq, pic, 0, 4);
 139
 140     register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
 141     register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
 142
 143     register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
 144     register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
 145     register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
 146     register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
 147     register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
 148     register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
 149
 150     PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
 151                                            PPC_PCIIO_write, s);
 152     cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
 153
 154     /* PCI host bridge */
 155     d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
 156                             sizeof(PCIDevice), 0, NULL, NULL);
 157     d->config[0x00] = 0x57; // vendor_id : Motorola
 158     d->config[0x01] = 0x10;
 159     d->config[0x02] = 0x01; // device_id : Raven
 160     d->config[0x03] = 0x48;
 161     d->config[0x08] = 0x00; // revision
 162     d->config[0x0A] = 0x00; // class_sub = pci host
 163     d->config[0x0B] = 0x06; // class_base = PCI_bridge
 164     d->config[0x0C] = 0x08; // cache_line_size
 165     d->config[0x0D] = 0x10; // latency_timer
 166     d->config[0x0E] = 0x00; // header_type
 167     d->config[0x34] = 0x00; // capabilities_pointer
 168
 169     return s->bus;
 170 }
 171